Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device. The display substrate comprises a substrate (101) and a plurality of sub-pixels (P1, P2, P3), at least one sub-pixel (P1, P2, P3) comprises a pixel driving circuit and a light-emitting device (103) connected to the pixel driving circuit, the pixel driving circuit comprises a plurality of transistors, at least one transistor comprises an active layer and two gate electrodes; a semiconductor layer and a plurality of conductive layers arranged on a side of the semiconductor layer away from the substrate are arranged on the substrate, at least one conductive layer is provided with at least one electrode plate, and an orthographic projection of the electrode plate on the substrate (101) and an orthographic projection of the active layer located between the two gate electrodes on the substrate (101) have an overlapping area.

Description

[0001] This application claims priority to the PCT application filed on January 27, 2021, with application number PCT / CN2021 / 073957 and invention name “Pixel driving circuit and driving method thereof, display substrate, and display device”, the content of which should be understood as being incorporated into this application by reference. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED as the light-emitting device and thin film transistor (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a display substrate, which includes a substrate and a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit including a plurality of transistors, at least one transistor including an active layer and two gate electrodes; a semiconductor layer and a plurality of conductive layers arranged on a side of the semiconductor layer away from the substrate are arranged on the substrate, at least one conductive layer is provided with at least one electrode plate, and an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer located between the two gate electrodes on the substrate have an overlapping area.

[0006] In an exemplary embodiment, the plurality of conductive layers include a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on a side of the semiconductor layer away from the substrate, and the electrode plate is disposed on the first conductive layer, the second conductive layer or the third conductive layer.

[0007] In an exemplary embodiment, the display substrate further includes a first power line connected to the pixel driving circuit, and at least one electrode plate is connected to the first power line.

[0008] In an exemplary embodiment, the plurality of transistors include at least a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; a first electrode of the first transistor is connected to a data signal line, and a second electrode of the first transistor is connected to a third node; a first electrode of the second transistor is connected to a first node, and a second electrode of the second transistor is connected to a fourth node; a gate electrode of the third transistor is connected to a first node, a first electrode of the third transistor is connected to a first power line, and a second electrode of the third transistor is connected to a fourth node; a first electrode of the fourth transistor is connected to an initial signal line, and a second electrode of the fourth transistor is connected to a first node; a first electrode of the fifth transistor is connected to a first power line, and a second electrode of the fifth transistor is connected to a second node.

[0009] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor and a threshold capacitor, the storage capacitor includes a storage capacitor first plate and a storage capacitor second plate, the threshold capacitor includes a threshold capacitor first plate and a threshold capacitor second plate; the storage capacitor first plate is connected to the third node, and the storage capacitor second plate is connected to the second node; the threshold capacitor first plate is connected to the first node, and the threshold capacitor second plate is connected to the second node.

[0010] In an exemplary embodiment, the storage capacitor first plate and the threshold capacitor first plate are disposed on the first conductive layer, the storage capacitor first plate and the threshold capacitor first plate are spaced apart, and the storage capacitor first plate does not overlap with the semiconductor layer.

[0011] In an exemplary embodiment, the storage capacitor second plate and the threshold capacitor second plate are arranged on the second conductive layer, the storage capacitor second plate and the threshold capacitor second plate are connected to each other, the orthographic projection of the storage capacitor second plate on the substrate and the orthographic projection of the storage capacitor first plate on the substrate have an overlapping area, and the orthographic projection of the threshold capacitor second plate on the substrate and the orthographic projection of the threshold capacitor first plate on the substrate have an overlapping area.

[0012] In an exemplary embodiment, the fifth transistor is a dual-gate transistor, and the fifth transistor includes at least a fifth active layer and two fifth gate electrodes; the electrode plate includes a first electrode plate, and an orthographic projection of the first electrode plate on the substrate has an overlapping area with an orthographic projection of the fifth active layer located between the two fifth gate electrodes on the substrate.

[0013] In an exemplary embodiment, the two fifth gate electrodes are disposed on the first conductive layer, the first electrode plate is disposed on the first conductive layer or the second conductive layer, the first power line is disposed on the third conductive layer, and the first power line is connected to the first electrode plate through a via.

[0014] In an exemplary embodiment, the second conductive layer further includes a first power connection line, the first electrode plate is connected to the first power connection line, and the first power line is connected to the first power connection line through a via hole.

[0015] In an exemplary embodiment, the second transistor is a dual-gate transistor, the second transistor includes at least a second active layer and two second gate electrodes; the electrode plate includes a second electrode plate, and an orthographic projection of the second electrode plate on the substrate and an orthographic projection of the second active layer located between the two second gate electrodes on the substrate have an overlapping area.

[0016] In an exemplary embodiment, the two second gate electrodes are disposed on the first conductive layer, the second electrode plate is disposed on the first conductive layer or the second conductive layer, the third conductive layer is further provided with a first connecting electrode, and the first connecting electrode is connected to the second electrode plate through a via.

[0017] In an exemplary embodiment, the first connecting electrode serves as a second electrode of the first transistor and is connected to the first electrode plate of the storage capacitor through a via hole.

[0018] In an exemplary embodiment, the fourth transistor is a dual-gate transistor, and the fourth transistor includes at least a fourth active layer and two fourth gate electrodes; there is an overlapping area between the orthographic projection of the first connecting electrode on the first power line and the orthographic projection of the fourth active layer located between the two fourth gate electrodes on the first power line.

[0019] In an exemplary embodiment, the third conductive layer is further provided with a second connecting electrode, the second connecting electrode simultaneously serves as the first electrode of the second transistor and the second electrode of the fourth transistor, and the second connecting electrode is connected to the first electrode plate of the threshold capacitor through a via.

[0020] In an exemplary embodiment, the third conductive layer is also provided with a second connecting electrode, and the third connecting electrode serves as the first electrode of the fourth transistor. The third connecting electrode is connected to the initial signal line through a via, and there is an overlapping area between the orthographic projection of the third connecting electrode on the substrate and the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor on the substrate.

[0021] The present disclosure also provides a display device, comprising the aforementioned display substrate.

[0022] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate comprises a substrate and a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit comprises a plurality of transistors, at least one transistor comprises an active layer and two gate electrodes; the preparation method comprises:

[0023] A semiconductor layer and a plurality of conductive layers are formed on the substrate and arranged on a side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and an orthographic projection of the electrode plate on the substrate overlaps with an orthographic projection of an active layer located between the two gate electrodes on the substrate.

[0024] In an exemplary embodiment, forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate includes:

[0025] forming a semiconductor layer on the substrate;

[0026] A first conductive layer, a second conductive layer and a third conductive layer are sequentially formed on the semiconductor layer, and the electrode plate is on the first conductive layer, the second conductive layer or the third conductive layer.

[0027] In an exemplary embodiment, a first power line connected to the pixel driving circuit is disposed on at least one conductive layer, and at least one electrode plate is connected to the first power line.

[0028] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0030] Figure 1 is a structural schematic diagram of a display device;

[0031] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0032] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0033] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0034] Figure 5 is a working timing diagram of a pixel driving circuit;

[0035] Figure 6 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 7 It is a schematic diagram of an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed;

[0037] Figure 8 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first conductive layer pattern;

[0038] Fig. 9 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second conductive layer pattern;

[0039] Fig.10 It is a schematic diagram of an exemplary embodiment of the present disclosure after a fourth insulating layer pattern is formed;

[0040] Fig.11 It is a schematic diagram of an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0041] Fig.12 It is a schematic diagram of an exemplary embodiment of the present disclosure after a fifth insulating layer pattern is formed;

[0042] Fig.13 It is a schematic diagram of an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0043] Fig.14 FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.

[0044] Description of reference numerals:

[0045] 11—first active layer; 12—second active layer; 13—third active layer;

[0046] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0047] 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line;

[0048] 22—second scanning signal line; 23—third scanning signal line; 24—light emitting control line;

[0049] 26—storage capacitor first plate; 27—threshold capacitor first plate; 31—initial signal line;

[0050] 32—reference signal connection line; 33—first power connection line; 34—second plate of storage capacitor;

[0051] 35—second electrode plate of threshold capacitor; 36—first electrode plate; 37—second electrode plate;

[0052] 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode;

[0053] 44—fourth connecting electrode; 45—fifth connecting electrode; 46—sixth connecting electrode;

[0054] 51—anode connection electrode; 52—second power connection line; 71—first power line;

[0055] 72—reference signal line; 73—data signal line; 74—second power line;

[0056] 101—substrate; 102—driving circuit layer; 103—light emitting device;

[0057] 104—encapsulation layer; 301—anode; 302—pixel definition layer;

[0058] 303—organic light emitting layer; 304—cathode; 401—first encapsulation layer;

[0059] 402 - second encapsulation layer; 403 - third encapsulation layer. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0061] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. One method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0062] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0063] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0064] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0065] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0066] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0067] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0068] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0069] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0070] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0071] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1 As shown, the OLED display device may include a scan signal driver, a data signal driver, a light emitting signal driver, an OLED display substrate, a first power supply unit, a second power supply unit, and an initial power supply unit. In an exemplary embodiment, the OLED display substrate includes at least a plurality of scan signal lines (S1 to S2). N ), multiple data signal lines (D1 to D M ) and multiple luminous signal lines (EM1 to EM N ), the scan signal driver is configured to sequentially provide a plurality of scan signal lines (S1 to S N ) provides a scan signal, and the data signal driver is configured to provide a plurality of data signal lines (D1 to D M ) provides a data signal, and the light emitting signal driver is configured to sequentially transmit data signals to a plurality of light emitting signal lines (EM1 to EM N ) provides a light emitting control signal. In an exemplary embodiment, a plurality of scan signal lines and a plurality of light emitting signal lines extend in a horizontal direction, and a plurality of data signal lines extend in a vertical direction. The display device includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device, and the pixel driving circuit of a sub-pixel can be connected to a scan signal line, a light emitting control line, and a data signal line. The first power supply unit, the second power supply unit, and the initial power supply unit are respectively configured to provide a first power supply voltage, a second power supply voltage, and an initial power supply voltage to the pixel driving circuit through the first power line, the second power line, and the initial signal line.

[0072] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0073] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white (W) sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle pattern. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern, which is not limited in the present disclosure.

[0074] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting device 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting device 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0075] In an exemplary embodiment, the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 3In the example, each sub-pixel includes a driving transistor and a storage capacitor. In some possible implementations, the driving circuit layer 102 of each sub-pixel may include: a first insulating layer disposed on a substrate; an active layer disposed on the first insulating layer; a second insulating layer covering the active layer; a gate electrode and a first electrode plate disposed on the second insulating layer; a third insulating layer covering the gate electrode and the first electrode plate; a second electrode plate disposed on the third insulating layer; a fourth insulating layer covering the second electrode plate, the second insulating layer, the third insulating layer and the fourth insulating layer having vias, the vias exposing the active layer; a source electrode and a drain electrode disposed on the fourth insulating layer, the source electrode and the drain electrode being connected to the active layer through the vias respectively; and a flat layer covering the aforementioned structure, the flat layer having vias, the vias exposing the drain electrode. The active layer, the gate electrode, the source electrode and the drain electrode constitute the driving transistor 210, and the first electrode plate and the second electrode plate constitute the storage capacitor 211.

[0076] In an exemplary embodiment, the light emitting device 103 may include an anode 301, a pixel definition layer 302, an organic light emitting layer 303, and a cathode 304. The anode 301 is disposed on the flat layer, and is connected to the drain electrode of the driving transistor 210 through a via hole provided on the flat layer; the pixel definition layer 302 is disposed on the anode 301 and the flat layer, and a pixel opening is provided on the pixel definition layer 302, and the pixel opening exposes the anode 301; the organic light emitting layer 303 is at least partially disposed in the pixel opening, and the organic light emitting layer 303 is connected to the anode 301; the cathode 304 is disposed on the organic light emitting layer 303, and the cathode 304 is connected to the organic light emitting layer 303; the organic light emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304.

[0077] In an exemplary embodiment, the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting device 103.

[0078] In an exemplary embodiment, the organic light-emitting layer 303 may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode 301. In an exemplary embodiment, the hole injection layers of all sub-pixels are a common layer connected together, the hole transport layers of all sub-pixels are a common layer connected together, the light-emitting layers of adjacent sub-pixels may overlap slightly, or may be isolated, and the hole blocking layer is a common layer connected together.

[0079] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T2C structure. Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit, illustrating an 8T2C structure. Figure 4 As shown, the pixel driving circuit may include 8 switch transistors (first transistor T1 to eighth transistor T8), 2 capacitors (storage capacitor Cst and threshold capacitor CVth), and the pixel driving circuit is connected to 9 signal lines respectively, and the 9 signal lines include a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a light emitting signal line EM, a reference signal line REF, an initial signal line INIT, a data signal line DATA, a first power line VDD, and a second power line VSS. In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the data signal line DATA, and the second electrode of the first transistor is connected to the second node N3. The gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the fourth node N4. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first power line VDD, and the second electrode of the third transistor T3 is connected to the fourth node N4. The gate electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the initial signal line INIT, and the second electrode of the fourth transistor T4 is connected to the first node N1. The gate electrode of the fifth transistor T5 is connected to the third scanning signal line S3, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the second scanning signal line S2, the first electrode of the sixth transistor T6 is connected to the initial signal line INIT, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The gate electrode of the seventh transistor T7 is connected to the light emitting signal line EM, the first electrode of the seventh transistor T7 is connected to the fourth node N4, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. The gate electrode of the eighth transistor T8 is connected to the light emitting signal line EM, the first electrode of the eighth transistor T8 is connected to the reference signal line REF, and the second electrode of the eighth transistor T8 is connected to the third node N3. The first end of the threshold capacitor CVth is connected to the first node N1, and the second end of the threshold capacitor CVth is connected to the second node N2. A first end of the storage capacitor Cst is connected to the second node N2 , and a second end of the storage capacitor Cst is connected to the third node N3 .

[0080] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include a P-type transistor and an N-type transistor.

[0081] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD continuously provides a high level signal.

[0082] In an exemplary embodiment, the second scan signal line S2 is a scan signal line in the pixel driving circuit of the current display row, and the third scan signal line S3 is a scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the second scan signal line S2 is S(n), and the third scan signal line S3 is S(n-1), and the third scan signal line S3 of the current display row and the second scan signal line S2 in the pixel driving circuit of the previous display row can be the same signal line, or, the second scan signal line S2 of the current display row and the third scan signal line S3 in the pixel driving circuit of the next display row can be the same signal line, so as to reduce the signal lines of the display panel and realize a narrow frame of the display panel.

[0083] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the emission signal line EM and the initial signal line INIT may extend in a horizontal direction, and the data signal line DATA, the first power line VDD, the second power line VSS and the reference signal line REF may extend in a vertical direction.

[0084] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0085] Figure 5 This is a working timing diagram of a pixel driving circuit. Figure 4 The operation process of the pixel driving circuit of the example is described in detail. Figure 4 The pixel driving circuit includes 8 switching transistors (first transistor T1 to eighth transistor T8), 2 capacitors (storage capacitor Cst and threshold capacitor CVth) and 9 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, light emitting signal line EM, reference signal line REF, initial signal line INIT, data signal line DATA, first power line VDD and second power line VSS), and all 8 transistors are P-type transistors.

[0086] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0087] The first stage A1 is called the reset and data refresh stage. The signals of the first scan signal line S1 and the third scan signal line S3 are low-level signals, and the signals of the second scan signal line S2 and the light-emitting signal line EM are high-level signals. The signal of the first scan signal line S1 is a low-level signal, which turns on the first transistor T1 and the fourth transistor T4. The first transistor T1 is turned on so that the data voltage output by the data signal line DATA is provided to the third node N3, and the data voltage Vdt is written to the third node N3. The fourth transistor T4 is turned on so that the initial signal of the initial signal line INIT is provided to the first node N1, and the first node N1 is reset to the initial voltage Vinit. The signal of the third scan signal line S3 is a low-level signal, which turns on the fifth transistor T5, and the power supply voltage output by the first power line VDD is provided to the second node N2, and the power supply voltage Vdd is written to the second node N2.

[0088] The second stage A2 is called the threshold acquisition stage. The signals of the second scanning signal line S2 and the third scanning signal line S3 are low-level signals, and the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals. The signal of the third scanning signal line S3 is a low-level signal, so that the fifth transistor T5 continues to be turned on, and the power supply voltage output by the first power line VDD is provided to the second node N2, and the second node N2 maintains the power supply voltage Vdd. The signal of the second scanning signal line S2 is a low-level signal, so that the second transistor T2 and the sixth transistor T6 are turned on. The second transistor T2 is turned on so that the first node N1 and the fourth node N4 have the same potential, and the third transistor T3 forms a "diode connection" structure. The first power line VDD charges the first node N1, and the first node N1 is charged to Vdd-|Vth| potential and then cuts off, and the information with the threshold voltage of the third transistor T3 is stored in the threshold capacitor CVth. The sixth transistor T6 is turned on so that the initial signal of the initial signal line INIT is provided to the first electrode of the OLED, and the first electrode of the OLED is reset to the initial voltage Vinit.

[0089] The third stage A3 is called the light-emitting stage. The signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scanning signal line S1, the second scanning signal line S2 and the third scanning signal line S3 are high-level signals. The signal of the light-emitting signal line EM is a low-level signal, which turns on the seventh transistor T7 and the eighth transistor T8. The seventh transistor T7 is turned on, and the potential of the first node N1 turns on the third transistor T3. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on third transistor T3 and the seventh transistor T7, driving the OLED to emit light. The eighth transistor T8 is turned on to provide the reference signal of the reference signal line REF to the third node N3, and the potential of the third node N3 changes from the data voltage Vdt to the reference voltage Vref. After the signals are superimposed, the potential of the first node N1 changes to: Vdd-|Vth|+(Vref-Vdt). The signal of the first scanning signal line S1 is a low-level signal to turn on the first transistor T1, and the data signal line DATA outputs the data voltage to the second node N2, and the second node N2 writes the data voltage Vdt. After the signals of the first node N1 and the second node N2 are superimposed, the potential of the first node N1 is Vdd-|Vth|+(Vref-Vdt). After that, the first node N1 is suspended and the original potential is maintained by the capacitor. During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Therefore, according to the potential of the first node N1, the driving current flowing through the third transistor T3 is:

[0090] I=β*(Vref-Vdt) 2

[0091] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, β is a constant, Vdt is the data voltage output by the data signal line DATA, and Vref is the reference voltage output by the reference signal line REF. The driving current formula does not contain the threshold voltage information of the third transistor T3, so the pixel driving circuit has a self-compensation effect on the threshold voltage of the third transistor T3.

[0092] During the operation of the pixel driving circuit, in the reset stage, the potential of the first node N1 is the initial voltage Vinit, the potential of the second node N2 is the power supply voltage Vdd, and the potential of the third node N3 is the data voltage Vdt. In the threshold acquisition stage, the potential of the first node N1 is Vdd-|Vth|, the potential of the second node N2 is the power supply voltage Vdd, and the potential of the third node N3 is the data voltage Vdt. In the light-emitting stage, the potential of the first node N1 is Vdd-|Vth|+(Vref-Vdt), the potential of the second node N2 is Vdd+Vref-Vdt, and the potential of the third node N3 is the reference voltage Vref.

[0093] Figure 6 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of three sub-pixels. Figure 6 As shown, in a plane parallel to the display substrate, a first scan signal line 21, two second scan signal lines 22 (a second scan signal line 22-1 and a second scan signal line 22-2), a third scan signal line 23, a light emitting control line 24, an initial signal line 31, a first power line 71, a reference signal line 72, a data signal line 73, a second power line 74, a pixel driving circuit and a light emitting device are arranged in the sub-pixel of the display substrate, and the pixel driving circuit may include a storage capacitor, a threshold capacitor and a plurality of transistors, each transistor including an active layer, a gate electrode, a first pole and a second pole, the storage capacitor including a storage capacitor first plate 26 and a storage capacitor second plate 34, and the threshold capacitor including a threshold capacitor first plate 27 and a threshold capacitor second plate 35. In an exemplary embodiment, the pixel driving circuit is connected to the first power line 71, and the first power line 71 provides a high level signal to the pixel driving circuit. In an exemplary embodiment, at least one transistor is a dual-gate transistor, and the dual-gate transistor includes an active layer, two gate electrodes, a first pole and a second pole. In an exemplary embodiment, the display substrate further includes at least one electrode plate, an orthographic projection of the at least one electrode plate on the substrate overlaps with an orthographic projection of the active layer between the two gate electrodes on the substrate, and the at least one electrode plate is connected to the first power line 71 .

[0094] In a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer and a plurality of conductive layers sequentially disposed on a base, and at least one conductive layer may be provided with an electrode plate. In an exemplary embodiment, the plurality of conductive layers may include a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the semiconductor layer, at least one electrode plate may be disposed on the first conductive layer or the second conductive layer, a first power line 71 is disposed on the third conductive layer, and the first power line 71 is connected to the electrode plate through a via.

[0095] In an exemplary embodiment, the semiconductor layer may include an active layer of multiple transistors, the first conductive layer may include a first scan signal line 21, a second scan signal line 22-1, a second scan signal line 22-2, a third scan signal line 23, a light emitting control line, a storage capacitor first plate 26 and a threshold capacitor first plate 27, the second conductive layer may include an initial signal line 31, a storage capacitor second plate 34 and a threshold capacitor second plate 35, the third conductive layer may include a first power line 71, a reference signal line 72 and a data signal line 73, and the fourth conductive layer may include a second power line 74.

[0096] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22-1, the second scan signal line 22-2, the third scan signal line 23 and the light emitting control line 24 extend along the first direction X, and the storage capacitor first plate 26 and the threshold capacitor first plate 27 are arranged at intervals. The initial signal line 31 extends along the first direction X, and the storage capacitor second plate 34 and the threshold capacitor second plate 35 are an integral structure connected to each other. The first power line 71, the reference signal line 72, the data signal line 73 and the second power line 74 extend along the second direction Y. The first direction X can be the extension direction of the scan signal line, and the second direction Y can be the extension direction of the data signal line.

[0097] In an exemplary embodiment, the second conductive layer may include a reference signal connection line 32 and a first power connection line 33. The reference signal connection line 32 and the first power connection line 33 both extend along the first direction X, the reference signal connection line 32 is connected to the reference signal line 72, and the first power connection line 33 is connected to the first power line 71, so that each sub-pixel in a sub-pixel row has the same reference voltage and power supply voltage, thereby improving display uniformity.

[0098] In an exemplary embodiment, the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5; a first electrode of the first transistor T1 is connected to the data signal line 74, and a second electrode of the first transistor T1 is connected to the first plate 26 of the storage capacitor; a first electrode of the second transistor T2 is connected to the first plate 27 of the threshold capacitor, and a second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3; a gate electrode of the third transistor T3 is connected to the first plate 27 of the threshold capacitor, and a first electrode of the third transistor T3 is connected to the first power line 71; a first electrode of the fourth transistor T4 is connected to the initial signal line 31, and a second electrode of the fourth transistor T4 is connected to the first plate 27 of the threshold capacitor; a first electrode of the fifth transistor T5 is connected to the first power line 71, and a second electrode of the fifth transistor T5 is connected to the second plate 34 of the storage capacitor and the second plate 35 of the threshold capacitor.

[0099] In an exemplary embodiment, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are dual-gate transistors. The second conductive layer may include a first electrode plate 36 and a second electrode plate 37. The first electrode plate 36 is configured to introduce a first parasitic capacitor at a dual-gate intermediate node of the fifth transistor T5, and the second electrode plate 37 is configured to introduce a second parasitic capacitor at a dual-gate intermediate node of the second transistor T2. In an exemplary embodiment, the third conductive layer may include a first connecting electrode 41, and the first connecting electrode 41 is configured to introduce a third parasitic capacitor at a dual-gate intermediate node of the fourth transistor T4.

[0100] In an exemplary embodiment, the first electrode plate 36 is directly connected to the first power connection line 33 , and the second electrode plate 37 is connected to the first connection electrode 41 through a via hole.

[0101] In an exemplary embodiment, the third conductive layer may include a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, and a sixth connection electrode 46. The first connection electrode 41 simultaneously serves as the second electrode of the first transistor T1 and the second electrode of the eighth transistor T8, the second connection electrode 42 simultaneously serves as the first electrode of the second transistor T2 and the second electrode of the fourth transistor T4, the third connection electrode 43 simultaneously serves as the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6, the fourth connection electrode 44 simultaneously serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, the fifth connection electrode 45 simultaneously serves as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the seventh transistor T7, and the sixth connection electrode 46 serves as the second electrode of the fifth transistor T5.

[0102] In an exemplary embodiment, the fourth conductive layer may include an anode connection electrode 51 and a second power connection line 52, the anode connection electrode 51 is configured to connect the fourth connection electrode 44 and the anode of the light-emitting device, and the second power connection line 52 extends along the first direction X and is connected to the second power line 74, so that each sub-pixel in a sub-pixel row has the same second power supply voltage, thereby improving display uniformity.

[0103] In an exemplary embodiment, the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, the first insulating layer being disposed between the substrate and the semiconductor layer, the second insulating layer being disposed between the semiconductor layer and the first conductive layer, the third insulating layer being disposed between the first conductive layer and the second conductive layer, the fourth insulating layer being disposed between the second conductive layer and the third conductive layer, and the fifth insulating layer being disposed between the third conductive layer and the fourth conductive layer.

[0104] The display substrate provided by the exemplary embodiment of the present disclosure avoids instantaneous high voltage at the middle node of the dual-gate transistor by setting a parasitic capacitor at the middle node of the dual-gate transistor, eliminates reverse leakage at the middle node of the dual-gate transistor, effectively stabilizes the potential of the key node, ensures the accuracy of the driving current, and improves the display effect.

[0105] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0106] In an exemplary embodiment, taking three sub-pixels in a sub-pixel row in a display substrate as an example, the preparation process of the display substrate may include the following operations.

[0107] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as Figure 7 shown.

[0108] In an exemplary embodiment, the semiconductor layer of at least one sub-pixel may include a first active layer of a first transistor T1 to an eighth active layer of an eighth transistor T8, the first active layer 11 of the first transistor T1 and the eighth active layer 18 of the eighth transistor T8 are interconnected as an integrated structure, the second active layer 12 of the second transistor T2 and the third active layer 13 of the third transistor T3 are interconnected as an integrated structure, the sixth active layer 16 of the sixth transistor T6 and the seventh active layer 17 of the seventh transistor T7 are interconnected as an integrated structure, the fourth active layer 14 of the fourth transistor T4 is separately set, and the fifth active layer 15 of the fifth transistor T5 is separately set.

[0109] In exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0110] In an exemplary embodiment, the first region 11-1 of the first active layer 11 is separately provided, and the second region 11-2 of the first active layer 11 also serves as the second region 18-2 of the eighth active layer 18, that is, the second region 11-2 of the first active layer 11 and the second region 18-2 of the eighth active layer 18 are connected to each other.

[0111] In an exemplary embodiment, the first region 12-1 of the second active layer 12 is separately provided, and the second region 12-2 of the second active layer 12 also serves as the second region 13-2 of the third active layer 13, that is, the second region 12-2 of the second active layer 12 and the second region 13-2 of the third active layer 13 are connected to each other.

[0112] In an exemplary embodiment, the first region 13-1 of the third active layer 13 is separately provided, and the second region 13-2 of the third active layer 13 also serves as the second region 12-2 of the second active layer 12, that is, the second region 13-2 of the third active layer 13 and the second region 12-2 of the second active layer 12 are connected to each other.

[0113] In an exemplary embodiment, the first region 14-1 of the fourth active layer 14 and the second region 14-2 of the fourth active layer 14 are each separately provided. The first region 15-1 of the fifth active layer 15 and the second region 15-2 of the fifth active layer 15 are each separately provided.

[0114] In an exemplary embodiment, the first region 16-1 of the sixth active layer 16 is provided separately, and the second region 16-2 of the sixth active layer 16 also serves as the second region 17-2 of the seventh active layer 17, that is, the second region 16-2 of the sixth active layer 16 and the second region 17-2 of the seventh active layer 17 are connected to each other.

[0115] In an exemplary embodiment, the first region 17-1 of the seventh active layer 17 is provided separately, and the second region 17-2 of the seventh active layer 17 also serves as the second region 16-2 of the sixth active layer 16, that is, the second region 17-2 of the seventh active layer 17 and the second region 16-2 of the sixth active layer 16 are connected to each other.

[0116] In an exemplary embodiment, the first region 18-1 of the eighth active layer 18 is separately provided, and the second region 18-2 of the eighth active layer 18 also serves as the second region 11-2 of the first active layer 11, that is, the second region 18-2 of the eighth active layer 18 and the second region 11-2 of the first active layer 11 are connected to each other.

[0117] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on a substrate having the aforementioned pattern, patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, wherein the first conductive layer pattern includes at least: a first scanning signal line 21, a second scanning signal line 22-1, a second scanning signal line 22-2, a third scanning signal line 23, a light emitting control line 24, a storage capacitor first plate 26, and a threshold capacitor first plate 27, such as Figure 8 shown.

[0118] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22-1, the second scan signal line 22-2, the third scan signal line 23 and the light emitting control line 24 may extend along the first direction X. The storage capacitor first plate 26 and the threshold capacitor first plate 27 are arranged at intervals and are both arranged between the second scan signal line 22-2 and the third scan signal line 23, the storage capacitor first plate 26 is close to the third scan signal line 23, and the threshold capacitor first plate 27 is close to the second scan signal line 22-2. The first scan signal line 21 is arranged on a side of the second scan signal line 22-2 away from the threshold capacitor first plate 27, and the light emitting control line 24 is arranged on a side of the first scan signal line 21 away from the third scan signal line 23. In an exemplary embodiment, the second scan signal line 22-1 and the second scan signal line 22-2 are connected to the same signal source and output the same signal.

[0119] In an exemplary embodiment, the storage capacitor first plate 26 may have a rectangular outline with chamfered corners. The threshold capacitor first plate 27 may have a rectangular outline with grooves disposed near the corners of the first region of the third active layer 13 and chamfered corners.

[0120] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22-1, the second scan signal line 22-2, the third scan signal line 23 and the light emitting control line 24 may be set with equal width or unequal width, and the width is the dimension in the second direction Y.

[0121] In an exemplary embodiment, a plurality of first gate blocks and a plurality of second gate blocks may be arranged on the third scanning signal line 23 (which is also the second scanning signal line of the sub-pixel in the previous sub-pixel row), a first gate block and a second gate block may be arranged in each sub-pixel, one end of the first gate block is connected to the third scanning signal line 23, and the other end extends along the second direction Y, one end of the second gate block is connected to the third scanning signal line 23, and the other end extends in the opposite direction of the second direction Y, and the first gate block and the second gate block are configured to form a dual gate electrode.

[0122] In an exemplary embodiment, the area where the first scan signal line 21 overlaps with the first active layer 11 serves as the gate electrode of the first transistor T1, the area where the first scan signal line 21 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4 (double gate structure), the area where the second scan signal line 22-2 overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2 (double gate structure), the area where the second scan signal line 22-1 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6, the area where the third scan signal line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5 (double gate structure), the area where the light emitting control line 24 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7, the area where the light emitting control line 24 overlaps with the eighth active layer 18 serves as the gate electrode of the eighth transistor T8, the orthographic projection of the threshold capacitor first plate 27 on the substrate and the orthographic projection of the third active layer 13 on the substrate have an overlapping area, and the threshold capacitor first plate 27 also serves as the gate electrode of the third transistor T3.

[0123] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 are all switch-type transistors, and the third transistor T3 is a driving-type transistor.

[0124] In an exemplary embodiment, the orthographic projection of the first electrode plate 26 of the storage capacitor on the substrate has no overlapping area with the orthographic projection of the third active layer 13 on the substrate.

[0125] In an exemplary embodiment, the storage capacitor first plates 26 of adjacent sub-pixels in a sub-pixel row are isolated from each other, and the threshold capacitor first plates 27 of adjacent sub-pixels are isolated from each other.

[0126] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer to the eighth active layer are both conductorized.

[0127] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, wherein the second conductive layer pattern at least includes: an initial signal line 31, a reference signal connection line 32, a first power connection line 33, a storage capacitor second plate 34, a threshold capacitor second plate 35, a first electrode plate 36, and a second electrode plate 37, such as Fig. 9 shown.

[0128] In an exemplary embodiment, the storage capacitor second plate 34 and the threshold capacitor second plate 35 are disposed between the second scan signal line 22 - 2 and the third scan signal line 23 , and the storage capacitor second plate 34 and the threshold capacitor second plate 35 may be an integral structure connected to each other.

[0129] In an exemplary embodiment, the storage capacitor second electrode plate 34 and the threshold capacitor second electrode plate 35 of the integrated structure may be rectangular, and the corners of the rectangular shape may be chamfered.

[0130] In an exemplary embodiment, the orthographic projection of the second plate 34 of the storage capacitor on the substrate and the orthographic projection of the first plate 26 of the storage capacitor on the substrate have an overlapping area. A first opening 34-1 is provided on the second plate 34 of the storage capacitor. The first opening 34-1 may be rectangular and located in the middle of the second plate 34 of the storage capacitor. The first opening 34-1 forms a ring structure of the second plate 34 of the storage capacitor. The first opening 34-1 exposes the third insulating layer covering the first plate 26 of the storage capacitor, and the orthographic projection of the first plate 26 of the storage capacitor on the substrate includes the orthographic projection of the first opening 34-1 on the substrate. In an exemplary embodiment, the first opening 34-1 is configured to accommodate a first via hole formed subsequently. The first via hole is located in the first opening 34-1 and exposes the first plate 26 of the storage capacitor, so that the first connecting electrode formed subsequently is connected to the first plate 26 of the storage capacitor through the first via hole.

[0131] In an exemplary embodiment, the orthographic projection of the threshold capacitor second plate 35 on the substrate and the orthographic projection of the threshold capacitor first plate 27 on the substrate have an overlapping area. A second opening 35-1 is provided on the threshold capacitor second plate 35. The second opening 35-1 may be rectangular and located in the middle of the threshold capacitor second plate 35. The second opening 35-1 forms a ring structure of the threshold capacitor second plate 35. The second opening 35-1 exposes the third insulating layer covering the threshold capacitor first plate 27, and the orthographic projection of the threshold capacitor first plate 27 on the substrate includes the orthographic projection of the second opening 35-1 on the substrate. In an exemplary embodiment, the second opening 35-1 is configured to accommodate a second via hole formed subsequently. The second via hole is located in the second opening 35-1 and exposes the threshold capacitor first plate 27, so that the second connecting electrode formed subsequently is connected to the threshold capacitor first plate 27 through the second via hole.

[0132] In an exemplary embodiment, the storage capacitor first plate 26 and the storage capacitor second plate 34 constitute the storage capacitor Cst of the pixel driving circuit, the storage capacitor first plate 26 serves as the second end of the storage capacitor Cst, and the storage capacitor second plate 34 serves as the first end of the storage capacitor Cst. The threshold capacitor first plate 27 and the threshold capacitor second plate 35 constitute the threshold capacitor CVth of the pixel driving circuit, the threshold capacitor first plate 27 serves as the first end of the threshold capacitor CVth and also serves as the gate electrode of the third transistor T3, and the threshold capacitor second plate 35 serves as the second end of the threshold capacitor. The first end of the storage capacitor Cst is connected to the second end of the threshold capacitor CVth, and the first end of the storage capacitor Cst also serves as the second end of the threshold capacitor CVth.

[0133] In an exemplary embodiment, the storage capacitor second plates 34 of adjacent sub-pixels in a sub-pixel row are arranged at intervals, and the threshold capacitor second plates 35 of adjacent sub-pixels in a sub-pixel row are arranged at intervals.

[0134] In an exemplary embodiment, the initial signal line 31, the reference signal connection line 32 and the first power connection line 33 extend along the first direction X, the initial signal line 31 is arranged on the side of the light-emitting control line 24 away from the first scanning signal line 21, the reference signal connection line 32 and the first power connection line 33 are arranged between the third scanning signal line 23 and the first electrode plate 26 of the storage capacitor, the reference signal connection line 32 is close to the first electrode plate 26 of the storage capacitor, and the first power connection line 33 is close to the third scanning signal line 23.

[0135] In an exemplary embodiment, the reference signal connection line 32 is configured to be connected to a subsequently formed reference signal line, so that the reference signal connection line 32 in a subpixel row serves as a connection line, so that each subpixel in a subpixel row has the same reference voltage, thereby improving display uniformity.

[0136] In an exemplary embodiment, the first power connection line 33 is configured to be connected to a first power line formed subsequently, so that the first power connection line 33 in a sub-pixel row serves as a connection line, so that each sub-pixel in a sub-pixel row has the same first power supply voltage, thereby improving display uniformity.

[0137] In an exemplary embodiment, the initial signal line 31 , the reference signal connection line 32 and the first power connection line 33 may be arranged with equal widths or with unequal widths.

[0138] In an exemplary embodiment, one end of the first electrode plate 36 is connected to the first power connection line 33, and the other end extends along the second direction Y, and the positive projection of the first electrode plate 36 on the substrate overlaps with the positive projection of the fifth active layer 15 between the two gate electrodes of the fifth transistor T5 of the dual-gate structure on the substrate. The first electrode plate 36 is configured to introduce a first parasitic capacitor at the dual-gate middle node of the fifth transistor T5, and the first parasitic capacitor is used to stabilize the potential of the dual-gate middle node of the fifth transistor T5, thereby stabilizing the potential of the second node. In an exemplary embodiment, the size of the first parasitic capacitor can be adjusted by adjusting the overlapping area of ​​the first electrode plate 36 and the fifth active layer 15 between the two gate electrodes of the fifth transistor T5.

[0139] In an exemplary embodiment, corresponding to sub-pixels emitting light of different colors, the overlapping areas of the fifth active layer 15 between the first electrode plate 36 and the two gate electrodes of the fifth transistor T5 may be different.

[0140] In an exemplary embodiment, the second electrode plate 37 is disposed between the first scan signal line 21 and the second scan signal line 22-2, and an orthographic projection of the second electrode plate 37 on the substrate overlaps with an orthographic projection of the second active layer 12 between the two gate electrodes of the second transistor T2 of the dual-gate structure on the substrate. The second electrode plate 37 is configured to introduce a second parasitic capacitor at the dual-gate intermediate node of the second transistor T2 to stabilize the potential of the first node N1. In an exemplary embodiment, the size of the second parasitic capacitor can be adjusted by adjusting the overlapping area of ​​the second electrode plate 37 and the second active layer 12 between the two gate electrodes of the second transistor T2.

[0141] In an exemplary embodiment, corresponding to sub-pixels emitting light of different colors, the overlapping areas of the second active layer 12 between the second electrode plate 37 and the two gate electrodes of the second transistor T2 may be different.

[0142] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, and the plurality of vias include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, and a twentieth via V20, such as Fig.10 shown.

[0143] In an exemplary embodiment, the first via hole V1 is located in the area where the first opening 34-1 of the second plate 34 of the storage capacitor is located, and the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first opening 34-1 on the substrate. The fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first plate 26 of the storage capacitor, and the first via hole V1 is configured to connect the subsequently formed first connecting electrode to the first plate 26 of the storage capacitor through the via hole.

[0144] In an exemplary embodiment, the second via hole V2 is located in the area where the second opening 35-1 of the second plate 35 of the threshold capacitor is set, and the fourth insulating layer and the third insulating layer in the second via hole V2 are etched away to expose the surface of the first plate 27 of the threshold capacitor, and the second via hole V2 is configured to connect the subsequently formed second connecting electrode to the first plate 27 of the threshold capacitor through the via hole.

[0145] In an exemplary embodiment, the third via hole V3 is located in the area where the second electrode plate 37 is located, the fourth insulating layer in the third via hole V3 is etched away to expose the surface of the second electrode plate 37, and the third via hole V3 is configured to connect the subsequently formed first connecting electrode to the second electrode plate 37 through the via hole.

[0146] In an exemplary embodiment, the fourth via hole V4 is located in the area where the first region of the first active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the fourth via hole V4 are etched away to expose the surface of the first region of the first active layer, and the fourth via hole V4 is configured to connect a subsequently formed data signal line to the first active layer through the via hole.

[0147] In an exemplary embodiment, the fifth via hole V5 is located in the area where the second area of ​​the first active layer (also the second area of ​​the eighth active layer) is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the first active layer, and the fifth via hole V5 is configured to connect a subsequently formed first connecting electrode to the first active layer through the via hole.

[0148] In an exemplary embodiment, the sixth via hole V6 is located in the area where the first zone of the eighth active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer 62 of the sixth via hole V6 are etched away to expose the surface of the first zone of the eighth active layer, and the sixth via hole V6 is configured to connect a subsequently formed reference signal line to the eighth active layer through the via hole.

[0149] In an exemplary embodiment, the seventh via hole V7 is located in the area where the first area of ​​the second active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the second active layer, and the seventh via hole V7 is configured to connect a subsequently formed second connecting electrode to the second active layer through the via hole.

[0150] In an exemplary embodiment, the eighth via hole V8 is located in the area where the second zone of the fourth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the eighth via hole V8 are etched away to expose the surface of the second zone of the fourth active layer, and the eighth via hole V8 is configured to connect a subsequently formed second connecting electrode to the fourth active layer through the via hole.

[0151] In an exemplary embodiment, the ninth via hole V9 is located in the area where the first zone of the fourth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the ninth via hole V9 are etched away to expose the surface of the first zone of the fourth active layer, and the ninth via hole V9 is configured to connect a subsequently formed third connecting electrode to the fourth active layer through the via hole.

[0152] In an exemplary embodiment, the tenth via hole V10 is located in the area where the initial signal line 31 is located, the fourth insulating layer in the tenth via hole V10 is etched away to expose the surface of the initial signal line 31, and the tenth via hole V10 is configured to connect the subsequently formed third connection electrode to the initial signal line 31 through the via hole.

[0153] In an exemplary embodiment, the eleventh via hole V11 is located in the area where the first zone of the sixth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the eleventh via hole V11 are etched away to expose the surface of the first zone of the sixth active layer, and the eleventh via hole V11 is configured to connect a subsequently formed third connecting electrode to the sixth active layer through the via hole.

[0154] In an exemplary embodiment, the twelfth via hole V12 is located in the area where the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the twelfth via hole V12 are etched away to expose the surface of the second area of ​​the sixth active layer, and the twelfth via hole V12 is configured to connect a subsequently formed fourth connecting electrode to the sixth active layer through the via hole.

[0155] In an exemplary embodiment, the thirteenth via hole V13 is located in the area where the first zone of the seventh active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the thirteenth via hole V13 are etched away to expose the surface of the first zone of the seventh active layer, and the thirteenth via hole V13 is configured to connect the subsequently formed fifth connecting electrode to the seventh active layer through the via hole.

[0156] In an exemplary embodiment, the fourteenth via hole V14 is located in the area where the second region of the second active layer (also the second region of the third active layer) is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the fourteenth via hole V14 are etched away to expose the surface of the second region of the second active layer, and the fourteenth via hole V14 is configured to connect a subsequently formed fifth connecting electrode to the second active layer through the via hole.

[0157] In an exemplary embodiment, the fifteenth via hole V15 is located in the area where the second electrode plate 34 of the storage capacitor is located, the fourth insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the second electrode plate 34 of the storage capacitor, and the fifteenth via hole V15 is configured to connect the subsequently formed sixth connecting electrode to the second electrode plate 34 of the storage capacitor through the via hole.

[0158] In an exemplary embodiment, the sixteenth via hole V16 is located in the area where the second zone of the fifth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the sixteenth via hole V16 are etched away to expose the surface of the second zone of the fifth active layer, and the sixteenth via hole V16 is configured to connect the subsequently formed sixth connecting electrode to the fifth active layer through the via hole.

[0159] In an exemplary embodiment, the seventeenth via hole V17 is located in the area where the reference signal connection line 32 is located, the fourth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the reference signal connection line 32, and the seventeenth via hole V17 is configured to connect a subsequently formed reference signal line to the reference signal connection line 32 through the via hole.

[0160] In an exemplary embodiment, the eighteenth via hole V18 is located in the area where the first zone of the third active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the eighteenth via hole V18 are etched away to expose the surface of the first zone of the third active layer, and the eighteenth via hole V18 is configured to connect a first power line formed subsequently to the third active layer through the via hole.

[0161] In an exemplary embodiment, the nineteenth via hole V19 is located in the area where the first zone of the fifth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the nineteenth via hole V19 are etched away to expose the surface of the first zone of the fifth active layer, and the nineteenth via hole V19 is configured to connect a first power line formed subsequently to the fifth active layer through the via hole.

[0162] In an exemplary embodiment, the twentieth via hole V20 is located in the area where the first power connection line 33 is located, the fourth insulating layer in the twentieth via hole V20 is etched away to expose the surface of the first power connection line 33, and the twentieth via hole V20 is configured to allow the subsequently formed first power connection line 71 to pass through the via hole and connect to the first power connection line 33.

[0163] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third metal film on the substrate having the aforementioned pattern, patterning the third metal film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, wherein the third conductive layer at least includes: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a first power line 71, a reference signal line 72, and a data signal line 73, such as Fig.11 shown.

[0164] In an exemplary embodiment, the first power line 71, the reference signal line 72 and the data signal line 73 extend along the second direction Y. The first power line 71, the reference signal line 72 and the data signal line 73 can be set with equal width or unequal width, can be straight lines, or can be broken lines.

[0165] In an exemplary embodiment, the first power line 71 is connected to the first area of ​​the third active layer through the eighteenth via hole V18, connected to the first area of ​​the fifth active layer through the nineteenth via hole V19, and connected to the first power connection line 33 through the twentieth via hole V20. The first power line 71 extending along the second direction Y is connected to the first power connection line 33 extending along the first direction X, so that multiple sub-pixels in a sub-pixel row have the same first power supply voltage, thereby improving display uniformity.

[0166] In an exemplary embodiment, the reference signal line 72 is connected to the first region of the eighth active layer through the sixth via hole V6, and is connected to the reference signal connection line 32 through the seventeenth via hole V17. The reference signal line 72 extending along the second direction Y is connected to the reference signal connection line 32 extending along the first direction X, so that multiple sub-pixels in a sub-pixel row have the same reference voltage, thereby improving display uniformity.

[0167] In an exemplary embodiment, the data signal line 73 is connected to the first region of the first active layer through the fourth via hole V4.

[0168] In an exemplary embodiment, the first connection electrode 41 is a straight line extending along the second direction Y, one end of which is connected to the first electrode plate 26 of the storage capacitor through the first via hole V1, the other end of which is connected to the second region of the first active layer (also the second region of the eighth active layer) through the fifth via hole V5, and the middle position between the two ends is connected to the second electrode plate 37 through the third via hole V3. The first connection electrode 41 simultaneously serves as the second electrode of the first transistor T1 and the second electrode of the eighth transistor T8, and has the same potential as the second end of the storage capacitor Cst (i.e., the third node N3).

[0169] In an exemplary embodiment, since the second electrode plate 37 is arranged at a node between the two gate electrodes of the second transistor T2 of the dual-gate structure, and the second electrode plate 37 has the same potential as the third node N3, an overlapping second parasitic capacitor is formed between the second active layer between the two gate electrodes and the second electrode plate 37 having the potential of the third node N3, and the second parasitic capacitor is used to stabilize the potential of the first node N1.

[0170] In an exemplary embodiment, the first connection electrode 41 is configured to introduce a third parasitic capacitor at a dual-gate intermediate node of the fourth transistor T4 of the dual-gate structure. The first connection electrode 41 extends along the second direction Y, and the third region 14-3 of the fourth active layer between the two gate electrodes of the fourth transistor T4 also extends along the second direction Y. The first connection electrode 41 is located on one side of the first power line 71 in the opposite direction of the first direction X, and the fourth active layer of the fourth transistor T4 is located on one side of the first connection electrode 41 in the opposite direction of the first direction X. The first connection electrode 41 is adjacent to the third region 14-3, and the positive projection of the third region 14-3 of the fourth active layer on the first power line 71 overlaps with the positive projection of the first connection electrode 41 on the first power line 71, that is, the positive projection of the first connection electrode 41 on the first power line 71 along the first direction X overlaps with the positive projection of the fourth active layer located between the two fourth gate electrodes on the first power line 71 along the first direction X. Therefore, a lateral third parasitic capacitor is formed between the first connection electrode 41 and the third region 14-3 of the fourth active layer, and the third parasitic capacitor is used to stabilize the potential of the first node N1.

[0171] In an exemplary embodiment, the second connection electrode 42 is a straight line extending along the second direction Y, one end of which is connected to the threshold capacitor first plate 27 through the second via V2, the other end of which is connected to the second region of the fourth active layer through the eighth via V8, and the middle position between the two ends is connected to the first region of the second active layer through the seventh via V7. The second connection electrode 42 simultaneously serves as the first pole of the second transistor T2 and the second pole of the fourth transistor T4, and has the same potential (i.e., the first node N1) as the first end of the threshold capacitor CVth. Since the threshold capacitor first plate 27 also serves as the gate electrode of the third transistor T3, the second connection electrode 42 realizes the mutual connection of the first pole of the second transistor T2, the gate electrode of the third transistor T3, the second pole of the fourth transistor T4, and the threshold capacitor first plate 27.

[0172] In an exemplary embodiment, the third connection electrode 43 is in a zigzag shape extending along the second direction Y, one end of which is connected to the first area of ​​the fourth active layer through the ninth via hole V9, the other end of which is connected to the first area of ​​the sixth active layer through the eleventh via hole V11, and the middle position between the two ends is connected to the initial signal line 31 through the tenth via hole V10. The third connection electrode 43 simultaneously serves as the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6, thereby realizing the simultaneous connection of the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6 with the initial signal line 31. In an exemplary embodiment, the orthographic projection of the third connection electrode 43 on the substrate overlaps with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 on the substrate.

[0173] In an exemplary embodiment, the fourth connection electrode 44 is block-shaped and connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the twelfth via hole V12. The fourth connection electrode 44 simultaneously serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, realizing the connection between the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0174] In an exemplary embodiment, the fifth connection electrode 45 is a straight line extending along the second direction Y, one end of which is connected to the first region of the seventh active layer through the thirteenth via hole V13, and the other end of which is connected to the second region of the second active layer (also the second region of the third active layer) through the fourteenth via hole V14. The fifth connection electrode 45 simultaneously serves as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the seventh transistor T7, so that the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the seventh transistor T7 have the same potential (i.e., the fourth node N4).

[0175] In an exemplary embodiment, the sixth connection electrode 46 is a straight line extending along the second direction Y, one end of which is connected to the storage capacitor second plate 34 through the fifteenth via hole V15, and the other end of which is connected to the second region of the fifth active layer through the sixteenth via hole V16. The sixth connection electrode 46 serves as the second electrode of the fifth transistor T5. Since it is connected to the storage capacitor second plate 34, and the storage capacitor second plate 34 and the threshold capacitor second plate 35 are an integral structure connected to each other, the second electrode of the fifth transistor T5, the first end of the storage capacitor Cst, and the second end of the threshold capacitor CVth have the same potential (i.e., the second node N2).

[0176] In the exemplary embodiment, since the first power line 71 is connected to the first power connection line 33, and the first power connection line 33 is connected to the first electrode plate 36, the first electrode plate 36 has the same potential as the first power line 71. Since there is an overlapped area between the orthographic projection of the first electrode plate 36 on the substrate and the orthographic projection of the fifth active layer 15 between the two gate electrodes of the fifth transistor T5 of the dual-gate structure on the substrate, an overlapping first parasitic capacitor is formed between the fifth active layer between the two gate electrodes and the first electrode plate 36 having the first power supply voltage, and the first parasitic capacitor is used to stabilize the potential of the dual-gate middle node of the fifth transistor T5, thereby stabilizing the potential of the second node.

[0177] (6) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: coating a fifth insulating film on the substrate formed with the aforementioned pattern, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein the fifth insulating layer is provided with a plurality of via holes, and the plurality of via holes includes at least a thirty-first via hole V31, such as Fig.12 shown.

[0178] In an exemplary embodiment, the thirty-first via hole V31 is located in the area where the fourth connecting electrode 44 is located, the fifth insulating layer in the thirty-first via hole V31 is removed, exposing the surface of the fourth connecting electrode 44, and the thirty-first via hole V31 is configured to connect the anode of the subsequently formed light-emitting device to the fourth connecting electrode 44 through the via hole.

[0179] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth metal film on the substrate on which the aforementioned pattern is formed, patterning the fourth metal film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, wherein the fourth conductive layer at least includes: an anode connection electrode 51, a second power connection line 52, and a second power line 74, such as Fig.13 shown.

[0180] In an exemplary embodiment, the anode connection electrode 51 is disposed on a side of the initial signal line 31 away from the first light-emitting signal line 24, the anode connection electrode 51 is rectangular, connected to the fourth connection electrode 44 through the thirty-first via hole V31, and the anode connection electrode 51 is configured to be connected to the anode of the subsequently formed light-emitting device. Since the fourth connection electrode 44 simultaneously serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, the connection between the anode of the light-emitting device and the pixel driving circuit is realized, so that the pixel driving circuit can drive the light-emitting device to emit light.

[0181] In an exemplary embodiment, the second power line 74 extends along the second direction Y, corresponding to the position of the first power line 71. The second power connection line 52 extends along the first direction X, is disposed between the first scan signal line 21 and the second scan signal line 22-2, and is connected to the second power line 74. Since the second power connection line 52 is connected to the second power line 74, the second power connection line 52 in a sub-pixel row serves as a low voltage signal connection line, so that each sub-pixel in a sub-pixel row has the same second power supply voltage, thereby improving display uniformity.

[0182] In an exemplary embodiment, the second power lines 74 may be arranged with equal widths, or may be arranged with unequal widths, and may be straight lines, or may be broken lines.

[0183] In an exemplary embodiment, the subsequent preparation process may include: forming a flat layer covering the pattern of the fourth conductive layer, forming an anode of the light-emitting device on the flat layer, forming a pixel definition layer covering the anode, the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposes the anode. Subsequently, an organic light-emitting layer is formed by an evaporation process, and a cathode is formed on the organic light-emitting layer. Subsequently, an encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting device.

[0184] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked, and the material of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the material of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. In an exemplary embodiment, the thickness of the first flexible material layer may be approximately 5 μm to 15 μm, for example, 10 μm; the thickness of the second flexible material layer may be approximately 5 μm to 15 μm, for example, 10 μm; the thickness of the first inorganic material layer may be approximately 0.3 μm to 0.9 μm, for example, 0.6 μm; the thickness of the second inorganic material layer may be approximately 0.3 μm to 0.9 μm, for example, 0.6 μm.

[0185] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first conductive layer is called the first gate metal (Gate1) layer, the second conductive layer is called the second gate metal (Gate2) layer, the third conductive layer is called the first source and drain metal (SD1) layer, and the fourth conductive layer is called the second source and drain metal (SD2) layer. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0186] In an exemplary embodiment, the first insulating layer has a thickness of 3000 to 5000 angstroms, the second insulating layer has a thickness of 1000 to 2000 angstroms, the third insulating layer has a thickness of 4500 to 7000 angstroms, the fourth insulating layer has a thickness of 3000 to 5000 angstroms, and the fifth insulating layer has a thickness of 3000 to 5000 angstroms.

[0187] High-resolution (PPI) displays have finer picture quality and display quality, and have become a design trend. Since the pixel area of ​​high-resolution displays is small, the arrangement of pixel drive circuits within a limited space needs to consider various interference factors, especially the impact of data signal lines on key nodes in pixel drive circuits. Figure 4 In the pixel driving circuit shown, in the light-emitting stage, the third node N3 is stabilized at the potential of the reference voltage provided by the reference signal line through the eighth transistor T8. Since the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are disconnected, in the light-emitting stage, the leakage path of the second node N2 is the single leakage channel of the fifth transistor T5, and the leakage path of the first node N1 is the double leakage channel of the second transistor T2 and the fourth transistor T4. In order to reduce the leakage of key nodes in the light-emitting stage, in a pixel driving circuit of a display substrate, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 all adopt a dual-gate structure, but this solution has the problem of poor potential stability of the first node N1 and the second node N2.

[0188] Research shows that the dual-gate middle node of the dual-gate transistor is in a suspended state, with gate-source capacitance (Cgs) and gate-drain capacitance (Cgd). When the gate voltage jumps from a low voltage to a high voltage, the middle node is coupled to a high voltage state, causing reverse leakage of the transistor, thereby affecting the potential of the first node N1 and the second node N2. The exemplary embodiment of the present disclosure proposes to set a parasitic capacitance at the dual-gate middle node of the dual-gate transistor to effectively stabilize the potential of the first node N1 and the second node N2. Fig.14 FIG. 1 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure. Fig.14As shown, in an exemplary embodiment, the dual-gate intermediate node N7 of the fifth transistor T5 is provided with a first parasitic capacitor C1, which is an overlapping capacitor formed by the fifth active layer and the first electrode plate 36 located between the two fifth gate electrodes of the fifth transistor T5, and the first electrode plate 36 has the same potential as the first power line. The dual-gate intermediate node N5 of the second transistor T2 is provided with a second parasitic capacitor C2, which is an overlapping capacitor formed by the second active layer and the second electrode plate 37 located between the two second gate electrodes of the second transistor T2, and the second electrode plate 37 has the same potential as the third node N3. The dual-gate intermediate node N6 of the fourth transistor T4 is provided with a third parasitic capacitor C3, which is a lateral capacitor formed by the fourth active layer and the first connection electrode 41 of the fourth transistor T4 located between the two fourth gate electrodes, and the first connection electrode 41 has the same potential as the third node N3. The dual-gate intermediate node N6 of the fourth transistor T4 is also provided with a fourth parasitic capacitor C4, which is an overlapping capacitor formed by the fourth active layer of the fourth transistor T4 located between the two fourth gate electrodes and the third connection electrode 43, and the third connection electrode 43 has the same potential as the initial signal line 31.

[0189] In an exemplary embodiment, for the single leakage channel of the second node N2 in the light-emitting stage, since one plate of the first parasitic capacitor C1 is connected to the dual-gate middle node N7 of the fifth transistor T5, and the other plate is connected to the first power line VDD, the double-gate middle node N7 of the fifth transistor T5 is prevented from jumping up due to the turning off of the third scan line S3, the reverse leakage is eliminated, and the potential of the second node N2 is effectively stabilized.

[0190] In an exemplary embodiment, for the dual leakage channel of the first node N1 in the light emitting stage, since one plate of the second parasitic capacitor C2 is connected to the dual-gate middle node N5 of the second transistor T2, and the other plate is connected to the third node N3, one plate of the third parasitic capacitor C3 is connected to the dual-gate middle node N6 of the fourth transistor T4, and the other plate is connected to the third node N3, when the data voltage Vdt is coupled to the first node N1, the dual-gate middle node N5 of the second transistor T2 and the dual-gate middle node N6 of the fourth transistor T4 jump synchronously, when the third node N3 is stabilized at the reference voltage Vref, the Vref-Vdt information is synchronously superimposed on the first node N1, the dual-gate middle node N5 and the dual-gate middle node N6, so that the potentials of the dual-gate middle node N5 and the dual-gate middle node N6 are close to the potential of the first node N1, thereby reducing the leakage of the second transistor T2 and the fourth transistor T4, and effectively stabilizing the potential of the first node N1.

[0191] In an exemplary embodiment, the capacitance values ​​of the first parasitic capacitor C1, the second parasitic capacitor C2, the third parasitic capacitor C3 and the fourth parasitic capacitor C4 can be designed according to the actual circuit to stabilize the potential of the key node. In an exemplary embodiment, the size of the parasitic capacitor can be adjusted by adjusting the overlapping area of ​​the electrode plate and the active layer, and the first parasitic capacitor C1, the second parasitic capacitor C2, the third parasitic capacitor C3 and the fourth parasitic capacitor C4 can be different for sub-pixels emitting light of different colors. For example, the capacitance values ​​of the first parasitic capacitor C1, the second parasitic capacitor C2, the third parasitic capacitor C3 and the fourth parasitic capacitor C4 can be approximately 0.1fF to 6.0fF.

[0192] It can be seen from the structure and preparation process of the display substrate described above that the display substrate provided by the exemplary embodiment of the present disclosure introduces parasitic capacitance at the dual-gate middle node of the dual-gate transistor, thereby avoiding instantaneous high voltage at the dual-gate middle node, eliminating reverse leakage at the dual-gate middle node, effectively stabilizing the potential of the key node, ensuring the accuracy of the driving current, and improving the display effect. The preparation process disclosed in the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0193] The structure and preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. In an exemplary embodiment, the first electrode plate and the second electrode plate can be arranged on other conductive layers. For example, the first electrode plate and the second electrode plate can be arranged on the first conductive layer, arranged on the same layer as the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor, and formed simultaneously by the same patterning process. The shape of the first electrode plate and the second electrode plate can be the same as the aforementioned exemplary embodiment. For another example, the first electrode plate and the second electrode plate can be arranged on the third conductive layer, arranged on the same layer as the first connecting electrode and the first power line, and formed simultaneously by the same patterning process. The shape of the first electrode plate and the second electrode plate and the structure of the corresponding connecting electrode can be changed according to actual needs, and the present disclosure is not limited here.

[0194] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0195] The exemplary embodiment of the present disclosure provides a method for preparing a display substrate to manufacture the display substrate of the above exemplary embodiment. In the exemplary embodiment, the display substrate may include a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit includes a plurality of transistors, at least one transistor includes an active layer and two gate electrodes; the preparation method includes:

[0196] A semiconductor layer and a plurality of conductive layers are formed on the substrate and arranged on a side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and an orthographic projection of the electrode plate on the substrate overlaps with an orthographic projection of an active layer located between the two gate electrodes on the substrate.

[0197] In an exemplary embodiment, forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate may include:

[0198] forming a semiconductor layer on the substrate;

[0199] A first conductive layer, a second conductive layer and a third conductive layer are sequentially formed on the semiconductor layer, and the electrode plate is on the first conductive layer, the second conductive layer or the third conductive layer.

[0200] In an exemplary embodiment, a first power line connected to the pixel driving circuit is disposed on at least one conductive layer, and at least one electrode plate is connected to the first power line.

[0201] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0202] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present invention. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

1. A display substrate, comprising a substrate and a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit comprising a plurality of transistors, at least one transistor comprising an active layer and two gate electrodes; a semiconductor layer and a plurality of conductive layers arranged on a side of the semiconductor layer away from the substrate are arranged on the substrate, at least one conductive layer is provided with at least one electrode plate, and an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer located between the two gate electrodes on the substrate have an overlapping area; in, The plurality of transistors include at least a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; A first electrode of the first transistor is connected to the data signal line, and a second electrode of the first transistor is connected to the third node; A first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the fourth node; The gate electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the first power line, and the second electrode of the third transistor is connected to the fourth node; A first electrode of the fourth transistor is connected to the initial signal line, and a second electrode of the fourth transistor is connected to the first node; A first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the second node; The pixel driving circuit further includes a storage capacitor and a threshold capacitor, the storage capacitor includes a storage capacitor first plate and a storage capacitor second plate, and the threshold capacitor includes a threshold capacitor first plate and a threshold capacitor second plate; The first plate of the storage capacitor is connected to the third node, and the second plate of the storage capacitor is connected to the second node; the first plate of the threshold capacitor is connected to the first node, and the second plate of the threshold capacitor is connected to the second node.

2. The display substrate according to claim 1, wherein: The multiple conductive layers include a first conductive layer, a second conductive layer and a third conductive layer which are sequentially arranged on a side of the semiconductor layer away from the substrate, and the electrode plate is arranged on the first conductive layer, the second conductive layer or the third conductive layer.

3. The display substrate according to claim 2, wherein: The display substrate further includes a first power line connected to the pixel driving circuit, and at least one electrode plate is connected to the first power line.

4. The display substrate according to claim 2, wherein: The first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are arranged on the first conductive layer, the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are arranged at intervals, and the first electrode plate of the storage capacitor does not overlap with the semiconductor layer.

5. The display substrate according to claim 2, wherein: The second plate of the storage capacitor and the second plate of the threshold capacitor are arranged on the second conductive layer, the second plate of the storage capacitor and the second plate of the threshold capacitor are connected to each other, the orthographic projection of the second plate of the storage capacitor on the substrate and the orthographic projection of the first plate of the storage capacitor on the substrate have an overlapping area, and the orthographic projection of the second plate of the threshold capacitor on the substrate and the orthographic projection of the first plate of the threshold capacitor on the substrate have an overlapping area.

6. The display substrate according to claim 2, wherein: The fifth transistor is a dual-gate transistor, and the fifth transistor at least includes a fifth active layer and two fifth gate electrodes; the electrode plate includes a first electrode plate, and an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the fifth active layer located between the two fifth gate electrodes on the substrate have an overlapping area.

7. The display substrate according to claim 6, wherein: The two fifth gate electrodes are arranged on the first conductive layer, the first electrode plate is arranged on the first conductive layer or the second conductive layer, the first power line is arranged on the third conductive layer, and the first power line is connected to the first electrode plate through a via.

8. The display substrate according to claim 7, wherein: The second conductive layer further includes a first power connection line, the first electrode plate is connected to the first power connection line, and the first power line is connected to the first power connection line through a via hole.

9. The display substrate according to claim 2, wherein: The second transistor is a dual-gate transistor, and the second transistor includes at least a second active layer and two second gate electrodes; the electrode plate includes a second electrode plate, and the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the second active layer located between the two second gate electrodes on the substrate have an overlapping area.

10. The display substrate according to claim 9, wherein: The two second gate electrodes are arranged on the first conductive layer, the second electrode plate is arranged on the first conductive layer or the second conductive layer, the third conductive layer is further provided with a first connecting electrode, and the first connecting electrode is connected to the second electrode plate through a via hole.

11. The display substrate according to claim 10, wherein: The first connecting electrode serves as the second electrode of the first transistor and is connected to the first electrode plate of the storage capacitor through a via hole.

12. The display substrate according to claim 10, wherein: The fourth transistor is a dual-gate transistor, and the fourth transistor at least includes a fourth active layer and two fourth gate electrodes; an orthographic projection of the first connecting electrode on the first power line and an orthographic projection of the fourth active layer located between the two fourth gate electrodes on the first power line have an overlapping area.

13. The display substrate according to claim 2, wherein: The third conductive layer is further provided with a second connecting electrode, which serves as the first electrode of the second transistor and the second electrode of the fourth transistor at the same time, and the second connecting electrode is connected to the first electrode plate of the threshold capacitor through a via hole.

14. The display substrate according to claim 2, wherein: The third conductive layer is also provided with a third connecting electrode, which serves as the first electrode of the fourth transistor. The third connecting electrode is connected to the initial signal line through a via hole, and there is an overlapping area between the orthographic projection of the third connecting electrode on the substrate and the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor on the substrate.

15. A display device, wherein: It comprises the display substrate as claimed in any one of claims 1 to 14.

16. A method for preparing a display substrate, the display substrate comprising a substrate and a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit comprising a plurality of transistors, at least one transistor comprising an active layer and two gate electrodes; the preparation method comprising: A semiconductor layer and a plurality of conductive layers are formed on the substrate, and are arranged on a side of the semiconductor layer away from the substrate, wherein at least one conductive layer is provided with at least one electrode plate, and an orthographic projection of the electrode plate on the substrate overlaps with an orthographic projection of an active layer located between the two gate electrodes on the substrate; Wherein, the plurality of transistors at least include a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; A first electrode of the first transistor is connected to the data signal line, and a second electrode of the first transistor is connected to the third node; A first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the fourth node; The gate electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the first power line, and the second electrode of the third transistor is connected to the fourth node; A first electrode of the fourth transistor is connected to the initial signal line, and a second electrode of the fourth transistor is connected to the first node; A first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the second node; The pixel driving circuit also includes a storage capacitor and a threshold capacitor, the storage capacitor includes a first storage capacitor plate and a second storage capacitor plate, the threshold capacitor includes a first threshold capacitor plate and a second threshold capacitor plate; the first storage capacitor plate is connected to the third node, and the second storage capacitor plate is connected to the second node; the first threshold capacitor plate is connected to the first node, and the second threshold capacitor plate is connected to the second node.

17. The method for preparing a display substrate according to claim 16, wherein: A semiconductor layer and a plurality of conductive layers are formed on the substrate and arranged on a side of the semiconductor layer away from the substrate, comprising: forming a semiconductor layer on the substrate; A first conductive layer, a second conductive layer and a third conductive layer are sequentially formed on the semiconductor layer, and the electrode plate is on the first conductive layer, the second conductive layer or the third conductive layer.

18. The method for preparing a display substrate according to claim 17, wherein: A first power line connected to the pixel driving circuit is disposed on at least one conductive layer, and at least one electrode plate is connected to the first power line.

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