Flash memory interleaving access method and device, electronic equipment and readable storage medium
By setting up an operation configuration group and a basic instruction queue in the solid-state drive controller chip, and using hardware arbitration to quickly respond to user commands, the problem of long processing time in existing flash memory access schemes is solved, achieving more efficient data access.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN CITY TECHWIN SEMICONDUCTOR COMPANY LIMITED
- Filing Date
- 2022-07-14
- Publication Date
- 2026-06-02
Smart Images
Figure CN115309326B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage technology, and in particular to a flash memory interleaved access method, apparatus, electronic device, and readable storage medium. Background Technology
[0002] When a solid-state drive (SSD) controller chip operates on a certain logical unit, it sends relevant instructions to the corresponding logical unit number (LUN). Some instructions may prevent the logical unit from accepting new instructions during operation, at which point the logical unit is in a waiting state.
[0003] When a corresponding logic unit is in a waiting state, the solid-state drive (SSD) controller chip switches to the next logic unit to perform instruction operations. The controller chip sequentially reads the status of each LUN in the SSD according to a polling order. After the controller chip reads a LUN that meets the operation requirements, it inputs the operation instruction for the LUN into the message queue and performs the operation processing on the LUN according to the operation instruction.
[0004] Existing flash memory access schemes are time-consuming and have low time utilization when executing multiple operation instructions. Therefore, there is an urgent need for a flash memory access scheme that is easy to operate and faster. Summary of the Invention
[0005] To address the aforementioned technical problems, this application provides a flash memory interleaved access method, apparatus, electronic device, and computer-readable storage medium, the specific solutions of which are as follows:
[0006] In a first aspect, embodiments of this application provide a flash memory interleaving access method applied to a solid-state drive controller chip, the flash memory interleaving access method comprising:
[0007] Search for the target instruction queue among multiple basic instruction queues according to the instruction queue order. The target instruction queue is a basic instruction queue containing preset operation instructions.
[0008] The target logic unit is determined according to the operation configuration group associated with the target instruction queue, wherein the operation configuration group includes the corresponding enable signal pin number and logic unit number;
[0009] Determine whether the state of the target logic unit meets the preset operating conditions;
[0010] If the state of the target logic unit meets the preset operation conditions, the preset operation instruction is executed in the target logic unit;
[0011] If the state of the target logic unit does not meet the preset operation conditions, the process jumps to the step of searching for the target instruction queue in multiple instruction queues according to the order of the instruction queues.
[0012] According to a specific embodiment of this application, the step of searching for the target instruction queue among multiple basic instruction queues according to a preset instruction queue order includes:
[0013] Arbitrate multiple basic instruction queues sequentially according to the instruction queue order, wherein each basic instruction queue is associated with an operation configuration group;
[0014] If the preset operation instruction exists in any basic instruction queue, the basic instruction queue is determined as the target instruction queue.
[0015] According to one specific implementation of the embodiments of this application, the operation configuration groups associated with each basic instruction queue are different.
[0016] According to a specific embodiment of this application, the flash memory interleaving method further includes:
[0017] If the preset operation instruction is not present in any of the basic instruction queues, after arbitrating all basic instruction queues, starting from the first basic instruction queue, multiple basic instruction queues are arbitrated sequentially according to the order of the instruction queues.
[0018] According to a specific embodiment of this application, before the step of searching the target instruction queue, the flash memory interleaved access method further includes:
[0019] Obtain the number of the operation configuration groups;
[0020] The storage space is divided into instruction queues based on the stated quantity, resulting in the same number of basic instruction queues.
[0021] According to a specific embodiment of this application, the solid-state drive controller chip includes a preset number of register groups, and the flash memory interleaved access method further includes:
[0022] A preset number of operation configuration groups are obtained based on the relevant parameters of the flash memory chips in the solid-state drive, wherein the relevant parameters include the enable signal pin number and the logic unit number;
[0023] Enter the corresponding operation configuration group in each register group.
[0024] According to a specific embodiment of this application, the flash memory interleaved access method further includes:
[0025] When executing the preset operation instruction, if a switching instruction is executed, the process jumps to the step of searching for the target instruction queue in multiple basic instruction queues according to the instruction queue order.
[0026] Secondly, embodiments of this application provide a flash memory interleaving access device applied to a solid-state drive controller chip, the flash memory interleaving access device comprising:
[0027] The search module is used to search for a target instruction queue in multiple basic instruction queues according to the instruction queue order. The target instruction queue is a basic instruction queue containing preset operation instructions.
[0028] The determination module is used to determine the target logic unit based on the operation configuration group associated with the target instruction queue, wherein the operation configuration group includes the corresponding enable signal pin number and logic unit number;
[0029] The judgment module is used to determine whether the state of the target logic unit meets the preset operation conditions;
[0030] The first execution module is configured to execute the preset operation instruction in the target logic unit if the state of the target logic unit meets the preset operation conditions.
[0031] The second execution module is used to jump to the step of searching for the target instruction queue in multiple instruction queues according to the order of the instruction queue if the state of the target logic unit does not meet the preset operation conditions.
[0032] Thirdly, embodiments of this application provide an electronic device, which includes a processor and a memory. The memory stores a computer program, and the computer program, when executed on the processor, performs the flash memory interleaving access method described in the first aspect and any embodiment of the first aspect.
[0033] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when run on a processor, executes the flash memory interleaving access method described in the first aspect and any embodiment of the first aspect.
[0034] This application provides a flash memory interleaved access method, apparatus, electronic device, and readable storage medium. The flash memory interleaved access method includes: searching for a target instruction queue in multiple basic instruction queues according to the instruction queue order; determining a target logical unit based on an operation configuration group associated with the target instruction queue; determining whether the state of the target logical unit meets preset operation conditions; if the state of the target logical unit meets the preset operation conditions, executing the preset operation instruction in the target logical unit; if the state of the target logical unit does not meet the preset operation conditions, jumping to the step of searching for the target instruction queue in multiple instruction queues according to the instruction queue order. This application effectively improves the speed and efficiency of searching for and executing preset operation instructions by setting an operation configuration group on the solid-state drive controller chip. Attached Figure Description
[0035] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.
[0036] Figure 1 This illustration shows a flowchart of a flash memory interleaved access method provided in an embodiment of this application.
[0037] Figure 2 This illustration shows a schematic diagram of the solid-state drive controller chip used in an embodiment of the present application of a flash memory interleaved access method.
[0038] Figure 3 This illustration shows a schematic diagram of the step of "searching for the target instruction queue in multiple basic instruction queues according to the instruction queue order" in a flash memory interleaved access method provided in an embodiment of this application;
[0039] Figure 4 A schematic diagram illustrating the steps of executing preset operation instructions in a prior art flash memory access method is shown;
[0040] Figure 5 This illustration shows a schematic diagram of the steps in executing preset operation instructions in a flash memory interleaved access method provided in an embodiment of this application;
[0041] Figure 6 A schematic diagram of a device module of a flash memory interleaved access apparatus provided in an embodiment of this application is shown. Detailed Implementation
[0042] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0043] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0044] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.
[0045] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.
[0047] refer to Figure 1 This is a schematic flowchart of a flash memory interleaving access method provided in an embodiment of this application. The flash memory interleaving access method provided in this embodiment of the application is applied to a solid-state drive controller chip, such as... Figure 1 As shown, the flash memory interleaved access includes:
[0048] Step S101: Search for the target instruction queue in multiple basic instruction queues according to the instruction queue order. The target instruction queue is a basic instruction queue containing preset operation instructions.
[0049] Specifically, the flash memory interleaving access method provided in this embodiment is applied to a solid-state drive (SSD) controller chip. The SSD controller chip includes a preset number of hardware circuits or registers, all of which are used to implement the setting function of operation configuration groups.
[0050] The solid-state drive controller chip is connected to multiple flash memory chips. Each flash memory chip may contain multiple targets, and each target uses an enable signal pin CE to send and receive enable signals.
[0051] Specifically, each target contains multiple logical units, and each logical unit can independently execute preset operation instructions.
[0052] The solid-state drive controller chip can control the corresponding logic units to execute preset operation instructions by sending an enable signal.
[0053] In a specific embodiment, the operation configuration group includes a one-to-one corresponding enable signal pin CE and logic unit LUN.
[0054] According to a specific embodiment of this application, the solid-state drive controller chip includes a preset number of register groups, and the flash memory interleaved access method further includes:
[0055] A preset number of operation configuration groups are obtained based on the relevant parameters of the flash memory chips in the solid-state drive, wherein the relevant parameters include the enable signal pin number and the logic unit number;
[0056] Enter the corresponding operation configuration group in each register group.
[0057] In a specific embodiment, the solid-state drive controller chip in this embodiment includes a preset number of register groups, wherein the specific value of the preset number is determined according to the user's usage requirements.
[0058] Users can input the enable signal pin numbers and logic unit numbers of multiple flash memory chips connected to the solid-state drive controller chip into the corresponding register group according to the actual application requirements, so as to form the corresponding operation configuration group.
[0059] After completing the parameter configuration of the register group, multiple register groups with preset numbers will be obtained. The numbering can start from the 0th register group or the 1st register group. There is no restriction on the numbering of the first register group.
[0060] like Figure 2As shown, the solid-state drive controller chip can connect to m flash memory chips, where flash memory chip 0 has n logic units, flash memory chip 1 has x logic units, and flash memory chip m has y logic units.
[0061] The solid-state drive controller chip has h register groups. The number of m, n, x, y, and h can be set according to the actual application scenario, and m, n, x, y, and h are all positive integers.
[0062] like Figure 2 As shown, the operation configuration groups in register group 0 are CE1 and LUN0; the operation configuration groups in register group 1 are CE3 and LUN3; and the operation configuration groups in register group 2 are CE2 and LUN2.
[0063] It should be noted that the bit width of each operation configuration group can be determined based on the number of enable signal pins and logic units in the actual application scenario, and no specific limitation is made here.
[0064] According to a specific embodiment of this application, before the step of searching the target instruction queue, the flash memory interleaved access method further includes:
[0065] Obtain the number of the operation configuration groups;
[0066] The storage space is divided into instruction queues based on the stated quantity, resulting in the same number of basic instruction queues.
[0067] In a specific embodiment, after setting the parameters of the operation configuration group according to the user's usage requirements, the number of operation configuration groups can be obtained.
[0068] Specifically, the solid-state drive controller chip can also obtain the number of operation configuration groups by obtaining the number of register groups, which is not limited here.
[0069] After obtaining the number of operation configuration groups, the external storage space of the solid-state drive controller chip is divided to obtain instruction queues that are the same number as the number of operation configuration groups. For example, when the solid-state drive controller chip has h operation configuration groups, the external space is divided into h instruction queues.
[0070] In practical applications, an association is established between each instruction queue and an operation configuration group. For example, instruction queue 0 corresponds to operation configuration group 0 in the 0th register group, and instruction queue 1 corresponds to operation configuration group 1 in the 1st register group.
[0071] During application, when the solid-state drive controller chip is in working state, it continuously polls and arbitrates the instruction queue according to the preset order of the operation configuration group.
[0072] According to a specific embodiment of this application, the step of searching for the target instruction queue among multiple basic instruction queues according to a preset instruction queue order includes:
[0073] Arbitrate multiple basic instruction queues sequentially according to the instruction queue order, wherein each basic instruction queue is associated with an operation configuration group;
[0074] If the preset operation instruction exists in any basic instruction queue, the basic instruction queue is determined as the target instruction queue.
[0075] like Figure 3 As shown, solid black dots indicate that the instruction queue contains instructions to be executed, white dots indicate that the instruction queue does not contain instructions to be executed, and irregular circles represent the target instruction queue arbitrated.
[0076] In a specific embodiment, during the first arbitration, instruction queue 0 has the highest priority, followed by instruction queue 1, instruction queue 2, instruction queue 3, and instruction queue 4 in that order. The target instruction queue obtained in the first arbitration process is instruction queue 0.
[0077] During the second arbitration, the priority order becomes 1, 2, 3, 4, 0. Queue instruction 1 contains instructions to be executed; therefore, the target instruction queue obtained from the second arbitration process is instruction queue 1.
[0078] The specific implementation process of the third to fifth arbitrations was consistent with that of the second arbitration.
[0079] During the 6th arbitration, the priority order is reset to 0, 1, 2, 3, 4. Therefore, the target instruction queue obtained from the 6th arbitration process becomes instruction queue 0 again.
[0080] During the 7th to 10th arbitrations, instruction queue 0 did not contain any instructions to be executed during the 7th arbitration; instruction queue 0 and instruction queue 2 did not contain any instructions to be executed during the 9th arbitration; and instruction queue 0, instruction queue 2, and instruction queue 3 did not contain any instructions to be executed during the 10th arbitration.
[0081] During the 11th arbitration, the priority order becomes 0, 1, 2, 3, 4. However, there are no instructions to be executed in instruction queue 0. Therefore, the target instruction queue obtained in the 11th arbitration process is instruction queue 1.
[0082] During the 12th arbitration, the priority order becomes 1, 2, 3, 4, 0. However, there are no instructions to be executed in instruction queues 1, 2, and 3. Therefore, the target instruction queue obtained from the 12th arbitration process is instruction queue 4.
[0083] This application's embodiments, through the aforementioned polling arbitration method, can quickly respond to operation commands pre-entered by the user in the basic command queue. The flash memory interleaved access method proposed in this application does not require cyclically reading the state of each logical unit during each arbitration switch; instead, it determines the state of the target logical unit only when an operation command for that unit is confirmed.
[0084] It should be noted that when there is one data channel between the solid-state drive (SSD) controller chip and the flash memory chip, the SSD can only operate one logical unit at a time. When there are multiple data channels between the SSD controller chip and the flash memory chip, the SSD can operate multiple logical units simultaneously when needed.
[0085] When the solid-state drive controller chip operates multiple logic units, after selecting a target logic unit through polling, the solid-state drive controller chip immediately performs the next round of polling arbitration process to find multiple target logic units simultaneously.
[0086] Step S102: Determine the target logic unit according to the operation configuration group associated with the target instruction queue, wherein the operation configuration group includes the corresponding enable signal pin number and logic unit number;
[0087] In a specific embodiment, the solid-state drive controller chip polls and arbitrates all basic instruction queues during operation, and selects the corresponding target instruction queue in each arbitration process.
[0088] Each instruction queue has a pre-associated operation configuration group. Based on the contents of the operation configuration group, the solid-state drive controller chip can determine the corresponding target logic unit.
[0089] According to one specific implementation of the embodiments of this application, the operation configuration groups associated with each basic instruction queue are different.
[0090] In a specific embodiment, the contents of the operation configuration group associated with each basic instruction queue can be user-defined enable signal pin numbers and logic unit numbers.
[0091] During application, when the solid-state drive controller chip sets the operation configuration group through the register group, the combination of enable signal pin numbers and logic units in the operation configuration group can be customized and updated by the user.
[0092] When the solid-state drive controller chip sets the operation configuration group through hardware logic circuits, the enable signal pin numbers and logic unit numbers in the operation configuration group can only be arranged in a pre-set order and cannot be customized or updated.
[0093] Specifically, ensuring that the operation configuration groups associated with each basic instruction queue are different can effectively save the number of register group settings and hardware logic circuit settings, thereby achieving fast access to flash memory while controlling costs.
[0094] Step S103: Determine whether the state of the target logic unit meets the preset operation conditions;
[0095] In a specific embodiment, after the solid-state drive controller chip selects a logic unit through arbitration, it will first detect the working status of the logic unit.
[0096] After confirming the target logic unit, the solid-state drive controller chip automatically sends a read command to the target logic unit to read the status of the logic unit, and receives the status detection result returned by the target logic unit.
[0097] Specifically, the states of the logical unit include an executable state and a waiting state.
[0098] In practical applications, after a logic unit executes a preset operation instruction, the preset operation instruction may cause the logic unit to run continuously for a period of time, during which the logic unit will be in a waiting state.
[0099] A logic unit in a waiting state cannot receive new operation instructions. After the waiting state has lasted for a period of time, the logic unit will reset its state, restoring it to an executable state, at which point the logic unit can continue to receive and execute new operation instructions.
[0100] The duration of the waiting state can be adaptively set according to the actual application scenario, and is not limited here.
[0101] Step S104: If the state of the target logic unit meets the preset operation conditions, execute the preset operation instruction in the target logic unit;
[0102] In a specific embodiment, if the target logic unit is in an executable state, then a corresponding preset operation instruction is executed in the target logic unit.
[0103] According to a specific embodiment of this application, the flash memory interleaved access method further includes:
[0104] When executing the preset operation instruction, if a switching instruction is executed, the process jumps to the step of searching for the target instruction queue in multiple basic instruction queues according to the instruction queue order.
[0105] In a specific embodiment, if the preset operation instruction is a switching instruction during the process of the target logic unit processing the preset operation instruction, it means that it is necessary to switch to another logic unit to execute the instruction.
[0106] The solid-state drive controller chip will take the next set of operation configuration groups corresponding to the current target logic unit as the starting point, and continue to poll and arbitrate all basic instruction queues in the order of the instruction queues until the next target instruction queue is arbitrated.
[0107] Step S105: If the state of the target logic unit does not meet the preset operation conditions, jump to the step of searching for the target instruction queue in multiple instruction queues according to the instruction queue order.
[0108] Specifically, if the target logic unit is in a waiting state, the solid-state drive controller chip will take the next set of operation configuration groups corresponding to the current target logic unit as the starting point and continue to poll and arbitrate all basic instruction queues in the order of the instruction queues until the next target instruction queue is arbitrated.
[0109] It should be noted that when the target logic unit is in a waiting state for more than a preset time threshold, the solid-state drive controller chip will directly skip the target logic unit in the subsequent polling arbitration process until the target logic unit recovers to an executable state, and the target logic unit includes instructions to be executed.
[0110] According to a specific embodiment of this application, the flash memory interleaving method further includes:
[0111] If the preset operation instruction is not present in any of the basic instruction queues, after arbitrating all basic instruction queues, starting from the first basic instruction queue, multiple basic instruction queues are arbitrated sequentially according to the order of the instruction queues.
[0112] In a specific embodiment, when the solid-state drive controller chip is working, it cyclically polls and arbitrates all the pre-set basic instruction queues so that the solid-state drive controller chip can respond to the operation instructions input in each basic instruction queue in a timely manner.
[0113] Users can upload preset operation commands to the corresponding basic command queue by setting the operation configuration group order in real time, so as to control each logical unit in the solid-state drive.
[0114] like Figure 4As shown, common flash memory interleaved access schemes only include one instruction queue, and the instruction queue cannot be pre-filled with operation instructions. During each arbitration switch, the main control chip's software needs to sequentially send status read instructions to each logic unit. Only after a logic unit's status check is successful can the preset operation instruction for the corresponding logic unit be written into the instruction queue. Therefore, since each status read takes a considerable amount of time, the time utilization for accessing data in the flash memory is low.
[0115] like Figure 5 As shown in the embodiments of this application, the flash memory interleaved access method can upload corresponding preset operation instructions to each basic instruction queue in advance, so that the solid-state drive controller chip can quickly send the instructions to the corresponding logic unit through hardware arbitration, without having to perform operation instruction configuration actions to the instruction queue again through software, which effectively improves the speed and efficiency of flash memory data access.
[0116] refer to Figure 6 This is a schematic diagram of a flash memory interleaved access device 600 provided in an embodiment of this application. The flash memory interleaved access device 600 provided in this embodiment of the application is applied to a solid-state drive controller chip, such as... Figure 6 As shown, the flash memory interleaved access device 600 includes:
[0117] The search module 601 is used to search for a target instruction queue in multiple basic instruction queues according to the instruction queue order, wherein the target instruction queue is a basic instruction queue containing preset operation instructions.
[0118] The determining module 602 is used to determine the target logic unit according to the operation configuration group associated with the target instruction queue, wherein the operation configuration group includes the corresponding enable signal pin number and logic unit number;
[0119] The judgment module 603 is used to determine whether the state of the target logic unit meets the preset operation conditions;
[0120] The first execution module 604 is used to execute the preset operation instruction in the target logic unit if the state of the target logic unit meets the preset operation conditions.
[0121] The second execution module 605 is used to jump to the step of searching for the target instruction queue in multiple instruction queues according to the order of the instruction queue if the state of the target logic unit does not meet the preset operation conditions.
[0122] In addition, this application embodiment also provides an electronic device, which includes a processor and a memory, wherein the memory stores a computer program, and the computer program executes the flash memory interleaving access method in the foregoing embodiment when it is run on the processor.
[0123] This application provides a computer-readable storage medium storing a computer program, which executes the flash memory interleaving access method described in the foregoing embodiments when run on a processor.
[0124] In summary, the embodiments of this application provide a flash memory interleaved access method, apparatus, electronic device, and readable storage medium. By pre-setting operation configuration groups on the solid-state drive controller chip and dividing the external storage space into basic instruction queues with the same number as the operation configuration groups, operation instructions for target logic units can be pre-configured in each basic instruction queue. This effectively saves the time of the solid-state drive controller chip in detecting the logic unit status and configuring operation instructions, greatly accelerating the speed and efficiency of accessing data content in flash memory. Furthermore, the specific implementation process of the flash memory interleaved access apparatus, electronic device, and computer-readable storage medium mentioned in the above embodiments can be found in the specific implementation process of the above method embodiments, and will not be repeated here.
[0125] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0126] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0127] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0128] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for flash memory interleaved access, the method comprising: The flash memory interleaving access method, applied to solid-state drive controller chips, includes: According to the order of the instruction queue, the target instruction queue is searched among multiple basic instruction queues, and the target instruction queue is a basic instruction queue containing preset operation instructions; The target logic unit is determined according to the operation configuration group associated with the target instruction queue, wherein the operation configuration group includes the corresponding enable signal pin number and logic unit number; Determine whether the state of the target logic unit meets the preset operating conditions; If the state of the target logic unit meets the preset operation conditions, the preset operation instruction is executed in the target logic unit; If the state of the target logic unit does not meet the preset operation conditions, the process jumps to the step of searching for the target instruction queue in multiple instruction queues according to the order of the instruction queues. The solid-state drive controller chip includes a preset number of register groups. Before the step of searching the target instruction queue, the flash memory interleaved access method further includes: A preset number of operation configuration groups are obtained based on the relevant parameters of the flash memory chips in the solid-state drive, wherein the relevant parameters include the enable signal pin number and the logic unit number; Enter the corresponding operation configuration group in each of the aforementioned register groups; Obtain the number of the operation configuration groups; The storage space is divided into instruction queues according to the quantity, resulting in the same number of basic instruction queues. Establish the association between each of the basic instruction queues and one of the operation configuration groups.
2. The flash memory interleaving access method of claim 1, wherein, The step of searching for the target instruction queue among multiple basic instruction queues according to a preset instruction queue order includes: Arbitrate multiple basic instruction queues sequentially according to the instruction queue order, wherein each basic instruction queue is associated with an operation configuration group; If the preset operation instruction exists in any basic instruction queue, the basic instruction queue is determined as the target instruction queue.
3. The flash memory interleaving access method according to claim 2, characterized in that, The operation configuration groups associated with each basic instruction queue are different.
4. The flash memory interleaved access method according to claim 2, characterized in that, The flash memory interleaved access method further includes: If the preset operation instruction is not present in any of the basic instruction queues, after arbitrating all basic instruction queues, starting from the first basic instruction queue, multiple basic instruction queues are arbitrated sequentially according to the order of the instruction queues.
5. The flash memory interleaved access method according to claim 1, characterized in that, The flash memory interleaved access method further includes: When executing the preset operation instruction, if a switching instruction is executed, the process jumps to the step of searching for the target instruction queue in multiple basic instruction queues according to the instruction queue order.
6. A flash memory interleaving access device, characterized by, The flash memory interleaving access device, applied to solid-state drive controller chips, includes: The search module is used to search for a target instruction queue among multiple basic instruction queues according to the instruction queue order. The target instruction queue is a basic instruction queue containing preset operation instructions. The determination module is used to determine the target logic unit according to the operation configuration group associated with the target instruction queue, wherein the operation configuration group includes the corresponding enable signal pin number and logic unit number; The judgment module is used to determine whether the state of the target logic unit meets the preset operation conditions; The first execution module is configured to execute the preset operation instruction in the target logic unit if the state of the target logic unit meets the preset operation conditions. The second execution module is used to jump to execute the step of searching for the target instruction queue in multiple instruction queues according to the order of the instruction queue if the state of the target logic unit does not meet the preset operation conditions. The solid-state drive controller chip includes a preset number of register groups. Before the step of searching the target instruction queue, the flash memory interleaved access method further includes: A preset number of operation configuration groups are obtained based on the relevant parameters of the flash memory chips in the solid-state drive, wherein the relevant parameters include the enable signal pin number and the logic unit number; Enter the corresponding operation configuration group in each of the aforementioned register groups; Obtain the number of the operation configuration groups; The storage space is divided into instruction queues according to the quantity, resulting in the same number of basic instruction queues. Establish the association between each of the basic instruction queues and one of the operation configuration groups.
7. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing a computer program that, when executed on the processor, performs the flash memory interleaving access method according to any one of claims 1 to 5.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed on a processor, performs the flash memory interleaving access method according to any one of claims 1 to 5.