An automatic simulation verification method for Block_RAM test cases

Abstract

The application discloses an automatic simulation verification method of a Block_RAM test case, and relates to the technical field of FPGA.The method analyzes an RTL level description file of the Block_RAM test case, extracts information of the types of input and output signals, signal parameters and the like, and further identifies data signals, address signals, clock signals and control signals to establish a signal dictionary.According to the signal dictionary, the construction of a test platform can be automatically completed, and according to the characteristics of various signals, control signals matched with working modes and random assignment modes of input signals can be automatically generated, so that the test under the current working mode can be quickly completed, and then the full coverage test of various working modes of the Block_RAM can be quickly completed, which is beneficial to guaranteeing the correctness of FPGA design.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA technology, and particularly relates to a method for automatically simulating and verifying a Block_RAM test case. BACKGROUND

[0002] With the rapid development of semiconductor technology, FPGA chips not only have a leap in capacity, but also have diversified on-chip resources. Among them, on-chip Block RAM has become an essential resource on the FPGA chip.

[0003] On-chip Block RAM can allow users to set up a variety of different architectures and a variety of different modes. For example, each Block RAM unit can be set to a single port, a double port, and the double port can be divided into a simple double port and a true double port. The read-write mode can be set to a "read priority mode", a "write priority mode", and a "hold mode". According to the different storage capacities required by FPGA design, a single Block RAM unit or multiple Block RAM units can be included in the FPGA chip and implemented in the form of cascading, parallel connection, and segmentation.

[0004] Due to the complexity of Block RAM, ensuring the correctness of Block RAM design becomes a prerequisite for ensuring the correctness of FPGA design and a quality that must be possessed by an FPGA design platform. However, due to the complexity of Block RAM, it is often difficult to simulate and verify the correctness of Block RAM design. SUMMARY

[0005] The present application relates to the field of FPGA technology, and particularly relates to a method for automatically simulating and verifying a Block_RAM test case.

[0006] The present application relates to the field of FPGA technology, and particularly relates to a method for automatically simulating and verifying a Block_RAM test case.

[0007] The description statements in the RTL level description file of the Block_RAM test case are parsed to obtain a signal dictionary, the signal dictionary includes all the parsed signals, the parsed signals are classified according to the transmission direction type to include at least one of an input signal, an output signal and an input-output signal, and the input signal is classified according to the signal quantity type to include a clock signal, an address signal, a control signal and a data signal;

[0008] The variable types of the signals are defined according to the transmission direction types of the signals;

[0009] According to the signal dictionary, a port corresponding to each signal obtained by analysis is generated, a clock signal is input into the corresponding port, a signal waveform corresponding to a working mode of the Block_RAM is generated, a control signal is input into the corresponding port, and in the reading and writing process of the control signal, the address signal and the data signal are non-blockingly assigned at each clock edge of the clock signal and input into the corresponding port, so that a test platform is constructed;

[0010] The test platform is used to complete simulation verification of the Block_RAM test case.

[0011] Further, the method for generating the clock signal comprises:

[0012] If the clock signal declared and defined in the signal dictionary is included, the clock signal in the signal dictionary is directly input into the corresponding port;

[0013] If the clock signal declared and defined in the signal dictionary is not included, a new clock signal is defined and input into the corresponding port.

[0014] Further, the non-blockingly assigning the address signal and the data signal comprises:

[0015] For any one to-be-assigned signal in the address signal and the data signal, values in the input file corresponding to the to-be-assigned signal are sequentially assigned to the corresponding to-be-assigned signal;

[0016] The number of values included in the input file of each to-be-assigned signal is equal to the array bit width of the to-be-assigned signal; and the same values included in the input files of the two to-be-assigned signals associated with the signal reach a predetermined proportion, and the same values are randomly distributed in the input files.

[0017] Further, when the two to-be-assigned signals are both address signals and read and write the same RAM array, it is determined that the two to-be-assigned signals are associated with the signal.

[0018] Further, the signal dictionary is obtained by analyzing the description statement in the RTL-level description file of the Block_RAM test case, comprising:

[0019] The description statement in the RTL-level description file is traversed and compared, when the comparison is consistent and both are input, the colon in the description statement is split to obtain the bit width of the signal; the variable name set is processed, and the variable names of multiple signals are split to obtain the variable names of the signals, the variable names of the signals and the bit widths are stored in the signal dictionary in correspondence, and the transmission direction of the signal is determined to be classified as an input signal;

[0020] And / or, the description statement in the RTL level description file is traversed and compared, and when the comparison is consistent and all are output, the colon in the description statement is split to obtain the bit width of the signal; a variable name set is processed, and the variable name of multiple signals is split to obtain the variable name of multiple signals, the variable name of the signal and the bit width are stored in the signal dictionary, and the transmission direction type of the signal is determined to be an output signal;

[0021] And / or, the description statement in the RTL level description file is traversed and compared, and when the comparison is consistent and all are inout, the colon in the description statement is split to obtain the bit width of the signal; a variable name set is processed, and the variable name of multiple signals is split to obtain the variable name of multiple signals, the variable name of the signal and the bit width are stored in the signal dictionary, and the transmission direction type of the signal is determined to be an input / output signal.

[0022] A further technical solution thereof is that the method further comprises:

[0023] The description statement in the RTL level description file is traversed, the description statement containing the parameter keyword is searched, and the description statement is split with a comma as a delimiter to obtain multiple parameter definitions to construct a parameter dictionary, and each parameter definition contains a parameter name and a corresponding parameter value of the parameter name;

[0024] Therefore, when the colon in the description statement is split to obtain the bit width of the signal, if the colon in the description statement is split to obtain a number, the bit width is directly obtained from the number; if the colon in the description statement is split to obtain a string, the bit width is obtained from the parameter value corresponding to the parameter name represented by the string in the parameter dictionary.

[0025] A further technical solution thereof is that the variable type of each signal is defined according to the transmission direction type of each signal, including:

[0026] The variable type of all input signals is defined as reg, and the variable type of all output signals and input / output signals is defined as wire.

[0027] A further technical solution thereof is that the control signal corresponding to the working mode of the signal waveform and the Block_RAM is generated, including:

[0028] The value of the control signal of the read operation and the control signal of the write operation is set according to the port mode of the Block_RAM in sequence, the Block_RAM is controlled to perform the read operation and / or the write operation, and the sequence of the read operation and / or the write operation performed by the Block_RAM corresponds to the read / write mode of the Block_RAM.

[0029] A further technical solution thereof is that when the read / write mode of the Block_RAM is a read priority mode, the sequence of the read operation and / or the write operation is:

[0030] all control signals are false, after a predetermined time, the control signal of the read operation is set to true, and the read operation is started; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to true; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to false; after a predetermined time, the control signal of the write operation is kept false, and the control signal of the read operation is set to false, and the process is ended after a predetermined time.

[0031] A further technical solution is that the process of setting values of the control signal of the read operation and the control signal of the write operation according to the port mode of the Block_RAM comprises:

[0032] When the port mode of the Block_RAM is the single-port mode, the simple dual-port mode and the true dual-port mode: all control signals are set to 0, after a predetermined time, the control signal of the read operation is set to 1, and the read operation is started; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 1; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 0; after a predetermined time, the control signal of the write operation is kept false, and the control signal of the read operation is set to 0, and the process is ended after a predetermined time;

[0033] When the port mode of the Block_RAM is the true dual-port mode supporting the BWE function, all control signals are set to 0, after a predetermined time, the control signal of the read operation is set to 1, and the read operation is started; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 1; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 3; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 7; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 15; after a predetermined time, the control signal of the read operation is kept true, and the control signal of the write operation is set to 0; after a predetermined time, the control signal of the write operation is kept false, and the control signal of the read operation is set to 0, and the process is ended after a predetermined time.

[0034] A further technical solution is that when the read-write mode of the Block_RAM is the write-priority mode, the order of the read operation and / or the write operation is:

[0035] all control signals are false, after a predetermined time, all control signals are true for read operation and write operation; after a predetermined time, the control signal of read operation is true, the control signal of write operation is false; after a predetermined time, the control signal of read operation is true, the control signal of write operation is true; after a predetermined time, the control signal of read operation is true, the control signal of write operation is false; after a predetermined time, the control signal of write operation is false, the control signal of read operation is false, and the process is ended after a predetermined time.

[0036] The further technical solution is that the process of setting values of the control signal of read operation and the control signal of write operation according to the port mode of Block_RAM in turn comprises:

[0037] When the port mode of Block_RAM is single-port mode, simple double-port mode and true double-port mode: all control signals are 0, after a predetermined time, all control signals are 1 for read operation and write operation; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 0; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 1; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 0; after a predetermined time, the control signal of write operation is 0, the control signal of read operation is 0, and the process is ended after a predetermined time;

[0038] When the port mode of Block_RAM is true double-port mode supporting BWE function, all control signals are 0, after a predetermined time, all control signals are 1 for read operation and write operation; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 0; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 1; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 3; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 7; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 15; after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 0; after a predetermined time, the control signal of write operation is 0, the control signal of read operation is 0, and the process is ended after a predetermined time.

[0039] The further technical solution is that when the read-write mode of Block_RAM is the holding mode, the order of read operation and / or write operation is:

[0040] All control signals are false, after a predetermined time, all control signals are true to read and write operation, after a predetermined time, the control signal of read operation is true, the control signal of write operation is false, after a predetermined time, the control signal of write operation is false, the control signal of read operation is false, and the process is ended after a predetermined time.

[0041] Further technical solutions are as follows:

[0042] When the port mode of Block_RAM is single port mode, simple double port mode and true double port mode, all control signals are 0, after a predetermined time, all control signals are 1 to read and write operation, after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 0, after a predetermined time, the control signal of write operation is 0, the control signal of read operation is 0, and the process is ended after a predetermined time;

[0043] When the port mode of Block_RAM is true double port mode supporting BWE function, all control signals are 0, after a predetermined time, all control signals are 1, after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 3, after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 7, after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 15, after a predetermined time, the control signal of read operation is 1, the control signal of write operation is 0, after a predetermined time, the control signal of write operation is 0, the control signal of read operation is 0, and the process is ended after a predetermined time.

[0044] The beneficial technical effects of the application are as follows:

[0045] The application discloses an automatic simulation verification method of Block_RAM test cases, which comprises the following steps: analyzing an RTL level description file of Block_RAM test cases, extracting information of types and signal parameters of input and output signals, and identifying data signals, address signals, clock signals and control signals to establish a signal dictionary. According to the analysis of Block_RAM ports, the test platform is constructed by automatically instantiating the test cases to be tested, and the control signals matched with the working mode and the random assignment mode of the input signals are automatically generated according to the characteristics of various signals, so that the test of Block_RAM under the current working mode can be quickly completed, and then the full coverage test of various working modes of Block_RAM can be quickly completed, which is beneficial to guarantee the correctness of FPGA design. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 is a method flow chart of the automatic simulation verification method in one embodiment of the present application. DETAILED DESCRIPTION

[0047] The specific embodiments of the present application will be further described below with reference to the accompanying drawings.

[0048] The present application discloses an automatic simulation verification method for Block_RAM test cases, which comprises the following steps, please refer to Figure 1 :

[0049] I. Parsing the RTL level description file of Block_RAM test cases

[0050] The description statements in the RTL level description file of Block_RAM test cases are parsed to obtain a signal dictionary, which includes all the signals parsed.

[0051] The parsed signals are classified into at least one of input signal input, output signal output and input / output signal inout according to the transmission direction type, and the inout signal refers to bidirectional transmission signal. The input signal input can be further classified into the following categories according to the signal quantity type: clock signal, address signal, control signal and data signal.

[0052] The signal dictionary parsed includes the signal parameters of each signal, and the signal parameters include the variable name, bit width and signal type of the signal, and the signal type indicates the transmission direction type of the signal.

[0053] In one embodiment, the method for parsing the RTL level description file to obtain the signal dictionary comprises the following steps, taking the method for parsing the input signal input as an example:

[0054] 1. The description statements in the RTL level description file are traversed and compared, the spaces before and after the description statements are removed, and then the start string is compared. When the comparison is consistent with "input", the parsing starts. First, define a variable row_bitWidth to store the bit width, and the default value is 0. The colon in the description statement is divided to obtain the bit width of the signal and assign it to the variable row_bitWidth.

[0055] 2、Processing the variable name set, after comparing with non-keywords, the variable name of the signal is obtained by cutting, and the variable name and bit width of the signal are stored in the signal dictionary after removing the spaces before and after the variable name, and the transmission direction type of the signal is determined to be an input signal. The signal quantity type of the signal can be identified and determined through the variable name of the signal, wherein the variable name of the clock signal contains the clk string, the address signal contains the addr string, and the control signal contains the en or we string, wherein the control signal containing en represents the control signal of the read operation, and the control signal containing we represents the control signal of the write operation. If the variable name does not contain any special string, the signal represented by the variable name is a data signal.

[0056] Similarly, the method for parsing the output signal output is: traversing and comparing the description statements in the RTL level description file, when the comparison is consistent and both are output, the bit width of the signal is obtained by cutting the colon in the description statement; processing the variable name set, cutting to obtain the variable names of multiple signals, storing the variable names and bit widths of the signals in the signal dictionary, and determining the transmission direction type of the signal to be an output signal.

[0057] The method for parsing the input / output signal inout is: traversing and comparing the description statements in the RTL level description file, when the comparison is consistent and both are inout, the bit width of the signal is obtained by cutting the colon in the description statement; processing the variable name set, cutting to obtain the variable names of multiple signals, storing the variable names and bit widths of the signals in the signal dictionary, and determining the transmission direction type of the signal to be an input / output signal.

[0058] The method for parsing output and inout is similar to the method for parsing input, and the specific details will not be described again. No matter which signal is parsed, the form a:b is generally obtained when the colon in the description statement of the signal is cut. According to the general definition of bit width, the colon in the description statement is generally cut to the form a:0, indicating that the signal occupies the 0th to a th bit, and the bit width is a+1. There are two cases to obtain the bit width of the signal:

[0059] (1) After cutting the colon in the description statement, a before the colon is a number, then the bit width of the signal is directly obtained from the number, and the specific bit width is a+1.

[0060] (2) In the RTL level description file, parameter is often used to define constants that remain unchanged during simulation to improve the readability of the program. In the description statement, the parameters defined in the parameter are used to represent the corresponding constants. When the colon in the description statement is cut, a obtained is not a number but a string, and the string related to a is defined in the parameter in advance.

[0061] For example, in one instance, part of the RTL level description file is as follows: module Block_RAM_5_12_32#(parameter ADDR_WIDTH=12, DATA_WIDTH=32) (input [ADDR_WIDTH-1:0] addra). When the colon in the description statement is split during parsing, the a before the colon is not a number, but a string represented by ADDR_WIDTH-1, and it can be seen that the string ADDR_WIDTH is defined in the parameter part.

[0062] Therefore, in order to adapt to this situation, a parameter dictionary needs to be established in advance, which is generally established before the signal is parsed, including the following steps: traversing the description statements in the RTL level description file, searching for the description statements containing the parameter keyword, removing the comments and spaces before and after, and splitting with the comma as the separator to obtain multiple parameter definitions to construct the parameter dictionary, each parameter definition containing the parameter name and the corresponding parameter value. Specifically, after splitting to obtain multiple parameter definitions, the parameter definitions are split with the equal sign as the separator to obtain the parameter name and the corresponding parameter value field, the parameter name is removed from the spaces before and after and symbols, and then the operators in the parameter value field are parsed, and the final parameter value is obtained by calculating the result according to the operator.

[0063] When the colon in the description statement of the signal is split, the bit width of the signal is obtained from the parameter dictionary according to the parameter value corresponding to the parameter name represented by the string before the colon, specifically, the parameter value corresponding to the parameter name represented by the string is substituted into a, the value of a is calculated, and a+1 is taken as the bit width. For example, in the above example, the parameter value of ADDR_WIDTH is defined as 12 in advance, then a is calculated as 11, and it is determined that the bit width of the signal with the variable name addra is 12.

[0064] In one embodiment, before parsing the signal, the main module range is selected first, a main_module_name variable is defined first, with the value of the file name, and a flag bit main_module_flag is defined, with the default value of false. Then all the description statements in the source file are processed, and the description statement containing the "module" string and not "endmodule" is found, and the module name of the description statement is obtained by splitting the description statement. If the module name is equal to the main_module_name, the flag bit main_module_flag is set to true. If the module name is not equal to the main_module_name, the flag bit main_module_flag is set to false. If the "endmodule" string is found in the description statement, the flag bit main_module_flag is set to false. Then, no matter which signal is parsed, when the starting string is "input" or "output" or "inout", the flag bit main_module_flag is checked. When the flag bit main_module_flag is true, the signal is parsed according to the method provided above. When the flag bit main_module_flag is false due to endmodule or other submodules, the signal is not parsed.

[0065] For example, in one instance, assume that the RTL level description file is as follows:

[0066]

[0067]

[0068] In this instance, the description statement containing the parameter keyword is searched first, and the parameter dictionary param_dict = { "ADDR_WIDTH": 12, "DATA_WIDTH": 32} is obtained. The input and output signals in the main module are parsed, and in this instance, there is only one module without other submodules, so all the input and output signals are parsed, and the flag bit main_module_flag is written as true.

[0069] The input, output and inout are parsed to obtain a signal dictionary d = {"input": [["clka", "clkb"], ["ena", "enb", "wea"], ["addra", "addrb"], ["dia"]], "input_bitWidth": [[1, 1], [1, 1, 1], [12, 12],

[32] ], "output": ["dob"], "output_bitWidth":

[32] , "inout": [], "inout_bitWidth": []}. The signal parameters of the signals contained in the signal dictionary can be represented in the following table:

[0070]

[0071]

[0072] As can be seen, the signal dictionary obtained by general parsing at least contains input signals and output signals, and optionally contains input and output signals.

[0073] II. Constructing a test platform

[0074] In step S1, the variable types of the signals are defined according to the transmission direction types of the signals. Specifically, the variable types of all input signals input are defined as reg, and the variable types of all output signals output and input and output signals inout are defined as wire. Then, an extra array of a predetermined size is defined for the signals that need to be randomly assigned in all input signals, such as a 512-size array. The signals that need to be randomly assigned generally include address signals and data signals.

[0075] In step S2, the main module is instantiated, ports corresponding to each signal obtained by parsing are generated according to the signal dictionary, and each signal is connected to the corresponding signal. For example, in the above example, two clock ports are generated to connect two clock signals clka and clkb, and other similar operations are performed.

[0076] In step S3, the clock signals are input to the corresponding ports. There are two cases for the clock signals:

[0077] (1) If the clock signal declared and defined in the signal dictionary is contained, the clock signal in the signal dictionary is directly input to the corresponding port.

[0078] (2) If the clock signal declared and defined in the signal dictionary is not contained, a new clock signal is defined and input to the corresponding port.

[0079] Step S4, generate control signals corresponding to the working mode of Block_RAM and input corresponding ports. In the process of reading and writing control signals, the address signal and the data signal are non-blockingly assigned at each clock edge of the clock signal and input corresponding ports. In the process of non-blockingly assigning, the array of the predetermined size defined in step S1 is generally used.

[0080] The working mode of Block_RAM is generally pre-configured by the user because the difference between different working modes of Block_RAM is generally small and it is difficult to accurately determine the working mode of Block_RAM to be tested by analyzing the RTL description file. The working mode of Block_RAM includes the port mode and the read-write mode of Block_RAM. The port mode mainly includes four types: single-port mode, simple dual-port mode, normal true dual-port mode, and true dual-port mode supporting BWE function. The read-write mode includes three types: read-priority mode, write-priority mode, and hold mode.

[0081] In the process of generating control signals corresponding to the working mode of Block_RAM, the values of the control signals for read operation and the control signals for write operation are set according to the port mode of Block_RAM, the Block_RAM performs read operation and / or write operation, and the sequence of performing read operation and / or write operation by Block_RAM corresponds to the read-write mode of Block_RAM.

[0082] According to the different read-write modes of Block_RAM, the sequence of generating control signals to make Block_RAM perform read operation and / or write operation is introduced as follows:

[0083] (1) When the read-write mode of Block_RAM is read-priority mode. The sequence of generating control signals to make Block_RAM perform read operation and / or write operation is as follows:

[0084] First, control all control signals to be false, after a predetermined time, set the control signal for read operation to be true, non-blockingly assign the address signal and the data signal to start read operation. After a predetermined time, keep the control signal for read operation to be true, set the control signal for write operation to be true, and then non-blockingly assign the address signal and the data signal. After a predetermined time, keep the control signal for read operation to be true, set the control signal for write operation to be false, and then non-blockingly assign the address signal and the data signal. After a predetermined time, keep the control signal for write operation to be false, set the control signal for read operation to be false to stop read and write. After a predetermined time, end the process.

[0085] On the basis of ensuring Block_RAM to execute read and write operations in the above-mentioned order, when the port mode of Block_RAM is different, the method for generating control signals is as follows:

[0086] (1a) When the port mode of Block_RAM is single-port mode, simple dual-port mode and true dual-port mode: first set all control signals to 0, after a predetermined time, set the control signal of read operation to 1, and non-blockingly assign address signal and data signal to start executing read operation. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 1, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 0, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of write operation as 0, set the control signal of read operation to 0 to stop read and write, and after a predetermined time, end the process.

[0087] (1b) When the port mode of Block_RAM is true dual-port mode supporting BWE function, keep the control signal of read operation as true, set the control signal of write operation to true, and the case containing multiple stages is as follows:

[0088] Set all control signals to 0, after a predetermined time, set the control signal of read operation to 1, and non-blockingly assign address signal and data signal to start executing read operation. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 1, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 3, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 7, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 15, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of read operation as 1, set the control signal of write operation to 0, and then non-blockingly assign address signal and data signal. After a predetermined time, keep the control signal of write operation as 0, set the control signal of read operation to 0 to stop read and write, and after a predetermined time, end the process.

[0089] (2) When the read and write mode of Block_RAM is write priority mode. The order of generating control signals to control Block_RAM to execute read operation and / or write operation is as follows:

[0090] The process starts by setting all control signals to false. After a predetermined time, all control signals are set to true, and non-blocking values ​​are assigned to the address and data signals for read and write operations. After another predetermined time, the read operation control signal remains true, the write operation control signal is set to false, and non-blocking values ​​are assigned to the address and data signals again. After another predetermined time, the read operation control signal remains true, the write operation control signal is set to true, and non-blocking values ​​are assigned to the address and data signals again. After another predetermined time, the read operation control signal remains true, the write operation control signal is set to false, and non-blocking values ​​are assigned to the address and data signals again. After another predetermined time, the write operation control signal remains false, the read operation control signal is set to false, read and write operations cease, and the process ends after another predetermined time.

[0091] Assuming that the Block_RAM performs read and write operations in the above order, the method for generating control signals when the Block_RAM port mode is different is as follows:

[0092] (2a) When the Block_RAM port mode is single-port mode, simple dual-port mode, or true dual-port mode: all control signals are set to 0. After a predetermined time, all control signals are set to 1, and non-blocking values ​​are assigned to the address and data signals for read and write operations. After a predetermined time, the control signal for read operations is kept at 1, the control signal for write operations is set to 0, and non-blocking values ​​are assigned to the address and data signals again. After a predetermined time, the control signal for read operations is kept at 1, the control signal for write operations is set to 1, and non-blocking values ​​are assigned to the address and data signals again. After a predetermined time, the control signal for read operations is kept at 1, the control signal for write operations is set to 0, and non-blocking values ​​are assigned to the address and data signals again. After a predetermined time, the control signal for write operations is kept at 0, the control signal for read operations is set to 0 to stop reading and writing, and the process ends after a predetermined time.

[0093] (2b) When the Block_RAM port mode is a true dual-port mode supporting BWE functionality, the situation of keeping the read operation control signal true and setting the write operation control signal true involves multiple stages, specifically:

[0094] All control signals are set to 0. After a predetermined time, all control signals are set to 1, and non-blocking values ​​are applied to the address and data signals for read and write operations. After another predetermined time, the read operation control signal is kept at 1, the write operation control signal is set to 0, and non-blocking values ​​are applied to the address and data signals again. After another predetermined time, the read operation control signal is kept at 1, the write operation control signal is set to 1, and non-blocking values ​​are applied to the address and data signals again. After another predetermined time, the read operation control signal is kept at 1, the write operation control signal is set to 3, and non-blocking values ​​are applied to the address and data signals again. After another predetermined time, the read operation control signal is kept at 1, the write operation control signal is set to 7, and non-blocking values ​​are applied to the address and data signals again. After another predetermined time, the read operation control signal is kept at 1, the write operation control signal is set to 15, and non-blocking values ​​are applied to the address and data signals again. After a predetermined timeout, the control signal for the read operation remains at 1, the control signal for the write operation is set to 0, and then non-blocking assignment is performed on the address and data signals. After another predetermined timeout, the control signal for the write operation remains at 0, the control signal for the read operation is set to 0, and reading and writing cease. The process ends after another predetermined timeout.

[0095] (3) When the Block_RAM read / write mode is hold mode, the order in which control signals are generated to control the Block_RAM to perform read and / or write operations is as follows:

[0096] The process starts by setting all control signals to false. After a predetermined time, all control signals are set to true, and non-blocking values ​​are assigned to the address and data signals for read and write operations. After another predetermined time, the read operation control signal is kept true, the write operation control signal is set false, and non-blocking values ​​are assigned to the address and data signals again. After yet another predetermined time, the write operation control signal is kept false, the read operation control signal is set false, and read and write operations cease. The process ends after another predetermined time.

[0097] Assuming that the Block_RAM performs read and write operations in the above order, the method for generating control signals when the Block_RAM port mode is different is as follows:

[0098] (3a) When the port mode of the Block_RAM is single-port mode, simple dual-port mode and true dual-port mode: set all control signals to 0, after a predetermined time duration, set all control signals to 1, non-block assignment of address signals and data signals, read operation and write operation. After a predetermined time duration, keep the control signal of the read operation as 1, set the control signal of the write operation as 0, and then non-block assignment of address signals and data signals. After a predetermined time duration, keep the control signal of the write operation as 0, set the control signal of the read operation as 0 to stop reading and writing, and end the process after a predetermined time duration.

[0099] (3b) When the port mode of the Block_RAM is true dual-port mode supporting BWE function, set all control signals to true, which includes multiple stages, and specifically:

[0100] set all control signals to 0, after a predetermined time duration, set all control signals to 1, non-block assignment of address signals and data signals. After a predetermined time duration, keep the control signal of the read operation as 1, set the control signal of the write operation as 3, and then non-block assignment of address signals and data signals. After a predetermined time duration, keep the control signal of the read operation as 1, set the control signal of the write operation as 7, and then non-block assignment of address signals and data signals. After a predetermined time duration, keep the control signal of the read operation as 1, set the control signal of the write operation as 15, and then non-block assignment of address signals and data signals. After a predetermined time duration, keep the control signal of the read operation as 1, set the control signal of the write operation as 0, and then non-block assignment of address signals and data signals. After a predetermined time duration, keep the control signal of the write operation as 0, set the control signal of the read operation as 0 to stop reading and writing, and end the process after a predetermined time duration.

[0101] Based on the above-described generation mode of the control signals, the control signals of the Block_RAM in different working modes can be summarized as shown in the following table. For single-port mode, the control signal of the read operation is en, and the control signal of the write operation is we. For simple dual-port mode, the control signal of the read operation includes ena and anb, and the control signal of the write operation is we. For normal true dual-port mode and true dual-port mode supporting BWE function, the control signal of the read operation includes ena and enb, and the control signal of the write operation includes wea and web.

[0102]

[0103]

[0104] It should be noted that the above description is explained by the change of each control bit of the control signal, when the bit width of the control signal is not 1 and contains multiple control bits, each control bit of the control signal is changed according to the method described above.

[0105] III. Simulation verification of Block_RAM test cases is completed by using the test platform.

[0106] When simulating and verifying the Block_RAM test case by using the constructed test platform, the address signal and the data signal need to be non-blockingly assigned at each clock edge of the control signal, and the value at the time of non-blockingly assigning is derived from the pre-written input file. Therefore, at each time of assigning, for any one to-be-assigned signal in the address signal and the data signal, the value is sequentially taken from the input file corresponding to the to-be-assigned signal and is assigned to the corresponding to-be-assigned signal. The input file corresponding to each to-be-assigned signal is pre-written and stored, and therefore, when simulating and verifying by using the test platform, the input file of each to-be-assigned signal is called to take and assign the value.

[0107] The number of values contained in the input file of each to-be-assigned signal is equal to the array bit width of the to-be-assigned signal, and generally, when writing the input file corresponding to each to-be-assigned signal, the value range is determined according to the bit width, and the corresponding number of values are randomly taken and written into the input file in a uniform distribution manner. In particular, the input files of two to-be-assigned signals associated with each other contain the same values reaching a predetermined proportion, and the same values are randomly distributed in the input files. Among them, when both of the two to-be-assigned signals are address signals and read and write the same RAM array, it is determined that the two to-be-assigned signals are associated with each other.

[0108] For example, in the example given in the first part of the present application, the parsed address signals include addra and addrb, and the data signal includes dia, and when constructing the test platform, the size of the array defined for the signals that need to be randomly assigned is 512, then the input file is pre-written for addra, addrb and dia respectively, and each input file contains 512 values. Among them, since the two address signals addra and addrb read and write the same RAM array, the two to-be-assigned signals are associated with each other, so the input file of addra and the input file of addrb finally obtained have 256 same values, and these same values are randomly distributed in different lines of the input file, so as to ensure that the read and write functions of the test case can be correctly verified.

[0109] The synthesized netlist obtained by the synthesis tool is simulated and verified with RTL to verify the correctness of the synthesized netlist. After obtaining the netlist of each RTL description file, the constructed test platform and the input file of each signal to be assigned are loaded, the test platform takes values from the input file and assigns them, the test platform outputs the input and output values at each time, and the simulation verification is completed by comparing whether the output results are consistent.

Claims

1. An automatic simulation verification method for Block_RAM test cases, characterized in that, The method comprises: parsing a description statement in an RTL level description file of a Block_RAM test case to obtain a signal dictionary, the signal dictionary comprising all parsed signals, the parsed signals being classified according to a transmission direction type into at least one of an input signal, an output signal and an input / output signal, the input signal being classified according to a signal quantity type into a clock signal, an address signal, a control signal and a data signal; defining a variable type of each signal according to the transmission direction type of the signal; generating a port corresponding to each parsed signal according to the signal dictionary, inputting a clock signal into the corresponding port, generating a signal waveform corresponding to a control signal of a working mode of the Block_RAM and inputting the control signal into the corresponding port, and non-blockedly assigning the address signal and the data signal at each clock edge of the clock signal and inputting the address signal and the data signal into the corresponding port during a read / write process of the control signal, to construct a test platform; completing simulation verification of the Block_RAM test case by using the test platform; wherein the parsed signal dictionary comprises signal parameters of each signal, the signal parameters comprising a variable name, a bit width and a signal type of the signal, the signal type indicating the transmission direction type of the signal; and the parsing of the description statement in the RTL level description file of the Block_RAM test case to obtain the signal dictionary comprises: iteratively comparing the description statement in the RTL level description file, and when the comparison is consistent and both are input, splitting a colon in the description statement to obtain a bit width of the signal; processing a variable name set to split the variable name of the signal, and storing the variable name and the bit width of the signal in the signal dictionary, and determining the transmission direction type of the signal to be classified as an input signal; and / or, iteratively comparing the description statement in the RTL level description file, and when the comparison is consistent and both are output, splitting a colon in the description statement to obtain a bit width of the signal; processing a variable name set to split the variable name of the signal, and storing the variable name and the bit width of the signal in the signal dictionary, and determining the transmission direction type of the signal to be classified as an output signal; and / or, iteratively comparing the description statement in the RTL level description file, and when the comparison is consistent and both are inout, splitting a colon in the description statement to obtain a bit width of the signal; processing a variable name set to split the variable name of the signal, and storing the variable name and the bit width of the signal in the signal dictionary, and determining the transmission direction type of the signal to be classified as an input / output signal.

2. The method of claim 1, wherein, The inputting of the clock signal into the corresponding port comprises: if the signal dictionary contains a declared and defined clock signal, directly inputting the clock signal in the signal dictionary into the corresponding port; if the signal dictionary does not contain a declared and defined clock signal, defining a new clock signal to input into the corresponding port.

3. The method of claim 1, wherein, The non-blocked assignment to the address signal and the data signal comprises: for any one to-be-assigned signal among the address signal and the data signal, sequentially taking values from an input file corresponding to the to-be-assigned signal and assigning the values to the corresponding to-be-assigned signal. The number of values contained in the input file of each signal to be assigned is equal to the array bit width of the signal to be assigned; and the same values contained in the input files of two signals to be assigned associated with the signal reach a predetermined proportion, and the same values are randomly distributed in each input file.

4. The method of claim 3, wherein, When both signals to be assigned are address signals and read and write the same RAM array, it is determined that the two signals to be assigned are associated with the signal.

5. The method of claim 1, wherein, The method further comprises: traversing the description statements in the RTL level description file, searching for the description statements containing the parameter keyword, and splitting the description statements by the comma to obtain a plurality of parameter definitions to construct a parameter dictionary, each parameter definition containing a parameter name and a corresponding parameter value; When splitting the colon in the description statement to the bit width of the signal, if the colon in the split description statement obtains a number, the bit width is directly obtained from the number; if the colon in the split description statement obtains a string, the bit width is obtained from the parameter value corresponding to the parameter name represented by the string in the parameter dictionary.

6. The method of claim 1, wherein, The variable type of each signal is defined according to the transmission direction type of each signal, comprising: The variable types of all input signals are defined as reg, and the variable types of all output signals and input-output signals are defined as wire.

7. The method of claim 1, wherein, The control signals corresponding to the working mode of the signal waveform and the Block_RAM are generated, comprising: The values of the control signals of the read operation and the control signals of the write operation are sequentially set according to the port mode of the Block_RAM, the Block_RAM is controlled to perform the read operation and / or the write operation, and the sequence of the read operation and / or the write operation performed by the Block_RAM corresponds to the read-write mode of the Block_RAM.

8. The method of claim 7, wherein, When the read-write mode of the Block_RAM is the read-priority mode, the sequence of the read operation and / or the write operation is: All control signals are controlled to be false, after a predetermined time, the control signal of the read operation is set to true to start the read operation, after a predetermined time, the control signal of the read operation is kept true and the control signal of the write operation is set to true, after a predetermined time, the control signal of the read operation is kept true and the control signal of the write operation is set to false, after a predetermined time, the control signal of the write operation is kept false and the control signal of the read operation is set to false, and after a predetermined time, the process is ended.

9. The method of claim 8, wherein, The process of sequentially setting the values of the control signals of the read operation and the control signals of the write operation according to the port mode of the Block_RAM comprises: When the port mode of the Block_RAM is the single-port mode, the simple dual-port mode and the true dual-port mode: all control signals are set to 0, after a predetermined time, the control signal of the read operation is set to 1 to start the read operation, after a predetermined time, the control signal of the read operation is kept 1 and the control signal of the write operation is set to 1, after a predetermined time, the control signal of the read operation is kept 1 and the control signal of the write operation is set to 0, after a predetermined time, the control signal of the write operation is kept 0 and the control signal of the read operation is set to 0, and after a predetermined time, the process is ended. When the port mode of the Block_RAM is the true dual-port mode supporting the BWE function, all the control signals are set to 0, after a predetermined time, the control signal of the read operation is set to 1 to start the read operation, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 1, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 3, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 7, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 15, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 0, after a predetermined time, the control signal of the write operation is kept to 0 and the control signal of the read operation is set to 0, and after a predetermined time, the process is ended.

10. The method of claim 7, wherein, When the read-write mode of the Block_RAM is the write-priority mode, the sequence of the read operation and / or the write operation is as follows: all the control signals are controlled to be false, after a predetermined time, all the control signals are set to true to perform the read operation and the write operation, after a predetermined time, the control signal of the read operation is kept to true and the control signal of the write operation is set to false, after a predetermined time, the control signal of the read operation is kept to true and the control signal of the write operation is set to true, after a predetermined time, the control signal of the read operation is kept to true and the control signal of the write operation is set to false, after a predetermined time, the control signal of the write operation is kept to false and the control signal of the read operation is set to false, and after a predetermined time, the process is ended.

11. The method of claim 10, wherein, The process of setting the values of the control signal of the read operation and the control signal of the write operation according to the port mode of the Block_RAM comprises: When the port mode of the Block_RAM is the single-port mode, the simple dual-port mode and the true dual-port mode, all the control signals are set to 0, after a predetermined time, all the control signals are set to 1 to perform the read operation and the write operation, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 0, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 1, after a predetermined time, the control signal of the read operation is kept to 1 and the control signal of the write operation is set to 0, after a predetermined time, the control signal of the write operation is kept to 0 and the control signal of the read operation is set to 0, and after a predetermined time, the process is ended. When the Block_RAM's port mode is a true dual-port mode supporting BWE functionality, all control signals are set to 0. After a predetermined time, all control signals are set to 1 to perform read and write operations. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 0. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 1. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 3. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 7. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 15. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 0. After a predetermined time, the control signal for write operations is kept at 0, and the control signal for read operations is set to 0. After a predetermined time, the process ends.

12. The method of claim 7, wherein, When the Block_RAM is in hold mode, the order of reading and / or writing operations is as follows: Set all control signals to false. After a predetermined time, set all control signals to true to perform read and write operations. After a predetermined time, keep the control signal for read operations true and set the control signal for write operations false. After a predetermined time, keep the control signal for write operations false and set the control signal for read operations false. After a predetermined time, end the process.

13. The method of claim 12, wherein, When the read / write mode of the Block_RAM is hold mode: When the port mode of the Block_RAM is single-port mode, simple dual-port mode, or true dual-port mode: all control signals are set to 0, and after a predetermined time, all control signals are set to 1 to perform read and write operations; after a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 0; after a predetermined time, the control signal for write operations is kept at 0, and the control signal for read operations is set to 0, and the process ends after a predetermined time. When the Block_RAM's port mode is a true dual-port mode supporting BWE functionality, all control signals are set to 0. After a predetermined time, all control signals are set to 1. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 3. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 7. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 15. After a predetermined time, the control signal for read operations is kept at 1, and the control signal for write operations is set to 0. After a predetermined time, the control signal for write operations is kept at 0, and the control signal for read operations is set to 0. After a predetermined time, the process ends.

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