Display device and refresh driving method

Abstract

The present invention provides a display device and a refresh driving method. The display device includes a display panel and a driving module; the display panel includes a first display area, a second display area, and a multi-row and multi-column pixel circuit; the driving module is configured to control the refresh frequency of the pixel circuit disposed in the first display area to be a first refresh frequency, and control the refresh frequency of the pixel circuit disposed in the second display area to be different from the first refresh frequency. The present invention can reduce power consumption while normally displaying a picture.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display device and a refresh driving method. Background Art

[0002] When a related OLED (organic light-emitting diode) display screen works, when the display screen is updated, the entire screen is updated, and the driving power consumption is relatively high. Summary of the Invention

[0003] The main object of the present invention is to provide a display device and a refresh driving method, so as to solve the problem in the prior art that power consumption cannot be reduced while a normal display screen is being displayed.

[0004] In one aspect, an embodiment of the present invention provides a display device, including a display panel and a driving module; the display panel includes a first display area, a second display area, and a plurality of pixel circuits arranged in multiple rows and columns;

[0005] The driving module is configured to control the refresh frequency of the pixel circuits arranged in the first display area to be a first refresh frequency, and control the refresh frequency of the pixel circuits arranged in the second display area to be different from the first refresh frequency.

[0006] Optionally, when the driving module determines that the picture displayed in a partial display area included in the display panel changes and the picture displayed in another partial display area included in the display panel does not change, the driving module is configured to control the refresh frequency of the pixel circuits in the partial display area to be a first refresh frequency, and control the refresh frequency of the other partial display area to be less than the first refresh frequency; the partial display area is an updated display area, and the other partial display area is an unupdated display area; the updated display area is the first display area, and the unupdated display area is the second display area.

[0007] Optionally, when there is at least one row of pixel circuits arranged in the updated display area, the driving module is further configured to adjust the refresh frequency of at least one row of pixel circuits in the updated display area by controlling the frequencies of a first start signal and a second start signal.

[0008] Optionally, the driving module includes a first updated GOA module and a second updated GOA module;

[0009] The first updated GOA module is configured to provide an N-type scan signal for the at least one row of pixel circuits;

[0010] The second updated GOA module is configured to provide a P-type scan signal for the at least one row of pixel circuits;

[0011] The first updated GOA module includes multiple levels of first updated GOA circuits, and the second updated GOA module includes multiple groups of second updated GOA circuits;

[0012] The first-level first updated GOA circuit included in the first updated GOA module accesses the first start signal, and the first-level second updated GOA circuit included in the second updated GOA module accesses the second start signal.

[0013] Optionally, two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area are provided in the non-updated display area; the adjacent pixel circuit groups include at least one row of transition pixel circuits;

[0014] The driving module is used to control the refresh frequency of the at least one row of transition pixel circuits to be a second refresh frequency, the second refresh frequency is less than the first refresh frequency, and the second refresh frequency is greater than the refresh frequency of the other part of the display area.

[0015] Optionally, non-adjacent pixel circuit groups other than the adjacent pixel circuit groups are also provided in the non-updated display area; the non-adjacent pixel circuit groups include at least one row of pixel circuits;

[0016] The driving module is used to control the refresh frequency of the pixel circuits included in the non-adjacent pixel circuit groups to be a third refresh frequency; the third refresh frequency is less than the second refresh frequency.

[0017] Optionally, when there are M rows and N columns of pixel circuits in the updated display area, and N is less than the total number of columns of pixel circuits included in the display panel, the pixel circuits include a writing control circuit; M and N are positive integers;

[0018] The control end of the writing control circuit is electrically connected to the writing control line, the first end of the writing control circuit is electrically connected to the data line, and the second end of the writing control circuit is electrically connected to the data writing node; the writing control circuit is used to control the connection between the data line and the data writing node under the control of the writing control signal provided by the writing control line;

[0019] The driving module is used to control the frequency of the writing control signal accessed by the control ends of the writing control circuits included in the pixel circuits in the same row but different columns as the M rows and N columns of pixel circuits, so that the refresh frequency of the pixel circuits in the same row but different columns as the M rows and N columns of pixel circuits is less than the first refresh frequency.

[0020] Optionally, the driving module is further configured to control the frequency of the writing control signal applied to the control terminal of the writing control circuit included in the M-row N-column pixel circuit, so that the refresh frequency of the M-row N-column pixel circuit is the first refresh frequency.

[0021] In a second aspect, an embodiment of the present invention provides a refresh driving method, which is applied to a display device. The display device includes a display panel and a driving module; the display panel includes a first display area, a second display area, and a multi-row multi-column pixel circuit; the refresh driving method includes:

[0022] The driving module controls the refresh frequency of the pixel circuit disposed in the first display area to be a first refresh frequency, and the driving module controls the refresh frequency of the pixel circuit disposed in the second display area to be different from the first refresh frequency.

[0023] Optionally, the refresh driving method according to at least one embodiment of the present invention includes:

[0024] When it is determined that the picture displayed in a partial display area included in the display panel changes and the picture displayed in another partial display area included in the display panel does not change, control the refresh frequency of the pixel circuit in the partial display area to be the first refresh frequency, and control the refresh frequency of the other partial display area to be less than the first refresh frequency;

[0025] The partial display area is an updated display area, and the other partial display area is an unupdated display area; the updated display area is the first display area, and the unupdated display area is the second display area.

[0026] Optionally, at least one embodiment of the present invention includes: when at least one row of pixel circuits is provided in the updated display area, adjusting the refresh frequency of at least one row of pixel circuits in the updated display area by controlling the frequency of a first start signal and the frequency of a second start signal.

[0027] Optionally, the display panel further includes a first updated GOA module and a second updated GOA module. The first updated GOA module is configured to provide an N-type scan signal for the at least one row of pixel circuits, and the second updated GOA module is configured to provide a P-type scan signal for the at least one row of pixel circuits; the first updated GOA module includes multiple levels of first updated GOA circuits, and the second updated GOA module includes multiple groups of second updated GOA circuits; the first-level first updated GOA circuit included in the first updated GOA module accesses the first start signal, and the first-level second updated GOA circuit included in the second updated GOA module accesses the second start signal.

[0028] Optionally, two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area are provided in the non-updated display area; each of the adjacent pixel circuit groups includes at least one row of transition pixel circuits.

[0029] The refresh driving method further includes: controlling the refresh frequency of the at least one row of transition pixel circuits to be a second refresh frequency, where the second refresh frequency is less than the first refresh frequency.

[0030] Optionally, non-adjacent pixel circuit groups other than the adjacent pixel circuit groups are further provided in the non-updated display area; each of the non-adjacent pixel circuit groups includes non-adjacent pixel circuits.

[0031] The refresh driving method further includes: controlling the refresh frequency of the non-adjacent pixel circuits to be a third refresh frequency; the third refresh frequency is less than the second refresh frequency.

[0032] Optionally, when there are M rows and N columns of pixel circuits in the updated display area, and N is less than the total number of columns of pixel circuits included in the display panel, the pixel circuits include a writing control circuit; a control end of the writing control circuit is electrically connected to a writing control line, a first end of the writing control circuit is electrically connected to a data line, and a second end of the writing control circuit is electrically connected to a data writing node; the writing control circuit is configured to control communication between the data line and the data writing node under the control of a writing control signal provided by the writing control line; M and N are positive integers; the refresh driving method includes:

[0033] By controlling the frequency of the writing control signal accessed by the control end of the writing control circuit included in the pixel circuits in the same row but different columns from the M rows and N columns of pixel circuits, so that the refresh frequency of the pixel circuits in the same row but different columns from the M rows and N columns of pixel circuits is less than the first refresh frequency.

[0034] Optionally, the refresh driving method according to at least one embodiment of the present invention further includes:

[0035] By controlling the frequency of the writing control signal accessed by the control end of the writing control circuit included in the M rows and N columns of pixel circuits, so that the refresh frequency of the M rows and N columns of pixel circuits is the first refresh frequency.

[0036] The display device and the refresh driving method according to the embodiments of the present invention can reduce power consumption while normally displaying a picture. Description of the Drawings

[0037] Figure 1 is a schematic diagram of the partition of the display panel of the display device according to the present invention;

[0038] Figure 2It is a structural diagram of at least one embodiment of the display device according to the present invention;

[0039] Figure 3 is Figure 2 The working timing diagram of at least one embodiment of the display device shown;

[0040] Figure 4 It is a structural diagram of at least one embodiment of the display device according to the present invention;

[0041] Figure 5 is Figure 4 The working timing diagram of at least one embodiment of the display device shown;

[0042] Figure 6 It is a schematic diagram of the partition of the display panel of the display device according to the present invention;

[0043] Figure 7 is Figure 4 Another working timing diagram of at least one embodiment of the display device shown;

[0044] Figure 8 It is a circuit diagram of at least one embodiment of the pixel circuit in the display device according to the present invention;

[0045] Figure 9 It is a circuit diagram of at least one embodiment of the pixel circuit;

[0046] Figure 10 It is a schematic diagram of the partition of the display panel;

[0047] Figure 11 It is a circuit diagram of at least one embodiment of the first GOA circuit in the display device according to the present invention;

[0048] Figure 12 It is a circuit diagram of at least one embodiment of the second GOA circuit in the display device according to the present invention. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0050] The display device described in the embodiments of the present invention includes a display panel and a driving module; the display panel includes a first display area, a second display area, and a plurality of rows and columns of pixel circuits;

[0051] The driving module is used to control the refresh frequency of the pixel circuits arranged in the first display area to be a first refresh frequency, and control the refresh frequency of the pixel circuits arranged in the second display area to be different from the first refresh frequency.

[0052] The display device according to the embodiment of the present invention can set corresponding refresh frequencies for different display areas, so as to reduce power consumption while normally displaying a picture.

[0053] In specific implementation, at least one row and at least one column of pixel circuits are arranged in the first display area, and at least one row and at least one column of pixel circuits are arranged in the second display area.

[0054] The display device according to the embodiment of the present invention includes a display panel and a driving module;

[0055] The display panel includes multiple rows and multiple columns of pixel circuits;

[0056] When the driving module determines that the picture displayed in a partial display area included in the display panel changes and the picture displayed in another partial display area included in the display panel does not change, the driving module is used to control the refresh frequency of the pixel circuits in the partial display area to be a first refresh frequency, and control the refresh frequency of the other partial display area to be less than the first refresh frequency;

[0057] The partial display area is an updated display area, and the other partial display area is an unupdated display area; the updated display area is the first display area, and the unupdated display area is the second display area.

[0058] It can be understood that the updated display area and the unupdated display area in this patent are relative. For example: the unupdated display area refers to the display area with a lower refresh frequency, and the refresh frequency of this area is lower than that of the updated display area. For example: the refresh frequency of the unupdated display area is 30HZ - 45HZ lower than that of the updated display area; or, in the unupdated display area, it seems to the human eye that the picture basically does not change or changes very slowly, such as 0HZ to 30HZ. (0HZ can refer to the state where the picture is static).

[0059] When the display device according to the embodiment of the present invention is working, when the driving module determines that the picture displayed in a partial display area included in the display panel changes while the picture displayed in another partial display area included in the display panel does not change, the driving module controls the refresh frequency of the pixel circuits in the display area where the picture is updated to be a first refresh frequency, and controls the refresh frequency of the pixel circuits in the display area where the picture is not updated to be less than the first refresh frequency, so as to reduce power consumption while normally displaying a picture.

[0060] When a related OLED (organic light-emitting diode) display screen is working and the display screen is updated, the entire screen is updated, resulting in a relatively high driving power consumption. For a display panel using low-frequency technologies such as LTPO (low-temperature polycrystalline oxide), which can maintain the display brightness unchanged for a long time, the local refresh driving method proposed in the embodiments of the present invention can be selected. In the local refresh driving method proposed in the embodiments of the present invention, when the local data of the display screen is updated, the display panel only highly refreshes the part of the screen data that is updated, and the other parts are refreshed at a low frequency, thereby minimizing the driving power consumption to the greatest extent.

[0061] In at least one embodiment of the present invention, the driving module is further configured to, when at least one row of pixel circuits is provided in the updated display area, adjust the refresh frequency of at least one row of pixel circuits in the updated display area by controlling the frequencies of the first start signal and the second start signal.

[0062] In specific implementation, the driving module can adjust the refresh frequency of the pixel circuits in the updated display area by controlling the frequencies of the first start signal and the second start signal.

[0063] Optionally, the driving module includes a first updated GOA (Gate On Array) module and a second updated GOA module;

[0064] The first updated GOA module is configured to provide an N-type scan signal for the at least one row of pixel circuits;

[0065] The second updated GOA module is configured to provide a P-type scan signal for the at least one row of pixel circuits;

[0066] The first updated GOA module includes multiple levels of first updated GOA circuits, and the second updated GOA module includes multiple groups of second updated GOA circuits;

[0067] The first-level first updated GOA circuit included in the first updated GOA module accesses the first start signal, and the first-level second updated GOA circuit included in the second updated GOA module accesses the second start signal.

[0068] In specific implementation, the first updated GOA module is configured to provide an N-type scan signal for the pixel circuits in the updated display area, and the second updated GOA module is configured to provide a P-type scan signal for the pixel circuits in the updated display area. The driving module may further include a driving control unit. In at least one embodiment of the present invention, the driving control unit can control the first start signal accessed by the first-level first updated GOA circuit and the second start signal accessed by the first-level second updated GOA circuit to control and adjust the refresh frequency of the pixel circuits in the updated display area.

[0069] In at least one embodiment of the present invention, two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area are provided in the unupdated display area; each of the adjacent pixel circuit groups includes at least one row of transition pixel circuits;

[0070] The driving module is configured to control the refresh frequency of the at least one row of transition pixel circuits to be a second refresh frequency, the second refresh frequency is less than the first refresh frequency, and the second refresh frequency is greater than the refresh frequency of the other part of the display area.

[0071] In a specific implementation, the display area adjacent to the updated display area can be set as a transition display area, and the refresh frequency of the transition display area is the second refresh frequency, and the second refresh frequency is between the low-frequency refresh frequency and the first refresh frequency, so as to reduce the display difference, prevent the human eye from detecting, and reduce the possible flicker and Mura (display unevenness) problems caused by the display difference between adjacent display areas. Wherein, the low-frequency display frequency is the refresh frequency of the other part of the display area.

[0072] Optionally, non-adjacent pixel circuit groups other than the adjacent pixel circuit groups are further provided in the unupdated display area; each of the non-adjacent pixel circuit groups includes non-adjacent pixel circuits;

[0073] The driving module is configured to control the refresh frequency of the non-adjacent pixel circuits to be a third refresh frequency; the third refresh frequency is less than the second refresh frequency.

[0074] In at least one embodiment of the present invention, the third refresh frequency is the low-frequency display frequency.

[0075] In at least one embodiment of the present invention, the third refresh frequency can be less than or equal to 60 Hz. For example, the third refresh frequency can be 1 Hz, 10 Hz, 20 Hz, 30 Hz, 40 Hz or 60 Hz, but not limited thereto.

[0076] Optionally, when there are M rows and N columns of pixel circuits in the updated display area, and N is less than the total number of columns of pixel circuits included in the display panel, the pixel circuit includes a write control circuit; M and N are positive integers;

[0077] The control end of the write control circuit is electrically connected to the write control line, the first end of the write control circuit is electrically connected to the data line, and the second end of the write control circuit is electrically connected to the data write node; the write control circuit is configured to control the connection between the data line and the data write node under the control of the write control signal provided by the write control line.

[0078] The driving module is used to control the frequency of the writing control signal applied to the control terminal of the writing control circuit included in the pixel circuits of different columns in the same row as the M-row N-column pixel circuit, so that the refresh frequency of the pixel circuits of different columns in the same row as the M-row N-column pixel circuit is less than the first refresh frequency.

[0079] In at least one embodiment of the present invention, when the number of columns of the pixel circuits in the updated display area is less than the total number of columns of the pixel circuits included in the display panel, the frequency of the writing control signal can be controlled to control the refresh frequency of the pixel circuits of different columns in the same row as the M-row N-column pixel circuit to be less than the first refresh frequency.

[0080] In at least one embodiment of the present invention, the driving module is further used to control the frequency of the writing control signal applied to the control terminal of the writing control circuit included in the M-row N-column pixel circuit, so that the refresh frequency of the M-row N-column pixel circuit is the first refresh frequency.

[0081] As Figure 1 shown, the effective display area of the display panel 10 can be divided into A display areas;

[0082] In Figure 1 it, the first preset display area labeled P1, the second preset display area labeled P2, the a-th preset display area labeled Pa, and the A-th preset display area labeled PA;

[0083] A is a positive integer, and a is a positive integer less than A.

[0084] During actual operation, the display area to be refreshed can be automatically matched according to the update situation of the display screen of the display panel, so as to minimize power consumption. For example, when the display screen of the a-th preset display area Pa is updated and the display screens of other display areas except the a-th preset display area Pa are not updated, the driving module controls the refresh frequency of the pixel circuits in the a-th preset display area Pa to be the first refresh frequency; the driving module controls the refresh frequencies of the pixel circuits in other display areas except the a-th preset display area Pa to be less than the first refresh frequency. For example, the first refresh frequency can be 120 Hz, and the refresh frequencies of the pixel circuits in other display areas except the a-th preset display area Pa can be 1 Hz; but not limited thereto.

[0085] In at least one embodiment of the present invention, the effective display area can be evenly divided into A display areas; alternatively, it can be divided into unequal areas according to the display rules. For example, the task bar on the desktop of an office computer can be separately divided into one display area, the central display area when playing a video can be separately divided into one display area, the menu area and the editing area for text office can be separately divided into one display area each; the folding or multi-folding areas of the folding display panel can be separately divided into one display area each; and so on.

[0086] Moreover, when local video, icon flashing, text input, etc. occur in a certain display area on the display panel, there will be a problem that the refresh frequency of this display area needs to be switched.

[0087] In specific implementation, when dividing the display area, the pixel circuit and the GOA circuit in the driving module can be divided.

[0088] When the effective display area is divided into A display areas, the driving module can include A first GOA modules and A second GOA modules; the a-th first GOA module corresponds to the a-th preset display area, and the a-th second GOA module corresponds to the a-th preset display area.

[0089] The a-th first GOA module is used to provide the corresponding N-type scanning signal for the pixel circuit disposed in the a-th preset display area.

[0090] The a-th second GOA module is used to provide the corresponding P-type scanning signal for the pixel circuit disposed in the a-th preset display area.

[0091] When the a-th preset display area is the refresh display area, the first updated GOA module is the a-th first GOA module, and the second updated GOA module is the a-th second GOA module.

[0092] In at least one embodiment of the present invention, when the effective display area is divided into A display areas, the driving module can include A first left GOA modules, A first right GOA modules, A second left GOA modules, and A second right GOA modules.

[0093] The a-th first left GOA module and the a-th first right GOA module provide the corresponding N-type scanning signal for the pixel circuit disposed in the a-th preset display area.

[0094] The a-th second left GOA module and the a-th second right GOA module provide the corresponding P-type scanning signal for the pixel circuit disposed in the a-th preset display area.

[0095] When the a-th preset display area is the refreshed display area, the first updated GOA module includes the a-th first left GOA module and the a-th first right GOA module, and the second updated GOA module includes the a-th second left GOA module and the a-th second right GOA module.

[0096] In at least one embodiment of the present invention, each GOA module may include at least one stage of cascaded GOA circuits; the first GOA module may include at least one stage of first GOA circuits, and the second GOA module may include at least one stage of second GOA circuits;

[0097] One stage of first GOA circuits may provide corresponding N-type scan signals for two rows of pixel circuits, and one stage of second GOA circuits may provide corresponding P-type scan signals for one row of pixel circuits; however, it is not limited thereto.

[0098] As Figure 2 shown, all row pixel circuits in the first preset display area are labeled as X1; all row pixel circuits in the (a - 1)-th preset display area are labeled as Xa - 1, all row pixel circuits in the a-th preset display area are labeled as Xa, all row pixel circuits in the (a + 1)-th preset display area are labeled as Xa + 1, all row pixel circuits in the (A - 1)-th preset display area are labeled as XA - 1, and all row display circuits in the A-th preset display area are labeled as XA;

[0099] The first first left GOA module is labeled as GN11, the (a - 1)-th first left GOA module is labeled as GNa - 11, the a-th first left GOA module is labeled as GNa1, the (a + 1)-th first left GOA module is labeled as GNa + 11, and the A-th first left GOA module is labeled as GNA1;

[0100] The first first right GOA module is labeled as GN12, the (a - 1)-th first right GOA module is labeled as GNa - 12, the a-th first right GOA module is labeled as GNa2, the (a + 1)-th first right GOA module is labeled as GNa + 12, and the A-th first right GOA module is labeled as GNA2;

[0101] The first second left GOA module is labeled as GP11, the (a - 1)-th second left GOA module is labeled as GPa - 11, the a-th second left GOA module is labeled as GPa1, the (a + 1)-th second left GOA module is labeled as GPa + 11, and the A-th second left GOA module is labeled as GPA1;

[0102] The one labeled GP12 is the first second right-side GOA module, the one labeled GPa-12 is the (a-1)-th second right-side GOA module, the one labeled GPa2 is the a-th second right-side GOA module, the one labeled GPa+12 is the (a+1)-th second right-side GOA module, and the one labeled GPA2 is the A-th second right-side GOA module.

[0103] As Figure 2 shown, the driving module may further include a driving control unit 20;

[0104] The driving control unit 20 is used to provide the first first start signal NSTV1 for GN11 and GN12, the (a-1)-th first start signal NSTVa-1 for GNa-11 and GNa-12, the a-th first start signal NSTVa for GNa1 and GNa2, the (a+1)-th first start signal NSTVa+1 for GNa+11 and GNa+12, and the A-th first start signal NSTVA for GNA1 and GNA2;

[0105] The driving control unit 20 is used to provide the first second start signal GSTV1 for GP11 and GP12, the (a-1)-th second start signal GSTVa-1 for GPa-11 and GPa-12, the a-th second start signal GSTVa for GPa1 and GPa2, the (a+1)-th second start signal GSTVa+1 for GPa+11 and GPa+12, and the A-th second start signal GSTVA for GPA1 and GPA2.

[0106] When the a-th preset display area is the updated display area and the other display areas included in the effective display area are the non-updated display areas, the refresh frequency of the pixel circuits located in the a-th preset display area can be increased by increasing the frequencies of NSTV2a-1, NSTV2a, GSTV2a-1, and GSTV2a.

[0107] In at least one embodiment of the present invention, for example, when Figure 8 at least one embodiment of the shown pixel circuit is working, the gate of the eighth transistor T8 included in the pixel circuit is electrically connected to the first scan line GN, and the gate of the second transistor T2 included in the pixel circuit and the gate of the fourth transistor included in the pixel circuit are electrically connected to the second scan line GP. Therefore, the refresh frequency of the pixel circuit is related to the frequency of the first start signal accessed by the first GOA module providing the first scan signal and the frequency of the second start signal accessed by the second GOA module providing the second scan signal.

[0108] In specific implementation, the frequency of the first start signal accessed by the first GOA module is the same as the frequency of the first scan signal output by the first GOA module, and the frequency of the second start signal accessed by the second GOA module is the same as the frequency of the second scan signal output by the second GOA module, but this is not limited thereto.

[0109] Figure 3 Yes Figure 2 is the working timing diagram of at least one embodiment shown.

[0110] In Figure 3 it, Vsync is the synchronization signal, DE is the data enable signal, and Vd is the data voltage.

[0111] As Figure 3 shown, the frequency of NSTVa is greater than the frequency of NSTV1, and the frequency of NSTVa is greater than the frequency of NSTVA; the frequency of GSTVa is greater than the frequency of GSTV1, and the frequency of GSTVa is greater than the frequency of GSTVA; so that the refresh frequency of the pixel circuit located in the a-th preset display area is greater than the refresh frequency of the pixels located in other display areas.

[0112] In at least one embodiment of the present invention, when the refresh frequency of the pixel circuits in the first display area is 120 Hz, the frequency of the first start signal accessed by the first GOA module that provides the first scan signal for the pixel circuits in the first display area, and the frequency of the second start signal accessed by the second GOA module that provides the second scan signal for the pixel circuits in the first display area can both be 120 Hz;

[0113] That is, when the refresh frequency of the pixel circuits in the display area is the predetermined frequency, the frequency of the first start signal accessed by the first GOA module that provides the first scan signal for the pixel circuits in the first display area, and the frequency of the second start signal accessed by the second GOA module that provides the second scan signal for the pixel circuits in the first display area can both be the predetermined frequency.

[0114] For example, when the ratio of the refresh frequency of the pixel circuits in the first display area to the refresh frequency of the pixel circuits in the second display area is 4, then the ratio of the frequency of the first start signal accessed by the first GOA module that provides the first scan signal for the pixel circuits in the first display area to the frequency of the first start signal accessed by the first GOA module that provides the first scan signal for the pixel circuits in the second display area can be 4, and the ratio of the frequency of the second start signal accessed by the second GOA module that provides the second scan signal for the pixel circuits in the first display area to the frequency of the second start signal accessed by the second GOA module that provides the second scan signal for the pixel circuits in the second display area can be 4.

[0115] As shown in Figure 4 the driving module may further include A light emission control modules and A third GOA modules based on at least one embodiment of the display panel shown in Figure 2 ; The module labeled ES1 is the first light emission control module, the module labeled ESa-1 is the (a-1)th light emission control module, the module labeled ESa is the ath light emission control module, the module labeled ESa+1 is the (a + 1)th light emission control module, and the module labeled ESA is the Ath light emission control module; Each light emission control module is configured to provide a light emission control signal to a pixel circuit disposed in a corresponding display area;

[0116] The module labeled S1 is the first third GOA module, the module labeled Sa-1 is the (a-1)th third GOA module, the module labeled Sa is the ath third GOA module, the module labeled Sa+1 is the (a + 1)th third GOA module, and the module labeled SA is the Ath third GOA module; Each third GOA module is configured to provide a third scan signal to a pixel circuit disposed in a corresponding display area.

[0117] As shown in

[0118] the A light emission control modules included in the driving module may be cascaded with each other, and the first light emission control module accesses a light emission control start signal ESTV; Figure 4 As shown in

[0119] the A third GOA modules included in the driving module may be cascaded with each other, and the first third GOA module accesses a third start signal STV3.

[0120] In specific implementation, the frequency of ESTV may be equal to the frequency of STV3, or the frequency of STV3 may be less than the frequency of ESTV.

[0121] In at least one embodiment of the present invention, the frequency of ESTV may be greater than or equal to 120 Hz, and the frequency of STV3 may be greater than or equal to 120 Hz; for example, the frequency of ESTV may be 480 Hz, and the frequency of STV3 may be 240 Hz, but not limited thereto.

[0122] Optionally, the frequency of the data enable signal DE may be equal to the maximum refresh frequency of the pixel circuits in each display area included in the display panel, but not limited thereto.

[0123] In specific implementation, the frequency of Vd is related to the refresh frequency of the corresponding display area. When the refresh frequency of the pixel circuit in the currently scanned display area is high, the frequency of Vd is high. When the refresh frequency of the pixel circuit in the currently scanned display area is low, the frequency of Vd is low.

[0124] In at least one embodiment of the present invention, the light-emitting control modules corresponding to different preset display areas may respectively correspond to a light-emitting start signal. At this time, the light-emitting control modules corresponding to the same preset display area are cascaded with each other, and the light-emitting control modules corresponding to different preset display areas are not cascaded with each other;

[0125] The third GOA modules corresponding to different preset display areas may respectively correspond to a third start signal. At this time, the third GOA modules corresponding to the same preset display area are cascaded with each other, and the third GOA modules corresponding to different preset display areas are not cascaded with each other.

[0126] Figure 5 Yes Figure 4 is the working timing diagram of at least one embodiment shown.

[0127] Figure 5 In Figure 3 Based on the working timing diagram shown, a light-emitting control start signal ESTV is added, and ESTV is provided to each light-emitting control module.

[0128] As Figure 5 shown, the frequency of ESTV is high.

[0129] In at least one embodiment of the present invention, in order to solve the problem of low-frequency flicker, each light-emitting control module and each third GOA module perform high-frequency refreshing.

[0130] As Figure 6 shown, the effective display area of the display panel 10 can be divided into A display areas;

[0131] In Figure 6 the first preset display area labeled P1, the second preset display area labeled P2, the (a - 1)th preset display area labeled Pa - 1, the ath preset display area labeled Pa, the (a + 1)th preset display area labeled Pa + 1, and the Ath preset display area labeled PA;

[0132] A is a positive integer, and a is a positive integer less than A.

[0133] In specific implementation, the display panel can be divided into A display areas. In order to reduce the flicker and Mura problems that may be caused by the differences between adjacent areas, the adjacent areas to the updated display area can be used as transition display areas.

[0134] In at least one embodiment of the present invention, when Figure 6 the ath preset display area Pa in is the updated display area, the (a - 1)th preset display area Pa - 1 and the (a + 1)th preset display area Pa + 1 are transition display areas;

[0135] The driving module is used to control the refresh frequency of the pixel circuit in Pa to be a first refresh frequency, control at least one of the refresh frequencies of the pixel circuits in Pa-1 and Pa+1 to be a second refresh frequency, and control at least one of the refresh frequencies of the pixel circuits in P1 and PA to be a third refresh frequency;

[0136] The first refresh frequency is greater than the second refresh frequency, and the second refresh frequency is greater than the third refresh frequency.

[0137] In specific implementation, the first refresh frequency can be, for example, 120 Hz, the second refresh frequency can be, for example, 60 Hz, and the third refresh frequency can be, for example, 1 Hz, but not limited thereto.

[0138] Figure 7 Yes Figure 4 Another working timing diagram of at least one of the illustrated embodiments.

[0139] In specific implementation, when the a-th preset display area Pa is an updated display area and the (a-1)-th preset display area Pa-1 and the (a+1)-th preset display area Pa+1 are transition display areas, the waveforms of the respective start signals are as Figure 7 shown.

[0140] In Figure 7 the Vsync is a synchronization signal, the DE is a data enable signal, the ESTV is a light emission control start signal, the GSTV1 is the first second start signal, the GSTVa-1 is the (a-1)-th second start signal, the GSTVa is the a-th second start signal, the GSTVa+1 is the (a+1)-th second start signal, the GSTVA is the A-th second start signal, the NSTV1 is the first first start signal, the NSTVa-1 is the (a-1)-th first start signal, the NSTVa is the a-th first start signal, the NSTVa+1 is the (a+1)-th first start signal, the NSTVA is the A-th first start signal, and the Vd is a data voltage.

[0141] As Figure 7 shown, the frequency of GSTVa is greater than the frequency of GSTVa-1, the frequency of GSTVa is greater than the frequency of GSTVa+1, the frequency of GSTVa-1 is greater than the frequency of GSTV1, the frequency of GSTVa-1 is greater than the frequency of GSTVA, the frequency of GSTVa+1 is greater than the frequency of GSTV1, and the frequency of GSTVa+1 is greater than the frequency of GSTVA;

[0142] The frequency of NSTVa is greater than the frequency of NSTVa-1, the frequency of NSTVa is greater than the frequency of NSTVa+1, the frequency of NSTVa-1 is greater than the frequency of NSTV1, the frequency of NSTVa-1 is greater than the frequency of NSTVA, the frequency of NSTVa+1 is greater than the frequency of NSTV1, and the frequency of NSTVa+1 is greater than the frequency of NSTVA.

[0143] As Figure 7 shown, the frequency of ESTV is high.

[0144] In at least one embodiment of the present invention, to solve the problem of low-frequency flicker, each light-emitting control module and each third GOA module perform high-frequency refreshing.

[0145] In at least one embodiment of the present invention, the structure of the pixel circuit may be as Figure 8 shown.

[0146] As Figure 8 shown, at least one embodiment of the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst, and an organic light-emitting diode O1;

[0147] The gate of T8 is electrically connected to the first scan line GN;

[0148] The gates of T2 and T4 are both electrically connected to the second scan line GP;

[0149] The gates of T1, T7, and T9 are all electrically connected to the third scan line Sc;

[0150] The gates of T5 and T6 are both electrically connected to the light-emitting control line EC;

[0151] T3 is a driving transistor;

[0152] The first scan line GN is used to provide a first scan signal, and the first scan signal is an N-type scan signal;

[0153] The second scan line GP is used to provide a second scan signal, and the second scan signal is a P-type scan signal;

[0154] The third scan line Sc is used to provide a third scan signal;

[0155] The light-emitting control line Sc is used to provide a light-emitting control signal.

[0156] In Figure 8Among them, the data line labeled D1 is a data line, and the data line D1 is used to provide a data voltage Vd; the first initial voltage labeled Vi1, the second initial voltage labeled Vi2, the reference voltage labeled Vref, the high voltage terminal labeled VDD, and the low voltage terminal labeled VSS.

[0157] In Figure 8 In at least one of the illustrated embodiments, T2 and T4 are p-type transistors, T8 is an n-type transistor, T1, T7, and T9 are p-type transistors, and T5 and T6 are p-type transistors.

[0158] In at least one embodiment of the present invention, the structure of the pixel circuit is not limited to being as Figure 8 shown, and the pixel circuit can emit light under the control of the first scan signal, the second scan signal, the third scan signal, and the light emission control signal.

[0159] As Figure 9 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 8 at least one embodiment of the pixel circuit may further include a write control circuit 90;

[0160] The control terminal of the write control circuit 90 is electrically connected to the write control line XC, the first end of the write control circuit 90 is electrically connected to the data line D1, and the second end of the write control circuit 90 is electrically connected to the data write node SX; the write control circuit 90 is used to control the connection between the data line D1 and the data write node SX under the control of the write control signal provided by the write control line XC.

[0161] As Figure 9 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 8 at least one embodiment of the pixel circuit may further include an auxiliary control circuit 91;

[0162] The control terminal of the auxiliary control circuit 91 is electrically connected to the auxiliary control line GC, the first end of the auxiliary control circuit 91 is electrically connected to the gate of the eighth transistor T8, that is, the second end of the auxiliary control circuit 91 is connected to the first scan line GN; the auxiliary control circuit 91 is used to control the connection between the first scan line GN and the gate of the eighth transistor T8 under the control of the auxiliary control signal provided by the auxiliary control line GC.

[0163] In Figure 9 at least one of the illustrated embodiments, the first scan signal on the first scan line GN may be provided by a corresponding first GOA circuit included in the first GOA module.

[0164] For example: As Figure 10As shown, when the effective display area of the display panel includes the unupdated area Pa1 and the updated display area Pa0, the auxiliary control line GC of the auxiliary control circuit 91 corresponding to the pixel circuit in the unupdated area Pa1 can be controlled to keep the eighth transistor in a non-operating state (e.g., off state). This can ensure that even if other transistors in the pixel circuit of the unupdated area Pa1 work, it will not affect the reset of the data signal in the unupdated area Pa1. At the same time, the auxiliary control line GC of the auxiliary control circuit 91 in the pixel circuit corresponding to the updated area Pa0 can be controlled to keep the eighth transistor in the pixel circuit of the updated area Pa0 in a normal operating state to update the corresponding picture.

[0165] Optionally, both the write control circuit 90 and the auxiliary control circuit 91 can be implemented by field effect transistors (e.g., they can have the same structure as other transistors in the pixel circuit and can be P-type or N-type). Details are not elaborated here. As Figure 10 shown, the refreshed display area included in the effective display area of the display panel is the middle display area Pa0 included in the a-th preset display area;

[0166] The display area located on the left side of the refreshed display area As included in the a-th preset display area is labeled as Pa1, and the display area located on the right side of the refreshed display area As included in the a-th preset display area is labeled as Pa2.

[0167] In Figure 10 it, the one labeled P1 is the first preset display area, and the one labeled PA is the A-th preset display area.

[0168] When the refreshed display area is the middle display area Pa0 included in the a-th preset display area, the structure of the pixel circuit in the a-th preset display area can be as Figure 9 shown. This pixel circuit includes a write control circuit. When the display panel is operating, the refresh frequency of the pixel circuit in Pa0 can be controlled to be the first frequency by controlling the frequency of the write control signal, and the refresh frequencies of the pixel circuits in Pa1 and Pa2 are controlled to be less than the first frequency.

[0169] It can be understood that Figure 9 the write control circuit 90 and the auxiliary control circuit 91 of

[0170] It can be understood that in some embodiments, the driving module can control the update frequency of the pixel circuit to achieve horizontal partitioning (e.g., P1...PA) by separately controlling the first updated GOA module and the second updated GOA module, etc.; of course, the longitudinal partitioning (e.g., Pa1...Pa2) can be achieved through the auxiliary control circuit 91 and / or the writing control circuit 90. Of course, the driving module can also combine the auxiliary control circuit 91 and / or the writing control circuit 90 to achieve a hybrid horizontal and vertical partitioning (as Figure 10 shown): For example: The driving module not only controls the update frequency of the pixel circuit by controlling the first updated GOA module and the second updated GOA module, etc., but also combines the frequency of the writing control signal of the data line D1 of the pixel circuit controlled by the writing control circuit 90 and the working frequency of the eighth transistor of the pixel circuit controlled by the auxiliary control circuit 90 to achieve a hybrid horizontal and vertical partitioning (as Figure 10 shown); of course, this is not limited thereto, and combinations of other multiple embodiments can also be used.

[0171] Figure 11 In at least one embodiment of the present invention, the circuit diagram of at least one embodiment of the first GOA circuit is shown, and the first GOA circuit is used to provide an N-type scanning signal.

[0172] As Figure 11 shown, at least one embodiment of the first GOA circuit may include a first display control transistor M1, a second display control transistor M2, a third display control transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a ninth display control transistor M9, a tenth display control transistor M10, an eleventh display control transistor M11, a twelfth display control transistor M12, a thirteenth display control transistor M13, a fourteenth display control transistor M14, a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0173] In Figure 11 , the one labeled as CK is the first clock signal terminal, the one labeled as I1 is the first input terminal, the one labeled as CB is the second clock signal terminal, the one labeled as VGL is the low voltage terminal, the one labeled as VGH is the high voltage terminal, the one labeled as PD1 is the first pull-down node, the one labeled as PU1 is the first pull-up node, the one labeled as SO1 is the first scanning signal output terminal, and the one labeled as R1 is the reset terminal.

[0174] In Figure 11 the at least one embodiment of the first GOA circuit shown, the second pole of M11 and the first pole of M8 can both be electrically connected to the high voltage terminal VGH.

[0175] In a specific implementation, the first pole may be a source or a drain, and the second pole may be a drain or a source.

[0176] When at least one embodiment of the first GOA circuit is used to provide an N-type scan signal, the first input terminal of the first-stage first GOA circuit included in each first GOA module is connected to a first start signal. For example, the first first left GOA module and the first first right GOA module can both be connected to the first first start signal, the (a - 1)-th first left GOA module and the (a - 1)-th first right GOA module can both be connected to the (a - 1)-th first start signal, the a-th first left GOA module and the a-th first right GOA module can both be connected to the a-th first start signal, the (a + 1)-th first left GOA module and the (a + 1)-th first right GOA module can both be connected to the (a + 1)-th first start signal, and the A-th first left GOA module and the A-th first right GOA module can both be connected to the A-th first start signal.

[0177] Figure 11 At least one embodiment of the shown circuit can also be used to provide a light emission control signal. In this case, the circuit can be a light emission control signal generation circuit included in each light emission control module; the input terminal of the first-stage light emission control signal generation circuit included in the first light emission control module can be connected to a light emission control start signal.

[0178] Figure 11 At least one embodiment of the shown circuit can also be used to provide a third scan signal. In this case, the circuit can be a third GOA circuit included in the third GOA module; the input terminal of the first-stage third GOA circuit included in the first third GOA module is connected to a third start signal.

[0179] Figure 11 At least one embodiment of the shown circuit can be used to provide an N-type scan signal, a light emission control signal, or a third scan signal. When Figure 11 At least one embodiment of the shown circuit provides different signals, the first clock signals provided by the first clock signal terminal CK can be different from each other, and the second clock signals provided by the second clock signal terminal CB can be different from each other.

[0180] Figure 12 FIG. is a circuit diagram of at least one embodiment of a second GOA circuit in at least one embodiment of the present invention. The second GOA circuit is used to provide a P-type scan signal.

[0181] As Figure 12As shown, at least one embodiment of the second GOA circuit may include a fifteenth display control transistor M15, a sixteenth display control transistor M16, a seventeenth display control transistor M17, an eighteenth display control transistor M18, a nineteenth display control transistor M19, a twentieth display control transistor M20, a twenty-first display control transistor M21, a twenty-second display control transistor M22, a twenty-third display control transistor M23, a twenty-fourth display control transistor M24, a fourth capacitor C4, and a fifth capacitor C5.

[0182] In Figure 12 , the one labeled I2 is the second input terminal, the one labeled R2 is the second reset terminal, the one labeled VGL is the low voltage terminal, the one labeled VGH is the high voltage terminal, the one labeled SO2 is the second scan signal output terminal, the one labeled GCK1 is the first output clock signal line, the one labeled GCK2 is the second output clock signal line, and the one labeled GCK3 is the third output clock signal line;

[0183] The second scan signal output terminal is used to provide a second scan signal.

[0184] In at least one embodiment of the present invention, the first output clock signal line GCK1 is used to provide a first output clock signal, the second output clock signal line GCK2 is used to provide a second output clock signal, and the third output clock signal line GCK3 is used to provide a third output clock signal.

[0185] When at least one embodiment of the second GOA circuit is used to provide a P-type scan signal, the second input terminal of the first-stage second GOA circuit included in the second GOA module is connected to a second start signal.

[0186] In at least one embodiment of the present invention, at least one embodiment of the first GOA circuit can be used to provide an N-type scan signal for the first scan line GN, at least one embodiment of the second GOA circuit can be used to provide a P-type scan signal for the second scan line GP, at least one embodiment of the light emission control signal generation circuit can be used to provide a light emission control circuit for the light emission control line EC, and at least one embodiment of the third GOA circuit can be used to provide a third scan signal for the third scan line Sc;

[0187] The structure of at least one embodiment of the first GOA circuit, the structure of at least one embodiment of the light emission control signal generation circuit, and the structure of at least one embodiment of the third GOA circuit can be as Figure 11 shown, and the structure of at least one embodiment of the second GOA circuit can be as Figure 12 shown.

[0188] The present invention is as Figure 4When at least one embodiment of the shown display device is working, each first left GOA module and each first right GOA module can both Figure 8 provide an N-type scanning signal for the gate of T8 in Figure 8 , each second left GOA circuit and each second right GOA circuit can both Figure 8 provide a P-type scanning signal for the gate of T2 in Figure 8 and the gate of T4 in Figure 8 , each light emission control module can Figure 8 provide a light emission control signal for the gate of T5 in Figure 8 and the gate of T6 in

[0189] , each third GOA module can Figure 8 provide a third scanning signal for the gate of T7 in Figure 8 and the gate of T9 in Figure 8 ; or, Figure 8 each first left GOA module and each first right GOA module can both Figure 8 provide an N-type scanning signal for the gate of T8 in Figure 8 each second left GOA circuit can be used to provide a P-type scanning signal for the gate of T2 in Figure 8 each second right GOA circuit can be used to provide a P-type scanning signal for the gate of T4 in

[0190] The refresh driving method described in the embodiments of the present invention is applied to a display device. The display device includes a display panel, and the display panel includes a plurality of pixel circuits arranged in multiple rows and columns. The refresh frequency method includes:

[0191] When it is determined that the picture displayed in a partial display area included in the display panel changes and the picture displayed in another partial display area included in the display panel does not change, control the refresh frequency of the pixel circuits in the partial display area to be a first refresh frequency, and control the refresh frequency of the other partial display area to be less than the first refresh frequency; the partial display area is an updated display area, and the other partial display area is an unupdated display area.

[0192] In the refresh driving method according to the embodiment of the present invention, when the driving module determines that the picture displayed in a partial display area included in the display panel changes, while the picture displayed in another partial display area included in the display panel does not change, the driving module controls the refresh frequency of the pixel circuits in the display area where the picture is updated to be a first refresh frequency, and controls the refresh frequency of the pixel circuits in the display area where the picture is not updated to be less than the first refresh frequency, so as to reduce power consumption while normally displaying the picture.

[0193] The refresh driving method according to at least one embodiment of the present invention includes: when at least one row of pixel circuits is provided in the updated display area, adjusting the refresh frequency of at least one row of pixel circuits in the updated display area by controlling the frequencies of a first start signal and a second start signal.

[0194] Optionally, the display panel further includes a first GOA module and a second GOA module. The first GOA module is configured to provide an N-type scan signal for the at least one row of pixel circuits, and the second GOA module is configured to provide a P-type scan signal for the at least one row of pixel circuits; the first GOA module includes multiple levels of first GOA circuits, and the second GOA module includes multiple groups of second GOA circuits; the first-level first GOA circuit included in the first GOA module accesses the first start signal, and the first-level second GOA circuit included in the second GOA module accesses the second start signal.

[0195] In at least one embodiment of the present invention, two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the non-updated display area are provided in the non-updated display area; each adjacent pixel circuit group includes at least one row of transition pixel circuits;

[0196] The refresh driving method further includes: controlling the refresh frequency of the at least one row of transition pixel circuits to be a second refresh frequency, and the second refresh frequency is less than the first refresh frequency.

[0197] Optionally, non-adjacent pixel circuit groups other than the adjacent pixel circuit groups are further provided in the non-updated display area; each non-adjacent pixel circuit group includes non-adjacent pixel circuits;

[0198] The refresh driving method further includes: controlling the refresh frequency of the non-adjacent pixel circuits to be a third refresh frequency; and the third refresh frequency is less than the second refresh frequency.

[0199] In at least one embodiment of the present invention, when there are M rows and N columns of pixel circuits provided in the updated display area, and N is less than the total number of columns of the pixel circuits included in the display panel, the pixel circuit includes a writing control circuit; a control end of the writing control circuit is electrically connected to a writing control line, a first end of the writing control circuit is electrically connected to a data line, and a second end of the writing control circuit is electrically connected to a data writing node; the writing control circuit is configured to control communication between the data line and the data writing node under the control of a writing control signal provided by the writing control line; M and N are positive integers; the refresh driving method includes:

[0200] Controlling the frequency of the writing control signal accessed by the control ends of the writing control circuits included in the pixel circuits in the same row but different columns from the M - row N - column pixel circuit to be less than the first refresh frequency.

[0201] The display device provided by the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0202] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A display device, characterized in that, It includes a display panel and a driving module; the display panel includes a first display area, a second display area, and a multi-row and multi-column pixel circuit; The driving module is configured to control the refresh frequency of the pixel circuit disposed in the first display area to be a first refresh frequency, and control the refresh frequency of the pixel circuit disposed in the second display area to be different from the first refresh frequency; The driving module is configured to, when it is determined that the picture displayed in a partial display area included in the display panel changes and the picture displayed in another partial display area included in the display panel does not change, control the refresh frequency of the pixel circuit in the partial display area to be the first refresh frequency, and control the refresh frequency of the other partial display area to be less than the first refresh frequency; the partial display area is an updated display area, and the other partial display area is an unupdated display area; the updated display area is the first display area, and the unupdated display area is the second display area; When there are M rows and N columns of pixel circuits disposed in the updated display area, and N is less than the total number of columns of the pixel circuits included in the display panel, the pixel circuit includes a write control circuit; M and N are positive integers; The control end of the write control circuit is electrically connected to a write control line, the first end of the write control circuit is electrically connected to a data line, and the second end of the write control circuit is electrically connected to a data write node; the write control circuit is configured to control the connection between the data line and the data write node under the control of a write control signal provided by the write control line; The driving module is configured to control the frequency of the write control signal applied to the control end of the write control circuit included in the pixel circuits in the same row but different columns from the M - row and N - column pixel circuits, so that the refresh frequency of the pixel circuits in the same row but different columns from the M - row and N - column pixel circuits is less than the first refresh frequency.

2. The display device according to claim 1, wherein The driving module is further configured to, when there is at least one row of pixel circuits disposed in the updated display area, adjust the refresh frequency of the at least one row of pixel circuits in the updated display area by controlling the frequency of a first start signal and the frequency of a second start signal.

3. The display device according to claim 2, wherein, The driving module includes a first updated GOA module and a second updated GOA module; The first updated GOA module is configured to provide an N - type scan signal for the at least one row of pixel circuits; The second updated GOA module is configured to provide a P - type scan signal for the at least one row of pixel circuits; The first updated GOA module includes multiple - stage first updated GOA circuits, and the second updated GOA module includes multiple groups of second updated GOA circuits; The first - stage first updated GOA circuit included in the first updated GOA module accesses the first start signal, and the first - stage second updated GOA circuit included in the second updated GOA module accesses the second start signal.

4. The display device according to claim 2, wherein There are two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area disposed in the unupdated display area; the adjacent pixel circuit group includes at least one row of transition pixel circuits; The driving module is used to control the refresh frequency of at least one row of transition pixel circuits to be a second refresh frequency, where the second refresh frequency is less than the first refresh frequency and greater than the refresh frequency of the other part of the display area.

5. The display device according to claim 4, characterized in that In the unupdated display area, there is also a non-adjacent pixel circuit group other than the adjacent pixel circuit group; the non-adjacent pixel circuit group includes at least one row of pixel circuits. The driving module is used to control the refresh frequency of the pixel circuits included in the non-adjacent pixel circuit group to be a third refresh frequency; the third refresh frequency is less than the second refresh frequency.

6. The display device according to claim 1, characterized in that, The driving module is further used to control the frequency of the write control signal applied to the control terminal of the write control circuit included in the M-row N-column pixel circuits, so that the refresh frequency of the M-row N-column pixel circuits is the first refresh frequency.

7. A refresh driving method, applied to a display device, the display device including a display panel and a driving module; the display panel including a first display area, a second display area, and a pixel circuit of multiple rows and multiple columns; characterized in that, The refresh driving method includes: The driving module controls the refresh frequency of the pixel circuits arranged in the first display area to be the first refresh frequency, and the driving module controls the refresh frequency of the pixel circuits arranged in the second display area to be different from the first refresh frequency. The refresh driving method described above includes: When it is determined that the picture displayed in a part of the display panel changes and the picture displayed in another part of the display panel does not change, control the refresh frequency of the pixel circuits in the part of the display area to be the first refresh frequency, and control the refresh frequency of the other part of the display area to be less than the first refresh frequency. The part of the display area is the updated display area, and the other part of the display area is the unupdated display area; the updated display area is the first display area, and the unupdated display area is the second display area. When there are M rows and N columns of pixel circuits arranged in the updated display area and N is less than the total number of columns of the pixel circuits included in the display panel, the pixel circuits include write control circuits; the control terminal of the write control circuit is electrically connected to the write control line, the first end of the write control circuit is electrically connected to the data line, and the second end of the write control circuit is electrically connected to the data write node; the write control circuit is used to control the connection between the data line and the data write node under the control of the write control signal provided by the write control line; M and N are positive integers; the refresh driving method includes: By controlling the frequency of the write control signal applied to the control terminal of the write control circuit included in the pixel circuits that are in the same row but different columns from the M-row N-column pixel circuits, so that the refresh frequency of the pixel circuits that are in the same row but different columns from the M-row N-column pixel circuits is less than the first refresh frequency.

8. The refresh driving method according to claim 7, wherein It includes: When there is at least one row of pixel circuits arranged in the updated display area, the refresh frequency of at least one row of pixel circuits in the updated display area is adjusted by controlling the frequency of the first start signal and the frequency of the second start signal.

9. The refresh driving method according to claim 8, wherein The display panel further includes a first updated GOA module and a second updated GOA module. The first updated GOA module is configured to provide an N-type scan signal to at least one row of pixel circuits, and the second updated GOA module is configured to provide a P-type scan signal to at least one row of pixel circuits. The first updated GOA module includes multiple stages of first updated GOA circuits, and the second updated GOA module includes multiple groups of second updated GOA circuits. The first stage of the first updated GOA circuits included in the first updated GOA module is connected to the first start signal, and the first stage of the second updated GOA circuits included in the second updated GOA module is connected to the second start signal.

10. The refresh driving method according to claim 8, wherein Two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area are provided in the non-updated display area. The adjacent pixel circuit groups include at least one row of transition pixel circuits. The refresh driving method further includes: controlling the refresh frequency of at least one row of transition pixel circuits to be a second refresh frequency, and the second refresh frequency is less than the first refresh frequency.

11. The refresh driving method according to claim 10, characterized in that, Non-adjacent pixel circuit groups other than the adjacent pixel circuit groups are also provided in the non-updated display area. The non-adjacent pixel circuit groups include non-adjacent pixel circuits. The refresh driving method further includes: controlling the refresh frequency of the non-adjacent pixel circuits to be a third refresh frequency. The third refresh frequency is less than the second refresh frequency.

12. The refresh driving method according to claim 7, wherein It further includes: By controlling the frequency of the write control signal connected to the control terminal of the write control circuit included in the M-row N-column pixel circuits, so that the refresh frequency of the M-row N-column pixel circuits is the first refresh frequency.

Images