Array substrate and manufacturing method thereof

Abstract

This application discloses an array substrate and its fabrication method. A first thin-film transistor (TFT) is disposed in the display area, comprising an amorphous oxide layer as the first semiconductor layer. A second TFT, comprising a crystalline oxide layer as the second semiconductor layer, is disposed in the non-display area. Since the mobility of crystalline oxide is higher than that of amorphous oxide, using crystalline oxide as the second semiconductor layer can improve mobility, ensuring that while reducing the size of the second TFT and achieving a narrow bezel, the second semiconductor layer maintains high mobility, resulting in a strong driving capability for the second TFT. Furthermore, a first insulating portion and a third insulating portion are stacked between the first gate and the first semiconductor layer in the first TFT, with the width of the third insulating portion being smaller than the width of the first insulating portion. Because the width of the third insulating portion is smaller than the width of the first insulating portion, voids are avoided under the film layers, preventing interference with the coverage and adhesion between film layers and the overall performance of the first TFT.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to an array substrate and its fabrication method. Background Technology

[0002] Currently, technologies such as AMOLED, Mini-LED, and Micro-LED require narrow bezel display technology to further improve display panel quality. This necessitates reducing the size of the driving circuitry to achieve narrow bezels in non-display areas, while simultaneously increasing the driving current capability of the GOA (Global Outlet) driving circuitry to meet the driving demands of large display areas. Therefore, it is necessary to solve the problem of reducing the size of the driving thin-film transistors (TFTs) and achieving narrow bezels while simultaneously improving the driving capability of the TFTs. Summary of the Invention

[0003] The purpose of this application is to provide an array substrate and its fabrication method, so as to reduce the size of the driving thin-film transistor while improving the driving capability of the driving thin-film transistor to meet the driving requirements of the display area.

[0004] To address the aforementioned technical problems, this application provides an array substrate, comprising:

[0005] A substrate, the substrate including a display area and a non-display area.

[0006] A first semiconductor layer is disposed on the substrate and located in the display area, the first semiconductor layer comprising amorphous oxide.

[0007] A first insulating layer is disposed on the substrate, the first insulating layer including a first insulating portion disposed on the first semiconductor layer.

[0008] A second semiconductor layer is located in the non-display area and disposed on the substrate, the second semiconductor layer comprising crystalline oxide.

[0009] The second insulating layer is disposed on the substrate and includes a third insulating portion and a fourth insulating portion. The third insulating portion is disposed on the first insulating portion and the width of the third insulating portion is smaller than the width of the first insulating portion. The fourth insulating portion is disposed on the second semiconductor layer.

[0010] A gate layer is disposed on the second insulating layer. The gate layer includes a first gate and a second gate. The first gate is disposed on the third insulating portion, and the second gate is disposed on the fourth insulating portion.

[0011] A third insulating layer is disposed on the substrate and covers the gate layer.

[0012] A source / drain layer is disposed on the third insulating layer. The source / drain layer includes a first source, a second source, a first drain, and a second drain. The first source is connected to one side of the first semiconductor layer, and the first drain is connected to the other side of the first semiconductor layer to form a first thin-film transistor. The second source is connected to one side of the second semiconductor layer, and the second drain is connected to the other side of the second semiconductor layer to form a second thin-film transistor.

[0013] In some embodiments, the width of the first gate is smaller than the width of the third insulating portion. The width of the second gate is smaller than the width of the fourth insulating portion.

[0014] In some embodiments, the first semiconductor layer and the second semiconductor layer have the same thickness.

[0015] In some embodiments, the first insulating layer further includes a second insulating portion located in the non-display area, the second insulating portion being located on the side of the second semiconductor layer near the substrate.

[0016] The width of the second insulating portion is greater than the width of the second semiconductor layer.

[0017] In some embodiments, the array substrate includes a light-shielding layer and a fourth insulating layer, the light-shielding layer being disposed on the substrate, the fourth insulating layer being disposed on the substrate and covering the light-shielding layer, the light-shielding layer being located in the display area; and the first semiconductor layer being disposed on the fourth insulating layer.

[0018] The light-shielding layer overlaps with the first semiconductor layer.

[0019] In some embodiments, the source / drain layer further includes an extension connected to the first source or the first drain, the third insulating layer has a first via exposed to the light-shielding layer, and the extension is connected to the light-shielding layer through the first via.

[0020] In some embodiments, the thickness of the second insulating portion is equal to the thickness of the light-shielding layer.

[0021] In some embodiments, the third insulating layer is further provided with a second via and a third via, the second via exposing the first semiconductor layer, the third via exposing the second semiconductor layer, and the depth of the second via being equal to the depth of the third via.

[0022] The first source electrode is connected to the first semiconductor layer through the second via, and the second source electrode is connected to the second semiconductor layer through the third via.

[0023] This application also provides a method for fabricating an array substrate, comprising the following steps:

[0024] A substrate is provided, the substrate including a display area and a non-display area.

[0025] A first semiconductor layer is formed on the display area of ​​the substrate, the first semiconductor layer comprising amorphous oxide.

[0026] A first insulating layer is formed on the substrate, the first insulating layer including a first insulating portion disposed on the first semiconductor layer.

[0027] A second semiconductor layer is formed on the non-display area of ​​the substrate, the second semiconductor layer comprising crystalline oxide.

[0028] A second insulating layer is formed on the substrate. The second insulating layer includes a third insulating portion and a fourth insulating portion. The third insulating portion is disposed on the first insulating portion, and the fourth insulating portion is disposed on the second semiconductor layer.

[0029] A gate layer is formed on the second insulating layer, the gate layer including a first gate and a second gate, the first gate being disposed on the third insulating portion, the width of the third insulating portion being smaller than the width of the first insulating portion; the second gate being disposed on the fourth insulating portion.

[0030] A third insulating layer is formed on the substrate, and the third insulating layer covers the gate layer.

[0031] A source-drain layer is formed on the third insulating layer. The source-drain layer includes a first source, a second source, a first drain, and a second drain. The first source is connected to one side of the first semiconductor layer, and the first drain is connected to the other side of the first semiconductor layer to form a first thin-film transistor. The second source is connected to one side of the second semiconductor layer, and the second drain is connected to the other side of the second semiconductor layer to form a second thin-film transistor.

[0032] In some embodiments, the method for fabricating the array substrate further includes forming a first gate with a width smaller than the width of the third insulating portion; and forming a second gate with a width smaller than the width of the fourth insulating portion.

[0033] The array substrate provided in this application embodiment has a first thin-film transistor in the display area, comprising an amorphous oxide as the first semiconductor layer, and a second thin-film transistor in the non-display area, comprising a crystalline oxide as the second semiconductor layer. Since the mobility of crystalline oxide is higher than that of amorphous oxide, using crystalline oxide as the second semiconductor layer in the non-display area can improve the mobility of the second semiconductor layer in the non-display area. This ensures that while reducing the size of the second thin-film transistor in the non-display area and achieving a narrow bezel, the second semiconductor layer maintains high mobility, resulting in a strong driving capability for the second thin-film transistor in the non-display area. Furthermore, a first insulating portion and a third insulating portion are stacked between the first gate and the first semiconductor layer in the first thin-film transistor, with the width of the third insulating portion being smaller than the width of the first insulating portion. Because the width of the third insulating portion is smaller than the width of the first insulating portion (i.e., the pattern width of the third insulating portion is small while the pattern width of the first insulating portion is large), voids are avoided under the film layers, which would affect the coverage and adhesion between the film layers, thereby preventing any impact on the overall performance of the first thin-film transistor. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application;

[0036] Figure 2 A flowchart illustrating the method for fabricating an array substrate according to an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of step S1 in the method for fabricating an array substrate provided in the embodiments of this application;

[0038] Figure 4 This is a schematic diagram of step S2 in the method for fabricating an array substrate provided in the embodiments of this application;

[0039] Figure 5 This is a schematic diagram of step S3 in the method for fabricating an array substrate provided in the embodiments of this application;

[0040] Figure 6 This is a schematic diagram of step S4 in the method for fabricating an array substrate provided in the embodiments of this application;

[0041] Figure 7 This is a schematic diagram of step S5 in the method for fabricating an array substrate provided in the embodiments of this application;

[0042] Figure 8 This is a schematic diagram of step S6 in the method for fabricating an array substrate provided in the embodiments of this application;

[0043] Figure 9 This is a schematic diagram of step S7 in the method for fabricating an array substrate provided in the embodiments of this application;

[0044] Figure 10 This is a schematic diagram of step S8 in the method for fabricating an array substrate provided in this application embodiment.

[0045] Reference numerals: 100 - Array substrate; AA - Display area; FA - Non-display area; TFT1 - First thin-film transistor; TFT2 - Second thin-film transistor; 10 - Substrate; 21 - First semiconductor layer; 22 - Second semiconductor layer; 31 - First gate; 32 - Second gate; 40 - Source / drain layer; 41 - First source; 42 - First drain; 43 - Second source; 44 - Second drain; K1 - First via; K2 - Second via; K3 - Third via; L1 - First insulating layer; LB1 - First insulating portion; LB2 - Second insulating portion; L2 - Second insulating layer; LB3 - Third insulating portion; LB4 - Fourth insulating portion; L3 - Third insulating layer; L4 - Fourth insulating layer; L5 - Fifth insulating layer; LS - Light-shielding layer. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] It should be noted that, in the description of this application, the orientations or positional relationships indicated by terms such as "upper," "lower," "front," "back," "left," "right," "inner," and "outer" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0048] Please refer to Figure 1 The array substrate 100 provided in this application embodiment includes:

[0049] The substrate 10 includes a display area AA and a non-display area FA.

[0050] The first semiconductor layer 21 is disposed on the substrate 10 and located in the display area AA. The first semiconductor layer 21 includes amorphous oxide.

[0051] A first insulating layer L1 is disposed on a substrate 10. The first insulating layer L1 includes a first insulating portion LB1, which is disposed on a first semiconductor layer 21.

[0052] The second semiconductor layer 22 is located in the non-display area FA and is disposed on the substrate 10. The second semiconductor layer 22 includes crystalline oxide.

[0053] A second insulating layer L2 is disposed on the substrate 10. The second insulating layer L2 includes a third insulating portion LB3 and a fourth insulating portion LB4. The third insulating portion LB3 is disposed on the first insulating portion LB1, and the width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1. The fourth insulating portion LB4 is disposed on the second semiconductor layer 22.

[0054] A gate layer is disposed on a second insulating layer L2. The gate layer includes a first gate 31 and a second gate 32. The first gate 31 is disposed on a third insulating portion LB3, and the second gate 32 is disposed on a fourth insulating portion LB4.

[0055] The third insulating layer L3 is disposed on the substrate 10 and covers the gate layer.

[0056] The source / drain layer 40 is disposed on the third insulating layer L3. The source / drain layer 40 includes a first source 41, a second source 43, a first drain 42, and a second drain 44. The first source 41 is connected to one side of the first semiconductor layer 21, and the first drain 42 is connected to the other side of the first semiconductor layer 21 to form a first thin film transistor TFT1. The second source 43 is connected to one side of the second semiconductor layer 22, and the second drain 44 is connected to the other side of the second semiconductor layer 22 to form a second thin film transistor TFT2.

[0057] The array substrate 100 provided in this application embodiment has a first thin-film transistor (TFT) 1 disposed in the display area AA, including an amorphous oxide first semiconductor layer 21, and a second thin-film transistor (TFT) 2 disposed in the non-display area, including a crystalline oxide second semiconductor layer 22. Since the mobility of crystalline oxide is higher than that of amorphous oxide, using crystalline oxide as the second semiconductor layer 22 of the non-display area AA can improve the mobility of the second semiconductor layer 22 of the non-display area AA. This ensures that while reducing the size of the second thin-film transistor TFT 2 in the non-display area AA and achieving a narrow bezel, the second semiconductor layer 22 has a high mobility characteristic, and the second thin-film transistor TFT 2 in the non-display area has a strong driving capability.

[0058] Understandably, a single-layer fourth insulating portion LB4 is provided in the non-display area FA, and a stacked first insulating portion LB1 and a third insulating portion LB3 are provided in the display area AA. Since the single-layer fourth insulating portion LB4 is thinner than the stacked first insulating portion LB1 and the third insulating portion LB3, the first thin-film transistor TFT1 can obtain a larger driving current than the second thin-film transistor TFT2 under the same driving voltage, which further enhances the driving capability of the second thin-film transistor TFT2 and is more conducive to reducing the size of the second thin-film transistor TFT2 and realizing a narrow bezel.

[0059] Furthermore, a first insulating portion LB1 and a third insulating portion LB3 are stacked between the first gate 31 and the first semiconductor layer 21 in the first thin-film transistor TFT1. The width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1. Because the width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1, i.e., the pattern of the third insulating portion LB3 is smaller and the pattern of the first insulating portion LB1 is larger, voids are avoided under the film layers, which would affect the coverage and bonding between the film layers, thereby avoiding affecting the overall performance of the first thin-film transistor TFT1.

[0060] Optionally, the first semiconductor layer 21 is made of an oxide material, such as indium gallium zinc oxide (IGZO). The thickness of the first semiconductor layer 21 can be 10-100 nanometers, for example, the thickness of the first semiconductor layer 21 can be 10 nanometers, 20 nanometers, 50 nanometers, 80 nanometers, etc.

[0061] The first insulating layer L1 includes a first insulating portion LB1, which is disposed on the first semiconductor layer 21. Since the first semiconductor layer 21 includes amorphous oxide, which has low tolerance to hydrogen, the first insulating portion LB1 on the first semiconductor layer 21 needs to have a low hydrogen content. The low hydrogen content makes the film layer more compact.

[0062] Optionally, the hydrogen content of the first insulating portion LB1 is less than the hydrogen content of the third insulating layer portion LB3. This setting can reduce the risk of hydrogen particles diffusing into the first semiconductor layer 21 and improve the performance of the first thin film transistor TFT1. It can also ensure that the etching rate of the third insulating portion LB3 is greater than the etching rate of the first insulating portion LB1 during wet etching, thus ensuring that the width of the first insulating portion LB1 is greater than the width of the third insulating portion LB3.

[0063] Therefore, during the preparation process, when the first insulating layer L1 and the second insulating layer L2 are etched to form the first insulating part LB1 and the third insulating part LB3, the third insulating layer LB3 disposed on the first insulating part LB1 is etched faster, and the resulting pattern width is smaller; the first insulating part LB1 is etched slower, and the resulting pattern width is larger.

[0064] The width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1, which avoids the formation of voids under the film layer, thereby affecting the coverage and bonding between the film layers and thus avoiding affecting the overall performance of the first thin film transistor TFT1.

[0065] Furthermore, during the fabrication process, because the first insulating portion LB1 covers the first semiconductor layer 21, the first semiconductor layer 21 remains amorphous and does not crystallize due to the crystallization treatment. Optionally, the first insulating layer L1 is made of silicon dioxide.

[0066] Understandably, the second semiconductor layer 22 includes a crystalline oxide. For oxides of the same material, the crystalline state has a higher mobility than the amorphous state. Consequently, the second thin-film transistor (TFT2) formed by the second semiconductor layer 22 has a smaller size but stronger driving capability. Furthermore, the crystalline oxide has fewer internal defects, reducing the length of carrier diffusion into the channel within the second semiconductor layer 22, thus decreasing the size of the second thin-film transistor (TFT2) and avoiding short-channel effects.

[0067] The thickness of the second semiconductor layer 22 can be 10-100 nanometers, for example, the thickness of the second semiconductor layer 22 can be 10 nanometers, 20 nanometers, 50 nanometers, 80 nanometers, etc. The second semiconductor layer 22 includes a crystalline oxide, and the grain size of the crystalline oxide is 10-1000 nanometers, for example, the grain size can be 10 nanometers, 200 nanometers, 500 nanometers, 800 nanometers, 1000 nanometers, etc.

[0068] It is understandable that if the grain size of the crystalline oxide is too small, it loses its crystallization effect and cannot effectively improve the mobility of the crystalline oxide. When the grain size of the crystalline oxide is too large, the grain size is close to the channel size in the second semiconductor layer 22, and the charge carriers are scattered at the grain interface, which reduces the uniformity of conductivity of the second thin film transistor TFT2.

[0069] The second insulating layer L2 includes a third insulating portion LB3 and a fourth insulating portion LB4. Optionally, the third insulating portion LB3 and the fourth insulating portion LB4 have the same hydrogen content. The third insulating portion LB3 is disposed on the first insulating portion LB1, and the fourth insulating portion LB4 is disposed on the second semiconductor layer 22. Since the second semiconductor layer 22 includes a crystalline oxide, which has high hydrogen tolerance, the film texture of the second insulating layer L2 can be relatively sparse, and the hydrogen content can also be relatively high.

[0070] Optionally, the thickness of the second insulating layer L2 can be 50-200 nanometers, for example, the thickness of the second insulating layer L2 can be 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, etc. Setting the thickness of the second insulating layer L2 is beneficial to improving the field effect while ensuring product yield.

[0071] Optionally, both the source / drain layer 40 and the gate layer may include a first metal layer and a second metal layer, wherein the first metal layer is used to enhance the adhesion between the film layers, and the second metal layer is used for conductivity. Optionally, the first metal layer is made of a transition metal material, such as molybdenum, titanium, chromium, and their alloys, and the second metal layer is made of a metal material with good conductivity, such as copper or aluminum. The first metal layer of the source / drain layer 40 may also be made of a conductive oxide material.

[0072] In this embodiment, the width of the first gate 31 is smaller than the width of the third insulating portion LB3. The width of the second gate 32 is smaller than the width of the fourth insulating portion LB4.

[0073] In other words, the widths of the first insulating portion LB1 and the third insulating portion LB3 are greater than the width of the first gate 31. The portions of the first insulating portion LB1 and the third insulating portion LB3 that are wider than the first gate 31 form a carrier diffusion buffer region in the first semiconductor layer 21. Due to the presence of the diffusion buffer region, carriers in the conductive region of the first semiconductor layer 21 are less likely to diffuse into the channel region, preventing carriers from directly diffusing into the channel region and mitigating the short-channel effect. Therefore, the width of the first gate 31 can be reduced, thereby reducing the size of the first thin-film transistor TFT1 and shrinking the bezel, while preventing the first semiconductor layer 21 from failing due to the short-channel effect.

[0074] In this embodiment, the first semiconductor layer 21 and the second semiconductor layer 22 have the same thickness.

[0075] Understandably, the first semiconductor layer 21 and the second semiconductor layer 22 have the same thickness and can be fabricated using the same process, which is convenient and helps to simplify the manufacturing process.

[0076] In this embodiment of the application, the first insulating layer L1 further includes a second insulating portion LB2 located in the non-display area FA, and the second insulating portion LB2 is located on the side of the second semiconductor layer 22 near the substrate 10.

[0077] The width of the second insulating portion LB2 is greater than the width of the second semiconductor layer 22.

[0078] The first insulating portion LB1 and the second insulating portion LB2 are patterned on the same film layer using the same photomask, which simplifies the process. The arrangement of the second insulating portion LB2 allows the first semiconductor layer 21 and the second semiconductor layer 22 to have similar heights, which facilitates heat treatment and hole opening, further simplifying the process.

[0079] In this embodiment, the array substrate 100 includes a light-shielding layer LS and a fourth insulating layer L4. The light-shielding layer LS is disposed on the substrate 10, and the fourth insulating layer L4 is disposed on the substrate 10 and covers the light-shielding layer LS. The light-shielding layer LS is located in the display area AA. The first semiconductor layer 21 is disposed on the fourth insulating layer L4.

[0080] The light-shielding layer LS is disposed overlapping the first semiconductor layer 21.

[0081] Understandably, the light-shielding layer LS overlaps with the first semiconductor layer 21, which can prevent light from shining on the first thin-film transistor TFT1, improve the stability of the first thin-film transistor TFT1, and improve the uniformity and stability of the large-area display area AA. The non-display area FA does not have the light-shielding layer LS, which saves space in the non-display area FA and further reduces the bezel size.

[0082] Optionally, the light-shielding layer LS may include a first metal layer and a second metal layer, wherein the first metal layer is used to enhance the adhesion between the fourth insulating layer L4 and the substrate 10, and the second metal layer is used for conductivity. Optionally, the first metal layer is made of a transition metal material, such as molybdenum, titanium, chromium, and their alloys, and the second metal layer is made of a metal material with good conductivity, such as copper or aluminum.

[0083] Please refer to Figure 1 and Figure 9 In this embodiment, the source / drain layer 40 further includes an extension portion connected to the first source 41 or the first drain 42. The third insulating layer L3 has a first via K1, which exposes the light-shielding layer LS. The extension portion is connected to the light-shielding layer LS through the first via K1.

[0084] Understandably, the light-shielding layer LS is connected to either the first source 41 or the first drain 42, since the light-shielding layer LS overlaps with the first semiconductor layer 21 and the first gate 31. When the array substrate 100 is operating, the voltage of the first source 41 or the first drain 42 changes with different applied voltages, causing the voltage on the light-shielding layer LS to also change, thus affecting the electrical performance of the first semiconductor layer 21. By connecting the light-shielding layer LS to the first source 41 or the first drain 42, the influence on the electrical performance of the first semiconductor layer 21 can be avoided.

[0085] In this embodiment of the application, the thickness of the second insulating portion LB2 is equal to the thickness of the light-shielding layer LS.

[0086] Understandably, the thickness of the second insulating portion LB2 is equal to the thickness of the light-shielding layer LS, which allows the second semiconductor layer 22 disposed on the second insulating portion LB2 to be at a similar height to the first semiconductor layer 21 disposed on the light-shielding layer LS. This facilitates the subsequent etching of vias for connecting the first semiconductor layer 21 and the second semiconductor layer 22, and helps to simplify the process.

[0087] In this embodiment, the third insulating layer L3 is further provided with a second via K2 and a third via K3, the second via K2 exposing the first semiconductor layer 21, and the third via K3 exposing the second semiconductor layer 22.

[0088] Optionally, the depth of the second via K2 is equal to the depth of the third via K3.

[0089] The first source electrode 41 is connected to the first semiconductor layer 21 through the second via K2, and the second source electrode 43 is connected to the second semiconductor layer 22 through the third via K3.

[0090] Understandably, the same depth as the second via K2 and the third via K3 facilitates the etching of both vias, preventing over-etching that could damage the first semiconductor layer 21 and the second semiconductor layer 22. Because of the same depth, during etching, the second via K2 exposes the first semiconductor layer 21, and the third via K3 exposes the second semiconductor layer 22, preventing incomplete etching that could prevent the source / drain layer 40 from contacting the first / second semiconductor layer 21 / 22, thus simplifying the process. Furthermore, the thickness of the second insulating portion LB2 is equal to the thickness of the light-shielding layer LS, placing the first and second semiconductor layers 21 and 22 at similar heights. The same depth as the third via K3 further facilitates etching, preventing either over-etching or under-etching.

[0091] Optionally, the array substrate 100 further includes a fifth insulating layer L5, which is used to protect the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0092] Optionally, the fifth insulating layer L5 is made of silicon dioxide and has a thickness of 100-500 nanometers. Optionally, the thickness can be 100 nanometers, 300 nanometers, 500 nanometers, etc.

[0093] Please refer to Figure 2 This is a flowchart of a method for fabricating an array substrate 100 according to an embodiment of this application. Accordingly, an embodiment of this application also provides a method for fabricating an array substrate 100, comprising the following steps:

[0094] Step S1: A substrate 10 is provided, the substrate 10 including a display area AA and a non-display area FA.

[0095] Step S2: A first semiconductor layer 21 is formed on the display area AA of the substrate 10. The first semiconductor layer 21 includes amorphous oxide.

[0096] Step S3: A first insulating layer L1 is formed on the substrate 10. The first insulating layer L1 includes a first insulating portion LB1, which is disposed on the first semiconductor layer 21.

[0097] Step S4: A second semiconductor layer 22 is formed on the non-display area FA of the substrate 10. The second semiconductor layer 22 includes crystalline oxide.

[0098] In step S5, a second insulating layer L2 is formed on the substrate 10. The second insulating layer L2 includes a third insulating portion LB3 and a fourth insulating portion LB4. The third insulating portion LB3 is disposed on the first insulating portion LB1, and the width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1. The fourth insulating portion LB4 is disposed on the second semiconductor layer 22.

[0099] Step S6: A gate layer is formed on the second insulating layer L2. The gate layer includes a first gate 31 and a second gate 32. The first gate 31 is disposed on the third insulating portion LB3, and the second gate 32 is disposed on the fourth insulating portion LB4.

[0100] Step S7: A third insulating layer L3 is formed on the substrate 10, and the third insulating layer L3 covers the gate layer.

[0101] In step S8, a source / drain layer 40 is formed on the third insulating layer L3. The source / drain layer 40 includes a first source 41, a second source 43, a first drain 42, and a second drain 44. The first source 41 is connected to one side of the first semiconductor layer 21, and the first drain 42 is connected to the other side of the first semiconductor layer 21 to form a first thin film transistor TFT1. The second source 43 is connected to one side of the second semiconductor layer 22, and the second drain 44 is connected to the other side of the second semiconductor layer 22 to form a second thin film transistor TFT2.

[0102] The method for fabricating the array substrate 100 provided in this application embodiment involves forming a first thin-film transistor (TFT) 1 in the display area AA of the substrate 10, including an amorphous oxide as the first semiconductor layer 21, and forming a second thin-film transistor (TFT) 2 in the non-display area FA, including a crystalline oxide as the second semiconductor layer 22. Since the mobility of crystalline oxide is higher than that of amorphous oxide, using crystalline oxide as the second semiconductor layer 22 in the non-display area FA can improve the mobility of the second semiconductor layer 22 in the non-display area FA. This ensures that while reducing the size of the second thin-film transistor TFT 2 in the non-display area FA and achieving a narrow bezel, the second semiconductor layer 22 has a high mobility, and the second thin-film transistor TFT 2 in the non-display area FA has strong driving capability.

[0103] Furthermore, a first insulating portion LB1 and a third insulating portion LB3 are stacked between the first gate 31 and the first semiconductor layer 21 in the first thin-film transistor TFT1. The width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1. Since the width of the formed third insulating portion LB3 is smaller than the width of the formed first insulating portion LB1, i.e., the pattern width of the formed third insulating portion LB3 is small and the pattern width of the first insulating portion LB1 is large, voids are avoided under the film layers, which would affect the coverage and bonding between the film layers, thereby avoiding affecting the overall performance of the first thin-film transistor TFT1.

[0104] The fabrication method of the array substrate in this embodiment will be described below.

[0105] Please refer to Figure 3 Step S1: A substrate 10 is provided, the substrate 10 including a display area AA and a non-display area FA.

[0106] Optionally, after step S1, the following steps may also be included:

[0107] Step S11: A light-shielding layer LS is formed on the display area AA of the substrate 10.

[0108] In step S12, a fourth insulating layer L4 is formed on the substrate 10, and the fourth insulating layer L4 covers the light-shielding layer LS.

[0109] Proceed to step S2.

[0110] Please refer to Figure 4 In step S2, a first semiconductor layer 21 is formed on the display area AA of the substrate 10. The first semiconductor layer 21 includes amorphous oxide.

[0111] Specifically, an amorphous oxide material layer is deposited on the display area AA of the substrate 10, and a first semiconductor layer 21 is formed by patterning.

[0112] Proceed to step S3.

[0113] Please refer to Figure 5 In step S3, a first insulating layer L1 is formed on the substrate 10. The first insulating layer L1 includes a first insulating portion LB1, which is disposed on the first semiconductor layer 21.

[0114] Specifically, a first insulating layer L1 is formed on the substrate 10, and the first insulating layer L1 covers the first semiconductor layer 21 to form a first insulating portion LB1. Since the first insulating portion LB1 covers the first semiconductor layer 21, it protects the first semiconductor layer 21 and keeps the first semiconductor layer 21 in an amorphous state.

[0115] Optionally, silicon dioxide is deposited on the substrate 10 to form a first insulating layer L1.

[0116] Optionally, the formed first insulating layer L1 further includes a second insulating portion LB2 located in the non-display area FA. The second insulating portion LB2 is located on the side of the second semiconductor layer 22 closest to the substrate 10. The width of the second insulating portion LB2 is greater than the width of the second semiconductor layer 22.

[0117] The first insulating portion LB1 and the second insulating portion LB2 are patterned on the same film layer using the same photomask, which simplifies the process. The arrangement of the second insulating portion LB2 makes the height of the first semiconductor layer 21 and the height of the second semiconductor layer 22 more consistent, which facilitates heat treatment and hole opening, and simplifies the process.

[0118] Proceed to step S4.

[0119] Please refer to Figure 6 In step S4, a second semiconductor layer 22 is formed on the non-display area FA of the substrate 10. The second semiconductor layer 22 includes crystalline oxide.

[0120] Optionally, a crystalline oxide material layer is deposited on the non-display area FA of the substrate 10, and a second semiconductor layer 22 is patterned to form it. Optionally, the deposition temperature is 100-350 degrees Celsius, and the oxygen content in the film-forming atmosphere is 5%-80%. Specifically, the deposition temperature can be 100 degrees Celsius, 200 degrees Celsius, 350 degrees Celsius, etc., and the oxygen content in the film-forming atmosphere can be 5%, 20%, 50%, 80%, etc. The grain size of the deposited crystalline oxide is 10 to 1000 nanometers. For example, the grain size can be 10 nanometers, 200 nanometers, 500 nanometers, 800 nanometers, 1000 nanometers, etc.

[0121] Optionally, the thickness of the second semiconductor layer 22 can be 10-100 nanometers. For example, the thickness of the first semiconductor layer 21 can be 10 nanometers, 20 nanometers, 50 nanometers, 80 nanometers, etc.

[0122] Optionally, an amorphous oxide material layer is deposited on the non-display area FA of the substrate 10, and then subjected to heat treatment to crystallize it, transforming the amorphous oxide layer into a crystalline oxide layer. This crystalline oxide layer is then patterned to form the second semiconductor layer 22. Because the first insulating portion LB1 covers the first semiconductor layer 21, the first semiconductor layer 21 remains amorphous and does not crystallize due to the crystallization treatment. Optionally, the heat treatment temperature is 150-400 degrees Celsius. Specifically, the heat treatment temperature can be 150 degrees Celsius, 200 degrees Celsius, 300 degrees Celsius, 400 degrees Celsius, etc. The grain size of the formed crystalline oxide is 10 to 1000 nanometers. For example, the grain size can be 10 nanometers, 200 nanometers, 500 nanometers, 800 nanometers, 1000 nanometers, etc.

[0123] Understandably, for oxides of the same material, the crystalline state has a higher mobility than the amorphous state. Consequently, the second thin-film transistor (TFT2) formed in the second semiconductor layer 22 is smaller in size but has a stronger driving capability. Furthermore, crystalline oxides have fewer internal defects, reducing the length of carrier diffusion into the channel within the second semiconductor layer 22. This reduces the size of the second thin-film transistor (TFT2) and also avoids the short-channel effect.

[0124] Proceed to step S5.

[0125] Please refer to Figure 7 In step S5, a second insulating layer L2 is formed on the substrate 10. The second insulating layer L2 includes a third insulating portion LB3 and a fourth insulating portion LB4. The third insulating portion LB3 is disposed on the first insulating portion LB1, and the width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1. The fourth insulating portion LB4 is disposed on the second semiconductor layer 22.

[0126] Specifically, a second insulating layer L2 is formed on the substrate 10. The second insulating layer L2 includes a fourth insulating portion LB4, which covers the second semiconductor layer 22.

[0127] Optionally, the thickness of the second insulating layer L2 can be 50-200 nanometers, for example, the thickness of the second insulating layer L2 can be 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, etc. Setting the thickness of the second insulating layer L2 is beneficial to improving the field effect while ensuring product yield.

[0128] Understandably, a single-layer fourth insulating portion LB4 is formed in the non-display area FA, and a stacked first insulating portion LB1 and a third insulating portion LB3 are formed in the display area AA. Since the single-layer fourth insulating portion LB4 is thinner than the stacked first insulating portion LB1 and the third insulating portion LB3, the first thin-film transistor TFT1 can obtain a larger driving current than the second thin-film transistor TFT2 under the same driving voltage, which further enhances the driving capability of the second thin-film transistor TFT2 and is more conducive to reducing the size of the second thin-film transistor TFT2 and realizing a narrow bezel.

[0129] Proceed to step S6.

[0130] Please refer to Figure 8 In step S6, a gate layer is formed on the second insulating layer L2. The gate layer includes a first gate 31 and a second gate 32. The first gate 31 is disposed on the third insulating portion LB3, and the second gate 32 is disposed on the fourth insulating portion LB4.

[0131] Specifically, a metal material layer is deposited on the second insulating layer L2, a photoresist is placed on the metal material layer, the metal layer is patterned using photolithography, and then a first gate 31 and a second gate 32 are etched using wet etching. The first gate 31 is disposed on the third insulating portion LB3, and the second gate 32 is disposed on the fourth insulating portion LB4.

[0132] Using photoresist, the first gate 31, and the second gate 32 as photomasks, dry etching is employed to etch the first insulating layer L1 and the second insulating layer L2, exposing both sides of the first semiconductor layer 21 and the second semiconductor layer 22, forming a first insulating portion LB1, a third insulating portion LB3, and a fourth insulating portion LB4. The width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1. Optionally, the width of the formed first gate 31 is smaller than the width of the formed third insulating portion LB3; and the width of the formed second gate 32 is smaller than the width of the formed fourth insulating portion LB4.

[0133] Conducting a conductive process is performed on the exposed first semiconductor layer 21 and second semiconductor layer 22 to form a conductive region.

[0134] During the fabrication process, when etching the first insulating layer L1 and the second insulating layer L2 to form the first insulating portion LB1 and the third insulating portion LB3, the third insulating layer LB3 disposed on the first insulating portion LB1 is etched faster, resulting in a smaller pattern width, while the first insulating portion LB1 is etched slower, resulting in a larger pattern width.

[0135] The width of the third insulating portion LB3 is smaller than the width of the first insulating portion LB1, which avoids the formation of voids under the film layer, thereby affecting the coverage and bonding between the film layers and thus avoiding affecting the overall performance of the first thin film transistor TFT1.

[0136] In this design, the widths of the first insulating portion LB1 and the third insulating portion LB3 are greater than the width of the first gate 31. The portions of the first insulating portion LB1 and the third insulating portion LB3 that are wider than the first gate 31 form a carrier diffusion buffer region in the first semiconductor layer 21. Due to the presence of the diffusion buffer region, carriers in the conductive region of the first semiconductor layer 21 are less likely to diffuse into the channel region, preventing direct diffusion of carriers into the channel region and mitigating the short-channel effect. Therefore, the width of the first gate 31 can be reduced, thereby reducing the size of the first thin-film transistor TFT1 and shrinking the bezel, while preventing the first semiconductor layer 21 from failing due to the short-channel effect.

[0137] Proceed to step S7.

[0138] Please refer to Figure 9 In step S7, a third insulating layer L3 is formed on the substrate 10, and the third insulating layer L3 covers the gate layer.

[0139] Specifically, a third insulating layer L3 is formed on the substrate 10, the third insulating layer L3 covers the gate layer, and vias are formed by etching the third insulating layer L3.

[0140] Proceed to step S8.

[0141] Please refer to Figure 10 In step S8, a source / drain layer 40 is formed on the third insulating layer L3. The source / drain layer 40 includes a first source 41, a second source 43, a first drain 42, and a second drain 44. The first source 41 is connected to one side of the first semiconductor layer 21, and the first drain 42 is connected to the other side of the first semiconductor layer 21 to form a first thin film transistor TFT1. The second source 43 is connected to one side of the second semiconductor layer 22, and the second drain 44 is connected to the other side of the second semiconductor layer 22 to form a second thin film transistor TFT2.

[0142] Optionally, step S9 may be included after step S8.

[0143] Step S9: A fifth insulating layer L5 is formed on the source / drain layer 40.

[0144] Specifically, silicon dioxide is deposited on the source / drain layer 40 and patterned to form a fifth insulating layer L5. The thickness can be 100-500 nanometers. Optionally, the thickness can be 100 nanometers, 300 nanometers, 500 nanometers, etc.

[0145] This completes the fabrication of the array substrate 100.

[0146] The array substrate provided in this application embodiment has a first thin-film transistor disposed in the display area, including an amorphous oxide as the first semiconductor layer, and a second thin-film transistor disposed in the non-display area, including a crystalline oxide as the second semiconductor layer. Since the mobility of crystalline oxide is higher than that of amorphous oxide, using crystalline oxide as the second semiconductor layer in the non-display area can improve the mobility of the second semiconductor layer in the non-display area. This ensures that while reducing the size of the second thin-film transistor in the non-display area and achieving a narrow bezel, the second semiconductor layer has high mobility, and the second thin-film transistor in the non-display area has strong driving capability.

[0147] Furthermore, a first insulating portion and a third insulating portion are stacked between the first gate and the first semiconductor layer in the first thin-film transistor, with the width of the third insulating portion being smaller than the width of the first insulating portion. Because the width of the third insulating portion is smaller than the width of the first insulating portion—that is, the upper pattern of the third insulating portion is smaller and the lower pattern of the first insulating portion is larger—voids are avoided from forming under the film layers, thus preventing them from affecting the coverage and adhesion between the film layers and consequently avoiding impacting the overall performance of the first thin-film transistor.

[0148] The array substrate and its fabrication method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An array substrate, characterized in that, include: A substrate, the substrate including a display area and a non-display area; A first semiconductor layer is disposed on the substrate and located in the display area, the first semiconductor layer comprising amorphous oxide; A first insulating layer is disposed on the substrate, the first insulating layer includes a first insulating portion, the first insulating portion is disposed on the first semiconductor layer; A second semiconductor layer is located in the non-display area and disposed on the substrate, the second semiconductor layer comprising crystalline oxide; A second insulating layer is disposed on the substrate. The second insulating layer includes a third insulating portion and a fourth insulating portion. The third insulating portion is disposed on the first insulating portion, and the width of the third insulating portion is smaller than the width of the first insulating portion. The fourth insulating portion is disposed on the second semiconductor layer; A gate layer is disposed on the second insulating layer. The gate layer includes a first gate and a second gate. The first gate is disposed on the third insulating portion, and the second gate is disposed on the fourth insulating portion. A third insulating layer is disposed on the substrate and covers the gate layer; A source / drain layer is disposed on the third insulating layer. The source / drain layer includes a first source, a second source, a first drain, and a second drain. The first source is connected to one side of the first semiconductor layer, and the first drain is connected to the other side of the first semiconductor layer to form a first thin-film transistor. The second source is connected to one side of the second semiconductor layer, and the second drain is connected to the other side of the second semiconductor layer to form a second thin-film transistor. The first insulating layer further includes a second insulating portion located in the non-display area, the second insulating portion being located on the side of the second semiconductor layer closer to the substrate. The thickness of the second insulating part is equal to the thickness of the light-shielding layer; The third insulating layer is further provided with a second via and a third via, the second via exposing the first semiconductor layer, the third via exposing the second semiconductor layer, and the depth of the second via being equal to the depth of the third via; The first source electrode is connected to the first semiconductor layer through the second via, and the second source electrode is connected to the second semiconductor layer through the third via; The plane containing the first source is flush with the plane containing the first drain, the plane containing the second source, and the plane containing the second drain.

2. The array substrate according to claim 1, characterized in that, The width of the first gate is smaller than the width of the third insulating portion; the width of the second gate is smaller than the width of the fourth insulating portion.

3. The array substrate according to claim 1, characterized in that, The first semiconductor layer and the second semiconductor layer have the same thickness.

4. The array substrate according to claim 1, characterized in that, The width of the second insulating portion is greater than the width of the second semiconductor layer.

5. The array substrate according to claim 1, characterized in that, The array substrate includes a light-shielding layer and a fourth insulating layer. The light-shielding layer is disposed on the substrate, and the fourth insulating layer is disposed on the substrate and covers the light-shielding layer. The light-shielding layer is located in the display area. The first semiconductor layer is disposed on the fourth insulating layer. The light-shielding layer overlaps with the first semiconductor layer.

6. The array substrate according to claim 5, characterized in that, The source / drain layer further includes an extension portion connected to the first source or the first drain. The third insulating layer has a first via, which exposes the light-shielding layer. The extension portion is connected to the light-shielding layer through the first via.

7. A method for fabricating an array substrate, characterized in that, Includes the following steps: A substrate is provided, the substrate including a display area and a non-display area; A first semiconductor layer is formed on the display area of ​​the substrate, the first semiconductor layer comprising amorphous oxide; A first insulating layer is formed on the substrate, the first insulating layer including a first insulating portion, the first insulating portion being disposed on the first semiconductor layer; A second semiconductor layer is formed on a non-display area of ​​the substrate, the second semiconductor layer comprising a crystalline oxide; A second insulating layer is formed on the substrate. The second insulating layer includes a third insulating portion and a fourth insulating portion. The third insulating portion is disposed on the first insulating portion, and the width of the third insulating portion is smaller than the width of the first insulating portion. The fourth insulating portion is disposed on the second semiconductor layer. A gate layer is formed on the second insulating layer, the gate layer including a first gate and a second gate, the first gate being disposed on the third insulating portion and the second gate being disposed on the fourth insulating portion; A third insulating layer is formed on the substrate, and the third insulating layer covers the gate layer; A source-drain layer is formed on the third insulating layer. The source-drain layer includes a first source, a second source, a first drain, and a second drain. The first source is connected to one side of the first semiconductor layer, and the first drain is connected to the other side of the first semiconductor layer to form a first thin-film transistor. The second source is connected to one side of the second semiconductor layer, and the second drain is connected to the other side of the second semiconductor layer to form a second thin-film transistor. The first insulating layer further includes a second insulating portion located in the non-display area, the second insulating portion being located on the side of the second semiconductor layer closer to the substrate. The thickness of the second insulating part is equal to the thickness of the light-shielding layer; The third insulating layer is further provided with a second via and a third via, the second via exposing the first semiconductor layer, the third via exposing the second semiconductor layer, and the depth of the second via being equal to the depth of the third via; The first source electrode is connected to the first semiconductor layer through the second via, and the second source electrode is connected to the second semiconductor layer through the third via; The plane containing the first source is flush with the plane containing the first drain, the plane containing the second source, and the plane containing the second drain.

8. The method for fabricating an array substrate according to claim 7, characterized in that, The width of the first gate formed is smaller than the width of the third insulating portion formed; the width of the second gate formed is smaller than the width of the fourth insulating portion formed.

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