Array substrate and display panel

Abstract

This invention provides an array substrate and a display panel. The array substrate includes: a substrate; an active layer located on one side of the substrate, including a first active portion and a second active portion; a first insulating layer located on the side of the active layer away from the substrate and covering the active layer; and a first opening provided on the first active portion, the first opening exposing the first insulating layer. This invention integrates the pixel driving element and the photosensitive element on the array substrate by placing the semiconductor structure of the pixel driving element and the semiconductor structure of the photosensitive element within the same active layer. Simultaneously, by providing a first opening within the photosensitive element, corresponding to the semiconductor structure of the photosensitive element, the photosensitive area and the transmittance of the photosensitive side of the photosensitive element are increased, thereby improving the photosensitive effect of the photosensitive element.

Description

Technical Field

[0001] This application relates to the field of display, and more particularly to an array substrate and a display panel. Background Technology

[0002] Photoelectric sensors can be used in various fields such as non-contact measurement, fingerprint recognition, ambient light detection, ultraviolet and infrared detection, and communication.

[0003] In existing display panel sensing technologies, light sensors are mostly externally mounted, requiring the display device and sensor to be processed separately, and then optical adhesive is used to bond the display device and sensor layers together. This method has a complex manufacturing process, high production costs, and is not conducive to industrialization.

[0004] Existing technologies propose an in-screen photosensitive sensor device, which fabricates the display device and the photosensitive sensor on the same substrate, thus appropriately reducing the complexity of the manufacturing process compared to traditional technologies. However, when the display device and the sensor are fabricated on the same substrate, the design of the sensor is limited by the performance of the display device and the sensor, as well as the actual layout, making it difficult for the sensor to achieve the desired effect. Summary of the Invention

[0005] The present invention provides an array substrate and a display panel, which integrates display devices and light sensors in the same array substrate to improve the light sensing performance of the light sensors.

[0006] To solve the above problems, the technical solution provided by the present invention is as follows:

[0007] This invention provides an array substrate, the array substrate comprising:

[0008] Substrate;

[0009] An active layer, located on one side of the substrate, includes a first active portion and a second active portion;

[0010] A first insulating layer is located on the side of the active layer away from the substrate and covers the active layer;

[0011] A first opening is provided on the first active part, and the first opening exposes the first insulating layer.

[0012] Optionally, in some embodiments of the present invention, the surface of the first insulating layer on the side away from the substrate includes a first surface and a second surface, the first surface being the bottom surface of the first opening, and the second surface surrounding the first surface; the first surface is recessed into or flush with the second surface.

[0013] Optionally, in some embodiments of the present invention, the first surface includes a third surface and a fourth surface, the fourth surface surrounding the third surface and the second surface surrounding the fourth surface; the fourth surface is recessed within the third surface and the second surface, and the third surface is recessed within the second surface.

[0014] Optionally, in some embodiments of the present invention, the depth of the fourth surface recessed relative to the second surface ranges from 50 micrometers to 200 micrometers, and the depth of the third surface recessed relative to the second surface ranges from 50 micrometers to 150 micrometers.

[0015] Optionally, in some embodiments of the present invention, the array substrate further includes a second insulating layer and a third insulating layer, the second insulating layer and the third insulating layer being disposed sequentially on the first insulating layer; the first opening penetrates the second insulating layer and the third insulating layer.

[0016] Optionally, in some embodiments of the present invention, the first active part is further provided with a second opening, the second opening penetrating the first insulating layer and the second insulating layer, and exposing the first active part; the opening diameter of the first opening is larger than the opening diameter of the second opening.

[0017] Optionally, in some embodiments of the present invention, the array substrate further includes a first conductive layer, the first conductive layer including a first electrode and a second electrode, the first electrode and the second electrode being connected to the two ends of the first active portion through the second opening.

[0018] Optionally, in some embodiments of the present invention, the array substrate further includes a transparent conductive layer disposed on the third insulating layer; the transparent conductive layer includes a first transparent electrode, the first transparent electrode covering the first opening.

[0019] Optionally, in some embodiments of the present invention, the first transparent electrode is electrically connected to the first electrode or the second electrode.

[0020] Optionally, in some embodiments of the present invention, the first active portion includes a first channel region and two first doped regions, the two first doped regions being located on both sides of the first channel region, and the projection of the bottom surface of the first opening on the substrate covers the projection of the first channel region on the substrate.

[0021] Optionally, in some embodiments of the present invention, the array substrate further includes a reflective layer disposed between the substrate and the active layer; the reflective layer includes a first reflective portion, the projection of the first active portion on the substrate falling within the projection of the first reflective portion on the substrate.

[0022] Optionally, in some embodiments of the present invention, the array substrate includes a pixel driving element and a photosensitive element, the photosensitive element including a first active portion and the pixel driving element including a second active portion.

[0023] Meanwhile, embodiments of the present invention provide a display panel, the display panel including the array substrate described in any embodiment of the present invention.

[0024] This invention provides an array substrate and a display panel. By placing the semiconductor structure of the pixel driving element and the semiconductor structure of the photosensitive element in the same active layer, the pixel driving element and the photosensitive element are integrated on the array substrate. At the same time, a first opening is provided in the photosensitive element, which corresponds to the semiconductor structure of the photosensitive element, thereby increasing the photosensitive area of ​​the photosensitive element and the light transmittance of the photosensitive side of the photosensitive element, and improving the light-sensing effect of the photosensitive element. Attached Figure Description

[0025] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of a first structure of an array substrate provided in an embodiment of the present invention;

[0027] Figure 2 for Figure 1 A magnified structural diagram of region 106 in the middle;

[0028] Figure 3 This is a schematic diagram of a second structure of the array substrate provided in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of a third structure of the array substrate provided in an embodiment of the present invention;

[0030] Figure 5 A flowchart illustrating the method for fabricating an array substrate according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the structure of the array substrate fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions in the embodiments and / or examples of the present invention will be clearly and completely described below with reference to specific implementation schemes. Obviously, the embodiments and / or examples described below are only a part of the embodiments and / or examples of the present invention, and not all of them. Based on the embodiments and / or examples of the present invention, all other embodiments and / or examples obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0033] The directional terms used in this invention, such as [up], [down], [left], [right], [front], [back], [inside], [outside], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0034] To address the problems of limited sensor design and difficulty in achieving the desired effect when display devices and sensors are fabricated on the same substrate, this invention provides an array substrate that can solve these issues.

[0035] In one embodiment, please refer to Figures 1 to 3 , Figure 1 This diagram illustrates a first structural schematic of an array substrate provided in an embodiment of the present invention. Figure 2 This diagram illustrates a second structural schematic of the array substrate provided in an embodiment of the present invention. Figure 3 A schematic diagram of a third structure of the array substrate provided in an embodiment of the present invention is shown. For example... Figures 1 to 3 As shown, the array substrate includes:

[0036] Substrate 11;

[0037] The active layer 14 is located on one side of the substrate 11 and includes a first active portion 141 and a second active portion 142.

[0038] The first insulating layer 15 is located on the side of the active layer 14 away from the substrate 11 and covers the active layer 14;

[0039] The first active part 141 has a first opening 103, which exposes the first insulating layer 15.

[0040] This invention provides an array substrate that integrates the pixel driving element and the photosensitive element on the array substrate by placing the semiconductor structure of the pixel driving element and the semiconductor structure of the photosensitive element in the same active layer. At the same time, a first opening is provided in the photosensitive element, which corresponds to the semiconductor structure of the photosensitive element, thereby increasing the photosensitive area of ​​the photosensitive element and the transmittance of the photosensitive side of the photosensitive element, and improving the photosensitive effect of the photosensitive element.

[0041] Example 1

[0042] Please refer to Figure 1 The array substrate provided in this embodiment of the invention includes a pixel driving element 101 and a photosensitive element 102. The first active portion 141 is a semiconductor structure of the photosensitive element 102, and the second active portion 142 is a semiconductor structure of the pixel driving element 101. The first active portion 141 includes a first channel region 143 and a first doped region. The first doped region is located on both sides of the first channel region 143. The first doped region includes a first lightly doped region 144 and a first heavily doped region 145. The first lightly doped region 144 connects the first heavily doped region 145 and the first channel region 143. The projection of the bottom surface of the first opening 103 onto the substrate 11 covers the projection of the first channel region 143 onto the substrate 11, thereby increasing the light sensitivity of the first channel region 143. Similarly, the second active region 142 includes a second channel region 146 and a second doped region. The second doped region is located on both sides of the second channel region 146. The second doped region includes a second lightly doped region 147 and a second heavily doped region 148. The second lightly doped region 147 connects the second heavily doped region 148 and the second channel region 146. In one embodiment, the active layer is a low-temperature polycrystalline silicon layer.

[0043] The first insulating layer 15 is a transparent insulating layer, and the material of the first insulating layer 15 is usually a transparent inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0044] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1A magnified structural diagram of region 106. The surface of the first insulating layer 15 away from the substrate 11 includes a first surface 151 and a second surface 152. The first surface 151 corresponds to the bottom surface of the first opening 103, and the second surface 152 surrounds the first surface 151. The first surface 151 is recessed into or flush with the second surface 152. The first surface 151 further includes a third surface 153 and a fourth surface 154. The fourth surface 154 surrounds the third surface 153, and the second surface 152 surrounds the fourth surface 154. The fourth surface 154 is recessed into the third surface 153 and the second surface 152. The third surface 153 is flush with or recessed into the second surface 152. The depth L1 of the recess of the fourth surface 154 relative to the second surface 152 ranges from 50 micrometers to 200 micrometers, and the depth L2 of the recess of the third surface 153 relative to the second surface 152 ranges from 50 micrometers to 150 micrometers.

[0045] The array substrate further includes a second insulating layer 17 and a third insulating layer 19, which are sequentially disposed on the first insulating layer 15. The first opening 103 penetrates the second insulating layer 17 and the third insulating layer 19. The projection of the first surface 151 on the substrate 11 covers the projection of the first channel region 143 on the substrate 11. The first active portion 141 and the second active portion 142 are each provided with a second opening 104, which penetrates the first insulating layer 15 and the second insulating layer 17, and exposes two first heavily doped regions 145 of the first active portion 141 and two second heavily doped regions 148 of the second active portion 142. The third insulating layer 19 is also provided with a third opening 105, which penetrates the third insulating layer 19. The opening diameter D1 of the first opening 103 is larger than the opening diameter D2 of the second opening 104, and the opening diameter D1 of the first opening 103 is larger than the opening diameter D3 of the third opening 105.

[0046] The array substrate further includes a first conductive layer 18 and a third insulating layer 19, wherein the first conductive layer 18 is disposed between the second insulating layer 17 and the third insulating layer 19. The first conductive layer 18 includes a first electrode 181, a second electrode 182, a third electrode 183, and a fourth electrode 184; the third electrode 183 and the fourth electrode 184 are respectively connected to both ends of the second active portion 142, specifically, they are respectively connected to the two second heavily doped regions 148 through the second opening 104. The third electrode 183 and the fourth electrode 184 are respectively the source and drain of the pixel driving element, or the third electrode 183 and the fourth electrode 184 are respectively the drain and source of the pixel driving element. The first electrode 181 and the second electrode 182 are respectively electrically connected to both ends of the first active portion 141, specifically, they are respectively connected to the two first heavily doped regions 145 through the second opening 104.

[0047] The array substrate further includes a transparent conductive layer 21, which is disposed on the side of the third insulating layer 19 away from the second insulating layer 17. The transparent conductive layer 21 includes a second transparent electrode 211, which is connected to the fourth electrode 184 through the third opening 105. The material of the transparent conductive layer 21 includes, but is not limited to, indium tin oxide, indium zinc oxide, and indium gallium zinc oxide.

[0048] In this embodiment, the photosensitive element 102 is a photodiode. By setting the photosensitive element 102 as a photodiode and providing a first opening 103 on the photosensitive side of the semiconductor structure of the photodiode, the photosensitive side of the photodiode is free of a light-shielding film layer, thereby increasing the light-receiving area of ​​the photodiode and improving its light-sensing effect.

[0049] The array substrate further includes a second conductive layer 16, which is disposed between the first insulating layer 15 and the second insulating layer 17, and the second insulating layer 17 is disposed between the second conductive layer 16 and the first conductive layer 18. The second conductive layer 16 includes a fifth electrode 161, the projection of which on the substrate 11 overlaps with the projection of the second channel region 146 on the substrate 11, and the fifth electrode 161 is the gate of the pixel driving element 101.

[0050] Furthermore, the array substrate also includes a reflective layer 12 and a buffer layer 13. The reflective layer 12 is disposed between the substrate 11 and the active layer 14, and the buffer layer 13 is disposed between the reflective layer 12 and the active layer 14. The reflective layer 12 includes a first reflective portion 121 and a second reflective portion 122. The projection of the first active portion 141 on the substrate 11 falls within the projection of the first reflective portion 121 on the substrate 11, and the projection of the second active portion 142 on the substrate 11 falls within the projection of the second reflective portion 122 on the substrate 11. The second reflective portion 122 is used to block the influence of light incident from the substrate 11 side on the second active portion 142; the first reflective portion 121 is used to block the influence of light incident from the substrate 11 side on the first active portion 141, and at the same time, it is used to reflect light incident from the first insulating layer 15 side to the first active portion 141, thereby increasing the photosensitivity of the first active portion 141 and improving the photosensitivity performance of the photosensitive element 102. The material of the reflective layer 12 is preferably a metal material or its alloy with good reflectivity.

[0051] When the pixel driving element 101 is a thin-film transistor with a bottom gate structure, the second conductive layer is located between the substrate and the active layer 14, and the second insulating layer is disposed between the second conductive layer and the active layer 14. The second conductive layer includes a fifth electrode and a reflective electrode. The projection of the fifth electrode on the substrate 11 overlaps with the projection of the second channel region 146 on the substrate 11. The projection of the reflective electrode on the substrate 11 covers the projection of the first channel region 143 on the substrate 11. The reflective electrode is used to block the influence of light incident from the substrate 11 side on the first active portion 141, and at the same time, it is used to reflect light incident from the first insulating layer 15 side to the first active portion 141, thereby increasing the light sensitivity of the first active portion 141 and improving the photosensitivity performance of the photosensitive element 102.

[0052] Example 2

[0053] Please refer to Figure 3In this embodiment, the basic structure of the array substrate is similar to that in Embodiment 1. The similar structures will not be described in detail here; please refer to Embodiment 1 above. The difference between this embodiment and Embodiment 1 is that the photosensitive element 102 is a thin-film transistor with a transparent top-gate structure. The transparent conductive layer 21 includes a second transparent electrode 211 and a first transparent electrode 212, with the first transparent electrode 212 covering the first opening 103. The projection of the first transparent electrode 212 onto the substrate 11 at least covers the first channel region 143, and the first transparent electrode 212 is the gate of the photosensitive element 102; the first electrode 181 is the source of the photosensitive element 102 and the second electrode 182 is the drain of the photosensitive element 102, or the first electrode 181 is the drain of the photosensitive element 102 and the second electrode 182 is the source of the photosensitive element 102. Further, the first transparent electrode 212 covers the bottom and side surfaces of the first opening and extends to the upper surface of the third insulating layer 19.

[0054] In this embodiment, by setting the photosensitive element 102 as a thin-film transistor with a transparent top gate structure, when light is incident from the first transparent electrode 212 side, the photosensitive element 102 has a larger light-receiving area, better light-sensing effect, and higher sensitivity compared to a traditional thin-film transistor structure photosensitive element.

[0055] Example 3

[0056] Please refer to Figure 4 In this embodiment, the basic structure of the array substrate is similar to that in Embodiments 1 and 2. The similar structures will not be described in detail here; please refer to Embodiments 1 and 2 above for details. The difference between this embodiment and Embodiments 1 and 2 is that the first transparent electrode 212 is connected to the first electrode 181 through the third opening 105.

[0057] Compared to Embodiment 2, this embodiment electrically connects the source or drain of the photosensitive element 102 to the gate, reducing the gate signal traces of the photosensitive element 102 and saving space on the array substrate.

[0058] In one embodiment, when the array substrate is applied to an FFS mode LCD display panel, the array substrate further includes a planarization layer and a common electrode layer, the planarization layer being located between the common electrode layer and the second conductive layer, and the common electrode layer being located between the planarization layer and the third insulating layer.

[0059] Accordingly, this invention also provides a method for preparing an array substrate, which is used to prepare the array substrate provided in this invention. Please refer to... Figure 5 and Figure 6 , Figure 5 A flowchart illustrating the fabrication method of the array substrate provided in an embodiment of the present invention is shown. Figure 6 A schematic diagram of the fabrication method of the array substrate provided in an embodiment of the present invention is shown. The fabrication method includes:

[0060] Step B1: Provide a substrate, fabricate a reflective layer on the substrate, and pattern the reflective layer to form a first reflective portion and a second reflective portion; please refer to [link / reference needed] for details. Figure 6 (a)

[0061] Step B2: A buffer layer and an active layer are sequentially fabricated on the reflective layer, and the active layer is patterned to form a first active portion and a second active portion; please refer to [reference needed] for details. Figure 6 (b) This step specifically includes: preparing the buffer layer 13 on the reflective layer 12; depositing an amorphous silicon layer on the buffer layer 13 and converting the amorphous silicon into polycrystalline silicon through an excimer laser annealing process (ELA) to form a low-temperature polycrystalline silicon layer; patterning the low-temperature polycrystalline silicon layer to form the second active portion 142 and the first active portion 141; and performing phosphorus ion heavy doping on both ends of the first active portion 141 and both ends of the second active portion 142 to form a first heavily doped region 145 and a second heavily doped region 148.

[0062] Step B3: Sequentially fabricate a first insulating layer and a second conductive layer on the active layer, and pattern the second conductive layer to form a fifth electrode and a sixth electrode; wherein, the projection of the fifth electrode 161 on the substrate 11 partially overlaps with the projection of the second active portion 142 on the substrate 11, and the projection of the sixth electrode 162 on the substrate 11 partially overlaps with the projection of the first active portion 141 on the substrate 11. (See details in [link to relevant documentation]). Figure 6 (c) Following this step, the method for fabricating the array substrate further includes: using the fifth electrode 161 and the sixth electrode 162 as self-reference masks, lightly doping the second active portion 142 and the first active portion 141 with phosphorus ions to form a second lightly doped region 147 and a first lightly doped region 144.

[0063] Step B4: A second insulating layer is fabricated on the second conductive layer, and a second opening is patterned to penetrate the second insulating layer and the first insulating layer; wherein the second opening 104 exposes the first heavily doped region 145 and the second heavily doped region 148, respectively. (See details below.) Figure 6 (d)

[0064] Step B5: A first conductive layer is fabricated on the second insulating layer, and the first conductive layer is patterned to form a first electrode, a second electrode, a third electrode, and a fourth electrode; wherein, the first electrode 181 and the second electrode 182 are electrically connected to the first heavily doped region 145 through the second opening 104, and the third electrode 183 and the fourth electrode 184 are electrically connected to the second heavily doped region 148 through the second opening 104, respectively. Please refer to [the relevant documentation] for details. Figure 6 Middle (e).

[0065] Step B6: Prepare a third insulating layer on the first conductive layer, and pattern a third opening penetrating the third insulating layer and a first opening penetrating the third insulating layer and the second insulating layer; wherein the third opening exposes the third electrode 183 or the fourth electrode 184, and the first opening 103 exposes the sixth electrode 162. See details below. Figure 6 (f)

[0066] In one embodiment, when the array substrate is applied to an FFS mode LCD display panel, between step B6 and step B5, the fabrication method further includes: fabricating a planarization layer on the first conductive layer, and fabricating a common electrode layer on the planarization layer.

[0067] Step B7: Remove the sixth electrode using an etching process; please refer to [link / reference needed] for details. Figure 6 Middle (g).

[0068] After etching is completed, on the surface of the first insulating layer 15 away from the substrate 11, the portion corresponding to the first opening 103 is the first surface 151, and the portion other than the first surface 151 is the second surface 152, which surrounds the first surface 151; in the first surface 151, the portion corresponding to the sixth electrode 162 is the third surface 153, and the portion other than the third surface 153 is the fourth surface 154, which surrounds the third surface 153, and the second surface 152 surrounds the fourth surface 154.

[0069] In one embodiment, the etching process for removing the sixth electrode 162 specifically employs a dry etching process. During dry etching, the etching gas simultaneously etches the material of the first insulating layer 15, and the etching selectivity of the etching gas for the sixth electrode 162 is greater than that for the first insulating layer 15. This results in the fourth surface 154 being recessed towards the substrate 11 relative to the second surface 152 after the sixth electrode 162 is removed by dry etching. To ensure complete removal of the sixth electrode 162, the third surface 153 is typically recessed towards the substrate 11 relative to the second surface 152, and the depth of the recess of the third surface 153 towards the substrate 11 is less than the depth of the recess of the fourth surface 154 towards the substrate 11. The depth of the third surface 153 recessed toward the substrate 11 ranges from 50 micrometers to 200 micrometers, and the depth of the fourth surface 154 recessed toward the substrate 11 ranges from 50 micrometers to 150 micrometers.

[0070] In another embodiment, the etching process to remove the sixth electrode 162 specifically involves using an etching solution prepared by mixing phosphoric acid, nitric acid, acetic acid, etc., in a certain proportion, to perform wet etching to remove the sixth electrode 162. Similarly, during the wet etching process, the etching solution etches the material of the first insulating layer 15. Compared with dry etching, the wet etching solution has a greater selectivity in etching the sixth electrode 162. After the sixth electrode is removed by wet etching, the recess depth of the fourth surface 154 towards the substrate 11 is smaller.

[0071] Step B8: Prepare a transparent conductive layer on the third insulating layer and pattern the transparent conductive layer.

[0072] In a first embodiment, patterning the transparent conductive layer 21 forms a second transparent electrode 211, which is electrically connected to the third electrode 183 or the fourth electrode 184 through the third opening; please refer to [the relevant documentation] for details. Figure 1 .

[0073] In the second embodiment, the patterning of the transparent conductive layer 21 constitutes the formation of a second transparent electrode 211 and a first transparent electrode 212. The second transparent electrode 211 is connected to the third electrode 183 or the fourth electrode 184 through the third opening, and the first transparent electrode 212 covers the bottom and sidewalls of the first opening. Please refer to [reference needed] for details. Figure 6 (h) and Figure 2 .

[0074] In a third embodiment, the patterning of the transparent conductive layer 21 constitutes the formation of a second transparent electrode 211 and a first transparent electrode 212. The second transparent electrode 211 is connected to the third electrode 183 or the fourth electrode 184 through the third opening, and the first transparent electrode 212 is electrically connected to the first electrode 181 or the second electrode 182 through the third opening. The first transparent electrode 212 covers the bottom and sidewalls of the first opening. Please refer to [reference needed] for details. Figure 3 .

[0075] The array substrate fabrication method provided in this embodiment of the invention integrates the pixel driving element and the photosensitive element on the same array substrate without increasing the number of photomasks. A first opening is provided within the photosensitive element, corresponding to the semiconductor structure of the photosensitive element. The light-incident side of the photosensitive element is a transparent film layer structure or a film-free structure. Compared to traditional photosensitive devices, the photosensitive element provided in this embodiment has a larger light-receiving area, better light-sensing effect, and higher sensitivity.

[0076] Meanwhile, embodiments of the present invention provide a display panel, which includes the array substrate described in any embodiment of the present invention. Since the display panel includes the array substrate described in any embodiment of the present invention, it possesses the technical features and beneficial effects of the array substrate described in any embodiment of the present invention. For details, please refer to the above-mentioned embodiments related to the array substrate, which will not be repeated here. The display panel includes, but is not limited to, LCD display panels, OLED display panels, LED display panels, MLED display panels, etc.

[0077] In summary, the embodiments of the present invention provide an array substrate and a display panel. By disposing the semiconductor structure of the pixel driving element and the semiconductor structure of the photosensitive element in the same active layer, the pixel driving element and the photosensitive element are integrated on the array substrate. At the same time, a first opening is provided in the photosensitive element, which corresponds to the semiconductor structure of the photosensitive element, thereby increasing the photosensitive area of ​​the photosensitive element and the transmittance of the photosensitive side of the photosensitive element, and improving the photosensitive effect of the photosensitive element.

[0078] The array substrate and display panel provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An array substrate, characterized in that, The array substrate includes: Substrate; An active layer, located on one side of the substrate, includes a first active portion and a second active portion; A first insulating layer is located on the side of the active layer away from the substrate and covers the active layer; The first active part has a first opening, which exposes the first insulating layer; The array substrate further includes a reflective layer disposed between the substrate and the active layer; the reflective layer includes a first reflective portion and a second reflective portion, wherein the projection of the first active portion on the substrate falls within the projection of the first reflective portion on the substrate, and the projection of the second active portion on the substrate falls within the projection of the second reflective portion on the substrate. The first reflective part is used to block light rays incident from the substrate side to the first active part, and to reflect light rays incident from the first insulating layer side to the first active part; The second reflective part is used to block the light incident from the substrate side to the second active part; The surface of the first insulating layer away from the substrate includes a first surface and a second surface, the first surface being the bottom surface of the first opening, and the second surface surrounding the first surface; the first surface is recessed into or flush with the second surface; the first surface includes a third surface and a fourth surface, the fourth surface surrounding the third surface, and the second surface surrounding the fourth surface; the fourth surface is recessed into the third surface and the second surface, and the third surface is recessed into the second surface.

2. The array substrate as described in claim 1, characterized in that, The fourth surface is recessed to a depth of 50 micrometers to 200 micrometers relative to the second surface, and the third surface is recessed to a depth of 50 micrometers to 150 micrometers relative to the second surface.

3. The array substrate as described in claim 1, characterized in that, The array substrate further includes a second insulating layer and a third insulating layer, which are sequentially disposed on the first insulating layer; the first opening penetrates the second insulating layer and the third insulating layer.

4. The array substrate as described in claim 3, characterized in that, The first active part is further provided with a second opening, which penetrates the first insulating layer and the second insulating layer and exposes the first active part; the opening diameter of the first opening is larger than the opening diameter of the second opening.

5. The array substrate as described in claim 4, characterized in that, The array substrate further includes a first conductive layer, which includes a first electrode and a second electrode. The first electrode and the second electrode are respectively connected to the two ends of the first active part through the second opening.

6. The array substrate as described in claim 5, characterized in that, The array substrate further includes a transparent conductive layer disposed on the third insulating layer; the transparent conductive layer includes a first transparent electrode, which covers the first opening.

7. The array substrate as described in claim 6, characterized in that, The first transparent electrode is electrically connected to either the first electrode or the second electrode.

8. The array substrate as claimed in claim 1, characterized in that, The first active portion includes a first channel region and two first doped regions, the two first doped regions being located on opposite sides of the first channel region, and the projection of the bottom surface of the first opening onto the substrate covers the projection of the first channel region onto the substrate.

9. The array substrate according to any one of claims 1 to 8, characterized in that, The array substrate includes a pixel driving element and a photosensitive element, the photosensitive element including a first active portion and the pixel driving element including a second active portion.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 9.

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