Display substrate, manufacturing method thereof, display panel, and display device

Abstract

Embodiments of the present application provide a display substrate, a manufacturing method thereof, a display panel and a display device. The display substrate comprises a display area, a first area of the display area comprises: a thin film transistor layer, a first planar layer, a first connection line, a second planar layer, a second connection line and an anode layer which are sequentially stacked on a substrate, the thin film transistor layer comprises a source-drain structure, the first planar layer is provided with a through hole, the first connection line fills the through hole and is connected with the source-drain structure, the second planar layer is provided with a through slot which leaks at least part of the first connection line, the second connection line covers at least part of the first connection line in the through slot and covers a part of the second planar layer adjacent to the through slot and connected with the anode layer, and a projection of the anode layer on the substrate does not exceed a projection of the second connection line on the substrate. Embodiments of the present application can reduce the area of the anode layer in the first area, improve the area ratio of the light-emitting layer in the first area, and improve the pixel density of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular, the present application relates to a display substrate and a manufacturing method thereof, a display panel and a display device. BACKGROUND

[0002] With the continuous development of organic electroluminescent display product (Organic Electro luminescent Display, OLED) technology, people's requirements for display panel are also increasing, such as high resolution and the like.

[0003] Therefore, it is necessary to provide a new structure of display substrate to improve the pixel density of the display panel, so as to improve the resolution of the display panel. SUMMARY

[0004] The present application aims at the shortcomings of the prior art, and provides a display substrate and a manufacturing method thereof, a display panel and a display device, which can reduce the area of the anode layer in the first area, improve the area ratio of the light emitting layer in the first area, and improve the pixel density of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display substrate, comprising a display area, the display area comprising: a thin film transistor layer, a part of which is located in a first area of the display area, and is arranged on one side of a substrate and comprises a source-drain structure; a first planar layer, arranged on a side of the thin film transistor layer away from the substrate, and a through hole is arranged in the first planar layer of the first area; a first connection line, arranged on a side of the first planar layer away from the thin film transistor layer, and filling the through hole and connected with the source-drain structure; a second planar layer, arranged on a side of the first connection line and the first planar layer, and provided with a through slot which leaks at least part of the first connection line; a second connection line, covering at least part of the first connection line in the through slot, and covering a part of the second planar layer adjacent to the through slot and connected with an anode layer; the anode layer, arranged on a side of the second connection line away from the first planar layer, and the orthographic projection of the anode layer in the substrate does not exceed the orthographic projection of the second connection line in the substrate.

[0006] In a second aspect, an embodiment of the present application provides a display panel, comprising: a display substrate as described above, a light emitting layer and a cathode layer which are stacked in sequence; the light emitting layer covers at least part of the anode layer of the display substrate.

[0007] In a third aspect, an embodiment of the present application provides a display device, comprising a display substrate as described above; or, comprising a display panel as described above.

[0008] Fourthly, embodiments of this application provide a method for manufacturing a display substrate, comprising: fabricating a thin-film transistor layer on one side of a substrate, such that a portion of the thin-film transistor layer is located in a first region of a display area, the thin-film transistor layer including a source-drain structure; fabricating a first planarization layer on the thin-film transistor layer, and forming a via in the first planarization layer in the first region; fabricating a first interconnecting line on the first planarization layer, such that the first interconnecting line fills the via and is connected to the source-drain structure; fabricating a second planarization layer on the first interconnecting line and the first planarization layer, and forming a through-slot in the second planarization layer exposing at least a portion of the first interconnecting line; fabricating a second interconnecting line on at least a portion of the first interconnecting line in the through-slot and on a portion of the second planarization layer adjacent to the through-slot, and connecting the second interconnecting line to an anode layer; fabricating an anode layer on the side of the second interconnecting line away from the first planarization layer, wherein the orthographic projection of the anode layer in the substrate does not exceed the orthographic projection of the second interconnecting line in the substrate.

[0009] The beneficial technical effects of the technical solution provided in this application include: by adding a first connecting line and a second connecting line below the anode layer in the first region to achieve electrical connection between the anode layer and the source / drain structure, the anode layer can be positioned directly above the via of the first planarization layer without needing to pass through the additional routing area of ​​the anode layer in related technologies (e.g., subsequent routing). Figure 3 The triangular trace area in the diagram connects the main area of ​​the anode layer (i.e., the area covered by the light-emitting layer) and the source-drain structure. In other words, by increasing the thickness of the first region of the display substrate along the Z-axis (perpendicular to the substrate) in exchange for reducing the area of ​​the anode layer in the XY plane (parallel to the substrate), the area ratio of the light-emitting layer in the first region is increased, thereby increasing the pixel density of the display panel.

[0010] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0011] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 This is a schematic diagram of the structure of the display substrate provided in the embodiments of this application;

[0013] Figure 2 This is a schematic diagram of various regions of the display substrate provided in the embodiments of this application;

[0014] Figure 3 This is a top view schematic diagram of the structure of the display panel in the related technology provided in the embodiments of this application;

[0015] Figure 4 A top view structural schematic diagram of a display panel composed of a display substrate and a light emitting layer provided by an embodiment of the present application;

[0016] Figure 5 A top view structural schematic diagram of a first connection line and a via provided by an embodiment of the present application;

[0017] Figure 6 Another top view structural schematic diagram of a first connection line and a via provided by an embodiment of the present application;

[0018] Figure 7 Still another top view structural schematic diagram of a first connection line and a via provided by an embodiment of the present application;

[0019] Figure 8 A flow chart of a manufacturing method of a display substrate provided by an embodiment of the present application;

[0020] Figure 9 A film layer structure schematic diagram after a part of a thin film transistor layer is prepared on a substrate side and located behind a first area of a display area in a manufacturing method of a display substrate provided by an embodiment of the present application;

[0021] Figure 10 A film layer structure schematic diagram after a first planar layer is prepared on the thin film transistor layer and a via is opened in the first planar layer of the first area in a manufacturing method of a display substrate provided by an embodiment of the present application;

[0022] Figure 11 A film layer structure schematic diagram after a first connection line is prepared on the first planar layer and the first connection line fills the via and connects with a source-drain structure in a manufacturing method of a display substrate provided by an embodiment of the present application;

[0023] Figure 12 A film layer structure schematic diagram after a second planar layer is prepared on the first connection line and the first planar layer and a via is opened in the second planar layer to expose at least a part of the first connection line in a manufacturing method of a display substrate provided by an embodiment of the present application;

[0024] Figure 13 A film layer structure schematic diagram after a second connection line is prepared on at least a part of the first connection line in the via and a part of the second planar layer adjacent to the via and the second connection line is connected with an anode layer in a manufacturing method of a display substrate provided by an embodiment of the present application;

[0025] Figure 14A manufacturing method of a display substrate provided by an embodiment of the present application includes preparing an anode layer on a side of the second connecting line away from the first planar layer. A projection of the anode layer in the substrate does not exceed a projection of the film layer structure of the second connecting line in the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0027] 100 - display area; 30 - first area; 40 - second area; 50 - third area;

[0028] 200 - trace area;

[0029] 60 - via hole;

[0030] 70 - through slot;

[0031] 80 - anode overlap hole;

[0032] 90 - pixel hole;

[0033] 10 - substrate;

[0034] 11 - thin film transistor layer; 111 - source-drain structure; 111a - source; 111b - drain; 112 - first insulating layer; 113 - semiconductor structure; 114 - gate structure; 115 - second insulating layer;

[0035] 12 - first planar layer;

[0036] 13 - first connecting line;

[0037] 14 - second planar layer;

[0038] 15 - second connecting line;

[0039] 16 - anode layer;

[0040] 17 - third planar layer;

[0041] 18 - pixel definition layer;

[0042] 19 - light-emitting layer;

[0043] 20 - cathode layer. DETAILED DESCRIPTION

[0044] Embodiments of the present application will be described below in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions of the technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.

[0045] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is further understood that the terms "comprise" and "comprising" and the like, when used in the specification, the specification, the description, and the claims, mean "including but not limited to" and / or "comprising but not limited to" and also mean "open", "inclusive" rather than "closed" or "exclusive." The use of "including" and "comprising" does not exclude the presence of elements or steps other than those listed in a process, method, system, composition, article, or apparatus, process, method, system, composition, article, or apparatus. The words "and / or" when used, for example, in a form such as A and / or B, means at least one of A or B. All combinations such as A alone, B alone, A and B together, are encompassed by this term.

[0046] For the purpose of making the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0047] The inventors of the present application have found that in the existing display panel, the light-emitting layer is arranged on the anode layer of different sizes, the anode layer is led out by the anode overlap hole, and the anode layer is connected to the source-drain structure of the thin film transistor layer through the anode overlap hole.

[0048] Since the anode layer and the source-drain structure have a certain distance in the XY plane (a plane parallel to the substrate), the main area of the anode layer (i.e., the area covered by the light-emitting layer) and the source-drain structure need to be connected through the additional wiring area (such as the triangular wiring area in the subsequent Figure 3 , of the anode layer, so the anode layer of a single pixel has a large area. The light-emitting layer of the pixel actually occupies a small area, and the large anode layer area affects the setting of high pixel density. At the same time, since the additional wiring area (such as the triangular wiring area in the subsequent Figure 3 , of the anode layer usually has sharp corners, the anode residue is prone to occur in the process of forming the patterned anode layer, causing point-like defects and affecting product yield.

[0049] The display substrate and the manufacturing method thereof, the display panel and the display device provided by the present application are aimed at solving the above technical problems of the prior art.

[0050] The display substrate provided by the embodiments of the present application includes a display area 100 and a wiring area 200 (IC area), and the display area 100 includes a thin film transistor layer 11, a first planar layer 12, a first connection line 13, a second planar layer 14, a second connection line 15, and an anode layer 16. Figure 1 , Figure 2 The display substrate provided by the embodiments of the present application includes a display area 100 and a wiring area 200 (IC area), and the display area 100 includes a thin film transistor layer 11, a first planar layer 12, a first connection line 13, a second planar layer 14, a second connection line 15, and an anode layer 16.

[0051] The thin film transistor layer 11 is partially located in the first area 30 of the display area 100, is arranged on one side of the substrate 10 (specifically, the thin film transistor layer 11 is located on one side of the substrate 10 and is connected with the substrate 10), and includes a source-drain structure 111.

[0052] The first planar layer 12 is arranged on a side of the thin film transistor layer 11 away from the substrate 10, and a through hole 60 is arranged in the first planar layer 12 in the first area 30.

[0053] The first connection line 13 is arranged on a side of the first planar layer 12 away from the thin film transistor layer 11, and the first connection line 13 fills the through hole 60 and is connected with the source-drain structure 111.

[0054] The second planar layer 14 is arranged on a side of the first connection line 13 and the first planar layer 12, and the second planar layer 14 is provided with a through slot 70 that leaks at least part of the first connection line 13.

[0055] The second connection line 15 covers at least part of the first connection line 13 in the through slot 70, and the second connection line 15 also covers a part of the second planar layer 14 adjacent to the through slot 70 and is connected with the anode layer 16.

[0056] The anode layer 16 is arranged on a side of the second connection line 15 away from the first planar layer 12, and a projection of the anode layer 16 in the substrate 10 does not exceed a projection of the second connection line 15 in the substrate 10. Specifically, the projection of the anode layer 16 in the substrate 10 overlaps the projection of the second connection line 15 in the substrate 10, or the projection of the anode layer 16 in the substrate 10 is located in the projection of the second connection line 15 in the substrate 10.

[0057] The display substrate provided by the embodiment of the present application increases the first connection line 13 and the second connection line 15 below the anode layer 16 in the first area 30, so as to realize the electrical connection between the anode layer 16 and the source-drain structure 111, thereby the anode layer 16 can be arranged directly above the through hole 60 of the first planar layer 12 without the need of connecting the main body area (i.e., the area covered by the light-emitting layer) of the anode layer 16 and the source-drain structure 111 through the additional wiring area (for example, the triangular wiring area in the subsequent Figure 3

[0058] ​In the first region 30, the orthogonal projection of the first connecting line 13 in the substrate 10 does not exceed the orthogonal projection of the second connecting line 15 in the substrate 10. In this way, the pixel density of the display panel can be ensured without the first connecting line 13 occupying too much area.

[0059] Optionally, the display substrate further comprises a third planar layer 17, which is arranged on one side of the second connecting line 15 and the second planar layer 14, and the third planar layer 17 in the first region 30 is provided with an anode overlap hole 80 for leaking out the second connecting line 15. The anode layer 16 covers at least part of the anode overlap hole 80 and is connected to the second connecting line 15. The third planar layer 17 is arranged on the second connecting line 15, which avoids the surface of the second connecting line 15 being uneven due to the arrangement of the first connecting line 13, and ensures the flatness of at least part of the surface of the anode layer 16, which is conducive to the arrangement of the light-emitting layer on the flat area of the anode layer 16.

[0060] Optionally, the orthogonal projection of the slot wall of the through slot 70 in the substrate 10 does not exceed the range circled by the orthogonal projection of the hole wall of the anode overlap hole 80 in the substrate 10, so as to facilitate the anode layer 16 being arranged on the part of the second connecting line 15 covering the second planar layer 14, and provide a more reliable connection mode of the anode layer 16 and the second connecting line 15.

[0061] In a feasible embodiment, the first connecting line 13 comprises a top surface away from the substrate 10, and the bottom surface of the through slot 70 is flush with the top surface of the first connecting line 13. In the case that the bottom surface of the through slot 70 is flush with the top surface of the first connecting line 13, the surface of the second connecting line 15 away from the substrate 10 is flat, so that the anode layer 16 can be directly made on the surface of the second connecting line 15, and the third planar layer 17 is not needed.

[0062] It should be noted that in the case that the third planar layer 17 is arranged, the bottom surface of the through slot 70 can be flush with the top surface of the first connecting line 13, or the bottom surface of the through slot 70 can be lower than the top surface of the first connecting line 13, as long as the bottom of the through slot 70 leaks out the first connecting line 13.

[0063] Optionally, the distance between the orthogonal projection of the edge of the second connecting line 15 in the substrate 10 and the orthogonal projection of the edge of the anode layer 16 in the substrate 10 is 0-2 μm (micrometers), for example, 0 μm, 1 μm, 1.5 μm, 2 μm, etc., so as to ensure that the area of the anode layer 16 does not exceed the area of the second connecting line 15, and ensure the area ratio of the light-emitting layer, and ensure the reliable connection of the anode layer 16 and the second connecting line 15.

[0064] In this embodiment, the first connecting line 13 may include transparent conductive materials such as indium tin oxide and zinc oxide, and the second connecting line 15 may include any one or more conductive materials such as silver, copper, aluminum and titanium, without limitation.

[0065] In this embodiment, the display area 100 may further include a second area 40 and a third area 50 that are adjacent to each other. The second area 40 includes another portion of the thin-film transistor layer 11. A first connection line 13 located in the second area 40 and the third area 50 includes a first end and a second end. The first end of the first connection line 13 is connected to the source-drain structure 111 of the other portion of the thin-film transistor layer 11 in the second area 40, and the second end of the first connection line 13 is located at the through-slot 70 of the second planarization layer 14 in the third area 50 and is covered by the second connection line 15 of the third area 50. The first connection line 13 is a transparent structure.

[0066] Specifically, a via 60 is provided in the first planarization layer 12 of the second region 40. In the second region 40, the first end of the first connecting line 13 fills the via 60 and is connected to the source-drain structure 111 of another part of the thin film transistor layer 11 located in the second region 40.

[0067] In other words, by setting the source-drain structure 111 (which may also include the gate structure 114 and the semiconductor structure 113) of a pixel and the anode layer 16 in the second region 40 and the third region 50 respectively, and by misaligning the source-drain structure 111 (which may also include the gate structure 114 and the semiconductor structure 113) with the anode layer 16, the light transmittance in the third region 50 is avoided due to the setting of the source-drain structure 111 (which may also include the gate structure 114 and the semiconductor structure 113). The third region 50 can be used as a camera region with high light transmittance requirements to improve image quality.

[0068] In practical applications, such as Figure 2 As shown, the display substrate includes a display area 100 and a wiring area 200. The display area 100 includes a first area 30, a second area 40, and a third area 50. The second area 40 may surround the third area 50, and the first area 30 may surround the second area 40. The first area 30 may be the main display area 100 of the display panel, the third area 50 may be the camera area, and the second area 40 may be a transition area.

[0069] Of course, the second area 40 may not be surrounded by the first area 30, but may be set at the edge of the display panel, or the third area 50 may not be surrounded by the second area 40, but may be set at the edge of the display panel. No limitation is made here.

[0070] In the embodiment, the thin-film transistor layer 11 can further include a first insulating layer 112, a semiconductor structure 113 (which can be a P-type conductive layer), and a gate structure 114. The semiconductor structure 113 is disposed on one side of the substrate 10, and the first insulating layer 112 is disposed on the semiconductor structure 113 and the one side of the substrate 10. The gate structure 114 is disposed on the side of the first insulating layer 112 away from the substrate 10, and the source-drain structure 111 is disposed on the side of the first insulating layer 112 away from the substrate 10 and connected to the semiconductor structure 113.

[0071] That is, the thin-film transistor layer 11 can be a top-gate structure. Specifically, the thin-film transistor layer 11 can include the semiconductor structure 113, the first insulating layer 112, the gate structure 114, the second insulating layer 115, and the source-drain structure 111 which are sequentially stacked, the source-drain structure 111 can include a source 111a and a drain 111b, the source 111a and the drain 111b can respectively fill two connection holes penetrating the first insulating layer 112 and the second insulating layer 115, and the first connection line 13 is connected to the drain 111b.

[0072] Further, the driving circuit composed of the semiconductor structure 113, the gate structure 114, and the source-drain structure 111 (including the source 111a and the drain 111b) can be a 7T1C circuit.

[0073] It should be noted that the thin-film transistor layer 11 can also be a bottom-gate structure. Specifically, the thin-film transistor layer 11 can include the gate structure, the first insulating layer, the semiconductor structure 113, the second insulating layer 115, and the source-drain structure 111 which are sequentially stacked.

[0074] In actual application, the display panel made of the display substrate can further include a pixel definition layer 18, a light-emitting layer 19, and a cathode layer 20.

[0075] The pixel definition layer 18 is disposed on the side of the anode layer 16 away from the second connection line 15 and on the side of the third planar layer 17 away from the second planar layer 14, and the pixel definition layer 18 is provided with a pixel hole 90, the pixel hole 90 is opposite to the flat area of the anode layer 16 and exposes the anode layer 16.

[0076] The light-emitting layer 19 covers the flat area of the anode layer 16 in the pixel hole 90 and covers a part of the pixel definition layer 18 adjacent to the pixel hole 90.

[0077] The cathode layer 20 is disposed on the side of the light-emitting layer 19 away from the anode layer 16 and the pixel definition layer 18 and on the side of the pixel definition layer 18 away from the third planar layer 17.

[0078] Referring to Figure 3 , Figure 3A schematic diagram of a structure of a display panel in the related art is shown. It can be seen that the light-emitting layer 19 and the via hole 60 above the source-drain structure have a certain distance in the XY plane (a plane parallel to the substrate), and the via hole 60 above the source-drain structure is not located directly below the light-emitting layer 19. Therefore, an additional wiring area (for example, a triangular wiring area in Figure 3 ) of the anode layer 16 is needed to connect the main area (that is, the area covered by the light-emitting layer) of the anode layer 16 and the source-drain structure, so that the area of the anode layer 16 is large, and the area ratio of the light-emitting layer 19 is small.

[0079] Referring to Figure 4 , Figure 4 A schematic diagram of a structure of a display panel composed of a display substrate and a light-emitting layer in the embodiment is shown. It can be seen that, in the projection on the XY plane, the via hole above the source-drain structure is completely hidden directly below the light-emitting layer 19, and no additional wiring area (for example, a triangular wiring area in Figure 3 ) of the anode layer 16 is needed to connect the main area (that is, the area covered by the light-emitting layer) of the anode layer 16 and the source-drain structure, so that the area of the anode layer 16 is small, and the area ratio of the light-emitting layer 19 is large.

[0080] In actual applications, the shape of the second connection line 15 can be a hexagon, which is the same as the shape of the light-emitting layer. The shape of the first connection line 13 can be variously set, which is illustrated by the following drawings:

[0081] Referring to Figure 5 , Figure 5 A schematic diagram of a structure of a first connection line and a via hole in the embodiment is shown. Figure 4 In the embodiment, the shape of the first connection line 13 in the orthogonal projection on the XY plane is a circle, and the orthogonal projection of the via hole 60 on the XY plane is located at the edge of the circular first connection line 13.

[0082] Referring to Figure 6 , Figure 6 A schematic diagram of another structure of a first connection line and a via hole in the embodiment is shown. Figure 4 In the embodiment, the shape of the first connection line 13 in the orthogonal projection on the XY plane is a square, and the via hole 60 is arranged at a corner of the square first connection line 13.

[0083] Referring to Figure 7 , Figure 7 A schematic diagram of still another structure of a first connection line and a via hole in the embodiment is shown. Figure 4 In the embodiment, the shape of the first connection line 13 in the orthogonal projection on the XY plane is a hexagon, and the orthogonal projection of the via hole 60 on the XY plane is located close to one side of the hexagonal first connection line 13.

[0084] The technical scheme provided by the embodiment has the following beneficial technical effects:

[0085] The first connecting line 13 and the second connecting line 15 are additionally arranged below the anode layer 16 in the first area 30, so that the via hole 60 above the source-drain electrode structure 111 is hidden below the light-emitting layer. The thickness of the display substrate in the Z-axis direction (the direction perpendicular to the substrate 10) of the first area 30 is increased to reduce the area of the anode layer 16 in the XY plane (the plane parallel to the substrate 10), so as to increase the area ratio of the light-emitting layer in the first area 30 and improve the pixel density of the display panel.

[0086] Since the first connecting line 13 and the second connecting line 15 can realize the electrical connection between the anode layer 16 and the source-drain electrode structure 111, the main area (i.e., the area covered by the light-emitting layer) of the anode layer 16 does not need to be connected to the source-drain electrode structure 111 by arranging an additional wiring area (for example, the triangular wiring area in the related art) of the anode layer 16. Figure 3 That is, the anode layer 16 does not have a triangular area including sharp corners, so that the anode residue is less likely to occur in the process of forming the patterned anode layer 16, thereby improving the product yield.

[0087] Based on the same inventive concept, the embodiment of the present application provides a display panel, comprising: the display substrate as described above, a light-emitting layer, and a cathode layer which are sequentially stacked, and the light-emitting layer covers at least part of the anode layer of the display substrate.

[0088] Since the display panel in the embodiment has been described in the foregoing embodiments, the related technical details can be referred to the foregoing embodiments, and similar technical effects can be achieved, which will not be described here again.

[0089] Based on the same inventive concept, the embodiment of the present application provides a display device, comprising the display substrate as described above; or, comprising the display panel as described above.

[0090] Since the display device in the embodiment comprises the display substrate or the display panel in the foregoing embodiments, the related technical details can be referred to the foregoing embodiments, and similar technical effects can be achieved, which will not be described here again.

[0091] Based on the same inventive concept, the embodiment of the present application provides a manufacturing method of a display substrate, as shown in Figure 8 , comprising:

[0092] S101: preparing a thin film transistor layer on one side of a substrate, so that part of the thin film transistor layer is located in a first area of a display area, and the thin film transistor layer comprises a source-drain electrode structure.

[0093] The film layer structure obtained by the above steps is as shown in Figure 9 .

[0094] Optionally, the step S101 can comprise: preparing the thin film transistor layer 11 on one side of the substrate 10, so that a part of the thin film transistor layer 11 is located in the first area 30, and another part of the thin film transistor layer 11 is located in the second area 40, and the display area can further comprise the second area 40 and the third area 50 which are adjacent to each other.

[0095] Optionally, the step of preparing the thin film transistor layer on one side of the substrate can further comprise: preparing the first insulating layer and the second insulating layer on one side of the substrate in the third area while a part of the thin film transistor layer is located in the first area of the display area.

[0096] S102: preparing the first planar layer on the thin film transistor layer, and opening a through hole in the first planar layer in the first area.

[0097] Optionally, the step of opening the through hole in the first planar layer in the first area can further comprise: opening a through hole in the first planar layer in the second area.

[0098] The film layer structure obtained by the above steps is shown in FIG. 1. Figure 10 As shown in FIG. 1, the display area can comprise the first area 30, the second area 40 and the third area 50, the first planar layer 12 is arranged on the side of the thin film transistor layer 11 away from the substrate 10, and the first planar layer 12 in the first area 30 is provided with a through hole 60.

[0099] S103: preparing the first connection line on the first planar layer, and making the first connection line fill the through hole and connect with the source-drain structure.

[0100] The step S103 can comprise: preparing the first connection line 13 on the first planar layer 12 in the first area 30, and preparing the first connection line 13 on the first planar layer 12 in the second area 40 and the third area 50, so that in the first area 30, the first connection line 13 fills the through hole 60 and connects with the source-drain structure 111 of a part of the thin film transistor layer 11, and in the second area 40 and the third area 50, the first end of the first connection line 13 connects with the source-drain structure 111 of another part of the thin film transistor layer 11 in the second area 40, wherein the first connection line 13 is made of transparent material.

[0101] The film layer structure obtained by the above steps is shown in FIG. 2. Figure 11 As shown in FIG. 2.

[0102] S104: preparing the second planar layer on the first connection line and the first planar layer, and opening a through slot in the second planar layer to expose at least part of the first connection line.

[0103] The step of preparing the second planar layer on the first connection line and the first planar layer can comprise: preparing the second planar layer 14 on the first connection line 13 and the first planar layer 12.

[0104] The step of opening the through-slots in the second flat layer to expose at least part of the first connection lines can include: opening the through-slots 70 in the second flat layer 14 of the first region 30 to expose the first connection lines 13 in the first region 30, and opening the through-slots 70 in the second flat layer 14 of the third region 50 to expose the second ends of the first connection lines 13 in the second region 40 and the third region 50.

[0105] The film layer structure obtained by the above steps is shown in FIG. 4. Figure 12 The film layer structure obtained by the above steps is shown in FIG. 4.

[0106] S105: preparing the second connection lines on at least part of the first connection lines in the through-slots and part of the second flat layer adjacent to the through-slots, and connecting the second connection lines to the anode layer.

[0107] The step S105 can include: preparing the second connection lines 15 on at least part of the first connection lines 13 in the through-slots 70 of the first region 30 and part of the second flat layer 14 adjacent to the through-slots 70, and preparing the second connection lines 15 on the second ends of the first connection lines 13 in the through-slots 70 of the third region 50 and part of the second flat layer 14 adjacent to the through-slots 70, and connecting the second connection lines 15 to the anode layer. The second connection lines 15 can not be prepared in the second region 40.

[0108] The film layer structure obtained by the above steps is shown in FIG. 4. Figure 13 The film layer structure obtained by the above steps is shown in FIG. 4.

[0109] S106: preparing the anode layer on the side of the second connection lines away from the first flat layer, and the orthogonal projection of the anode layer in the substrate does not exceed the orthogonal projection of the second connection lines in the substrate.

[0110] Optionally, before preparing the anode layer 16 on the side of the second connection lines 15 away from the first flat layer 12, the method can further include: disposing a third flat layer 17 on the side of the second connection lines 15 away from the first flat layer 12 and on the side of the second flat layer 14 away from the first flat layer 12, and the third flat layer 17 of the first region 30 and the third region 50 is provided with anode overlap holes 80 for exposing part of the second connection lines 15.

[0111] The step S106 can include: preparing the anode layer 16 on the side of the second connection lines 15 of the first region 30 and the third region 50 away from the first flat layer 12, and the orthogonal projection of the anode layer 16 in the substrate 10 does not exceed the orthogonal projection of the second connection lines 15 in the substrate 10. The anode layer 16 can not be prepared in the second region 40.

[0112] The film layer structure obtained by the above steps is shown in FIG. 4. Figure 14 The film layer structure obtained by the above steps is shown in FIG. 4.

[0113] By using the embodiments of the present application, the following beneficial effects can be achieved.

[0114] By additionally arranging the first connection line and the second connection line under the anode layer in the first region, the via hole above the source-drain structure is hidden under the light-emitting layer, the thickness of the display substrate in the Z-axis direction (the direction perpendicular to the substrate) is increased in exchange for the reduction of the area of the anode layer in the XY plane (the plane parallel to the substrate), so as to increase the area ratio of the light-emitting layer in the first region and improve the pixel density of the display panel.

[0115] Since the first connection line and the second connection line can realize the electrical connection between the anode layer and the source-drain structure, there is no need to arrange the additional wiring area (for example, the triangular wiring area in the related art) of the anode layer to connect the main area (i.e., the area covered by the light-emitting layer) of the anode layer and the source-drain structure. Figure 3 That is, the anode layer does not have additional wiring areas (for example, the triangular wiring area in the related art) including sharp corners, so that the anode residue is less likely to occur in the process of forming the patterned anode layer, thereby improving the product yield. Figure 3

[0116] Those skilled in the art can understand that the steps, measures, and schemes in the various operations, methods, and processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the various operations, methods, and processes in the prior art can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0117] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are based on the exemplary directions or positional relationships shown in the drawings, and are for the convenience of description or simplification of the description of the embodiments of the present application, and do not indicate or imply that the devices or components referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0118] The terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0119] ​In the description of the present application, it should be noted that unless specifically stated and limited otherwise, the terms "mounting", "connected", "connecting" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be directly connected, or indirectly connected through an intermediate medium; can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0120] In the description of the present application, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0121] It should be understood that although each step in the flowchart of the accompanying drawings is displayed in sequence according to the direction of the arrow, the implementation order of the steps is not limited to the order indicated by the arrow. Unless otherwise specified herein, in some implementation scenarios of the embodiments of the present application, the steps in each flowchart can be executed in other orders as required. Moreover, part or all of the steps in each flowchart can include multiple sub-steps or multiple stages based on the actual implementation scenario. Part or all of these sub-steps or stages can be executed at the same time or at different times. In the scenario where the execution time is different, the execution order of these sub-steps or stages can be flexibly configured according to the requirements, and the embodiments of the present application do not limit this.

[0122] The above only describes some embodiments of the present application. It should be noted that for those skilled in the art, without departing from the technical concept of the present application, other similar implementation means based on the technical idea of the present application also belong to the protection scope of the embodiments of the present application.

Claims

1. A display substrate comprising a display area, characterized in that, The display region comprises: a thin film transistor layer, a part of which is located in a first region of the display region, is arranged on one side of a substrate, and comprises a source-drain structure; a first planar layer, which is arranged on a side of the thin film transistor layer away from the substrate, and a through hole is arranged in the first planar layer of the first region; a first connection line, which is arranged on a side of the first planar layer away from the thin film transistor layer, fills the through hole, and is connected with the source-drain structure; a second planar layer, which is arranged on a side of the first connection line and the first planar layer, and a through slot is arranged in the second planar layer to expose at least part of the first connection line; a second connection line, which covers at least part of the first connection line in the through slot, and covers a part of the second planar layer adjacent to the through slot and connected with an anode layer; the anode layer, which is arranged on a side of the second connection line away from the first planar layer, a projection of the anode layer in the substrate does not exceed a projection of the second connection line in the substrate, and a distance between a projection of an edge of the second connection line in the substrate and a projection of an edge of the anode layer in the substrate is greater than 0 and less than or equal to 2 μm.

2. The display substrate of claim 1, wherein, In the first region, a projection of the first connection line in the substrate does not exceed a projection of the second connection line in the substrate.

3. The display substrate of claim 1, wherein, Further comprising a third planar layer, which is arranged on a side of the second connection line and the second planar layer, and an anode overlap hole is arranged in the third planar layer of the first region to expose part of the second connection line; the anode layer, which covers at least part of the anode overlap hole, and is connected with the second connection line.

4. The display substrate of claim 3, wherein, A projection of a slot wall of the through slot in the substrate does not exceed a range circled by a hole wall of the anode overlap hole in the substrate.

5. The display substrate of claim 1, wherein, The first connection line comprises a top surface away from the substrate; a bottom surface of the through slot close to the substrate is flush with the top surface of the first connection line. 6.The display substrate of claim 1, wherein, The display region further comprises a second region and a third region adjacent to each other; the second region comprises another part of the thin film transistor layer; the first connection line located in the second region and the third region comprises a first end and a second end; the first end of the first connection line is connected with a source-drain structure of another part of the thin film transistor layer located in the second region, and the second end of the first connection line is located at a through slot of a second planar layer in the third region and is covered by a second connection line in the third region; the first connection line is a transparent structure. 7.The display substrate of claim 6, wherein, The second region is surrounded by a periphery of the third region, and the first region is surrounded by a periphery of the second region.

8. A display panel, characterized by, comprise: the display substrate, the light-emitting layer and the cathode layer in the display panel are sequentially stacked; the light-emitting layer covers at least part of the anode layer of the display substrate.

9. A display device, characterized by comprising: comprise the display substrate in any one of claims 1-7; or, comprise the display panel in claim 8.

10. A method for manufacturing the display substrate according to any one of claims 1 to 7, characterized by, comprise: a thin film transistor layer is prepared on one side of a substrate, so that a part of the thin film transistor layer is located in a first region of a display region, and the thin film transistor layer comprises a source-drain structure; forming a first planar layer on the thin film transistor layer, and forming a through hole in the first planar layer in the first region; forming a first connection line on the first planar layer, and making the first connection line fill the through hole and connect with the source-drain structure; forming a second planar layer on the first connection line and the first planar layer, and forming a through slot in the second planar layer to expose at least part of the first connection line; forming a second connection line on at least part of the first connection line in the through slot and a part of the second planar layer adjacent to the through slot, and making the second connection line connect with an anode layer; forming an anode layer on a side of the second connection line away from the first planar layer, a projection of the anode layer in the substrate does not exceed a projection of the second connection line in the substrate.

11. The manufacturing method according to claim 10, wherein forming a thin film transistor layer on a side of a substrate, so that a part of the thin film transistor layer is located in a first region of a display region, comprising: forming the thin film transistor layer on a side of a substrate, so that a part of the thin film transistor layer is located in a first region of a display region, and another part of the thin film transistor layer is located in a second region; the display region further comprises a second region and a third region adjacent to each other; forming a first connection line on the first planar layer, and making the first connection line fill the through hole and connect with the source-drain structure, comprising: forming a first connection line on the first planar layer in the first region, and forming a first connection line on the first planar layer in the second region and the third region, so that in the first region, the first connection line fills the through hole and connects with the source-drain structure of a part of the thin film transistor layer, and in the second region and the third region, a first end of the first connection line connects with a source-drain structure of another part of the thin film transistor layer in the second region; the first connection line is a transparent material; forming a through slot in the second planar layer to expose at least part of the first connection line, comprising: forming a through slot in the second planar layer in the first region to expose the first connection line in the first region, and forming a through slot in the second planar layer in the third region to expose a second end of the first connection line in the second region and the third region; forming a second connection line on at least part of the first connection line in the through slot and a part of the second planar layer adjacent to the through slot, comprising: forming a second connection line on at least part of the first connection line in the through slot in the first region and a part of the second planar layer adjacent to the through slot, and forming a second connection line on the second end of the first connection line in the through slot in the third region and a part of the second planar layer adjacent to the through slot.

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