Cmos image sensor and method of forming the same

Abstract

A CMOS image sensor and a method for forming the same, wherein the method comprises: forming a substrate and a plurality of light-doped layers, the substrate comprising a plurality of mutually separated pixel regions, and the light-doped layers being respectively located on the pixel regions; and forming a switching device on each of the light-doped layers, the switching device being formed on the light-doped layer in a stacked manner, so as to reduce the area occupied by the pixel region, increase the pixel density, and balance the size of the light-doped region and the reading circuit, thereby facilitating better light-sensing characteristics and switching performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a CMOS image sensor and a forming method thereof. BACKGROUND

[0002] Image sensors are devices that convert optical signals into electrical signals, and are widely used in digital television and visual communication markets. Currently, the two most widely used image sensors are CCD (Charge-Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor). Among them, CMOS is the most promising and is considered to have the most development potential.

[0003] With the development of CMOS image sensor (CIS) product technology, the requirements for pixels of image sensors are becoming higher and higher. Generally, a single pixel of a CMOS image sensor is composed of a light sensing area (PN junction as light sensing) and a reading circuit (one transistor device as a selection switch). Because the larger the light sensing area, the better the light sensing performance, the larger the transistor size, and the smaller the noise introduced by the switch, the more stable the performance. Therefore, under the condition of the same pixel density, the size of the light sensing area and the reading circuit needs to be balanced.

[0004] Therefore, the existing CMOS image sensor structure needs to be further improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a CMOS image sensor and a forming method thereof to improve the performance of the formed CMOS image sensor.

[0006] To solve the above technical problems, the technical scheme of the present application provides a CMOS image sensor, comprising: a substrate comprising a plurality of mutually separate pixel areas; a light sensing doped layer located on each of the pixel areas; and a switch device located on each of the light sensing doped layers.

[0007] Optionally, each of the switch devices comprises an active area located on part of the light sensing doped layer, a gate located on the active area and the light sensing doped layer, the active area has a source-drain layer on top, the gate has an opening therein, and the opening exposes part of the surface of the source-drain layer.

[0008] Optionally, the source-drain layer further has a lightly doped region on top, and the opening exposes part of the lightly doped region.

[0009] Optionally, the method further comprises: forming a plurality of conductive plugs on the surface of the source-drain layer, the plurality of conductive plugs on each of the photo-doped layers being arranged along the extending direction of the photo-doped layer.

[0010] Optionally, the method further comprises: forming an isolation structure between adjacent photo-doped layers, the isolation structure being further formed between adjacent switching devices.

[0011] Optionally, the substrate comprises a first region and a second region, the plurality of mutually separated pixel regions being formed on the first region, and the second region having peripheral devices formed thereon.

[0012] Correspondingly, the application further provides a method for forming a CMOS image sensor, comprising: forming a substrate and a plurality of photo-doped layers, the substrate comprising a plurality of mutually separated pixel regions, and each of the photo-doped layers being formed on each of the pixel regions; and forming a switching device on each of the photo-doped layers.

[0013] Optionally, each of the switching devices comprises an active region formed on part of the photo-doped layer, a gate formed on the active region and the photo-doped layer, a source-drain layer formed on the top of the active region, and an opening formed in the gate, the opening exposing part of the surface of the source-drain layer.

[0014] Optionally, the method for forming the substrate and the plurality of photo-doped layers comprises: forming a substrate structure, the substrate structure comprising the substrate and an initial photo-doped layer formed on the substrate; forming an isolation structure in the substrate structure, the isolation structure penetrating the initial photo-doped layer, and the isolation structure being further formed between adjacent pixel regions, so that the initial photo-doped layer forms a plurality of mutually separated photo-doped layers.

[0015] Optionally, the substrate structure further comprises: an initial well-doped layer formed on the initial photo-doped layer; and the isolation structure further penetrating the initial well-doped layer, so that the initial well-doped layer forms a plurality of mutually separated well-doped layers.

[0016] Optionally, the method for forming the substrate structure comprises: providing an initial substrate; implanting first doping ions into the initial substrate to form an initial photo-doped layer in the initial substrate, the top surface of the initial photo-doped layer being lower than the surface of the initial substrate; forming the substrate structure, the initial substrate below the initial photo-doped layer forming the substrate, and the initial substrate on the initial photo-doped layer forming the substrate structure.

[0017] Optionally, the method for forming the substrate structure comprises: providing an initial substrate; implanting first doping ions into the initial substrate to form the substrate and the initial photo-doped layer on the substrate, the top surface of the initial photo-doped layer being exposed; forming an epitaxial layer on the surface of the initial photo-doped layer; implanting second doping ions into the epitaxial layer to form the initial well-doped layer on the epitaxial layer.

[0018] Optionally, the method for forming the switching device comprises: etching the well-doped layer until the photo-doped layer is exposed to form a gate trench, the active region being formed on the well-doped layer, the gate trench exposing the active region and the isolation structure; forming a gate and an opening in the gate on the surface of the active region, the opening exposing part of the top surface of the active region; implanting first ions into the opening to form the source-drain region.

[0019] Optionally, the method for forming the gate and the opening comprises: forming an initial gate on the surface of the gate trench and the active region; etching back the initial gate until the surface of the isolation structure and part of the surface of the active region are exposed to form the gate and the opening.

[0020] Optionally, before forming the initial gate, the method further comprises: forming a gate dielectric layer on the surface of the gate trench and the active region.

[0021] Optionally, the method further comprises: implanting second ions into the surface of the well-doped layer to form an initial lightly-doped region before etching the well-doped layer; the initial lightly-doped region is etched to form the lightly-doped region.

[0022] Optionally, the process parameters of the process for forming the initial lightly-doped region comprise: the doping ions comprise N-type ions, the implantation dose ranges from 5E12 atom / cm 2 to 5E14 atom / cm 2 .

[0023] Optionally, after forming the switching device, the method further comprises: forming a plurality of conductive plugs on the surface of the source-drain region, the plurality of conductive plugs on each photo-doped layer being arranged along the extension direction of the photo-doped layer.

[0024] Optionally, before forming the plurality of conductive plugs, the method further comprises: forming a sidewall on the sidewall of the gate.

[0025] Optionally, the substrate comprises a first region and a second region, the plurality of mutually discrete pixel regions being located in the first region; the method comprises: forming a peripheral device on the second region.

[0026] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0027] The forming method of the CMOS image sensor provided by the technical scheme reduces the area occupied by the pixel region, improves the pixel density, and does not need to balance the size of the light sensing region and the read circuit, which is conducive to obtaining better light sensing characteristics and switching performance.

[0028] Further, before etching the well doped layer, a second ion is implanted on the surface of the well doped layer to form a lightly doped region, and the lightly doped region is located on the surface of the source-drain layer below the gate electrode. A lower doping concentration is used to reduce the short channel effect of the switching device.

[0029] Further, a plurality of conductive plugs are formed on the surface of the source-drain region, and the plurality of conductive plugs on each light sensing doped layer are arranged along the extension direction of the light sensing doped layer. The plurality of conductive plugs are conducive to reducing the contact resistance and improving the performance of the device.

[0030] The CMOS image sensor provided by the technical scheme reduces the area occupied by the pixel region, improves the pixel density, and does not need to balance the size of the light sensing region and the read circuit, which is conducive to obtaining better light sensing characteristics and switching performance. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figures 1 to 12 is a structural schematic diagram of each step of the forming method of the CMOS image sensor of the embodiment of the present application. DETAILED DESCRIPTION

[0032] It should be noted that the "surface", "upper", and "lower" in the present specification are used to describe the relative position relationship in space and do not limit whether they are in direct contact.

[0033] As described in the background, the CMOS image sensor formed by using the existing CMOS image sensor technology needs to balance the size performance of the light sensing region and the read circuit in the case of the same pixel density, and the performance of the obtained CMOS image sensor needs to be further improved.

[0034] In order to solve the above problems, the CMOS image sensor and the forming method thereof provided by the present application form the switching device in a stacked manner on the light sensing doped layer, reduce the area occupied by the pixel region, improve the pixel density, and do not need to balance the size of the light sensing region and the read circuit, which is conducive to obtaining better light sensing characteristics and switching performance.

[0035] In order to make the above-mentioned purposes, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 12 is a structural schematic diagram of each step of the forming method of the CMOS image sensor of the embodiment of the present application.

[0037] In the embodiment, a substrate and a plurality of light-doped layers are formed, the substrate comprises a plurality of mutually separate pixel regions, and the light-doped layers are respectively located on the pixel regions. For the specific process of forming the substrate and the plurality of light-doped layers, please refer to Figures 1 to 4 .

[0038] For the specific process of forming the substrate and the plurality of light-doped layers, please refer to Figure 1 and Figure 2 , Figure 1 is a top view structural schematic diagram, Figure 2 is Figure 1 is a cross-sectional structural schematic diagram along the EE1 direction in

[0039] In the embodiment, the substrate 100 comprises a first region and a second region II, and the plurality of mutually separate pixel regions I are located on the first region.

[0040] In the embodiment, subsequently, a peripheral device is also formed on the second region II.

[0041] In the embodiment, the substrate structure further comprises an initial well-doped layer 102 located on the initial light-doped layer 101.

[0042] In the embodiment, the forming method of the substrate structure comprises: providing an initial substrate (not shown in the figure); implanting first doped ions into the initial substrate to form the substrate 100 and the initial light-doped layer 101 located on the substrate 100, and the top surface of the initial light-doped layer 101 is exposed; forming an epitaxial layer (not shown in the figure) on the surface of the initial light-doped layer 101; implanting second doped ions into the epitaxial layer to form the initial well-doped layer 102 with the epitaxial layer.

[0043] In the embodiment, the conductive type of the initial substrate is P type, the conductive type of the first doped ions is N type, and the conductive type of the second doped ions is P type. A PN junction is formed between the initial light-doped layer 101 and the initial substrate for forming a photodiode; and the epitaxial layer is used to form a channel of a switching device.

[0044] In this embodiment, the well doping layer 105 on the first region and the second region II are formed simultaneously. In other embodiments, the well doping layer on the first region and the well doping layer on the second region can be formed at different times so that the doping ions or the concentration of the doping ions in the well doping layer on the first region and the well doping layer on the second region are different.

[0045] The well doping layer 105 on the first region is used to form the well region of the switching device; the well doping layer 105 on the second region II is used to form the well region of the peripheral device.

[0046] Please refer to Figure 3 and Figure 4 , Figure 3 is a schematic diagram of a top view structure, Figure 4 is Figure 3 is a schematic diagram of a cross-sectional structure along the EE1 direction in the substrate structure, the isolation structure 103 is formed in the substrate structure, the isolation structure 103 penetrates the initial light doping layer 101, and the isolation structure 103 is also located between adjacent pixel regions I, so that the initial light doping layer 101 forms a plurality of mutually separated light doping layers 104.

[0047] In this embodiment, the isolation structure 103 also penetrates the initial well doping layer 102, so that the initial well doping layer 102 forms a plurality of mutually separated well doping layers 105.

[0048] The method for forming the isolation structure 103 includes: etching the substrate structure to form an isolation trench (not labeled in the figure) in the substrate structure; forming an insulating medium material layer (not labeled in the figure) in the isolation trench and on the surface of the substrate structure; and planarizing the insulating medium material layer until the surface of the substrate structure is exposed, thereby forming the isolation structure 103.

[0049] In another embodiment, the method for forming the substrate structure includes: providing an initial substrate; implanting first doping ions into the initial substrate to form an initial light doping layer in the initial substrate, the top surface of the initial light doping layer being lower than the surface of the initial substrate; forming the substrate structure, the initial substrate below the initial light doping layer forming the substrate, and the initial substrate on the initial light doping layer.

[0050] Subsequently, the switching device is formed on each of the light doping layers 104.

[0051] In this embodiment, each of the switching devices includes an active region located on a portion of the photosensitive doped layer 104, a gate located on the active region and the photosensitive doped layer, a source / drain layer at the top of the active region, and an opening in the gate exposing a portion of the surface of the source / drain layer. Specifically, the method for forming the switching device is described in [reference needed]. Figures 5 to 10 .

[0052] Please refer to Figure 5 and Figure 6 , Figure 5 This is a top-down structural diagram. Figure 6 yes Figure 5 A cross-sectional view along the EE1 direction is shown. The well doped layer 105 is etched until the photosensitive doped layer 104 is exposed to form a gate trench 106. The active region 107 is formed by the well doped layer 105. The gate trench 106 exposes the active region 107 and the isolation structure 103.

[0053] Specifically, the well doped layer 105 on each of the pixel regions I is etched until the photosensitive doped layer 104 is exposed, forming a gate trench 106, and the active region 107 is formed by the well doped layer 105. The gate trench 106 exposes the active region 107 and the isolation structure 103.

[0054] In this embodiment, the well doped layer 105 is etched to form the well region 200 of the peripheral device on the well doped layer 105 on the second region II.

[0055] More specifically, the method for forming the gate trench 106 and the active region 107 further includes: forming a first patterned layer (not shown in the figure) on the surface of the well doped layer 105, the first patterned layer exposing a portion of the surface of each pixel region I; using the first patterned layer as a mask, etching the well doped layer 105 on each pixel region I.

[0056] In this embodiment, before etching the well doped layer 105, a second ion is implanted on the surface of the well doped layer 105 to form an initial lightly doped region (not shown in the figure); the initial lightly doped region is etched to form a lightly doped region 108.

[0057] The lightly doped region 108 is located on the surface of the source / drain layer below the subsequently formed gate. The use of a lower doping concentration helps to reduce the short-channel effect of the switching device.

[0058] Specifically, second ions are implanted on the surface of the well doped layer 105 on each of the pixel regions I to form an initial lightly doped region.

[0059] More specifically, the method for forming the initial lightly doped region further includes: forming a second patterned layer (not shown in the figure) on the substrate 100 before implanting the second ions, the second patterned layer exposing the surface of the well doped layer 105 on each of the pixel regions I; and removing the second patterned layer after forming the initial lightly doped region.

[0060] In this embodiment, the process parameters for forming the initial lightly doped region include: the dopant ions include N-type ions, and the implantation dose range is 5E12 atom / cm. 2 Up to 5E14 atom / cm 2 Specifically, the N-type ion is phosphorus. In other embodiments, the dopant ion may be arsenic.

[0061] In this embodiment, the concentration range of the initial lightly doped region is 1E18 atom / cm³. 3 Up to 1E21atom / cm 3 The initial lightly doped region formed has a doping depth ranging from 50 nanometers to 500 nanometers.

[0062] Subsequently, a gate and an opening located within the gate trench 106 and the surface of the active region 107 are formed, the opening exposing a portion of the top surface of the active region 107. For the method of forming the gate and the opening in this embodiment, please refer to [reference needed]. Figures 7 to 9 .

[0063] Please refer to Figure 7 , Figure 7 The view direction is the same Figure 6 An initial gate 109 is formed in the gate trench 106 and on the surface of the plurality of active regions 107.

[0064] In this embodiment, before forming the initial gate 109, a gate dielectric layer 110 is also formed in the gate trench 106 and on the surface of the plurality of active regions 107.

[0065] Specifically, the gate dielectric layer 110 is also located on the surface of the well doped layer 105 on the second region II. The gate dielectric layer 110 on the second region II is used to form the gate dielectric layer of the second region device.

[0066] In this embodiment, specifically, the surfaces of the plurality of active regions 107 exposed by the gate trench 106 and the surface of the photosensitive doped layer 104 are oxidized to form the gate dielectric layer 110.

[0067] In this embodiment, the initial gate 109 is made of polycrystalline silicon.

[0068] In this embodiment, the initial gate 109 is used to form the gate of the switching device on each of the pixel regions I, and also to form the peripheral gate of the peripheral device on the second region II.

[0069] Please refer to Figure 8 and Figure 9 , Figure 8 This is a top-down structural diagram. Figure 9 yes Figure 8 A cross-sectional view along the EE1 direction shows the initial gate 109 being etched back until the surface of the isolation structure 103 and part of the active region 107 are exposed, forming the gate 111 and the opening 112.

[0070] Specifically, the initial gate 109 is etched back until the gate dielectric layer 110 on the surface of the isolation structure 103 and part of the surface of the active region 107 is exposed, forming the gate 111 and the opening 112.

[0071] In this embodiment, the initial gate 109 is etched back, and a peripheral gate 201 is also formed on a portion of the well region 200.

[0072] Please refer to Figure 10 , Figure 10 The view direction is the same Figure 9 A first ion is injected into the opening 112 to form the source / drain region 113.

[0073] In this embodiment, the first ion is an N-type conductive ion. In other embodiments, the first ion can be a P-type conductive ion.

[0074] In this embodiment, peripheral source / drain regions 202 are also formed in the well regions 200 of the peripheral devices on both sides of the peripheral gate 201 in the second region II.

[0075] Each of the switching devices includes an active region 107 located on a portion of the photosensitive doped layer 104, a gate 111 located on the active region 107 and the photosensitive doped layer 104, a source / drain layer 113 at the top of the active region 107, and an opening 112 in the gate 111 that exposes a portion of the surface of the source / drain layer 113.

[0076] By stacking the switching devices on the photosensitive doped layer 104, the area occupied by the pixel area is reduced, the pixel density is increased, and there is no need to balance the size of the photosensitive area and the readout circuit, which is beneficial to obtaining better photosensitive characteristics and switching performance.

[0077] Please refer to Figure 11 and Figure 12 , Figure 11 yes Figure 12 Top view structural diagram,Figure 12 yes Figure 11 A cross-sectional view along the EE1 direction shows that after the switching device is formed, a plurality of conductive plugs 114 are formed on the surface of the source / drain region 113. The plurality of conductive plugs 114 on each photosensitive doped layer 104 are arranged along the extension direction of the photosensitive doped layer 104.

[0078] The plurality of conductive plugs 114 on each of the photosensitive doped layers 104 are arranged along the extension direction of the photosensitive doped layer 104. The multiple conductive plugs help to reduce contact resistance and improve device performance.

[0079] In this embodiment, the method for forming the plurality of conductive plugs 114 includes: forming a dielectric material layer on the switching device; forming a plurality of contact holes (not shown in the figure) in the dielectric material layer, the bottom of the plurality of contact holes exposing the surface of the source / drain region 113; and forming the plurality of conductive plugs 114 in the plurality of contact holes.

[0080] In this embodiment, the plurality of conductive plugs 114 are also located on the surface of the gate 111, the surface of the peripheral gate 201, and the surface of the peripheral source / drain region 202.

[0081] In this embodiment, before forming the plurality of conductive plugs 114, a sidewall 115 is also formed on the sidewall of the gate 111.

[0082] Accordingly, this invention also provides a CMOS image sensor formed using the above method. Please refer to [link / reference needed]. Figure 11 and Figure 12 The system includes: a substrate 100, the substrate 100 including a plurality of mutually discrete pixel regions I; photosensitive doped layers 104 respectively located on each of the pixel regions I; and switching devices located on each of the photosensitive doped layers 104.

[0083] By stacking the switching devices on the photosensitive doped layer 104, the area occupied by the pixel area is reduced, the pixel density is increased, and there is no need to balance the size of the photosensitive area and the readout circuit, which is beneficial to obtaining better photosensitive characteristics and switching performance.

[0084] In this embodiment, each of the switching devices includes an active region 107 located on a portion of the photosensitive doped layer 104, and a gate 111 located on the active region 107 and the photosensitive doped layer 104. The active region 107 has a source / drain layer 113 at its top, and the gate 111 has an opening 112 that exposes a portion of the surface of the source / drain layer 113.

[0085] In this embodiment, the substrate includes a first region and a second region II, and the plurality of mutually discrete pixel regions are located in the first region; the second region II has peripheral devices.

[0086] In this embodiment, the peripheral device includes a well region 200 of the peripheral device, a peripheral gate 201 located on a portion of the well region 200, and peripheral source / drain regions 202 located in the well region 200 on both sides of the peripheral gate 201.

[0087] In this embodiment, the top of the source / drain layer 113 also has a lightly doped region 108, and the opening 112 exposes a portion of the lightly doped region 108.

[0088] In this embodiment, the concentration range of the lightly doped region 108 is 1E18 atom / cm³. 3 Up to 1E21atom / cm 3 The lightly doped region 108 has a doping depth ranging from 50 nanometers to 500 nanometers.

[0089] In this embodiment, it further includes: a plurality of conductive plugs 114 located on the surface of the source / drain layer 113, wherein the plurality of conductive plugs 114 on each photosensitive doped layer 104 are arranged along the extension direction of the photosensitive doped layer 104.

[0090] In this embodiment, it also includes: an isolation structure 103 between adjacent photosensitive doped layers 104, and the isolation structure 103 is also located between adjacent switching devices.

[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A CMOS image sensor, characterized in that, include: A substrate, the substrate comprising a plurality of mutually discrete pixel regions; A photosensitive doped layer is located on each of the pixel regions, and a photodiode is formed between the photosensitive doped layer and the pixel region; A switching device located on each of the photosensitive doped layers, each of the switching devices including an active region located on a portion of the photosensitive doped layer, a gate located on the active region and the photosensitive doped layer, the active region having a source / drain layer at its top, and the gate having an opening that exposes a portion of the surface of the source / drain layer.

2. The CMOS image sensor as described in claim 1, characterized in that, The top of the source / drain layer also has a lightly doped region, and the opening exposes a portion of the lightly doped region.

3. The CMOS image sensor as described in claim 1, characterized in that, Also includes: A plurality of conductive plugs are located on the surface of the source / drain layer, and the plurality of conductive plugs on each of the photosensitive doped layers are arranged along the extension direction of the photosensitive doped layer.

4. The CMOS image sensor as described in claim 1, characterized in that, Also includes: There is an isolation structure between adjacent photosensitive doped layers, and the isolation structure is also located between adjacent switching devices.

5. The CMOS image sensor as described in claim 1, characterized in that, The substrate includes a first region and a second region, with the plurality of mutually discrete pixel regions located in the first region; the second region has peripheral devices.

6. A method for forming a CMOS image sensor, characterized in that, include: A substrate and several photosensitive doped layers are formed. The substrate includes several mutually discrete pixel regions. The photosensitive doped layers are respectively located on each of the pixel regions, and a photodiode is formed between the photosensitive doped layers and the pixel regions. A switching device is formed on each of the photosensitive doped layers. Each switching device includes an active region located on a portion of the photosensitive doped layer, a gate located on the active region and the photosensitive doped layer, a source / drain layer at the top of the active region, and an opening in the gate that exposes a portion of the surface of the source / drain layer.

7. The method for forming a CMOS image sensor as described in claim 6, characterized in that, The method of forming the substrate and a plurality of photosensitive doped layers includes: forming a substrate structure, the substrate structure including the substrate and an initial photosensitive doped layer located on the substrate; forming an isolation structure within the substrate structure, the isolation structure penetrating the initial photosensitive doped layer and the isolation structure also located between adjacent pixel regions, such that the initial photosensitive doped layer forms a plurality of mutually discrete photosensitive doped layers.

8. The method for forming a CMOS image sensor as described in claim 7, characterized in that, The substrate structure further includes: an initial well doped layer located on the initial photosensitive doped layer; the isolation structure also extends through the initial well doped layer, so that the initial well doped layer forms a plurality of mutually discrete well doped layers.

9. The method for forming a CMOS image sensor as described in claim 8, characterized in that, The method for forming the substrate structure includes: providing an initial substrate; implanting a first dopant ion into the initial substrate to form an initial photosensitive doped layer in the initial substrate, wherein the top surface of the initial photosensitive doped layer is lower than the surface of the initial substrate to form the substrate structure; forming the substrate with the initial substrate under the initial photosensitive doped layer; and forming the initial substrate on the initial photosensitive doped layer.

10. The method for forming a CMOS image sensor as described in claim 8, characterized in that, The method for forming the substrate structure includes: providing an initial substrate; implanting a first dopant ion into the initial substrate to form the substrate and an initial photosensitive doped layer located on the substrate, wherein the top surface of the initial photosensitive doped layer is exposed; forming an epitaxial layer on the surface of the initial photosensitive doped layer; and implanting a second dopant ion into the epitaxial layer to form the initial well doped layer.

11. The method for forming a CMOS image sensor as described in claim 8, characterized in that, The method for forming the switching device includes: etching the well-doped layer until the photosensitive doped layer is exposed to form a gate trench; forming the active region with the well-doped layer, the gate trench exposing the active region and the isolation structure; forming a gate and an opening located in the gate within the gate trench and on the surface of the active region, the opening exposing a portion of the top surface of the active region; and implanting a first ion into the opening to form the source / drain layer.

12. The method for forming a CMOS image sensor as described in claim 11, characterized in that, The method for forming the gate and the opening includes: forming an initial gate in the gate trench and on the surfaces of the plurality of active regions; etching back the initial gate until the surface of the isolation structure and part of the surface of the active regions are exposed, thereby forming the gate and the opening.

13. The method for forming a CMOS image sensor as described in claim 12, characterized in that, Before forming the initial gate, the method further includes forming a gate dielectric layer in the gate trench and on the surface of the plurality of active regions.

14. The method for forming a CMOS image sensor as described in claim 11, characterized in that, Also includes: Before etching the well-doped layer, a second ion is implanted on the surface of the well-doped layer to form an initial lightly doped region. The initial lightly doped region is etched to form a lightly doped region.

15. The method for forming a CMOS image sensor as described in claim 14, characterized in that, The process parameters for forming the initial lightly doped region include: dopant ions include N-type ions, and the implantation dose range is 5E12 atom / cm². 2 Up to 5E14 atom / cm 2 .

16. The method for forming a CMOS image sensor as described in claim 6, characterized in that, After forming the switching device, the method further includes: forming a plurality of conductive plugs on the surface of the source / drain layer, wherein the plurality of conductive plugs on each photosensitive doped layer are arranged along the extension direction of the photosensitive doped layer.

17. The method for forming a CMOS image sensor as described in claim 16, characterized in that, Before forming the plurality of conductive plugs, the method further includes: forming a sidewall on the gate sidewall.

18. The method for forming a CMOS image sensor as described in claim 6, characterized in that, The substrate includes a first region and a second region, and the plurality of mutually discrete pixel regions are located in the first region; the method includes: forming peripheral devices on the second region.

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