A method for preparing a pip capacitor

Abstract

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

Description

Technical Field

[0001] The present invention relates to the field of CMOS integrated circuit manufacturing processes, and particularly to a method for fabricating a PIP capacitor. Background Art

[0002] In large-scale integrated circuit manufacturing processes, doped polysilicon is often used as gate electrodes and polycrystalline interconnect materials. With the continuous improvement of circuit integration, device dimensions are further reduced, the polycrystalline thickness is continuously decreased, and the polycrystalline resistance increases instead, failing to meet the requirements of lower resistance for device gate electrodes and polycrystalline interconnects. In sub-micron integrated circuit manufacturing processes, doped polysilicon is replaced by tungsten silicide (WSi x , 1.5 < x < 2.5) polycide. In the WSi x polycide process, polysilicon is first grown, then the polysilicon is doped by diffusion, and then a layer of tungsten silicide WSi x is deposited to form a polycide stacked structure, thereby reducing the resistance of the gate electrode. At the same time, this stacked structure can be used as the lower electrode of a polysilicon-insulator-polysilicon (abbreviated as PIP) capacitor, thereby realizing a digital-analog hybrid process.

[0003] However, using WSi x as the lower electrode of the PIP capacitor has two drawbacks. The first drawback is that WSi x has a very large stress, reaching 5 - 15×10 8 Pa. In the polycide CMOS process, after the deposition of WSi x , it will undergo multiple high-temperature thermal processes above 8**0**0 °C, such as sidewall deposition, source-drain annealing (or drive-in) and dielectric reflow, etc. During the high-temperature thermal processes, due to its own stress exceeding the adhesion force to the underlying polysilicon, the WSi x layer is extremely prone to upward curling and large-area peeling separation, seriously affecting the stability and reliability of the PIP capacitor. The second drawback is that the surface of WSi x is prone to oxidation, which is particularly obvious during high-temperature thermal processes. A parasitic SiO2 layer capacitor is formed on the lower electrode of the PIP capacitor, resulting in a decrease in the capacitance value of the PIP capacitor and a deterioration in accuracy.

[0004] For WSi xStress can be optimized by using thin film growth methods with lower stress. "Chemical Vapor Deposition of Tungsten and Tungsten Silicides for VLSI / ULSI Applications" (Publisher: William Andrew, December 31, 1992, p. 204) proposes replacing SiH4 with SiH2Cl2 as the reactant gas in WSi... x Thin film peeling was significantly reduced. The paper "Analysis of stress in chemical vapor deposition silicide film" (Journal of Applied Physics, 1985, Vol. 58, p. 4194) suggests that increasing the Si / W ratio can significantly reduce stress. However, even under optimal growth conditions, WSi... x The stress still fluctuates significantly, WSi x Peeling is difficult to avoid. Currently, the most commonly used process is in WSi... x After thin film deposition, a SiO2 cap layer (CAP) is deposited, as described in the US patent "Polycide gate MOSFET process for integrated circuits" (US patent 5089432, February 18, 1992). This is because the SiO2 film stress is -10... 9 Pa can effectively alleviate WSi. x Tensile stress in thin films. The research on WSi Polycide process (Electronics & Packaging, 2012, No. 12, p. 29) indicates that the CAP layer can only maintain the current WSi... x The stress of the thin film cannot reduce WSi x The stress on the thin film. Moreover, the CAP layer increases the complexity of the process, especially making it difficult to control the morphology of polycrystalline etching.

[0005] For WSi x Surface oxidation, as described in "Oxidation mechanisms in WSi2 thin films" (Applied Physics Letters, 1978, No. 33, p. 76), indicates that during high-temperature thermal processes at 800–1100℃, WSi… x Si in the lower polycrystalline layer will move to WSi x The upper surface reacts with oxygen to form parasitic SiO2. Due to the polycide CMOS process, WSi... xAfter deposition, it undergoes multiple high-temperature thermal processes exceeding 800℃, WSi x The quality and thickness of the parasitic SiO2 film formed on the surface are difficult to control precisely. Summary of the Invention

[0006] In order to overcome the defects of the prior art, the purpose of this invention is to provide a method for preparing PIP capacitors, so as to solve the technical problem of low capacitance value of PIP capacitors in the current metal silicide process.

[0007] This invention is achieved through the following technical solution:

[0008] A method for manufacturing a PIP capacitor includes the following steps:

[0009] Step 1: Deposit an undoped polysilicon layer on a silicon substrate wafer that has undergone trap implantation, active region photolithography and etching, field region isolation and gate oxide, and then perform N-type diffusion doping on the polysilicon layer.

[0010] Step 2: Deposit WSi on the polycrystalline silicon layer after N-type diffusion doping. x layer;

[0011] Step 3, for deposited WSi x The polysilicon layer behind the layer is photolithographically and etched. After etching, the resist is removed to form the lower electrode of the PIP capacitor.

[0012] Step 4: Perform reverse photolithography on the lower electrode of the PIP capacitor to implant phosphorus into the WSi of the lower electrode of the PIP capacitor. x Layers, enabling WSi x Layer amorphization reduces WSi x The stress on the thin film;

[0013] Step 5, WSi of the lower plate of the PIP capacitor after phosphorus injection. x Surface etching of the layer, removing WSi by dry etching. x The parasitic SiO2 on the surface of the layer is etched and then the resist is removed.

[0014] Step 6: Deposit a PIP capacitor dielectric layer on the lower electrode of the de-adhesive PIP capacitor;

[0015] Step 7: Deposit polycrystalline PIP capacitor upper plate on the PIP capacitor dielectric layer and perform N-type implantation doping.

[0016] Step 8: Perform photolithography and etching on the polycrystalline upper plate of the PIP capacitor, and remove the resist after etching to form the PIP capacitor.

[0017] Preferably, in step 1, N-well implantation, P-well implantation, active region photolithography and etching, field isolation, and gate oxide growth are first performed on the silicon substrate wafer; then, a thickness is deposited using a CVD method. An undoped polycrystalline silicon layer was subjected to N-type diffusion doping using a liquid phosphorus source, POCl3.

[0018] Preferably, in step 2, a layer is formed by depositing a CVD or PVD method on the polycrystalline silicon layer after N-type diffusion doping. WSi x layer.

[0019] Preferably, in step 3, the deposited WSi x The polysilicon layer behind the photolithography layer is subjected to photolithography and etching. Photolithography includes coating, exposure and development. An etching masking layer is formed on the polysilicon layer after photolithography using photoresist.

[0020] Preferably, in step 4, PIP capacitor reverse photolithography is performed on the lower electrode of the PIP capacitor. The photolithography includes photoresist coating, exposure and development. A capacitor reverse masking layer is formed on the lower electrode of the PIP capacitor using photoresist. The size of the capacitor reverse masking layer is 0 to 0.2 μm larger than that of the PIP capacitor. The polarity of the layout layers of the capacitor reverse photolithography and the PIP capacitor photolithography is opposite.

[0021] Preferably, in step 4, the energy range for phosphorus injection is 20–100 keV, and the injection dose is 1 × 10⁻⁶. 15 ~1×10 16 / cm 2 The principle for selecting the injection energy is to maximize the depth (R) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness.

[0022] Preferably, in step 5, the WSi of the lower electrode of the PIP capacitor after phosphorus injection is... x Surface etching of the layer, removing WSi by dry etching. x Parasitic SiO2 on the layer surface, with CF4 and CHF3 as the main etching gases, SiO2 / WSi x The etching selectivity ratio is 10:1. After etching, the photoresist masking layer of the PIP capacitor reverse photolithography is removed.

[0023] Preferably, in step 6, a SiO2 or Si3N4 dielectric layer is deposited using a CVD method as the dielectric layer for the PIP capacitor, and the thickness of the SiO2 dielectric layer ranges from [missing information]. The thickness range of the Si3N4 dielectric layer is:

[0024]

[0025] Preferably, in step 7, the thickness is deposited using a CVD method. Undoped polycrystalline silicon layers were implanted using energy ranges of 50–80 keV and implantation doses of 1–2 × 10⁻⁶. 16 / cm 2 N-type doping is achieved by phosphorus implantation.

[0026] Preferably, in step 8, photolithography and etching are performed on the polycrystalline upper electrode of the PIP capacitor. The photolithography includes photoresist coating, exposure and development. A PIP capacitor etching masking layer is formed on the polycrystalline upper electrode of the PIP capacitor using photoresist. After etching, the photoresist is removed by dry and wet methods to form the PIP capacitor.

[0027] Compared with the prior art, the present invention has the following beneficial technical effects:

[0028] This invention provides a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by injection. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

[0029] WSi is removed by dry etching. x The parasitic SiO2 on the thin film surface reduces the parasitic capacitance of the lower electrode of the PIP capacitor, significantly increasing the capacitance value of the PIP capacitor. Dry etching offers high selectivity for WSi. x Thin film damage is minimal. The main etching gases for SiO2 are CF4 and CHF3, SiO2 / WSi x The etching selectivity can reach 10:1, and this gas etching can effectively remove WSi. x SiO2 on the thin film surface, without causing excessive WSi x Layer loss. Attached Figure Description

[0030] Figure 1 This is a flowchart of the PIP capacitor preparation method in this invention.

[0031] Figure 2This is a schematic diagram of a CMOS structure containing a PIP capacitor in an embodiment of the present invention.

[0032] Figure 3 This is a schematic diagram of the silicon substrate after gate oxide deposition and before the first polycrystalline deposition in an embodiment of the present invention.

[0033] Figure 4 In this embodiment of the invention, the lower electrode of the PIP capacitor undergoes first polycrystalline deposition and diffusion doping, and WSi... x Schematic diagram of layer deposition.

[0034] Figure 5 This is a schematic diagram of the first polycrystalline photolithography and etching of the lower electrode of the PIP capacitor in an embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of the lower electrode of the PIP capacitor after the first polycrystalline etching and resist removal in an embodiment of the present invention.

[0036] Figure 7 This is a schematic diagram of the lightly doped source / drain, sidewalls, and source / drain components completed in an embodiment of the present invention.

[0037] Figure 8 This is a schematic diagram of reverse photolithography and implantation of PIP capacitors in an embodiment of the present invention.

[0038] Figure 9 WSi is an embodiment of the present invention. x Schematic diagram of etching parasitic SiO2 layer on the surface of the layer.

[0039] Figure 10 WSi is an embodiment of the present invention. x A schematic diagram of the parasitic SiO2 layer on the surface after etching and removing the resist.

[0040] Figure 11 This is a schematic diagram of SiO2 or Si3N4 deposition in the dielectric layer of the PIP capacitor in an embodiment of the present invention.

[0041] Figure 12 This is a schematic diagram of the second polycrystalline deposition and implantation doping of the upper plate of the PIP capacitor in an embodiment of the present invention.

[0042] Figure 13 This is a schematic diagram of PIP capacitor photolithography and etching in an embodiment of the present invention.

[0043] In the diagram: 001 - Silicon substrate; 002 - First field isolation structure; 0021 - Second field isolation structure; 0022 - Third field isolation structure; 003 - P-well; 004 - N-well; 005 - Gate oxide; 006 - First polycrystalline structure; 007 - WSi xLayer; 008-N-type lightly doped source / drain; 009-P-type lightly doped source / drain; 010-Sidewall; 011-N-type source / drain; 012-P-type source / drain; 013-Parasitic SiO2 layer; 014-PIP capacitor dielectric layer; 015-Second polysilicon; 031-First photoresist; 032-Second photoresist; 033-Third photoresist; 041-N-type polysilicon gate; 042-P-type polysilicon gate; 051-NMOS transistor; 052-PMOS transistor; 053-PIP capacitor. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] The present invention will now be described in further detail with reference to the accompanying drawings:

[0047] The purpose of this invention is to provide a method for preparing PIP capacitors, so as to solve the technical problem of low capacitance value of PIP capacitors in the current metal silicide process.

[0048] For details, see Figure 1 The method for manufacturing a PIP capacitor includes the following steps:

[0049] Step 1: Deposit an undoped polysilicon layer (first polysilicon 006) on a wafer that has completed well implantation, active region photolithography and etching, field isolation 002 and gate oxide 005, and perform N-type diffusion doping on the polysilicon layer (first polysilicon 006).

[0050] Specifically, on the silicon substrate 001 wafer, N-well 004 implantation, P-well 003 implantation, active area photolithography and etching, field isolation 002 and gate oxide 005 growth are first performed; then, a thickness is formed by deposition using CVD methods. An undoped polycrystalline silicon layer (first polycrystalline 006) is subjected to N-type diffusion doping using a liquid phosphorus source POCl3.

[0051] Step 2: Deposit WSi on the polycrystalline silicon layer (first polycrystalline 006) after N-type diffusion doping. x Layer 007;

[0052] Specifically, N-type diffusion doping is performed on a polycrystalline silicon layer, which is then deposited using CVD or PVD methods to form... WSi x Layer 007.

[0053] Step 3, for deposited WSi x The polysilicon layer after layer 007 (first polysilicon 006) is photolithographically and etched. After etching, the resist is removed to form the lower electrode of the PIP capacitor.

[0054] Specifically, for deposited WSi x The polysilicon layer (first polysilicon 006) after layer 007 is subjected to photolithography and etching, wherein photolithography includes coating, exposure and development, and an etching masking layer is formed on the photolithographic polysilicon layer (first polysilicon 006) using photoresist.

[0055] Step 4: Perform reverse photolithography on the lower electrode of the PIP capacitor to implant phosphorus into the WSi of the lower electrode of the PIP capacitor. x Layer 007 enables WSi x Layer 007 is amorphized to reduce WSi x The stress on the thin film;

[0056] Specifically, reverse photolithography of the lower electrode of the PIP capacitor is performed. The photolithography includes photoresist coating, exposure, and development. A reverse masking layer is formed on the lower electrode of the PIP capacitor using photoresist. The size of the reverse masking layer is 0–0.2 μm larger than that of the PIP capacitor. The polarity of the layout layers in the reverse photolithography and the PIP capacitor photolithography are opposite. The phosphorus implantation energy range is 20–100 keV, and the implantation dose is 1 × 10⁻⁶. 15 ~1×10 16 / cm 2 The principle for selecting the injection energy is to maximize the depth (R) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness.

[0057] Step 5, WSi of the lower plate of the PIP capacitor after phosphorus injection. x Layer 007 surface etching, WSi is removed by dry etching. x The parasitic SiO2 layer 013 on the surface of layer 007 is etched and then the resist is removed.

[0058] Specifically, regarding the WSi of the lower plate of a PIP capacitor after phosphorus injection... x Layer 007 surface etching, WSi is removed by dry etching. x A parasitic SiO2 layer 013 is present on the surface of layer 007, in which CF4 and CHF3 are used as the main etching gases, and the SiO2 / WSi ratio is... x The etching selectivity ratio is 10:1. After etching, the photoresist masking layer of the PIP capacitor reverse photolithography is removed.

[0059] Step 6: Deposit the PIP capacitor dielectric layer 014 on the lower electrode of the de-adhesive PIP capacitor;

[0060] Specifically, SiO2 or Si3N4 dielectric layers are deposited using CVD as the dielectric layer 014 of the PIP capacitor. The thickness range of the SiO2 dielectric layer is [missing information]. The thickness range of the Si3N4 dielectric layer is:

[0061] Step 7: Deposit the polycrystalline upper plate (second polycrystalline 015) of the PIP capacitor on the dielectric layer 014 of the PIP capacitor and perform N-type implantation doping.

[0062] Specifically, thickness is deposited using CVD methods. An undoped polycrystalline silicon layer (second polycrystalline 015) was implanted with an energy range of 50–80 keV and an implantation dose of 1–2 × 10⁻⁶. 16 / cm 2 N-type doping is achieved by phosphorus implantation.

[0063] Step 8: Perform photolithography and etching on the polycrystalline upper plate (second polycrystalline 015) of the PIP capacitor, and remove the resist after etching to form the PIP capacitor.

[0064] Specifically, photolithography and etching are performed on the polycrystalline upper electrode (second polycrystalline 015) of the PIP capacitor. Photolithography includes photoresist coating, exposure and development. A PIP capacitor etching mask layer is formed on the polycrystalline upper electrode (second polycrystalline 015) of the PIP capacitor using photoresist. After etching, the photoresist is removed by dry and wet methods to form the PIP capacitor 053.

[0065] In one embodiment of the present invention, a CMOS process containing PIP capacitors is provided, the specific steps of which are as follows:

[0066] Step 1: Provide a silicon substrate 001. Following known processes, perform N-well 004 implantation, P-well 003 implantation, active area photolithography and etching, field isolation 002 (second field isolation structure 0021 and third field isolation structure 0022), and gate oxide 005. The field isolation 002, second field isolation structure 0021, and third field isolation structure 0022 are made of the same material. Figure 3 As shown;

[0067] Step 2: Deposit a thickness using CVD method. An undoped polycrystalline silicon layer was used as the first polycrystalline 006. The first polycrystalline 006 was then N-type diffused doped using a liquid phosphorus source, POCl3, and deposited using CVD or PVD methods. WSi x Layer 007, such as Figure 4 As shown;

[0068] Step 3, first polycrystalline 006 photolithography (including resist coating, exposure, and development), first polycrystalline 006 dry etching, the first photoresist 031 is the etching mask layer for the first polycrystalline 006, such as... Figure 5 As shown;

[0069] Step 4: After etching the first polycrystalline substrate 006, dry and wet resist removal is performed to form the lower electrode of the PIP capacitor. Simultaneously, a polycrystalline gate for the MOS device is formed in the CMOS device region, including an N-type polycrystalline gate 041 and a P-type polycrystalline gate 042. Later, an NMOS transistor 051, a PMOS transistor 052, and a PIP capacitor 053 will be formed on the silicon substrate 001, as follows... Figure 6 As shown;

[0070] Step 5: Following known processes such as N-type lightly doped source / drain 008, P-type lightly doped source / drain 009, sidewall 010, N-type source / drain 011, P-type source / drain 012, and source / drain annealing (or push-up), complete the front-end process of the MOS device. Since WSi... x 007 oxidizes during the thermal processes of sidewall deposition and source / drain annealing (or push-bonding), WSi x A parasitic SiO2 layer 013 is grown on the surface of layer 007, such as... Figure 7 As shown;

[0071] Step 6: Add PIP capacitor reverse photolithography (including resist coating, exposure, and development) and perform WSi. x Phosphorus implantation in layer 007, through implantation to WSi x Layer 007 is amorphized, thereby reducing WSi xThe stress on the thin film. The second photoresist 32 is a PIP capacitor reverse masking layer. The PIP capacitor reverse photolithography is designed to have the same pattern size as the PIP capacitor photolithography, but with opposite polarity. Alternatively, considering overlay deviations, the PIP capacitor reverse photolithography is slightly larger than the PIP capacitor photolithography by 0.05–0.2 μm. The phosphorus implantation energy range is 20–100 keV, and the implantation dose is 1 × 10⁻⁶. 15 ~1×10 16 / cm 2 The principle for selecting the injection energy is to maximize the depth (R) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x The film thickness is 80%. Additionally, phosphorus implantation also increases WSi. x The doping concentration of the first polycrystalline 006 layer under layer 007 reduces polycrystalline depletion, such as... Figure 8 As shown;

[0072] Step 7, perform WSi x Layer 007 surface etching, WSi is removed by dry etching. x A parasitic SiO2 layer 013 is grown on the surface of layer 007. CF4 and CHF3 are selected as the main etching gases to achieve a high SiO2 / WSi ratio. x Etching selectivity, such as Figure 9 As shown;

[0073] Step 8, WSi x After etching the parasitic SiO2 layer 013 on the surface of layer 007, dry and wet photoresist removal is performed to remove the second photoresist 32, as shown below. Figure 10 As shown;

[0074] Step 9: Deposit a SiO2 or Si3N4 dielectric layer using CVD as the PIP capacitor dielectric layer 014. The thickness of the SiO2 dielectric layer ranges from [missing information]. The thickness range of the Si3N4 dielectric layer is: The thickness of the 014 dielectric layer in a PI capacitor determines the capacitance value; the thinner the layer, the larger the capacitance. Figure 11 As shown;

[0075] Step 10: Deposit thickness using CVD method Undoped polycrystalline silicon layers were implanted using energy ranges of 50–80 keV and implantation doses of 1–2 × 10⁻⁶. 16 / cm 2 Phosphorus implantation achieves N-type doping, serving as the second polycrystalline 015 on the upper plate of a PIP capacitor, such as... Figure 12 As shown;

[0076] Step 11, photolithography of PIP capacitors (including resist coating, exposure, and development), dry etching of PIP capacitors, the third photoresist 033 is the PIP capacitor etching mask layer, such as... Figure 13 As shown, after etching, the third photoresist 033 is removed using both dry and wet methods to form the PIP capacitor 053, and simultaneously, the NMOS transistor 051 and the PMOS transistor 052 are formed. The final structure is as follows. Figure 2 As shown.

[0077] This invention first reduces the WSi of the lower electrode by injection. x Thin film stress can improve the reliability of PIP capacitors; then, by reducing parasitic SiO2 on the surface of the lower electrode through dry etching, the capacitance of the PIP capacitor can be improved.

[0078] Injection can reduce the WSi of the lower electrode plate of PIP. x Thin film stress. WSi x Stress was measured using a stress analyzer. Table 1 shows the WSi values. x The stress of the thin film after various element implantations. The film structure is: P-type (100) silicon substrate + SiO2. +polycrystalline +WSi x The principle for selecting the injection energy is to make the R of the injected element... p The values ​​are comparable, and the depth of the injected Gaussian distribution (R) is similar. p +3ΔR p ) to reach the entire WSi x The film thickness is approximately 80%. It can be seen that after implantation, WSi... x The stress in the thin film was reduced by an order of magnitude. This invention selects phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

[0079]

[0080] Table 1 WSi x Stress variation of thin film with different element injections (injection dose: 6×10) 15 / cm 2 )

[0081] WSi is removed by dry etching. x The parasitic SiO2 on the thin film surface reduces the parasitic capacitance of the lower electrode of the PIP capacitor. Dry etching offers high selectivity for WSi. x Thin film damage is minimal. The main etching gases for SiO2 are CF4 and CHF3, SiO2 / WSi xThe etching selectivity can reach 10:1, and this gas etching can effectively remove WSi. x SiO2 on the thin film surface, without causing excessive WSi x Layer loss.

[0082] Table 2 shows the test results of PIP capacitors in the old and new processes. As can be seen from the table, the PIP capacitor value of the old process (baseline) is smaller. After increasing PIP implantation and etching, the PIP capacitor value is 163% to 213% of that of the old process.

[0083]

[0084] Table 2 Test Results of PIP Capacitors under New and Old Processes

[0085] The present invention will now be further described with reference to the embodiments:

[0086] Example 1: 0.35μm silicon gate CMOS process with high-precision PIP

[0087] (1) Oxidation growth on the original silicon wafer SiO2;

[0088] (2) In CVD deposition growth on SiO2 Silicon nitride;

[0089] (3) Active region photolithography, dry etching field region Silicon nitride, etching followed by removal of resist;

[0090] (4) Oxidation formation field isolation;

[0091] (5) Complete stripping of silicon nitride;

[0092] (6) N-well photolithography, PMOS well implantation, including well implantation, anti-penetration implantation and threshold implantation, and then resist removal after implantation;

[0093] (7) P-well photolithography, NMOS well implantation, including well implantation, anti-penetration implantation and threshold implantation, and then resist removal after implantation;

[0094] (8) Oxidative growth SiO2 gate oxide layer;

[0095] (9) CVD deposition formation Polycrystalline silicon layer, N-type polycrystalline diffusion doping;

[0096] (10) CVD deposition formation WSi x layer;

[0097] (11) First polycrystalline photolithography and etching, followed by resist removal to form the lower electrode of the PIP capacitor, and simultaneously in the CMOS.

[0098] The device region forms the polysilicon gate of the MOS device;

[0099] (12) N-type lightly doped source drain lithography and implantation, followed by resist removal;

[0100] (13) P-type lightly doped source drain photolithography and implantation, followed by resist removal;

[0101] (14) CVD deposition formation The sidewall oxide layer;

[0102] (15) Sidewall etching;

[0103] (16) N-type source-drain photolithography and implantation, followed by resist removal;

[0104] (17) P-type source-drain photolithography and implantation, followed by resist removal;

[0105] (18) Source drain annealing;

[0106] (19) Add PIP capacitor reverse lithography, first perform WSi x Phosphorus implantation was performed at an energy of 40 keV and a dose of 5 × 10⁻⁶. 15 / cm 2 WSi is made through injection x Layer amorphization, thereby reducing WSi x The stress in the thin film. Additionally, implantation increases the polycrystalline doping concentration and reduces polycrystalline depletion;

[0107] (20) Increase WSi x Surface etching of the layer, removing WSi by dry etching. x For parasitic SiO2 on the layer surface, CF4 and CHF3 are selected as the main etching gases to achieve a high SiO2 / WSi ratio. x Etching selectivity, and resist removal after etching;

[0108] (21) CVD deposition forms the SiO2 dielectric layer of PIP capacitor. The dielectric thickness is set according to the target capacitance value. The smaller the thickness, the larger the capacitance value.

[0109] (22) A second polycrystalline material is formed by CVD deposition to serve as the upper electrode of the PIP capacitor. The thickness of the second polycrystalline material is [missing information]. Pass

[0110] The over-injection energy was 60 keV and the injection dose was 1.4 × 10⁻⁶. 16 / cm 2 Phosphorus implantation achieves N-type doping;

[0111] (23) Photolithography and etching of PIP capacitors, followed by removal of the resist after etching to form PIP capacitors;

[0112] (24) Deposition and formation of Ti silicides.

[0113] (25) CVD deposition formation USG layer;

[0114] (26) CVD deposition formation BPSG layer;

[0115] (27) Medium reflux;

[0116] (28) Chemical mechanical grinding BPSG layer;

[0117] (29) CVD deposition formation USG layer, thus the equivalent ILD thickness on the active region is

[0118] (30) Ohmic aperture lithography and etching, followed by resist removal;

[0119] (31) Sputtering formation Ti and TiN;

[0120] (32) CVD deposition formation Metallic tungsten layer;

[0121] (33) Chemical mechanical grinding Metallic tungsten layer;

[0122] (34) Sputtering formation Ti and TiN;

[0123] (35) Sputtering formation AlSiCu metal layer;

[0124] (36) Metal photolithography and etching, followed by resist removal;

[0125] (37) CVD deposition formation SiO2 / Si3N4 passivation layer;

[0126] (38) Photolithography and etching of passivation layer, followed by removal of resist after etching;

[0127] (39) Alloy;

[0128] (40) Test the output of the film.

[0129] Example 2: 0.5μm silicon gate CMOS process with high-precision PIP

[0130] (1) Oxidation growth on the original silicon wafer SiO2;

[0131] (2) In CVD deposition growth on SiO2 Silicon nitride;

[0132] (3) Photolithography active region, dry etching field region Silicon nitride, etching followed by removal of resist;

[0133] (4) Photolithography is used to implant the N-well into the PMOS well, and the resist is removed after implantation;

[0134] (5) Photolithography of the P-well is used to implant the NMOS well, and the resist is removed after implantation;

[0135] (6) Oxidation formation field isolation and push trap;

[0136] (7) Fully stripped silicon nitride;

[0137] (8) Threshold adjustment injection;

[0138] (9) Oxidative growth SiO2 gate oxide layer;

[0139] (10) CVD deposition formation Polycrystalline silicon layer, N-type polycrystalline diffusion doping;

[0140] (11) CVD deposition formation WSi x layer;

[0141] (12) First polycrystalline photolithography and etching, followed by resist removal to form the lower electrode of the PIP capacitor, and simultaneously in the CMOS.

[0142] The device region forms the polysilicon gate of the MOS device;

[0143] (13) N-type lightly doped source drain lithography and implantation, followed by resist removal;

[0144] (14) P-type lightly doped source drain lithography and implantation, followed by resist removal;

[0145] (15) CVD deposition formation The sidewall oxide layer;

[0146] (16) Sidewall etching;

[0147] (17) N-type source-drain photolithography and implantation, followed by resist removal;

[0148] (18) P-type source-drain photolithography and implantation, followed by resist removal;

[0149] (19) Source-drain push-to-connection;

[0150] (20) Add PIP capacitor reverse photolithography, first perform WSi x Phosphorus implantation was performed at an energy of 60 keV and a dose of 6 × 10⁻⁶. 15 / cm 2 WSi is made through injection x Layer amorphization, thereby reducing WSi x The stress on the thin film, in addition, the implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion;

[0151] (21) Perform WSi again x Surface etching of the layer, removing WSi by dry etching. x For parasitic SiO2 on the layer surface, CF4 and CHF3 are selected as the main etching gases to achieve a high SiO2 / WSi ratio. x Etching selectivity, and resist removal after etching;

[0152] (22) CVD deposition forms the SiO2 dielectric layer of PIP capacitor. The dielectric thickness is set according to the target capacitance value. The smaller the thickness, the larger the capacitance value.

[0153] (23) A second polycrystalline material is formed by CVD deposition to serve as the upper electrode of the PIP capacitor. The thickness of the second polycrystalline material is [missing information]. By injecting energy of 70 keV and an injection dose of 1.6 × 10⁻⁶ 16 / cm 2 Phosphorus implantation achieves N-type doping;

[0154] (24) Photolithography and etching of PIP capacitors, followed by removal of the resist after etching to form PIP capacitors;

[0155] (25) Source-drain push-connection;

[0156] (26) CVD deposition formation USG layer;

[0157] (27) CVD deposition formation BPSG layer;

[0158] (28) Medium reflux;

[0159] (29) Chemical mechanical grinding BPSG layer;

[0160] (30) CVD deposition formation USG layer, thus the equivalent ILD thickness on the active region is

[0161] (31) Ohmic aperture lithography and etching, followed by resist removal;

[0162] (32) Sputtering formation Ti and TiN;

[0163] (33) CVD deposition formation Metallic tungsten layer;

[0164] (34) Chemical mechanical grinding Metallic tungsten layer;

[0165] (35) Sputtering formation Ti and TiN;

[0166] (36) Sputtering formation AlSiCu metal layer;

[0167] (37) Metal photolithography and etching, followed by resist removal;

[0168] (38) CVD deposition formation SiO2 / Si3N4 passivation layer;

[0169] (39) Photolithography and etching of passivation layer, followed by removal of resist after etching;

[0170] (40) Alloy;

[0171] (41) Test the output of the film.

[0172] In summary, this invention provides a method for fabricating a PIP capacitor. First, by implanting a method to reduce the WSi of the lower electrode of the PIP capacitor... x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is often addressed by using phosphorus as a dopant in N-type polycrystalline implantation. Phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion. Dry etching is used to eliminate WSi stress. x The parasitic SiO2 on the thin film surface reduces the parasitic capacitance of the lower electrode of the PIP capacitor, significantly increasing the capacitance value of the PIP capacitor. Dry etching offers high selectivity for WSi. x Thin film damage is minimal. The main etching gases for SiO2 are CF4 and CHF3, which essentially do not etch WSi.x SiO2 / WSi x The etching selectivity can reach 10:1, and this gas etching can effectively remove WSi. x SiO2 on the thin film surface, without causing excessive WSi x Layer loss.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a PIP capacitor, characterized in that, Includes the following steps: Step 1: Deposit an undoped polysilicon layer on a silicon substrate wafer that has undergone trap implantation, active region photolithography and etching, field region isolation and gate oxide, and then perform N-type diffusion doping on the polysilicon layer. Step 2: Deposit WSi on the polycrystalline silicon layer after N-type diffusion doping. x layer; Step 3, for deposited WSi x The polysilicon layer behind the layer is photolithographically and etched. After etching, the resist is removed to form the lower electrode of the PIP capacitor. Step 4: Perform reverse photolithography on the lower electrode of the PIP capacitor to implant phosphorus into the WSi of the lower electrode of the PIP capacitor. x Layers, enabling WSi x Layer amorphization reduces WSi x The stress on the thin film; The energy range for phosphorus injection is 20~100 keV, and the injection dose is 1×10⁻⁶. 15 ~1×10 16 / cm 2 The principle for selecting the injection energy is to ensure that the injection Gaussian distribution depth ( R p +3 ΔR p ) to reach the entire WSi x The film thickness increased by 80%; phosphorus implantation also increased WSi. x The doping concentration of the first polycrystalline layer below the current layer reduces polycrystalline depletion; Step 5, WSi of the lower plate of the PIP capacitor after phosphorus injection. x Surface etching of the layer, removing WSi by dry etching. x The parasitic SiO2 on the surface of the layer is etched and then the resist is removed. WSi of the lower plate of a PIP capacitor after phosphorus injection x Surface etching of the layer, removing WSi by dry etching. x Parasitic SiO2 on the layer surface, with CF4 and CHF3 as the main etching gases, SiO2 / WSi x The etching selectivity ratio is 10:

1. After etching, the photoresist masking layer of the reverse photolithography of the PIP capacitor is removed. Step 6: Deposit a PIP capacitor dielectric layer on the lower electrode of the de-adhesive PIP capacitor; Step 7: Deposit polycrystalline PIP capacitor upper plate on the PIP capacitor dielectric layer and perform N-type implantation doping. Step 8: Perform photolithography and etching on the polycrystalline upper plate of the PIP capacitor, and remove the resist after etching to form the PIP capacitor. Photolithography and etching are performed on the polycrystalline upper electrode of the PIP capacitor. Photolithography includes photoresist coating, exposure and development. A PIP capacitor etching masking layer is formed on the polycrystalline upper electrode of the PIP capacitor using photoresist. After etching, the photoresist is removed by dry and wet methods to form the PIP capacitor.

2. The method for preparing a PIP capacitor according to claim 1, characterized in that, In step 1, N-well implantation, P-well implantation, active region photolithography and etching, field isolation and gate oxide growth are performed on the silicon substrate wafer. Then, an undoped polycrystalline silicon layer with a thickness of 1500~2500Å is deposited using the CVD method, and the polycrystalline silicon layer is N-type diffusion doped by liquid phosphorus source POCl3.

3. The method for preparing a PIP capacitor according to claim 1, characterized in that, In step 2, 500~2000 Å WSi is deposited on the polycrystalline silicon layer after N-type diffusion doping using CVD or PVD methods. x layer.

4. The method for preparing a PIP capacitor according to claim 1, characterized in that, In step 3, the deposited WSi x The polysilicon layer behind the photolithography layer is subjected to photolithography and etching. Photolithography includes coating, exposure and development. An etching masking layer is formed on the polysilicon layer after photolithography using photoresist.

5. The method for preparing a PIP capacitor according to claim 1, characterized in that, In step 4, PIP capacitor reverse photolithography is performed on the lower electrode of the PIP capacitor. The photolithography includes photoresist coating, exposure and development. A capacitor reverse masking layer is formed on the lower electrode of the PIP capacitor using photoresist. The size of the capacitor reverse masking layer is 0~0.2μm larger than that of the PIP capacitor. The polarity of the layout layers of the capacitor reverse photolithography and the PIP capacitor photolithography is opposite.

6. The method for preparing a PIP capacitor according to claim 1, characterized in that, In step 6, SiO2 or Si3N4 dielectric layers are deposited using CVD as the dielectric layer of the PIP capacitor. The thickness of the SiO2 dielectric layer ranges from 100 to 500 Å, and the thickness of the Si3N4 dielectric layer ranges from 50 to 300 Å.

7. The method for preparing a PIP capacitor according to claim 1, characterized in that, In step 7, an undoped polycrystalline silicon layer with a thickness of 1500–2500 Å is deposited using a CVD method, with an implantation dose of 1–2 × 10⁻⁶ keV at an energy range of 50–80 keV. 16 / cm 2 N-type doping is achieved by phosphorus implantation.

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