Semiconductor structure, method of manufacturing a semiconductor structure, and semiconductor memory

Abstract

The embodiment of the present disclosure provides a semiconductor structure, a preparation method of the semiconductor structure and a semiconductor memory, the semiconductor structure comprising: a channel doped region; a drain doped region and a source doped region formed on both sides of the channel doped region; an insulating isolation layer comprising a first insulating isolation part and a second insulating isolation part, the first insulating isolation part being formed on a surface of the channel doped region, and the second insulating isolation part being formed on a part of a surface of the drain doped region; a first metal layer formed on a surface of the first insulating isolation part; and a second metal layer formed on a surface of the second insulating isolation part. The embodiment of the present disclosure can inhibit the gate-induced drain leakage current caused by the band-to-band tunneling effect.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor memory. Background Technology

[0002] Gate-induced drain leakage (GIDL) is the primary off-state leakage mechanism in metal-oxide-semiconductor field-effect transistors (MOSFETs), significantly impacting device reliability. When the gate of a MOSFET is off and the drain is connected to voltage, the energy band near the interface of the overlap between the drain impurity diffusion layer and the gate undergoes strong bending, forming an inversion layer on the surface. Since the depletion layer is very narrow, conduction band electrons and valence band holes undergo band-to-band tunneling (BTBT), resulting in drain leakage current. As device size continues to shrink, the transverse electric field within the device continuously strengthens, increasing the probability of off-state leakage due to hot carrier effects. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor memory:

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0005] Channel doped region;

[0006] Drain doped regions and source doped regions are formed on both sides of the channel doped region;

[0007] An insulating isolation layer includes a first insulating isolation portion and a second insulating isolation portion, wherein the first insulating isolation portion is formed on the surface of the channel doped region and the second insulating isolation portion is formed on a portion of the surface of the drain doped region;

[0008] A first metal layer is formed on the surface of the first insulating portion;

[0009] A second metal layer is formed on the surface of the second insulating portion.

[0010] In some embodiments, the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold.

[0011] In some embodiments, the preset work function threshold is 4.6 electron volts.

[0012] In some embodiments, the material of the first metal layer includes at least one of the following: iridium, nickel, platinum, and cobalt.

[0013] In some embodiments, the semiconductor structure further includes a third metal layer, the third metal layer being made of the same material as the second metal layer; wherein...

[0014] The third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer.

[0015] In some embodiments, the dopant ions in the channel doped region, the drain doped region, and the source doped region are of the same type.

[0016] In some embodiments, the channel doped region is a lightly doped region;

[0017] Both the drain doped region and the source doped region are heavily doped regions;

[0018] The dopant concentration in the heavily doped region is greater than that in the lightly doped region.

[0019] In some embodiments, the drain doped region includes a first sub-doped region and a second sub-doped region, and the first sub-doped region is located between the channel doped region and the second sub-doped region; wherein the second insulating isolation portion is formed on the surface of the first sub-doped region.

[0020] In some embodiments, the insulating isolation layer further includes a third insulating isolation portion formed on a portion of the surface of the source doped region;

[0021] The semiconductor structure further includes a fourth metal layer formed on the surface of the third insulating portion.

[0022] In some embodiments, the source doped region includes a third sub-doped region and a fourth sub-doped region, wherein the third sub-doped region is located between the channel doped region and the fourth sub-doped region, and the third insulating isolation portion is formed on the surface of the third sub-doped region; wherein,

[0023] The channel doped region is a lightly doped region;

[0024] Both the first sub-doped region and the third sub-doped region are medium-doped regions;

[0025] Both the second sub-doped region and the fourth sub-doped region are heavily doped regions;

[0026] The dopant concentration in the medium-doped region is greater than that in the lightly doped region, and the dopant concentration in the medium-doped region is less than that in the heavily doped region.

[0027] In some embodiments, the semiconductor structure further includes a fifth metal layer; wherein,

[0028] The fifth metal layer is formed on the surface of the first metal layer, and both ends of the fifth metal layer are respectively connected to the second metal layer and the fourth metal layer.

[0029] In some embodiments, the semiconductor structure further includes bit lines and capacitors; wherein,

[0030] The bit line is connected to the side of the source doped region away from the channel doped region;

[0031] The capacitor is connected to the side of the drain doped region that is away from the channel doped region.

[0032] In some embodiments, the semiconductor structure further includes control leads; wherein...

[0033] The first metal layer and the second metal layer are connected;

[0034] One end of the control lead is connected to the first metal layer and / or the second metal layer, and the other end of the control lead is connected to the control terminal.

[0035] In some embodiments, the semiconductor structure further includes a metal isolation layer, a first control lead, and a second control lead; wherein,

[0036] The metal insulating layer is formed between the first metal layer and the second metal layer to provide insulation between the first metal layer and the second metal layer.

[0037] One end of the first control lead is connected to the first metal layer, and the other end of the first control lead is connected to the first control terminal;

[0038] One end of the second control lead is connected to the second metal layer, and the other end of the second control lead is connected to the second control terminal.

[0039] Secondly, embodiments of this disclosure provide a method for fabricating a semiconductor structure, including:

[0040] Provide substrate;

[0041] The substrate is doped to form a channel doped region, a drain doped region, and a source doped region in the substrate, with the drain doped region and the source doped region forming on both sides of the channel doped region;

[0042] An insulating isolation layer is formed, the insulating isolation layer including a first insulating isolation portion and a second insulating isolation portion, the first insulating isolation portion being formed on the surface of the channel doped region, and the second insulating isolation portion being formed on a portion of the surface of the drain doped region;

[0043] A first metal layer is formed on the surface of the first insulating portion;

[0044] A second metal layer is formed on the surface of the second insulating isolation portion.

[0045] In some embodiments, forming a first metal layer on the surface of the first insulating portion includes:

[0046] A mask layer is formed on the surface of the second insulating isolation portion;

[0047] Using the mask layer as a mask, a first metal layer is formed on the surface of the first insulating and isolating portion;

[0048] Remove the mask layer.

[0049] In some embodiments, when forming a second metal layer on the surface of the second insulating portion, the method further includes:

[0050] A third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer; wherein the material of the third metal layer is the same as the material of the second metal layer.

[0051] In some embodiments, the method further includes:

[0052] A bit line and a capacitor are formed; wherein the bit line is connected to the side of the drain doped region away from the channel doped region; and the capacitor is connected to the side of the source doped region away from the channel doped region.

[0053] In some embodiments, the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold; wherein the preset work function threshold is 4.6 electron volts.

[0054] Thirdly, embodiments of this disclosure provide a semiconductor memory, including the semiconductor structure described in any of the first aspects.

[0055] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor memory. The semiconductor structure includes: a channel doped region; a drain doped region and a source doped region formed on both sides of the channel doped region; an insulating isolation layer including a first insulating isolation portion and a second insulating isolation portion, the first insulating isolation portion being formed on the surface of the channel doped region and the second insulating isolation portion being formed on a portion of the surface of the drain doped region; a first metal layer formed on the surface of the first insulating isolation portion; and a second metal layer formed on the surface of the second insulating isolation portion. Thus, in the semiconductor structure, the second metal layer can reduce the impurity concentration gradient from the drain doped region to the channel doped region, reduce the number of charge carriers near the drain doped region, thereby effectively reducing the electric field strength of the channel doped region and suppressing gate-induced drain leakage current caused by the band-to-band tunneling effect. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the structure of a junctionless transistor;

[0057] Figure 2 This is a schematic diagram of the structure of a junctionless transistor in accumulation mode;

[0058] Figure 3 This is a schematic diagram illustrating the relationship between channel length and electric field strength.

[0059] Figure 4 This is a schematic diagram of an energy band profile;

[0060] Figure 5 A schematic diagram of the composition of a semiconductor structure provided in this disclosure embodiment. Figure 1 ;

[0061] Figure 6 A three-dimensional structural schematic diagram of a transistor provided in an embodiment of this disclosure;

[0062] Figure 7 A schematic diagram of the composition of a semiconductor structure provided in this disclosure embodiment. Figure 2 ;

[0063] Figure 8 A schematic diagram of the composition of a semiconductor structure provided in this disclosure embodiment. Figure 3 ;

[0064] Figure 9 A schematic diagram of the composition of a semiconductor structure provided in this disclosure embodiment. Figure 4 ;

[0065] Figure 10 A schematic diagram of the composition of a semiconductor structure provided in this disclosure embodiment. Figure 5 ;

[0066] Figure 11 A schematic diagram of the composition of a semiconductor structure provided in this disclosure embodiment. Figure 6 ;

[0067] Figure 12 A schematic diagram showing the relationship between channel length and electric field strength provided in this embodiment of the present disclosure;

[0068] Figure 13 A schematic diagram of bandgap contrast provided for embodiments of this disclosure;

[0069] Figure 14 This is a schematic diagram of a control lead connection for individually controlled metal layers, provided in an embodiment of the present disclosure.

[0070] Figure 15 This is a schematic diagram of a control lead connection for joint control of metal layers provided in an embodiment of the present disclosure;

[0071] Figure 16 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0072] Figure 17 A schematic diagram of the structure obtained after forming a channel doped region, a drain doped region, and a source doped region, provided in an embodiment of this disclosure;

[0073] Figure 18 This is a schematic diagram of a structure obtained after forming an insulating layer, provided by an embodiment of the present disclosure;

[0074] Figure 19 This is a schematic diagram of the structure obtained after forming a mask layer according to an embodiment of the present disclosure;

[0075] Figure 20 This is a schematic diagram of a structure obtained after forming a first metal layer, provided by an embodiment of the present disclosure;

[0076] Figure 21 This is a schematic diagram of the structure obtained after removing the mask layer, provided by an embodiment of the present disclosure;

[0077] Figure 22 This is a schematic diagram of a structure obtained after forming a second metal layer, provided by an embodiment of the present disclosure;

[0078] Figure 23 This is a schematic diagram of a structure obtained after forming a third metal layer, provided by an embodiment of the present disclosure;

[0079] Figure 24 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0080] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and not for limiting the applications. Furthermore, it should be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0082] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0083] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0084] Compared to junction-type transistors (JLTs), junctionless transistors eliminate the steep concentration gradient between the channel and the source / drain, reducing the thermal budget, simplifying the fabrication process, and also eliminating the effects of short-channel interference. JLTs can be mainly divided into junction-less transistors (JLTs) and accumulation-mode junction-less transistors (JLAMTs).

[0085] Figure 1 This is a schematic diagram of the structure of a junctionless transistor (JLT). Figure 1 As shown, a JLT may include a channel 101, a drain 102 and a source 103 located on both sides of the channel, a gate dielectric layer 104 formed on the surface of the channel 101, and a gate 105 formed on the surface of the gate dielectric layer 104, wherein D represents a device connected to the drain 102, and S represents a device connected to the source 103. Figure 1 As shown, in the JLT, the channel 101, drain 102, and source 103 are all N-type medium dopant (denoted by N). For example, the ion concentration of N-type medium dopant is: e19 per cubic centimeter (e 19 / cm 3 At this point, due to the expansion of light doping, the transistor has a better off-state, but the transistor's turn-on current is low.

[0086] Figure 2 This is a schematic diagram of the structure of a junctionless transistor (JLAMT) in accumulation mode. Figure 2 As shown, a JLAMT may include a channel 201, a drain 202 and a source 203 located on both sides of the channel, a gate dielectric layer 204 formed on the surface of the channel 201, and a gate 205 formed on the surface of the gate dielectric layer 204, wherein D represents a device connected to the drain 202, and S represents a device connected to the source 203. Figure 2 As shown, in JLAMT, the doping type of channel 201 is N-type light dopant (denoted by N-). For example, the ion concentration of N-type light dopant is: e 18 / cm 3 Both drain 202 and source 203 are N-type heavily doped (denoted by N+). For example, the N-type heavily doped ion concentration is: e 20 / cm 3 At this point, the transistor's turn-on voltage is high, but due to the effects of BTBT, current leakage is more severe.

[0087] Figure 3 This is a schematic diagram illustrating the relationship between channel length and electric field strength. Figure 4 This is a schematic diagram of an energy band profile. Wherein, Figure 3 and Figure 4 All correspond Figure 2 The JLAMT shown. In Figure 3 In the diagram, the horizontal axis represents the channel length (in nanometers (nm)) and the vertical axis represents the electric field strength (in millivolts per centimeter (mV / cm)). In this JLAMT, the electric field strength is relatively strong, resulting in a large leakage current in the transistor. Figure 4 In the JLAMT, the horizontal axis corresponds to the location of the source, channel, and drain, and the vertical axis represents energy (in electron volts (eV)); for example... Figure 4 As shown, this bandgap profile was obtained with a source-drain voltage Vd = 1V and a gate-source voltage Vg = 0V. Due to the strong electric field, the bandgap is large, and the overlap between the conduction band (Ec) of the drain and the valence band (Ev) of the channel is large. These factors all contribute to severe current leakage in the JLAMT.

[0088] Based on this, embodiments of this disclosure provide a semiconductor structure, including: a channel doped region; a drain doped region and a source doped region formed on both sides of the channel doped region; an insulating isolation layer, including a first insulating isolation portion and a second insulating isolation portion, the first insulating isolation portion being formed on the surface of the channel doped region and the second insulating isolation portion being formed on a portion of the surface of the drain doped region; a first metal layer being formed on the surface of the first insulating isolation portion; and a second metal layer being formed on the surface of the second insulating isolation portion. Thus, in the semiconductor structure, the second metal layer formed near the drain doped region can reduce the concentration gradient of impurities from the drain doped region to the channel doped region, reduce the number of charge carriers near the drain doped region, thereby effectively reducing the electric field strength of the channel doped region and suppressing gate-induced drain leakage current (GIDL) caused by the band-to-band tunneling effect (BTBT).

[0089] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0090] In one embodiment of this disclosure, see [link to embodiment]. Figure 5 It illustrates a schematic diagram of the composition of a semiconductor structure 300 provided in an embodiment of this disclosure. Figure 1 .like Figure 5 As shown, the semiconductor structure 300 may include:

[0091] Channel doped region 301;

[0092] Drain doped region 302 and source doped region 303 are formed on both sides of channel doped region 301;

[0093] The insulating isolation layer 304 includes a first insulating isolation portion and a second insulating isolation portion. The first insulating isolation layer portion is formed on the surface of the channel doped region 301, and the second insulating isolation portion is formed on a portion of the surface of the drain doped region 302.

[0094] A first metal layer 305 is formed on the surface of the first insulating portion;

[0095] The second metal layer 306 is formed on the surface of the second insulating isolation portion.

[0096] It should be noted that the semiconductor structure 300 can be formed in the active region of a substrate, which is not shown in the attached figure. Furthermore, this semiconductor structure can be applied to dynamic random access memory (DRAM), such as three-dimensional DRAM (3D DRAM), in which multiple spatially stacked semiconductor structures 300 are formed.

[0097] like Figure 5As shown, the semiconductor structure 300 includes three doped regions: a channel doped region 301, a drain doped region 302, and a source doped region 303, with the drain doped region 302 and the source doped region 303 distributed on both sides of the channel doped region 301. An insulating isolation layer 304 is formed on the surface of the channel doped region 301 and a portion of the surface of the drain doped region 302. A second insulating isolation portion is formed on the side of the drain doped region 302 closest to the channel doped region 301. The insulating isolation layer 304 formed on the surface of the channel doped region 301 is referred to as the first insulating isolation portion, and the insulating isolation layer 304 formed on a portion of the surface of the drain doped region 302 is referred to as the second insulating isolation portion. The first insulating isolation portion and the second insulating isolation portion constitute the complete insulating isolation layer 304. It can be understood that the insulating isolation layer 304 is a complete unit, and the division into the first insulating isolation portion and the second insulating isolation portion is only for ease of description.

[0098] A metal layer is formed on the surface of the insulating layer 304, specifically including a first metal layer 305 and a second metal layer 306; wherein, the first metal layer 305 is formed on the surface of the first insulating portion, and the second metal layer 306 is formed on the surface of the second insulating portion.

[0099] It should be noted that the lengths of the drain doped region 302 and the source doped region 303 can be the same, and the length of the second metal layer 306 can be one-fifth to one-half the length of the drain doped region 302 or the source doped region 303.

[0100] It should also be noted that in the semiconductor structure 300, the channel doped region 301, drain doped region 302, source doped region 303, insulating isolation layer 304, first metal layer 305, and second metal layer 306 constitute a transistor (MOS transistor). Specifically, the channel doped region 301 forms the channel of the transistor, the drain doped region 302 forms the drain of the transistor, the source doped region 303 forms the source of the transistor, and the first metal layer 305 can form the gate of the transistor. The insulating isolation layer 304 is equivalent to the gate dielectric layer of the transistor, and the second metal layer 306 can also be considered as part of the gate.

[0101] It should also be noted that the transistor can be a junctionless transistor, specifically a JLAMT, meaning that in the semiconductor structure 300, the channel doped region 301, drain doped region 302, and source doped region 303 have the same type of doped ions. For example, the channel doped region 301, drain doped region 302, and source doped region 303 can all be doped with N-type ions, thereby forming an N-type metal-oxide-semiconductor field-effect transistor (NMOS transistor), or the channel doped region 301, drain doped region 302, and source doped region 303 can all be doped with P-type ions, thereby forming a P-type metal-oxide-semiconductor field-effect transistor (PMOS transistor). In this embodiment, N-type ion doping is used as an example for description.

[0102] Furthermore, such as Figure 5 As shown in the embodiments of this disclosure, the channel doped region 301 can be a lightly doped region (N-); the drain doped region 302 and the source doped region 303 can both be heavily doped regions (N+). That is, the channel doped region 301, the drain doped region 302, and the source doped region 303 have the same type of dopant ions, but different concentrations of dopant ions, wherein the dopant ion concentration in the heavily doped region is greater than that in the lightly doped region.

[0103] Thus, in this embodiment of the present disclosure, a second metal layer 306 is formed at the end of the drain (drain doped region 302) of the junctionless transistor near the channel (channel doped region 301). The second metal layer 306 can reduce the concentration gradient of the impurity distribution from the drain to the channel, thereby effectively reducing the electric field strength of the channel, reducing the leakage current generated by the transistor in the off state, effectively suppressing the GIDL effect, and reducing the turn-off current of the transistor. In addition, when the gate is turned on, the gate voltage will increase the carrier quantity, reduce the resistance, and also increase the turn-on current of the transistor.

[0104] In addition, the length of the second metal layer can be one-fifth to one-half the length of the drain doped region or the source doped region. This way, the normal operation of the transistor can be guaranteed without being affected while suppressing the GIDL effect.

[0105] It should also be noted that, Figure 5 The diagram shown is a cross-sectional view of semiconductor structure 300. For the transistors in semiconductor structure 300, see [link to relevant documentation]. Figure 6 This illustrates a three-dimensional structural diagram of a transistor provided in an embodiment of the present disclosure. Figure 6As shown, the gate of the transistor can be a surrounding gate. That is, an insulating isolation layer 304 is formed around the surface of the channel doped region 301 and a portion of the surface of the drain doped region 302, and a first metal layer 305 and a second metal layer 306 are formed around the surface of the insulating isolation layer 304.

[0106] In some embodiments, the work function of the second metal layer 306 is less than or equal to the work function of the first metal layer 305, and the work function of the second metal layer 306 is greater than a preset work function threshold.

[0107] It should be noted that the first metal layer 305 (also called the control gate) is the switch for controlling the channel. The material of the first metal layer 305 can be a metal with a high work function, such as iridium (Ir), nickel (Ni), platinum (Pt), and cobalt (Co). Among them, the work function of iridium is 5.27 eV, that of nickel is 5.15 eV, that of platinum is 5.65 eV, and that of cobalt is 5 eV.

[0108] The second metal layer 306 is used to adjust the impurity distribution near the drain in the channel, reducing the concentration gradient of impurities from the drain to the channel, thereby effectively reducing the channel electric field. The work function of the second metal layer 306 is greater than a preset work function threshold and less than or equal to the work function of the first metal layer 305. The preset work function threshold can be 4.6 eV, ensuring that the second metal layer 306 can effectively reduce the channel electric field.

[0109] The work function (WF) refers to the minimum energy required to move an electron from the interior of a solid to its surface. The work function is approximately half the ionization energy of a free atom in a metal. The magnitude of the work function indicates the strength of electron binding within the metal; a higher work function means a less likely electron is to leave the metal. Since the second metal layer 306 has a relatively large work function (greater than 4.6 eV), it effectively reduces the number of charge carriers in the drain doped region 302 (drain). This forms a gradually varying concentration junction between the channel doped region 301 (channel) and the drain doped region 302 (drain), ultimately reducing the electric field strength. This reduces the leakage current generated by the transistor's drain in the off state, improves the BTBT effect, and suppresses the GIDL effect. Furthermore, when the gate is turned on, the gate voltage increases the number of charge carriers, reduces resistance, and thus increases the transistor's turn-on current.

[0110] Further, see Figure 7 It illustrates a schematic diagram of the composition of a semiconductor structure 300 provided in an embodiment of this disclosure. Figure 2 ,like Figure 7 As shown, in some embodiments, the semiconductor structure 300 may further include a third metal layer 307; wherein,

[0111] A third metal layer 307 is formed on the surface of the first metal layer 305, and the third metal layer 307 is connected to the second metal layer 304.

[0112] It should be noted that, as Figure 7 As shown in this embodiment, the semiconductor structure 300 may further include a third metal layer 307 formed on the surface of the first metal layer 305, and the third metal layer 307 is connected to the second metal layer 306. That is, the third metal layer 307 is also formed on a portion of the surface of the second metal layer 306, and the third metal layer 307 can also be considered as part of the gate. The material of the third metal layer 307 may be the same as the material of the second metal layer 306. In this case, the third metal layer 307 and the second metal layer 306 work together to effectively reduce the leakage current of the transistor, reduce the GIDL effect caused by BTBT, reduce the turn-off current of the transistor, and increase the turn-on current of the transistor.

[0113] Furthermore, the first metal layer 305 and the second metal layer 306 can be made of the same material. See also Figure 8 It illustrates a schematic diagram of the composition of a semiconductor structure 300 provided in an embodiment of this disclosure. Figure 3 ,like Figure 8 As shown, in some embodiments, the drain doped region may include a first sub-doped region 3021 and a second sub-doped region 3022, and the first sub-doped region 3021 is located between the channel doped region 301 and the second sub-doped region 3022; wherein, a second insulating isolation portion is formed on the surface of the first sub-doped region 3021.

[0114] It should be noted that, as Figure 8 As shown, the drain doped region can be specifically divided into a first sub-doped region 3021 and a second sub-doped region 3022. The first sub-doped region 3021 is the portion of the drain doped region covered by the second insulating isolation portion, and the second sub-doped region 3022 is the portion of the drain doped region not covered by the second insulating isolation portion. The channel doped region 301 is a lightly doped region, the first sub-doped region 3021 is a moderately doped region, and the second sub-doped region 3022 and the source doped region 303 are heavily doped regions. The dopant concentration in the moderately doped region is greater than that in the lightly doped region but less than that in the heavily doped region. In other words, this embodiment of the present disclosure can divide the drain doped region into a heavily doped second sub-doped region 3022 and a moderately doped first sub-doped region 3021, and the moderately doped first sub-doped region 3021 is connected to the lightly doped channel doped region 301, thereby making the concentration gradient between the second doped region and the channel doped region more gradual, which is beneficial for reducing the transistor's leakage current and mitigating the GIDL effect.

[0115] Furthermore, Figure 9 This illustration shows a schematic diagram of the composition of a semiconductor structure 300 provided in an embodiment of the present disclosure. Figure 4 , Figure 10 This illustration shows a schematic diagram of the composition of a semiconductor structure 300 provided in an embodiment of the present disclosure. Figure 5 ,like Figure 9 or Figure 10 As shown, in some embodiments, the insulating isolation layer 304 may further include a third insulating isolation portion formed on a portion of the surface of the source doped region; the semiconductor structure 300 may further include a fourth metal layer 308 formed on the surface of the third insulating isolation portion.

[0116] The fourth metal layer 308 can also be considered as part of the gate.

[0117] In some embodiments, the source doped region may include a third sub-doped region 3031 and a fourth sub-doped region 3032, wherein the third sub-doped region 3031 is located between the channel doped region 301 and the fourth sub-doped region 3032, and a third insulating isolation portion is formed on the surface of the third sub-doped region 3031; wherein,

[0118] The channel doped region 301 is a lightly doped region;

[0119] Both the first sub-doped region 3021 and the third sub-doped region 3031 are medium-doped regions;

[0120] Both the second sub-doped region 3022 and the fourth sub-doped region 3032 are heavily doped regions;

[0121] The dopant concentration in the medium-doped region is greater than that in the lightly doped region, and the dopant concentration in the medium-doped region is less than that in the heavily doped region.

[0122] It should be noted that, as Figure 9 or Figure 10 As shown, the insulating isolation layer 304 can also be formed on a portion of the surface of the source doped region, specifically on the portion of the surface of the source doped region near the junction with the channel doped region 301. This portion of the insulating isolation layer 304 formed on the surface of the source doped region is referred to as the third insulating isolation portion. It can be understood that the first insulating isolation portion, the second insulating isolation portion, and the third insulating isolation portion constitute the completed insulating isolation layer 304; the division into three parts is merely for ease of description, and the insulating isolation layer 304 is a complete unit. Furthermore, correspondingly, a third metal layer 308 is formed on the surface of the third insulating isolation portion.

[0123] It should also be noted that, such as Figure 9 or Figure 10As shown, the source doped region can be divided into a third sub-doped region 3031 and a fourth sub-doped region 3032. The third sub-doped region 3031 is located between the channel doped region 301 and the fourth sub-doped region 3032, that is, the third sub-doped region 3031 is connected to the channel doped region 301. The third insulating isolation portion is formed on the surface of the third sub-doped region 3031.

[0124] In this embodiment, the channel doped region 301 can be a lightly doped region, the first sub-doped region 3021 and the third sub-doped region 3031 can both be medium-doped regions, and the second sub-doped region 3022 and the fourth sub-doped region 3032 can both be heavily doped regions. That is to say, in this embodiment, the source doped region can also be divided into a heavily doped fourth sub-doped region 3032 and a medium-doped third sub-doped region 3031, and the medium-doped third sub-doped region 3031 is connected to the lightly doped channel doped region 301.

[0125] It should also be noted that, in the embodiments of this disclosure, the dopant ion concentration in the medium-doped region is greater than that in the lightly doped region, and the dopant ion concentration in the medium-doped region is less than that in the heavily doped region. That is, for the three doping methods—heavily doped, medium-doped, and lightly doped regions—in the embodiments of this disclosure, the dopant ion concentration is ordered from highest to lowest as follows: the heavily doped region has the highest dopant ion concentration, followed by the medium-doped region, and the lightly doped region has the lowest dopant ion concentration. For example, the dopant ion concentration in the heavily doped region can be e. 20 / cm 3 The dopant ion concentration in the medium-doped region can be e 19 / cm 3 The dopant concentration in the heavily doped region can be e 18 / cm 3 .

[0126] This not only causes the concentration gradient between the channel doped region 301 (channel) and the drain doped region (drain) to change slowly, but also causes the concentration gradient between the channel doped region 301 (channel) and the source doped region (source) to change slowly, thereby reducing the leakage current of the transistor.

[0127] It should also be noted that the materials of the first metal layer 305, the second metal layer 306, and the fourth metal layer 308 can be the same (e.g., Figure 9 (as shown), or the materials of the second metal layer 306 and the fourth metal layer 308 may also be different from the material of the first metal layer 305 (e.g. Figure 10(As shown). Since the embodiments of this disclosure have metal layers formed at both the source (source doped region) and the drain (drain doped region), they can weaken both the source and the drain, reduce the number of charge carriers, thereby reducing the electric field strength, improving the BTBT effect, suppressing the GIDL effect, and reducing the leakage current of the transistor in the off state. Weakening the source can also reduce leakage current during the pre-charging process of the transistor, thus providing a more comprehensive leakage protection effect.

[0128] Furthermore, in Figure 10 Based on the semiconductor structure shown, see [link to relevant documentation]. Figure 11 It illustrates a schematic diagram of the composition of a semiconductor structure 300 provided in an embodiment of this disclosure. Figure 6 ,like Figure 11 As shown, in some embodiments, the semiconductor structure 300 may further include a fifth metal layer 309; wherein,

[0129] A fifth metal layer 309 is formed on the surface of the first metal layer 305, and the two ends of the fifth metal layer 309 are respectively connected to the second metal layer 306 and the fourth metal layer 308.

[0130] It should be noted that, as Figure 11 As shown, in Figure 10 Based on the structure shown, the semiconductor structure 300 may further include a fifth metal layer 309. The fifth metal layer 309 is formed on the surface of the first metal layer 305 and is also connected to the second metal layer 306 and the fourth metal layer 308, respectively. That is, the fifth metal layer 309 is also formed on a portion of the surfaces of the second metal layer 306 and the fourth metal layer 308. The fifth metal layer 309 can also be considered as part of the gate.

[0131] It should also be noted that, such as Figure 11 As shown, the material of the fifth metal layer 309 can be the same as that of the second metal layer 306 and the fourth metal layer 308. The second metal layer 306 can weaken the drain doped region (drain), and the fourth metal layer 308 can weaken the source doped region (source). Simultaneously, the weakened portion can serve as a lightly doped drain (LDD) in the semiconductor structure; that is, the first sub-doped region 3021 and the third sub-doped region 3031 can serve as lightly doped drains, thus making the weakening effect on the source / drain adjustable. High doping of the source and drain can reduce resistance, provide carriers for transistor conduction, and reduce the Schottky barrier width. Furthermore, the lightly doped drain can weaken the drain field in the transistor, thereby improving a series of short-channel effects such as hot electron degradation.

[0132] For example, see Figure 12 and Figure 13 , Figure 12This is a schematic diagram comparing the relationship between channel length and electric field strength provided by an embodiment of the present disclosure. Figure 13 This is a schematic diagram comparing bandgap contours provided for embodiments of this disclosure. Figure 12 and Figure 13 In the diagram, JLAMT is a schematic diagram showing the relationship between the electric field strength and the channel length of a conventional accumulation-mode junctionless transistor, represented by a solid line; WF-JLAMT is a schematic diagram showing the relationship between the electric field strength and the channel length of a junctionless transistor including a second metal layer provided in an embodiment of this disclosure, represented by a dashed line. Figure 12 As shown, compared with conventional JLAMT, in the semiconductor structure provided in this embodiment, since a second insulating isolation portion of an insulating isolation layer 304 is formed on a portion of the surface of the drain doped region 302, and a second metal layer 306 is formed on the surface of the second insulating isolation portion, and the second metal layer 306 is made of a material with a work function greater than 4.6 eV and less than or equal to the work function of the first metal layer 305, the electric field strength of the channel of the WF-JLAMT is significantly reduced compared with a conventional JLAMT with only a single metal gate.

[0133] like Figure 13 As shown, compared to conventional JLAMT, in WF-JLAMT, the electric field near the channel portion of the drain is reduced, resulting in decreased band bending. Under the action of the second metal layer 306, as... Figure 13 As shown in the dashed box, the drain band of the WF-JLAMT has an additional step. This step raises the band height at the junction of the drain and the channel, thus increasing the overlap between the conduction band (Ec) of the drain and the valence band (Ev) of the channel (as shown in the image). Figure 13 (As shown in the dashed elliptical box in the image) the BTBT effect is reduced or even eliminated; ultimately, the BTBT effect can be effectively improved, the drain current is reduced, and the turn-off current of the transistor is effectively reduced, thus suppressing the GIDL effect.

[0134] Furthermore, as mentioned above Figure 4 or Figures 7 to 11 As shown in any of the accompanying drawings, in some embodiments, the semiconductor structure 300 may further include bit lines 310 and capacitors 311; wherein,

[0135] Bit line 310 is connected to the side of source doped region 303 away from channel doped region 301;

[0136] The capacitor 311 is connected to the side of the drain doped region 302 that is away from the channel doped region 301.

[0137] It should be noted that, with Figure 5 For example, Figure 5As shown, bit line 310 (BL in the figure) is connected to the source doped region 303, and capacitor 311 (CAP in the figure) is connected to the drain doped region 302. Thus, the transistor, bit line 310, and capacitor 311 enable operations such as data storage and retrieval.

[0138] Furthermore, in some embodiments, the semiconductor structure may further include a metal isolation layer, a first control lead, and a second control lead; wherein,

[0139] A metal insulating layer is formed between the first metal layer and the second metal layer to provide insulation between the first metal layer and the second metal layer;

[0140] One end of the first control lead is connected to the first metal layer, and the other end of the first control lead is connected to the first control terminal;

[0141] One end of the second control lead is connected to the second metal layer, and the other end of the second control lead is connected to the second control terminal.

[0142] It should be noted that, in this embodiment, the first metal layer and the second metal layer can be controlled separately via a first control lead and a second control lead. In this case, a metal insulating layer can be added between the first metal layer and the second metal layer to insulate them. For example, see... Figure 14 This diagram illustrates a control lead connection diagram for individually controlled metal layers according to an embodiment of this disclosure. In diagram (a), a three-dimensional structural diagram of semiconductor structure 300 is shown; in diagrams (b) and (c), bit lines 310, capacitors 311, and other structures are not shown. Figure 14 The meanings of the serial numbers in the figure are the same as those in the aforementioned figure.

[0143] like Figure 14 As shown in the figures, one end of the first control lead 313a is connected to the first metal layer 305, and the other end is connected to the first control terminal (not shown in the figure). One end of the second control lead 313b is connected to the second metal layer 306, and the other end is connected to the second control terminal (not shown in the figure). A metal insulating layer 312 is provided between the first metal layer 305 and the second metal layer 306 to insulate them. The first control lead 313a and the second control lead 313b can be configured as follows: Figure 14 As shown in (a) above, located on different sides of the transistor, it can also be as follows: Figure 14 As shown in (b) above, they are located on the same side of the transistor. Additionally, as... Figure 14 As shown in (c), the semiconductor structure may further include a third control lead 313c, one end of which is connected to the fourth metal layer 308, and the other end is connected to a third control terminal (not shown in the figure). A metal isolation layer 312 is also present between the fourth metal layer 308 and the first metal layer 305 for insulation. Figure 14 In (c), the three control leads are distributed on different sides of the transistor. Alternatively, the three control leads can also be located on the same side of the transistor.

[0144] It should also be noted that the first control terminal, the second control terminal, and the third control terminal can be the same control terminal or different control terminals, and can be external power supplies, word lines, other devices in semiconductor memory, etc.

[0145] Furthermore, the first metal layer and the second metal layer can also be controlled via the same control lead, in which case insulation between the first metal layer and the second metal layer is not required. In some embodiments, the semiconductor structure may further include a control lead; wherein,

[0146] The first metal layer and the second metal layer are connected;

[0147] One end of the control lead is connected to the first metal layer and / or the second metal layer, and the other end of the control lead is connected to the control terminal.

[0148] It should be noted that, Figure 15 This is a schematic diagram of a control lead connection for joint control of metal layers provided in an embodiment of the present disclosure. Figure 15 The bit line 310, capacitor 311, and other structures are not shown in the diagram. Figure 15 As shown in (a), one end of the control lead 313 is connected to the first metal layer 305, and the other end is connected to the control terminal, or, as shown in (a), Figure 15 As shown in (b), one end of the control lead 313 is connected to the second metal layer 306, and the other end is connected to the control terminal. Alternatively, the control lead 313 can also be connected to both the first metal layer 305 and the second metal layer 306 simultaneously for controlling both layers. Furthermore, in... Figure 15 As shown in (c), the control lead 313 can be connected to the first metal layer 305, or to the second metal layer 306 or the fourth metal layer 308. The control terminal can be an external power supply, a word line, other devices in the semiconductor memory, etc.

[0149] In other words, in the embodiments of this disclosure, the first metal layer and the second metal layer can be controlled separately or jointly, for example, controlled separately or jointly from the same side of the transistor, or controlled separately from opposite directions on both sides of the transistor. Thus, the embodiments of this disclosure can achieve flexible control of the first metal layer, the second metal layer, and the fourth metal layer in various ways.

[0150] In short, the embodiments of this disclosure utilize metal materials with different work functions as gates to control the doping distribution of the channel, thereby reducing the channel electric field, decreasing the turn-off current, and suppressing the GIDL effect generated by BTBT. By employing a method of weakening part of the drain with a metal of varying work function, the portion of the drain near the channel can be weakened without changing the doping, thus reducing the turn-off current, suppressing the GIDL effect, and simultaneously enhancing the turn-on current.

[0151] This disclosure provides a semiconductor structure including: a channel doped region; a drain doped region and a source doped region formed on both sides of the channel doped region; an insulating isolation layer including a first insulating isolation portion and a second insulating isolation portion, the first insulating isolation portion being formed on the surface of the channel doped region and the second insulating isolation portion being formed on a portion of the surface of the drain doped region; a first metal layer being formed on the surface of the first insulating isolation portion; and a second metal layer being formed on the surface of the second insulating isolation portion. The channel doped region, drain doped region, source doped region, insulating isolation layer, first metal layer, and second metal layer can constitute a transistor. Thus, in the semiconductor structure, the second metal layer formed near the drain doped region can reduce the impurity concentration gradient from the drain doped region to the channel doped region, reduce the number of charge carriers near the drain doped region, thereby effectively reducing the electric field strength of the channel doped region. When the transistor is off, this reduces the transistor's leakage current, thereby reducing the transistor's turn-off current and suppressing the GIDL effect caused by BTBT. Furthermore, when the transistor is on, the gate voltage increases the number of charge carriers, reduces the resistance, and can also increase the transistor's turn-on current.

[0152] In another embodiment of this disclosure, see Figure 16 This illustration shows a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 16 As shown, the method may include:

[0153] S1001, Provide substrate.

[0154] S1002. The substrate is doped to form a channel doped region, a drain doped region, and a source doped region in the substrate, with the drain doped region and the source doped region formed on both sides of the channel doped region.

[0155] It should be noted that, firstly, a substrate is provided, and multiple active regions are formed within the substrate. For 3D semiconductor structures, these active regions can be arranged in a spatial array. Then, the active regions are doped to form multiple doped regions. Specifically, Figure 17 This is a schematic diagram of the structure obtained after forming the channel doped region 301, the drain doped region 302, and the source doped region 303. Figure 17 Only the active region is shown in the image.

[0156] like Figure 17 As shown, the drain doped region 302 and the source doped region 303 are located on both sides of the channel doped region 301. Furthermore, these three doped regions can be the three doped regions of a junctionless transistor. Therefore, in some embodiments, the doped ion types of the channel doped region 301, drain doped region 302, and source doped region 303 are the same; for example, the doped ion types of the three doped regions can all be either N-type or P-type ion doped.

[0157] In some embodiments, such as Figure 17 As shown, the channel doped region 301 can be a lightly doped region (N-), and the drain doped region 302 and the source doped region 303 can be heavily doped regions (N+). Alternatively, the drain doped region 302 and the source doped region 303 can also be as described above. Figures 7 to 11 As shown, the drain doped region 302 includes a first sub-doped region 3021 and a second sub-doped region 3022, and / or the source doped region 303 includes a third sub-doped region 3031 and a fourth sub-doped region 3032. In this case, only the doping concentration needs to be changed.

[0158] S1003, forming an insulating layer.

[0159] The insulating isolation layer includes a first insulating isolation portion and a second insulating isolation portion. The first insulating isolation portion is formed on the surface of the channel doped region, and the second insulating isolation portion is formed on a portion of the surface of the drain doped region.

[0160] It should be noted that, Figure 18 This is a schematic diagram of the structure obtained after forming the 304 insulating layer. Figure 18 As shown, an insulating isolation layer 304 is formed on the surface of the channel doped region 301 and a portion of the surface of the drain doped region 302. The insulating isolation layer 304 formed on the surface of the channel doped region 301 is referred to as the first insulating isolation portion, and the insulating isolation layer 304 formed on a portion of the surface of the drain doped region 302 is referred to as the second insulating isolation portion. The length of the second insulating isolation portion can be one-fifth to one-half of the length of the drain doped region 302 or the source doped region 303.

[0161] S1004. A first metal layer is formed on the surface of the first insulating and isolating portion.

[0162] S1005. A second metal layer is formed on the surface of the second insulating isolation portion.

[0163] A first metal layer and a second metal layer are formed on the surfaces of the first insulating isolation portion and the second insulating isolation portion, respectively, thereby obtaining a junctionless transistor.

[0164] In some embodiments, forming a first metal layer on the surface of the first insulating portion may include:

[0165] A mask layer is formed on the surface of the second insulating isolation portion;

[0166] Using a mask layer as a mask, a first metal layer is formed on the surface of the first insulating and isolating portion;

[0167] Remove the mask layer.

[0168] It should be noted that, Figure 19 This is a schematic diagram of the structure obtained after forming the mask layer 316. Figure 19 As shown, when forming the first metal layer, a mask layer 316 is first formed on the surface of the second insulating isolation portion. The material of the mask layer 316 can be photoresist or the like.

[0169] Then, using the mask layer 316 as a mask, a first metal layer 305 is formed on the surface of the first insulating isolation portion. Figure 20 This is a schematic diagram of the structure obtained after the formation of the first metal layer 305.

[0170] After removing the mask layer 316, the result is as follows: Figure 21 The structure shown. (As illustrated) Figure 21 As shown, a first metal layer 305 is formed on the surface of the first insulating portion, and the second insulating portion is exposed. A second metal layer 306 is formed on the surface of the second insulating portion, resulting in... Figure 22 The structure shown.

[0171] In some embodiments, the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold.

[0172] It should be noted that the second metal layer 306 is used to adjust the impurity distribution near the drain in the channel, reducing the impurity concentration gradient from the drain to the channel, which can effectively reduce the channel electric field. The work function of the second metal layer 306 is greater than a preset work function threshold and less than or equal to the work function of the first metal layer 305. The preset work function threshold can be 4.6 eV to ensure that the second metal layer 306 can effectively reduce the channel electric field.

[0173] In some embodiments, when forming a second metal layer on the surface of the second insulating isolation portion, the method may further include:

[0174] A third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer. The material of the third metal layer is the same as that of the second metal layer.

[0175] It should be noted that, Figure 23This is a schematic diagram of the structure obtained after forming the third metal layer 307. At this point, it is possible to form the structure as described above. Figure 7 In the semiconductor structure shown, the second metal layer 305 and the third metal layer 307 can work together to reduce the GIDL effect.

[0176] Furthermore, in some embodiments, the method may further include:

[0177] A bit line and a capacitor are formed; wherein the bit line is connected to the side of the drain doped region away from the channel doped region; and the capacitor is connected to the side of the source doped region away from the channel doped region.

[0178] It should be noted that the structure obtained after forming the capacitors and bit lines can be referred to the above. Figure 5 or Figure 7 As shown. Furthermore, the embodiments disclosed herein are only for the purpose of forming... Figure 5 or Figure 7 The semiconductor structure shown is used as an example to illustrate the fabrication method of the semiconductor structure. Based on a similar method, the aforementioned semiconductor structure can also be formed. Figures 8 to 11 The semiconductor structures shown in any of these examples will not be described in detail here.

[0179] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0180] This disclosure provides a method for fabricating a semiconductor structure. In the semiconductor structure fabricated by this method, a second metal layer is formed near the drain doped region. The second metal layer can reduce the concentration gradient of impurities from the drain doped region to the channel doped region, reduce the number of charge carriers near the drain doped region, thereby effectively reducing the electric field strength of the channel doped region and suppressing the gate-induced drain leakage current caused by the band-to-band tunneling effect.

[0181] In another embodiment of this disclosure, see [reference needed]. Figure 24 This illustrates a schematic diagram of the structural composition of a semiconductor memory 400 provided in an embodiment of this disclosure. For example... Figure 24 As shown, the semiconductor memory 400 includes the semiconductor structure 300 described in any of the foregoing embodiments.

[0182] The semiconductor memory 400 may include 3D DRAM.

[0183] Since the semiconductor memory 400 includes the semiconductor structure 300 described in the foregoing embodiments, it is able to effectively suppress gate-induced drain leakage current caused by the band-to-band tunneling effect.

[0184] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0185] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0186] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0187] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0188] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0189] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0190] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Channel doped region; The drain doped region and the source doped region are formed on both sides of the channel doped region, and the dopant ion types of the channel doped region, the drain doped region and the source doped region are the same; An insulating isolation layer includes a first insulating isolation portion and a second insulating isolation portion, wherein the first insulating isolation portion is formed on the surface of the channel doped region and the second insulating isolation portion is formed on a portion of the surface of the drain doped region; A first metal layer is formed on the surface of the first insulating portion; A second metal layer is formed on the surface of the second insulating portion; Wherein, the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold, wherein the preset work function threshold is 4.6 electron volts.

2. The semiconductor structure according to claim 1, characterized in that, The material of the first metal layer includes at least one of the following: iridium, nickel, platinum, and cobalt.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a third metal layer, the material of which is the same as that of the second metal layer; wherein... The third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The channel doped region is a lightly doped region; Both the drain doped region and the source doped region are heavily doped regions; The dopant concentration in the heavily doped region is greater than that in the lightly doped region.

5. The semiconductor structure according to claim 1, characterized in that, The drain doped region includes a first sub-doped region and a second sub-doped region, and the first sub-doped region is located between the channel doped region and the second sub-doped region; wherein, the second insulating isolation portion is formed on the surface of the first sub-doped region.

6. The semiconductor structure according to claim 5, characterized in that, The insulating isolation layer further includes a third insulating isolation portion, which is formed on a portion of the surface of the source doped region; The semiconductor structure further includes a fourth metal layer formed on the surface of the third insulating portion.

7. The semiconductor structure according to claim 6, characterized in that, The source doped region includes a third sub-doped region and a fourth sub-doped region, and the third sub-doped region is located between the channel doped region and the fourth sub-doped region. The third insulating isolation portion is formed on the surface of the third sub-doped region; wherein, The channel doped region is a lightly doped region; Both the first sub-doped region and the third sub-doped region are medium-doped regions; Both the second sub-doped region and the fourth sub-doped region are heavily doped regions; The dopant concentration in the medium-doped region is greater than that in the lightly doped region, and the dopant concentration in the medium-doped region is less than that in the heavily doped region.

8. The semiconductor structure according to claim 6 or 7, characterized in that, The semiconductor structure further includes a fifth metal layer; wherein... The fifth metal layer is formed on the surface of the first metal layer, and both ends of the fifth metal layer are respectively connected to the second metal layer and the fourth metal layer.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes bit lines and capacitors; wherein... The bit line is connected to the side of the source doped region away from the channel doped region; The capacitor is connected to the side of the drain doped region that is away from the channel doped region.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes control leads; wherein... The first metal layer and the second metal layer are connected; One end of the control lead is connected to the first metal layer and / or the second metal layer, and the other end of the control lead is connected to the control terminal.

11. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a metal isolation layer, a first control lead, and a second control lead; wherein... The metal insulating layer is formed between the first metal layer and the second metal layer to provide insulation between the first metal layer and the second metal layer. One end of the first control lead is connected to the first metal layer, and the other end of the first control lead is connected to the first control terminal; One end of the second control lead is connected to the second metal layer, and the other end of the second control lead is connected to the second control terminal.

12. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; The substrate is doped to form a channel doped region, a drain doped region, and a source doped region in the substrate, wherein the drain doped region and the source doped region are formed on both sides of the channel doped region, and the dopant ion types of the channel doped region, the drain doped region, and the source doped region are the same. An insulating isolation layer is formed, the insulating isolation layer including a first insulating isolation portion and a second insulating isolation portion, the first insulating isolation portion being formed on the surface of the channel doped region, and the second insulating isolation portion being formed on a portion of the surface of the drain doped region; A first metal layer is formed on the surface of the first insulating portion; A second metal layer is formed on the surface of the second insulating portion; Wherein, the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold, wherein the preset work function threshold is 4.6 electron volts.

13. The method according to claim 12, characterized in that, The formation of a first metal layer on the surface of the first insulating portion includes: A mask layer is formed on the surface of the second insulating isolation portion; Using the mask layer as a mask, a first metal layer is formed on the surface of the first insulating and isolating portion; Remove the mask layer.

14. The method according to claim 12, characterized in that, When forming a second metal layer on the surface of the second insulating portion, the method further includes: A third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer; wherein the material of the third metal layer is the same as the material of the second metal layer.

15. The method according to claim 12, characterized in that, The method further includes: A bit line and a capacitor are formed; wherein the bit line is connected to the side of the drain doped region away from the channel doped region; and the capacitor is connected to the side of the source doped region away from the channel doped region.

16. A semiconductor memory, characterized in that, The semiconductor memory includes the semiconductor structure as described in any one of claims 1 to 11.

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