Ferroelectric multi-gate silicon-based impurity atom transistors and their fabrication methods

Abstract

This disclosure provides an impurity atom transistor based on a ferroelectric multi-gate silicon substrate and its fabrication method. The impurity atom transistor includes: a silicon substrate; an oxide insulating layer disposed on the silicon substrate; a source region silicon conductivity mesa, a drain region silicon conductivity mesa, and a silicon nanowire channel, respectively disposed on the upper surface of the oxide insulating layer, with the two ends of the silicon nanowire channel connected to the source region silicon conductivity mesa and the drain region silicon conductivity mesa, respectively; a first gate dielectric layer covering the silicon nanowire channel; a ferroelectric gate dielectric layer covering the first gate dielectric layer; multiple barrier gates covering the ferroelectric gate dielectric layer for modulating the height of the barrier regions located below the multiple barrier gates; a second gate dielectric layer covering the ferroelectric gate dielectric layer and the multiple barrier gates; a multi-finger control gate covering the second gate dielectric layer for modulating the position, number, and energy level of impurity atoms in the silicon nanowire channel located in the lower region; and a source electrode, a drain electrode, multiple barrier gate electrodes, and a control gate electrode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a ferroelectric multi-gate silicon-based impurity atom transistor and its fabrication method. Background Technology

[0002] The basic principle of impurity atom transistors is that ionized impurity atoms can induce the formation of quantum dots in the channel. Charge carriers at the source end are transported to the drain end through quantum dot coupling, exhibiting the characteristics of single-electron transport. However, the distribution of impurity atoms in the nanoscale channel has a large degree of randomness, which leads to significant fluctuations in the quantum electrical properties of impurity atom transistors, which is detrimental to the construction of quantum computer systems.

[0003] Currently, for example, single-ion implantation techniques based on focused ion beams are used to implant individual impurity atoms into predetermined positions in the channel to obtain a minority of impurity atom arrays, thereby obtaining silicon-based transistors with single-electron transport characteristics. For instance, single-atom transistors have been fabricated using scanning tunneling microscopy and hydrogen resist lithography, and the quantum transport of electrons through single phosphorus impurity atoms has been observed at liquid helium temperatures. However, impurity atom transistors fabricated using these two semiconductor technologies have low precision in controlling the positions of impurity atoms (~100 nm), and their fabrication efficiency is low and the cost is too high, which is not conducive to large-scale device fabrication. Furthermore, the coupling barrier between impurity atom quantum dots in the channel of currently proposed impurity atom transistors is difficult to adjust, which is detrimental to modulating the single-electron electrical characteristics of the device. Therefore, existing impurity atom transistor technologies cannot meet all the requirements for being a fundamental building block of quantum computers. Summary of the Invention

[0004] In view of the above problems, this disclosure provides an impurity atom transistor based on ferroelectric multi-gate silicon and a method for its fabrication.

[0005] According to a first aspect of this disclosure, a ferroelectric multi-gate silicon-based impurity atom transistor is provided, comprising:

[0006] silicon substrate;

[0007] An oxide insulating layer is disposed on a silicon substrate;

[0008] The source region silicon conductivity mesa and the drain region silicon conductivity mesa are respectively disposed on opposite sides of the upper surface of the oxide insulating layer;

[0009] The silicon nanowire channel is disposed on the upper surface of the oxide insulating layer, and its two ends are connected to the silicon conductivity mesa of the source region and the silicon conductivity mesa of the drain region, respectively.

[0010] The first gate dielectric layer covers the silicon nanowire channel;

[0011] A ferroelectric gate dielectric layer covers the first gate dielectric layer;

[0012] Multiple barrier gates, covering the ferroelectric gate dielectric layer, are used to modulate the height of the barrier region located below the multiple barrier gates;

[0013] The second gate dielectric layer covers the ferroelectric gate dielectric layer and multiple barrier gates;

[0014] A multi-finger control gate, covering the second gate dielectric layer, is used to modulate the position, number, and energy level of impurity atoms in the silicon nanowire channel located below the multi-finger control gate; and

[0015] The source electrode is disposed on the silicon conductivity mesa of the source region, the drain electrode is disposed on the silicon conductivity mesa of the drain region, the multiple barrier gate electrodes are disposed on multiple barrier gates, and the control gate electrode is disposed on multiple finger control gates.

[0016] According to embodiments of the present disclosure, a plurality of barrier gates are distributed parallel to each other and perpendicular to the arrangement direction of the silicon nanowire channel, with both ends of the plurality of barrier gates extending onto the oxide insulating layer.

[0017] According to embodiments of the present disclosure, a plurality of gate bars and a plurality of barrier gates of a multi-finger control gate are arranged alternately in parallel along the silicon nanowire channel direction, the connection end of the multi-finger control gate extends to the oxide insulating layer, and the control gate electrode is disposed on the connection end of the multi-finger control gate.

[0018] According to embodiments of this disclosure, the materials of the plurality of barrier gates include at least one of the following: polycrystalline silicon, polycrystalline germanium, metal, metal compound; and

[0019] The material of the multi-finger control gate includes at least one of the following: polycrystalline silicon, polycrystalline germanium, metal, and metal compound.

[0020] According to embodiments of this disclosure, a plurality of barrier gates form a discrete parallel structure, the distance between the plurality of barrier gates ranges from 20 nm to 200 nm, the width of each barrier gate ranges from 10 nm to 100 nm, and the thickness ranges from 10 nm to 200 nm.

[0021] According to embodiments of this disclosure, a plurality of gate strips of a multi-finger control gate form a multi-finger structure, the distance between the plurality of gate strips of the multi-finger control gate ranges from 20 nm to 200 nm, the width of each of the plurality of gate strips ranges from 10 nm to 100 nm, and the thickness ranges from 10 nm to 200 nm.

[0022] According to embodiments of the present disclosure, the materials of the first gate dielectric layer and the second gate dielectric layer include at least one of the following: SiO2, oxynitride, TiO2, Si3N4, Ta2O5, HfO2, ZrO2, Al2O3, and the thickness of the first gate dielectric layer and the second gate dielectric layer ranges from 1 nm to 20 nm.

[0023] According to embodiments of this disclosure, the material of the ferroelectric gate dielectric layer includes at least one of the following: (Ba, Sr, Pb)TiO3, Pb(Zr)TiO3, etc. x Ti 1-x O3、[Pb(Mg) 1 / 3 Nb 2 / 3 )O3] 1-x [PbTiO3] x Hf x (Zr, Al, Y, Gd, La, Sr) 1-x O2, the thickness of the ferroelectric gate dielectric layer ranges from 1 nm to 20 nm, where 0 < x < 1.

[0024] According to embodiments of this disclosure, the source region silicon conductivity mesa, the drain region silicon conductivity mesa, and the silicon nanowire channel are doped with n-type or p-type doping, and the doping concentration ranges from 1 × 10⁻⁶. 15 cm -3 Up to 1×10 20 cm -3 .

[0025] A second aspect of this disclosure provides a method for fabricating a ferroelectric multi-gate silicon-based impurity atom transistor, comprising:

[0026] An oxide insulating layer is fabricated on a silicon substrate;

[0027] Source region silicon conductivity mesa, drain region silicon conductivity mesa, and silicon nanowire channel are fabricated on oxide insulating layer. The source region silicon conductivity mesa and drain region silicon conductivity mesa are respectively disposed on opposite sides of the upper surface of oxide insulating layer. The two ends of silicon nanowire channel are respectively connected to the source region silicon conductivity mesa and drain region silicon conductivity mesa.

[0028] A first gate dielectric layer is fabricated on a silicon nanowire channel;

[0029] A ferroelectric gate dielectric layer is fabricated on the first gate dielectric layer;

[0030] Multiple barrier gates are fabricated on a ferroelectric gate dielectric layer;

[0031] A second gate dielectric layer is fabricated on a ferroelectric gate dielectric layer and multiple barrier gates;

[0032] Fabricating a multi-finger control gate on the second gate dielectric layer; and

[0033] A source electrode is fabricated on a silicon conductivity mesa in the source region, a drain electrode is fabricated on a silicon conductivity mesa in the drain region, multiple barrier gate electrodes are fabricated on multiple barrier gates, and a control gate electrode is fabricated on a multi-finger control gate.

[0034] This disclosure provides an impurity atom transistor based on a ferroelectric multi-gate silicon substrate. The impurity atom transistor with a ferroelectric dielectric layer is fabricated on an SOI substrate using CMOS technology. By introducing a ferroelectric gate dielectric layer, multiple barrier gates, and a multi-finger control gate, the impurity atom transistor provided by this disclosure can not only define the position and number of impurity atoms involved in transport in the channel through the multi-finger control gate, but also adjust the coupling barrier height between impurity atoms through the barrier gate to modulate the quantum transport mechanism of charge carriers, thereby achieving effective control of the single-electron electrical characteristics of the impurity atom transistor. Attached Figure Description

[0035] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0036] Figure 1 A schematic diagram of a three-dimensional structure of a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure is shown.

[0037] Figure 2 A schematic top view of a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure is shown.

[0038] Figure 3 This schematically illustrates a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure. Figure 2 A longitudinal cross-section cut along line AB in the diagram;

[0039] Figure 4 This schematically illustrates the valence band profile and carrier transport mechanism in the channel direction of a silicon nanowire according to an embodiment of the present disclosure.

[0040] Figure 5 This schematically illustrates a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure. Figure 4 The transfer characteristic curves are shown for the band structure case.

[0041] Figure 6 A schematic diagram illustrating the valence band profile and carrier transport mechanism in the channel direction of a silicon nanowire according to another embodiment of the present disclosure is shown.

[0042] Figure 7 This schematically illustrates a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure. Figure 6 The transfer characteristic curves for the band structure shown are as follows; and

[0043] Figure 8 A flowchart illustrating a method for fabricating a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure is shown.

[0044] Explanation of reference numerals in the attached figures

[0045] 100 Dosage Atom Transistors Based on Ferroelectric Multi-Gate Silicon

[0046] 10 Silicon substrate

[0047] 11 Oxide Insulation Layer

[0048] 12 Source Region Silicon Conductivity Mesa

[0049] 121 Source Electrode

[0050] 13 Drain region silicon conductivity mesa

[0051] 131 Drain electrode

[0052] 14 Silicon nanowire channels

[0053] 15 First gate dielectric layer

[0054] 16 Ferroelectric grid dielectric layer

[0055] More than 17 potential barriers

[0056] 171 Barrier Gate Electrode

[0057] 18 Second gate dielectric layer

[0058] 19 Multi-finger control gate

[0059] 191 Control gate electrode Detailed Implementation

[0060] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0062] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0063] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0064] Figure 1 A schematic diagram of a three-dimensional structure of a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure is shown. Figure 2 A top view of a ferroelectric multi-gate silicon-based impurity atom transistor is schematically shown according to an embodiment of the present disclosure. Figure 3 This schematically illustrates a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure. Figure 2 The longitudinal cross-section diagram cut along line AB.

[0065] like Figure 1 As shown, the ferroelectric multi-gate silicon-based impurity atom transistor 100 includes: a silicon substrate 10, an oxide insulating layer 11, a source region silicon conductivity mesa 12, a drain region silicon conductivity mesa 13, a silicon nanowire channel 14, a first gate dielectric layer 15, a ferroelectric gate dielectric layer 16, multiple barrier gates 17, a second gate dielectric layer 18, a multi-finger control gate 19, a source electrode 121, a drain electrode 131, multiple barrier gate electrodes 171, and a control gate electrode 191.

[0066] An oxide insulating layer 11 is disposed on the upper surface of a silicon substrate 10, and a source region silicon conductivity mesa 12, a drain region silicon conductivity mesa 13, and a silicon nanowire channel 14 are respectively disposed on the upper surface of the oxide insulating layer 11.

[0067] For example, the silicon substrate 10 can be a back substrate located at the bottom of the SOI substrate, and the oxide insulating layer 11 can be an oxide layer located between the top silicon layer of the SOI substrate and the back substrate. The source region silicon conductivity mesa 12, the drain region silicon conductivity mesa 13, and the silicon nanowire channel 14 can be formed by etching the top silicon layer of the SOI substrate.

[0068] The source region silicon conductivity mesa 12 and the drain region silicon conductivity mesa 13 are located on opposite sides of the upper surface of the oxide insulating layer 11. For example, the source region silicon conductivity mesa 12 and the drain region silicon conductivity mesa 13 can be located at both ends of the upper surface of the oxide insulating layer 11, and the source region silicon conductivity mesa 12 and the drain region silicon conductivity mesa 13 can also be symmetrically distributed about the center of the oxide insulating layer 11.

[0069] A source electrode 121 is also provided on the silicon conductivity mesa 12 of the source region, and a drain electrode 131 is also provided on the silicon conductivity mesa 13 of the drain region. The thickness of the source electrode 121 and the drain electrode 131 can range from 20 nm to 500 nm.

[0070] The two ends of the silicon nanowire channel 14 are connected to the silicon conductivity mesa 12 in the source region and the silicon conductivity mesa 13 in the drain region, respectively. The diameter of the silicon nanowire channel 14 can range from 2 nm to 50 nm.

[0071] The silicon nanowire channel 14 is used to transport charge carriers in the transistor from the source terminal to the drain terminal. For example, the silicon nanowire channel 14 transports charge carriers from the source electrode 121 to the drain electrode 131.

[0072] The silicon conductivity mesa 12 in the source region, the silicon conductivity mesa 13 in the drain region, and the silicon nanowire channel 14 can be doped with either n-type or p-type doping concentrations ranging from 1 × 10⁻⁶. 15 cm -3 Up to 1×10 20 cm -3 .

[0073] When the nanowire channel 14 is n-type doped, the majority carriers involved in transport in the transistor are electrons. When the nanowire channel 14 is p-type doped, the majority carriers involved in transport in the transistor are holes.

[0074] like Figure 2 and Figure 3 As shown, a first gate dielectric layer 15 covers the silicon nanowire channel 14, a ferroelectric gate dielectric layer 16 covers the first gate dielectric layer 15, a plurality of barrier gates 17 cover the ferroelectric gate dielectric layer 16, a second gate dielectric layer 18 covers the ferroelectric gate dielectric layer 16 and the plurality of barrier gates 17, and a multi-finger control gate 19 covers the second gate dielectric layer 18.

[0075] For example, the materials of the first gate dielectric layer 15 and the second gate dielectric layer 18 may include at least one of the following: SiO2, oxynitride, TiO2, Si3N4, Ta2O5, HfO2, ZrO2, and Al2O3. The thickness of the first gate dielectric layer 15 and the second gate dielectric layer 18 may range from 1 nm to 20 nm.

[0076] For example, the material of the ferroelectric gate dielectric layer 16 may include at least one of the following: (Ba, Sr, Pb)TiO3, Pb(Zr)TiO3, etc. x Ti 1-x O3、[Pb(Mg) 1 / 3 Nb 2 / 3 )O3] 1-x [PbTiO3] x Hf x (Zr, Al, Y, Gd, La, Sr) 1-x O2, the thickness of the ferroelectric gate dielectric layer can range from 1 nm to 20 nm, where 0 < x < 1.

[0077] For example, the material of the plurality of barrier gates 17 may include at least one of the following: polysilicon, polysilicon, polygermanium, metal, or metal compound. The material of the plurality of control gates 19 may include at least one of the following: polysilicon, polysilicon, polygermanium, metal, or metal compound.

[0078] like Figure 3 As shown, multiple barrier gates 17 are distributed parallel to each other and perpendicular to the orientation of the silicon nanowire channel 14, with both ends of the multiple barrier gates 17 extending onto the oxide insulating layer 11. For example, the multiple barrier gates 17 form a discrete parallel structure, with the distance between the multiple barrier gates 17 ranging from 20 nm to 200 nm, the width of each barrier gate 17 ranging from 10 nm to 100 nm, and the thickness ranging from 10 nm to 200 nm.

[0079] Multiple barrier gate electrodes 171 are respectively disposed at one end of multiple barrier gates 17, and the width of the end of the barrier gate 17 with barrier gate electrodes 171 is greater than the width of the end without barrier gate electrodes 171. For example, the thickness of the barrier gate electrodes 171 can range from 20 nm to 500 nm.

[0080] Multiple gate bars of the multi-finger control gate 19 and multiple barrier gates 17 are arranged alternately and parallelly along the direction of the silicon nanowire channel 14. The connection ends of the multi-finger control gate 19 extend to the oxide insulating layer 11, and the control gate electrode 191 is disposed on the connection ends of the multi-finger control gate 19. For example, the multiple gate bars of the multi-finger control gate 19 form a multi-finger structure, the distance between the multiple gate bars of the multi-finger control gate 19 ranges from 20 nm to 200 nm, the width of each gate bar ranges from 10 nm to 100 nm, and the thickness ranges from 10 nm to 200 nm. The thickness of the multi-finger control gate electrode 191 can range from 20 nm to 500 nm.

[0081] By applying a pulse voltage to the ferroelectric gate dielectric layer 16, the polarization intensity and direction in the ferroelectric gate dielectric layer 16 can be adjusted. By applying a pulse voltage to multiple barrier gates 17, the coupling barrier height between impurity atoms participating in transport in the silicon nanowire channel 14 located below the multiple barrier gates 17 can be adjusted, thereby modulating the quantum transport mechanism of charge carriers and realizing the effective control of the single-electron electrical characteristics of the impurity atom transistor.

[0082] The multi-finger control gate 19 can modulate the position and number of transport impurity atoms in the silicon nanowire channel 14 located in the region below the multi-finger control gate 19, and can modulate the energy level of the transport impurity atoms, thereby realizing the ordered control of the impurity atom array in the device.

[0083] Figure 4 The schematic diagram illustrates the valence band profile and carrier transport mechanism in the channel direction of a silicon nanowire according to an embodiment of the present disclosure. Figure 5 This schematically illustrates a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure. Figure 4 The figure shows the transfer characteristic curves under the band structure condition.

[0084] Figure 4 The nanowire channel 14 of the ferroelectric multi-gate silicon-based impurity atom transistor shown is n-type doped, and the majority carriers involved in transport in the transistor are electrons. A forward scanning voltage V is applied to the control gate electrode 191. CG A reverse pulse voltage is applied to multiple barrier gate electrodes 171, and a positive bias voltage V is applied between the drain electrode 131 and the source electrode 121. DS .

[0085] like Figure 4 As shown, the shaded area represents the Fermi Sea, the dashed line below the source region represents the Fermi level of the source region, the dashed line below the drain region represents the Fermi level of the drain region, the solid curve represents the conduction band, the short horizontal line below the control gate represents the impurity atom energy level, and the dashed arrow represents the electron transport process. Figure 4 The horizontal axis represents the distribution area of ​​the source region silicon conductivity mesa 12, the drain region silicon conductivity mesa 13, multiple barrier gates 17, and multiple finger control gates 19 along the direction of the silicon nanowire channel 14. Figure 4 The vertical axis represents the electron potential energy.

[0086] Impurity atoms in the silicon nanowire channels 14, located beneath multiple control gates formed by the multiple gate bars of the multi-finger control gate 19, are bound. These bound impurity atoms act as quantum dots, providing transport energy levels for electrons. The surface potential of the silicon nanowire channels 14, located beneath multiple barrier gates 17, is relatively high, resulting in high barriers between impurity atoms and weak coupling between them. Therefore, electrons are primarily transported through the impurity atoms via tunneling.

[0087] like Figure 5 As shown in the transfer characteristic curve (current I at the drain electrode), D -Scanning voltage V CG The isolated current oscillation peaks observed in the silicon nanowire channel 14 indicate that the coupling energy between the bound impurity atoms is relatively large and the coupling effect between the impurity atoms is relatively weak.

[0088] Figure 6 The diagram illustrates the valence band profile and carrier transport mechanism in the channel direction of a silicon nanowire according to another embodiment of the present disclosure. Figure 7 This schematically illustrates a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure. Figure 6 The figure shows the transfer characteristic curves under the band structure condition.

[0089] Figure 6 The nanowire channel 14 of the ferroelectric multi-gate silicon-based dopant transistor shown is n-type doped, and the majority carriers involved in transport in the transistor are electrons. When a forward scanning voltage V is applied to the control gate electrode 191... CG A positive pulse voltage is applied to multiple barrier gate electrodes 171, and a positive bias voltage V is applied between the drain electrode 131 and the source electrode 121. DS .

[0090] like Figure 6 As shown, the shaded area represents the Fermi Sea, the dashed line below the source region represents the Fermi level of the source region, the dashed line below the drain region represents the Fermi level of the drain region, the solid curve represents the conduction band, the short horizontal line below the control gate represents the impurity atom energy level, and the dashed arrow represents the electron transport process. Figure 6 The horizontal axis represents the distribution area of ​​the source region silicon conductivity mesa 12, the drain region silicon conductivity mesa 13, multiple barrier gates 17, and multiple finger control gates 19 along the direction of the silicon nanowire channel 14. Figure 6 The vertical axis represents the electron potential energy.

[0091] Electrons transition within the silicon nanowire channel 14 located beneath the multi-finger control gate 19 and multiple barrier gates, with impurity atoms acting as quantum dots providing transport energy levels for the electrons. The surface potential of the silicon nanowire channel 14, located beneath the multiple barrier gates 17, is relatively low, resulting in lower barriers between impurity atoms and stronger coupling between them. Therefore, electrons are primarily transported through impurity atoms via transition mechanisms.

[0092] like Figure 7 As shown in the transfer characteristic curve (current I at the drain electrode), D -Scanning voltage V CG The coupled current oscillation peak envelope is shown in the data, which indicates that the coupling energy between the bound impurity atoms in the silicon nanowire channel 14 is small and the coupling effect between the impurity atoms is strong.

[0093] This disclosure does not limit the doping type of the silicon nanowire channel 14. When the silicon nanowire channel 14 is p-type doped, a negative scanning voltage V is applied to the control gate electrode 191. CG A positive pulse voltage is applied to multiple barrier gate electrodes 171, and a negative bias voltage V is applied between the drain electrode 131 and the source electrode 121. DS It can achieve the same as Figure 4 and Figure 5 Similar modulation effect. With the silicon nanowire channel 14 doped p-type, a negative scanning voltage V is applied to the control gate electrode 191. CG A negative pulse voltage is applied to multiple barrier gate electrodes 171, and a negative bias voltage V is applied between the drain electrode 131 and the source electrode 121. DS It can achieve the same as Figure 6 and Figure 7 Similar modulation effect.

[0094] In this embodiment, a ferroelectric gate dielectric layer 16 and multiple barrier gates 17 are introduced into the impurity atom transistor. By applying pulsed voltages, the polarization intensity and direction in the ferroelectric gate dielectric layer 16 are adjusted, as well as the coupling barrier height between transport impurity atoms in the silicon nanowire channel 14 is adjusted, thereby modulating the quantum transport mechanism of charge carriers and achieving effective control of the single-electron electrical characteristics of the impurity atom transistor. A multi-finger control gate 19 is introduced into the impurity atom transistor to define the position and number of transport impurity atoms in the silicon nanowire channel 14 and modulate the energy levels of these atoms, achieving ordered control of the impurity atom array in the device.

[0095] Figure 8 A flowchart illustrating a method for fabricating a ferroelectric multi-gate silicon-based impurity atom transistor according to an embodiment of the present disclosure is shown.

[0096] like Figure 8 As shown, the fabrication method of the ferroelectric multi-gate silicon-based impurity atom transistor in this embodiment includes operations S210 to S240. The fabrication of the ferroelectric multi-gate silicon-based impurity atom transistor based on the SOI substrate can be performed using a silicon-based CMOS fully compatible process.

[0097] In operation S210, an oxide insulating layer 11 is prepared on the silicon substrate 10.

[0098] In operation S220, a source region silicon conductivity mesa 12, a drain region silicon conductivity mesa 13, and a silicon nanowire channel 14 are fabricated on an oxide insulating layer 11.

[0099] The source region silicon conductivity mesa 12 and the drain region silicon conductivity mesa 13 are respectively disposed on opposite sides of the upper surface of the oxide insulating layer 11, and the two ends of the silicon nanowire trench are respectively connected to the source region silicon conductivity mesa 12 and the drain region silicon conductivity mesa 13.

[0100] In operation S230, a first gate dielectric layer 15 is fabricated on the silicon nanowire channel 14.

[0101] In operation S240, a ferroelectric gate dielectric layer 16 is prepared on the first gate dielectric layer 15.

[0102] In operation S250, a plurality of barrier gates 17 are fabricated on the ferroelectric gate dielectric layer 16.

[0103] In operation S260, a second gate dielectric layer 18 is fabricated on the ferroelectric gate dielectric layer 16 and the plurality of barrier gates 17.

[0104] In operation S270, a multi-finger control gate 19 is fabricated on the second gate dielectric layer 18.

[0105] In operation S280, a source electrode 121 is fabricated on the silicon conductivity mesa 12 in the source region, a drain electrode 131 is fabricated on the silicon conductivity mesa 13 in the drain region, multiple barrier gate electrodes 171 are fabricated on multiple barrier gates 17, and a control gate electrode 191 is fabricated on a multi-finger control gate 19.

[0106] In this embodiment, the silicon substrate 10, oxide insulating layer 11, source region silicon conductivity mesa 12, drain region silicon conductivity mesa 13, and silicon nanowire channel 14 can be fabricated from an SOI substrate.

[0107] For example, an SOI substrate includes a top silicon layer, an oxide layer, and a silicon substrate. The top silicon layer can serve as a silicon substrate 10, and the oxide layer can serve as an oxide insulating layer 11. The top silicon layer can have a (100) or (110) crystal plane structure, and etching the top silicon layer can yield a source region silicon conductivity mesa 12, a drain region silicon conductivity mesa 13, and a silicon nanowire channel 14.

[0108] For example, a 30 nm thick silicon oxide mask layer is obtained by dry thermal oxidation at 950 °C for 30 min on the top silicon layer, with an energy of 30 keV and a surface dose of 1 × 10⁻⁶. 11 cm -2 Up to 1×10 15 cm -2 An n-type (or p-type) impurity is implanted into the silicon oxide mask layer. For example, the n-type impurity atom can be a phosphorus atom or an arsenic atom, and the p-type impurity atom can be a boron atom.

[0109] The silicon oxide mask layer behind the impurity atoms undergoes rapid thermal annealing at temperatures ranging from 800℃ to 1100℃ for 10 to 20 seconds. After annealing, the doping concentration in the top silicon layer can reach 1 × 10⁻⁶. 15 cm -3 Up to 5×10 19 cm -3 .

[0110] The annealed top silicon layer is processed sequentially using photolithography, dry etching, and hydrofluoric acid wet etching to fabricate a source region silicon conductivity mesa 12, a drain region silicon conductivity mesa 13, and a silicon nanowire channel 14 on the surface of the oxide insulating layer 11. The diameter of the silicon nanowire channel 14 can be 10 nm.

[0111] In this embodiment of the disclosure, for the first gate dielectric layer 15 and the ferroelectric gate dielectric layer 16, 2 nm HfO2 and 5 nm Hf can be deposited sequentially on the sample surface using an atomic layer deposition device. 0.95 Zr 0.05 O2 is used, and then photolithography and dry etching processes are used sequentially to prepare the first gate dielectric layer 15 and the ferroelectric gate dielectric layer 16 on the silicon nanowire channel 14.

[0112] For multiple barrier gates 17, a photoresist structure can be fabricated on the ferroelectric gate dielectric layer 16 of the sample using photolithography, for example, by growing 50nm TiN using magnetron sputtering, and then using a peel-off process to fabricate multiple barrier gates 17 on the ferroelectric gate dielectric layer 16. The multiple barrier gates 17 are discrete parallel structures, and the distance between the multiple barrier gates 17 can be 40nm, and the width can be 20nm.

[0113] To prepare the second gate dielectric layer 18, 2 nm Al2O3 can be deposited sequentially on the sample surface using an atomic layer deposition device, and then photolithography and dry etching processes can be used sequentially on the ferroelectric gate dielectric layer 16 and multiple barrier gates 17 to obtain the second gate dielectric layer 18.

[0114] For the multi-finger control gate 19, a photoresist structure is prepared on the second gate dielectric layer 18 of the sample by photolithography, 50nm TaN is grown by magnetron sputtering, and finally a peel-off process is used to prepare the multi-finger control gate 19 on the second gate dielectric layer 18. The distance between the multiple gate strips of the multi-finger control gate 19 is 40nm and the width is 20nm.

[0115] In this embodiment, a photoresist structure can be prepared on a sample by photolithography, and 400nm Al can be grown by electron beam evaporation. Then, a peel-stripping and mixed gas annealing process is used to prepare a source electrode 121 on the silicon conductivity mesa 12 in the source region, a drain electrode 131 on the silicon conductivity mesa 13 in the drain region, a plurality of barrier gate electrodes 171 on a plurality of barrier gates 17, and a control gate electrode 191 on a multi-finger control gate 19.

[0116] It should also be noted that, in specific embodiments of the present invention, unless otherwise stated otherwise, the numerical parameters in this specification and the appended claims are approximate values ​​and can be changed according to the desired characteristics obtained from the content of the present invention. Specifically, all numbers used in the specification and claims to indicate dimensions, range conditions, etc., of the composition should be understood to be modified by the term "about" in all cases. Generally, this means that there may be variations of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments.

[0117] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0118] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A dot atom transistor based on ferroelectric multi-gate silicon, comprising: Silicon substrate (10); An oxide insulating layer (11) is disposed on the silicon substrate (10); The source region silicon conductivity mesa (12) and the drain region silicon conductivity mesa (13) are respectively disposed on opposite sides of the upper surface of the oxide insulating layer (11); A silicon nanowire channel (14) is disposed on the upper surface of the oxide insulating layer (11), and its two ends are connected to the source region silicon conductivity mesa (12) and the drain region silicon conductivity mesa (13), respectively. A first gate dielectric layer (15) covers the silicon nanowire channel (14); A ferroelectric gate dielectric layer (16) covers the first gate dielectric layer (15); Multiple barrier gates (17) are covered on the ferroelectric gate dielectric layer (16) for modulating the height of the barrier region located below the multiple barrier gates (17); A second gate dielectric layer (18) covers the ferroelectric gate dielectric layer (16) and the plurality of barrier gates (17); A multi-finger control gate (19) is covered on the second gate dielectric layer (18). Multiple gate bars of the multi-finger control gate (19) and multiple barrier gates (17) are alternately arranged in parallel along the direction of the silicon nanowire channel (14). The multi-finger control gate (19) is used to modulate the position, number and energy level of impurity atoms in the silicon nanowire channel (14) located in the region below the multi-finger control gate (19). The polarization intensity and direction in the ferroelectric gate dielectric layer (16) are adjusted by applying a pulse voltage through the ferroelectric gate dielectric layer (16). The coupling barrier height between impurity atoms participating in transport in the silicon nanowire channel (14) located below the multiple barrier gates (17) is adjusted by applying a pulse voltage through the multiple barrier gates (17). as well as The source electrode (121) is disposed on the silicon conductivity mesa (12) of the source region, the drain electrode (131) is disposed on the silicon conductivity mesa (13) of the drain region, the multiple barrier gate electrodes (171) are disposed on the multiple barrier gates (17), and the control gate electrode (191) is disposed on the multiple finger control gate (19).

2. The impurity atom transistor according to claim 1, wherein, The plurality of barrier gates (17) are distributed parallel to each other and perpendicular to the arrangement direction of the silicon nanowire channel (14), and the two ends of the plurality of barrier gates (17) extend to the oxide insulating layer (11).

3. The impurity atom transistor according to claim 2, wherein, The connection end of the multi-finger control gate (19) extends to the oxide insulating layer (11), and the control gate electrode (191) is disposed on the connection end of the multi-finger control gate (19).

4. The impurity atom transistor according to claim 1, wherein, The materials of the plurality of barrier gates (17) include at least one of the following: polycrystalline silicon, polycrystalline germanium, metal, metal compound; and The material of the multi-finger control gate (19) includes at least one of the following: polycrystalline silicon, polycrystalline germanium, metal, and metal compound.

5. The impurity atom transistor according to claim 4, wherein, The plurality of barrier gates (17) form a discrete parallel structure, the distance between the plurality of barrier gates (17) ranges from 20 nm to 200 nm, the width of each of the plurality of barrier gates (17) ranges from 10 nm to 100 nm, and the thickness ranges from 10 nm to 200 nm.

6. The impurity atom transistor according to claim 1, wherein, The multiple gate bars of the multi-finger control gate (19) form a multi-finger structure. The distance between the multiple gate bars of the multi-finger control gate (19) ranges from 20 nm to 200 nm. The width of each gate bar ranges from 10 nm to 100 nm, and the thickness ranges from 10 nm to 200 nm.

7. The impurity atom transistor according to claim 1, wherein, The materials of the first gate dielectric layer (15) and the second gate dielectric layer (18) include at least one of the following: SiO2, oxynitride, TiO2, Si3N4, Ta2O5, HfO2, ZrO2, Al2O3, and the thickness of the first gate dielectric layer (15) and the second gate dielectric layer (18) ranges from 1 nm to 20 nm.

8. The impurity atom transistor according to claim 1, wherein, The material of the ferroelectric gate dielectric layer (16) includes at least one of the following: (Ba, Sr, Pb)TiO3, Pb(Zr)TiO3, etc. x Ti 1-x O3、[Pb(Mg) 1 / 3 Nb 2 / 3 )O3] 1-x [PbTiO3] x Hf x (Zr,Al, Y, Gd, La, Sr) 1-x O2, the thickness of the ferroelectric gate dielectric layer (16) ranges from 1 nm to 20 nm, wherein 0 <x<1。 9. The impurity atom transistor according to claim 1, wherein, The source region silicon conductivity mesa (12), drain region silicon conductivity mesa (13), and silicon nanowire channel (14) are doped with n-type or p-type doping, and the doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 1×10 20 cm -3 .

10. A method for fabricating a ferroelectric multi-gate silicon-based impurity atom transistor as described in any one of claims 1-9, comprising: An oxide insulating layer (11) is prepared on a silicon substrate (10). A source region silicon conductivity mesa (12), a drain region silicon conductivity mesa (13), and a silicon nanowire channel (14) are fabricated on the oxide insulating layer (11). The source region silicon conductivity mesa (12) and the drain region silicon conductivity mesa (13) are respectively disposed on opposite sides of the upper surface of the oxide insulating layer (11). The two ends of the silicon nanowire channel (14) are respectively connected to the source region silicon conductivity mesa (12) and the drain region silicon conductivity mesa (13). A first gate dielectric layer (15) is fabricated on the silicon nanowire channel (14); A ferroelectric gate dielectric layer (16) is prepared on the first gate dielectric layer (15). Multiple barrier gates (17) are fabricated on the ferroelectric gate dielectric layer (16). A second gate dielectric layer (18) is fabricated on the ferroelectric gate dielectric layer (16) and the plurality of barrier gates (17). A multi-finger control gate (19) is fabricated on the second gate dielectric layer (18); and A source electrode (121) is fabricated on the silicon conductivity mesa (12) in the source region, a drain electrode (131) is fabricated on the silicon conductivity mesa (13) in the drain region, a plurality of barrier gate electrodes (171) are fabricated on the plurality of barrier gates (17), and a control gate electrode (191) is fabricated on the multi-finger control gate (19).

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