A method and apparatus for driving multiple parallel power modules

Abstract

This application discloses a method and apparatus for driving multiple parallel power modules, comprising: acquiring current sampling signals corresponding to multiple power modules respectively within a first detection cycle; determining the start and end times corresponding to the multiple current sampling signals respectively; and adjusting the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, in response to the difference between the start and end times corresponding to the first current sampling signal and the start and end times corresponding to the second current sampling signal in the next detection cycle, so that the start and end times corresponding to the first current sampling signal in the next detection cycle are the same as the start and end times corresponding to the second current sampling signal. Thus, in this application, the pulse width modulation signal of the power module corresponding to the current sampling signal is adjusted based on the error value to achieve active current sharing among the parallel power modules, thereby improving the current sharing effect among the parallel power modules.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a method and apparatus for driving multiple parallel power modules. Background Technology

[0002] With the rapid development of power electronics technology and the continuous expansion of its applications, such as in some high-current capacity applications, the power module drive solution of motor controllers has become a necessary choice.

[0003] Currently, the power module drive scheme for motor controllers adopts the form of MCU (control board) + driver board + power module. However, when the power modules are used in parallel, uneven current in the parallel branches is inevitable. Furthermore, the driver board in this power module drive scheme does not integrate an adjustment module for uneven current in parallel modules, resulting in poor current sharing effect among the parallel power modules.

[0004] Therefore, how to improve the current sharing effect among parallel power modules is a key issue of concern to those skilled in the art. Summary of the Invention

[0005] To address the aforementioned problems, this application provides a method and apparatus for driving multiple parallel power modules, thereby improving the current sharing effect among the parallel power modules. The embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, this application discloses a method for driving multiple parallel power modules, including:

[0007] Acquire current sampling signals corresponding to multiple power modules within the first detection period, wherein the multiple power modules are connected in parallel;

[0008] Determine the start and end times for each of the multiple current sampling signals;

[0009] In response to the difference between the start and end times of the first current sampling signal and the second current sampling signal, the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle is adjusted so that the start and end times of the first current sampling signal in the next detection cycle are the same as the start and end times of the second current sampling signal. The first current sampling signal and the second current sampling signal are any two of the plurality of current sampling signals.

[0010] Optionally, adjusting the pulse width modulation signal of the power module corresponding to the first current sampling signal of the next detection cycle of the first detection cycle includes:

[0011] The pulse width modulation signal is processed by either phase lag or phase lead.

[0012] Optionally, after adjusting the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, in response to the difference between the start time and end time corresponding to the first current sampling signal and the start time and end time corresponding to the second current sampling signal, the method further includes:

[0013] Obtain the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal within the second detection period;

[0014] Calculate the difference between the first current slope and the second current slope;

[0015] Adjust the gate drive voltage of the power module corresponding to the first current sampling signal of the next detection cycle of the second detection cycle so that the difference is within the error threshold range.

[0016] Optionally, adjusting the gate drive voltage of the power module corresponding to the first current sampling signal in the next detection cycle of the second detection cycle includes:

[0017] The gate drive voltage is either reduced or increased.

[0018] Optionally, acquiring the current sampling signals corresponding to the multiple power modules within the first detection period includes:

[0019] The current sampling signals corresponding to multiple power modules within the first detection period are obtained by a driver adapter board. The driver adapter board is determined based on the module information of the multiple power modules, which includes the type of power module and the number of power modules determined based on the type of power module.

[0020] Secondly, this application discloses a power module multi-parallel drive device, comprising:

[0021] The acquisition module is used to acquire the current sampling signals corresponding to multiple power modules in the first detection period, wherein the multiple power modules are connected in parallel.

[0022] The determination module is used to determine the start and end times of multiple current sampling signals respectively;

[0023] An adjustment module is configured to adjust the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle in response to the difference between the start time and end time of the first current sampling signal and the start time and end time of the second current sampling signal, so that the start time and end time of the first current sampling signal in the next detection cycle are the same as the start time and end time of the second current sampling signal, wherein the first current sampling signal and the second current sampling signal are any two of the plurality of current sampling signals.

[0024] Optionally, the adjustment module includes:

[0025] The first processing module is used to perform phase lag processing or phase advance processing on the pulse width modulation signal.

[0026] Optionally, after the adjustment module, in response to the difference between the start time and end time corresponding to the first current sampling signal and the start time and end time corresponding to the second current sampling signal, the method further includes:

[0027] The first acquisition submodule is used to acquire the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal within the second detection period;

[0028] The calculation module is used to calculate the difference between the first current slope and the second current slope;

[0029] The first adjustment submodule is used to adjust the gate drive voltage of the power module corresponding to the first current sampling signal of the next detection cycle of the second detection cycle, so that the difference is within the error threshold range.

[0030] Optionally, the first adjustment submodule includes:

[0031] The second processing module is used to perform gate drive voltage reduction processing or gate drive voltage increase processing on the gate drive voltage.

[0032] Optionally, the acquisition module includes:

[0033] The first sub-acquisition module is used to acquire the current sampling signals corresponding to multiple power modules within the first detection period through a driver adapter board. The driver adapter board is determined based on the module information of the multiple power modules, including the power module type and the number of power modules determined based on the power module type.

[0034] Compared with the prior art, this application has the following beneficial effects:

[0035] This application first acquires current sampling signals corresponding to multiple power modules connected in parallel within a first detection cycle. Then, it determines the start and end times of each current sampling signal. Finally, in response to the difference between the start and end times of the first and second current sampling signals, it adjusts the pulse width modulation (PWM) signal of the power module corresponding to the first current sampling signal in the next detection cycle, making the start and end times of the first and second current sampling signals the same. The first and second current sampling signals are any two of the multiple current sampling signals. Thus, this application achieves active current sharing among the parallel power modules by adjusting the PWM signal of the power module corresponding to the current sampling signal based on the error value, thereby improving the current sharing effect among the parallel power modules. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart of a power module multi-parallel driving method provided in an embodiment of this application;

[0038] Figure 2 System block diagram provided for embodiments of this application;

[0039] Figure 3 This is a block diagram of the internal structure of the intermediate controller provided in an embodiment of this application;

[0040] Figure 4 This is a block diagram of the internal structure of the driver core provided in an embodiment of this application;

[0041] Figure 5 This is a block diagram of the internal components of the driver adapter board provided in an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of a power module multi-parallel drive device provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0044] It should be noted that the power module multi-parallel drive method and apparatus provided in this application are for the field of data processing technology. The above is only an example and does not limit the application field of the method and apparatus provided in this application.

[0045] As described earlier, in some high-current applications, power module drive solutions for motor controllers have become a necessary choice. Currently, the power module drive solution for motor controllers adopts the form of MCU (controller board) + driver board + power modules. However, when power modules are used in parallel, uneven current distribution in the parallel branches is inevitable. Furthermore, the driver board in this power module drive solution does not integrate an adjustment module to address the uneven current distribution among the parallel modules, resulting in poor current sharing among the parallel power modules. Therefore, how to improve the current sharing effect among the parallel power modules is a key issue of concern for those skilled in the art.

[0046] Therefore, the inventors propose the technical solution of this application. This application first acquires current sampling signals corresponding to multiple power modules within a first detection cycle, wherein the multiple power modules are connected in parallel. Then, it determines the start and end times corresponding to the multiple current sampling signals. Finally, in response to the difference between the start and end times corresponding to the first current sampling signal and the second current sampling signal, it adjusts the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, so that the start and end times corresponding to the first current sampling signal in the next detection cycle are the same as the start and end times corresponding to the second current sampling signal. The first current sampling signal and the second current sampling signal are any two of the multiple current sampling signals. Thus, in this application, active current sharing among the parallel power modules is achieved by adjusting the pulse width modulation signal of the power module corresponding to the current sampling signal based on the error value, thereby improving the current sharing effect among the parallel power modules.

[0047] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Method Implementation Examples

[0049] The following embodiment illustrates a power module multi-parallel driving method provided in this application.

[0050] See Figure 1 The figure is a flowchart of a power module multi-parallel driving method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method may include:

[0051] S101: Acquire the current sampling signals corresponding to the multiple power modules in the first detection cycle.

[0052] In this step, the current sampling signals corresponding to multiple power modules within the first detection cycle are acquired through a driver adapter board. These power modules are connected in parallel, or in other words, multiple power modules connected in parallel on the driver adapter board. The driver adapter board is determined based on the module information of the multiple power modules, including the type of power module, and the number of power modules is determined based on the type of power module. In essence, the types of power modules are first determined, then the number of power modules used is determined based on the types of power modules, and finally the driver adapter board is determined based on the types and number of power modules used. This reduces the cost of system porting and improves the system's versatility. The power modules can be SiC power modules; no specific limitation is made here.

[0053] In one feasible implementation, such as Figure 2 As shown, the power module drive scheme for the motor controller in this solution is: MCU (control board) + intermediate controller + driver core + driver adapter board + power module. Among them, as... Figure 3 As shown, the intermediate controller consists of a fiber optic interface for communication with the MCU, an FPGA, peripheral configuration circuitry, and fiber optic and cable interfaces for communication with the driver adapter board. It interacts with the MCU (control board) via the fiber optic interface for pulse width modulation (PWM) signals and fault signals; interacts with the driver adapter board via the fiber optic interface for PWM signals; and interacts with the gate voltage control signals and current sampling signals via the cable interface. The FPGA chip integrates an active current sharing control algorithm, analyzes the current sampling signal, and performs phase adjustment control of the PWM signal and gate drive voltage. The peripheral configuration circuitry implements the basic function configuration of the FPGA chip and the power supply configuration of the intermediate controller. Thus, the intermediate controller realizes the current signal acquisition and active control of multiple parallel power modules.

[0054] like Figure 4 As shown, the driver core consists of a driver chip, peripheral configuration circuits, and a board-to-board interface with the driver adapter board. By pairing with different driver adapter boards, it can achieve plug-and-play functionality for different power modules.

[0055] like Figure 5As shown, the driver adapter board consists of a driver power supply, a gate voltage adjustment module, a power adapter module, a current detection module, an optical fiber interface, a ribbon cable interface, and a power module interface. The driver power supply provides the drive voltage to the power modules; the gate voltage adjustment module adjusts the gate drive voltage according to the control signal from the intermediate controller to achieve dynamic current sharing of the power modules; the power adapter module enhances the drive capability of the driver core according to the drive requirements of different power modules to adapt to applications with larger drive currents; the current detection module mainly performs current detection of the power modules and feeds back the start and end times of the current sampling signal and the rate of change of current to the intermediate controller.

[0056] In some feasible implementations, the current sampling signal is sent to an intermediate controller after this step.

[0057] S102: Determine the start and end times corresponding to the multiple current sampling signals.

[0058] In this step, the start and end times of the multiple current sampling signals are determined by the intermediate controller.

[0059] S103: In response to the difference between the start time and end time of the first current sampling signal and the start time and end time of the second current sampling signal, adjust the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, so that the start time and end time of the first current sampling signal in the next detection cycle are the same as the start time and end time of the second current sampling signal, wherein the first current sampling signal and the second current sampling signal are any two of the plurality of current sampling signals.

[0060] In this step, within the first detection period, the start and end times corresponding to the first and second current sampling signals are compared. If the start and end times corresponding to the first and second current sampling signals are different, the phase of the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection period is either delayed or advanced, so that the start and end times of the first and second current sampling signals in the next detection period are the same. A current sharing algorithm can be used to adjust the pulse width modulation signal. The first and second current sampling signals can be any two of multiple current sampling signals; that is, the phase of the pulse width modulation signal of the power module corresponding to the second current sampling signal in the next detection period can also be delayed or advanced.

[0061] The following example illustrates this. In this example, during the first detection cycle, the current sampling signals a1 and a2 corresponding to the two power modules A1 and A2 are acquired respectively. Then, the start and end times of a1 are determined to be 0µs and 7µs, respectively, and the start and end times of a2 are determined to be 1µs and 8µs, respectively. At this time, the start and end times of a1 and a2 are different, and the start and end times of a2 are both lagging behind the start and end times of a1. Therefore, by using the current sharing algorithm to either lag the phase of the pulse width modulation signal of A1 or advance the phase of the pulse width modulation signal of A2 in the next detection cycle, the start and end times of a1 and a2 can be made the same.

[0062] Furthermore, in some feasible implementations, after adjusting the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, in response to the difference between the start time and end time corresponding to the first current sampling signal and the start time and end time corresponding to the second current sampling signal, the method further includes: acquiring the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal within the second detection cycle; calculating the difference between the first current slope and the second current slope; and adjusting the gate drive voltage of the power module corresponding to the first current sampling signal in the next detection cycle of the second detection cycle so that the difference is within the error threshold range.

[0063] In this step, after ensuring that the start and end times of the first current sampling signal are the same as those of the second current sampling signal, if a situation arises in the second detection cycle where the start and end times of the first and second current sampling signals are different, the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal are obtained. The difference between the first and second current slopes is calculated, and a preset error threshold is established. If the difference exceeds the error threshold, the gate drive voltage of the power module corresponding to the first current sampling signal in the next detection cycle is either reduced or increased. Alternatively, the gate drive voltage of the power module corresponding to the second current sampling signal in the next detection cycle can be reduced or increased to ensure that the difference is within the error threshold range. The first current slope includes the rate of change of current rise corresponding to the first current sampling signal, and the second current slope includes the rate of change of current rise corresponding to the second current sampling signal.

[0064] The following example illustrates this. In this example, if the start and end times of a1 and a2 differ again during the second detection cycle, the first current slope and the second current slope corresponding to the two power modules A1 and A2 are obtained respectively. If the difference between the first current slope and the second current slope exceeds the error threshold, the gate drive voltage of a1 is increased or the gate drive voltage of a2 is decreased to ensure that the difference between a1 and a2 is within the error threshold range.

[0065] As can be seen, this optional solution mainly describes how to achieve active current sharing among the parallel power modules. Specifically, in this optional solution, the application first acquires the current sampling signals corresponding to multiple power modules in a first detection cycle, wherein the multiple power modules are connected in parallel. Then, it determines the start and end times corresponding to the multiple current sampling signals. Finally, in response to the difference between the start and end times corresponding to the first current sampling signal and the second current sampling signal, it adjusts the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, so that the start and end times corresponding to the first current sampling signal in the next detection cycle are the same as the start and end times corresponding to the second current sampling signal. The first current sampling signal and the second current sampling signal are any two of the multiple current sampling signals.

[0066] In summary, in this embodiment, the pulse width modulation signal of the power module corresponding to the current sampling signal is adjusted based on the error value to achieve active current sharing among the parallel power modules, thereby improving the current sharing effect among the parallel power modules.

[0067] Device Examples

[0068] The following describes a power module multi-parallel drive device provided by an embodiment of this application. The power module multi-parallel drive device described below and the power module multi-parallel drive method described above can be referred to in correspondence.

[0069] See Figure 6 The figure is a schematic diagram of the structure of a power module multi-parallel drive device provided in an embodiment of this application, as shown below. Figure 6 As shown, the device may include:

[0070] The acquisition module 100 is used to acquire the current sampling signals corresponding to multiple power modules in the first detection period, wherein the multiple power modules are connected in parallel.

[0071] The determination module 200 is used to determine the start time and end time corresponding to the multiple current sampling signals respectively;

[0072] The adjustment module 300 is used to adjust the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle in response to the difference between the start time and end time of the first current sampling signal and the start time and end time of the second current sampling signal, so that the start time and end time of the first current sampling signal in the next detection cycle are the same as the start time and end time of the second current sampling signal, wherein the first current sampling signal and the second current sampling signal are any two of the plurality of current sampling signals.

[0073] Optionally, the adjustment module 300 includes:

[0074] The first processing module is used to perform phase lag processing or phase advance processing on the pulse width modulation signal.

[0075] Optionally, after the adjustment module, in response to the difference between the start time and end time corresponding to the first current sampling signal and the start time and end time corresponding to the second current sampling signal, the method further includes:

[0076] The first acquisition submodule is used to acquire the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal within the second detection period;

[0077] The calculation module is used to calculate the difference between the first current slope and the second current slope;

[0078] The first adjustment submodule is used to adjust the gate drive voltage of the power module corresponding to the first current sampling signal of the next detection cycle of the second detection cycle, so that the difference is within the error threshold range.

[0079] Optionally, the first adjustment submodule includes:

[0080] The second processing module is used to perform gate drive voltage reduction processing or gate drive voltage increase processing on the gate drive voltage.

[0081] Optionally, the acquisition module 100 includes:

[0082] The first sub-acquisition module is used to acquire the current sampling signals corresponding to multiple power modules within the first detection period through a driver adapter board. The driver adapter board is determined based on the module information of the multiple power modules, including the power module type and the number of power modules determined based on the power module type.

[0083] The power module multi-parallel drive device provided in this application embodiment has the same beneficial effects as the power module multi-parallel drive method provided in the above embodiments, so it will not be described again.

[0084] It should be noted that the "first" and "second" in the names mentioned in the embodiments of this application are only used as name identifiers and do not represent the first and second in order.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0086] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0087] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0088] The foregoing has provided a detailed description of a power module multi-parallel driving method and apparatus provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for driving multiple parallel power modules, characterized in that, include: Acquire current sampling signals corresponding to multiple power modules within the first detection period, wherein the multiple power modules are connected in parallel; The current sampling signal is sent to an intermediate controller, which determines the start and end times corresponding to the multiple current sampling signals. In response to the difference between the start and end times of the first current sampling signal and the second current sampling signal, the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle is adjusted so that the start and end times of the first current sampling signal in the next detection cycle are the same as the start and end times of the second current sampling signal. The first current sampling signal and the second current sampling signal are any two of the plurality of current sampling signals. After adjusting the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, in response to the difference between the start time and end time corresponding to the first current sampling signal and the start time and end time corresponding to the second current sampling signal, the method further includes: Obtain the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal within the second detection period; Calculate the difference between the first current slope and the second current slope; Adjust the gate drive voltage of the power module corresponding to the first current sampling signal of the next detection cycle of the second detection cycle so that the difference is within the error threshold range; The intermediate controller is used to adjust and control the phase of the pulse width modulation signal and the gate drive voltage.

2. The method according to claim 1, characterized in that, The adjustment of the pulse width modulation signal of the power module corresponding to the first current sampling signal of the next detection cycle of the first detection cycle includes: The pulse width modulation signal is processed by either phase lag or phase lead.

3. The method according to claim 1, characterized in that, The adjustment of the gate drive voltage of the power module corresponding to the first current sampling signal of the next detection cycle of the second detection cycle includes: The gate drive voltage is either reduced or increased.

4. The method according to claim 1, characterized in that, The acquisition of current sampling signals corresponding to multiple power modules within the first detection period includes: The current sampling signals corresponding to multiple power modules within the first detection period are obtained by a driver adapter board. The driver adapter board is determined based on the module information of the multiple power modules, which includes the type of power module and the number of power modules determined based on the type of power module.

5. A power module multi-parallel drive device, characterized in that, include: The acquisition module is used to acquire the current sampling signals corresponding to multiple power modules in the first detection period, wherein the multiple power modules are connected in parallel. The determination module is used to send the current sampling signal to the intermediate controller, and the intermediate controller determines the start time and end time corresponding to the multiple current sampling signals respectively; An adjustment module is configured to adjust the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle in response to the difference between the start time and end time of the first current sampling signal and the start time and end time of the second current sampling signal, so that the start time and end time of the first current sampling signal in the next detection cycle are the same as the start time and end time of the second current sampling signal, wherein the first current sampling signal and the second current sampling signal are any two of the plurality of current sampling signals; After adjusting the pulse width modulation signal of the power module corresponding to the first current sampling signal in the next detection cycle of the first detection cycle, in response to the difference between the start time and end time corresponding to the first current sampling signal and the start time and end time corresponding to the second current sampling signal, the method further includes: The first acquisition submodule is used to acquire the first current slope corresponding to the first current sampling signal and the second current slope corresponding to the second current sampling signal within the second detection period; The calculation module is used to calculate the difference between the first current slope and the second current slope; The first adjustment submodule is used to adjust the gate drive voltage of the power module corresponding to the first current sampling signal of the next detection cycle of the second detection cycle, so that the difference is within the error threshold range. The intermediate controller is used to adjust and control the phase of the pulse width modulation signal and the gate drive voltage.

6. The apparatus according to claim 5, characterized in that, The adjustment module includes: The first processing module is used to perform phase lag processing or phase advance processing on the pulse width modulation signal.

7. The apparatus according to claim 5, characterized in that, The first adjustment submodule includes: The second processing module is used to perform gate drive voltage reduction processing or gate drive voltage increase processing on the gate drive voltage.

8. The apparatus according to claim 5, characterized in that, The acquisition module includes: The first sub-acquisition module is used to acquire the current sampling signals corresponding to multiple power modules within the first detection period through a driver adapter board. The driver adapter board is determined based on the module information of the multiple power modules, including the power module type and the number of power modules determined based on the power module type.

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