Power amplifier with harmonic filtering circuit

Abstract

An amplifier includes a signal input terminal for inputting an input signal; a voltage input terminal for inputting a power supply voltage; an amplification circuit for generating an amplified input signal based on the input signal, wherein the amplified input signal has a fundamental frequency, a first harmonic, and a second harmonic, wherein the first harmonic is the second harmonic of the fundamental frequency, and the second harmonic is the third harmonic of the fundamental frequency; a harmonic filter circuit coupled between the voltage input terminal and the amplification circuit for filtering the first harmonic and the second harmonic; and a signal output terminal coupled to the harmonic filter circuit for outputting an output signal based on the amplified input signal.

Description

Technical Field

[0001] This invention relates to a power amplifier, and more particularly to a power amplifier with a harmonic filtering circuit. Background Technology

[0002] Radio frequency (RF) power amplifiers (PAs) are widely used in various circuits to improve signal quality. During operation, the input signal generates harmonics, affecting the circuit's performance and efficiency. According to current technology, λ / 4 transmission lines can only filter the second harmonic generated by the input signal, but cannot filter the third harmonic. Furthermore, the λ / 4 transmission line has a relatively small bandwidth and a large area (or volume), making it susceptible to interference. Therefore, the processing and filtering of harmonics generated when the input signal passes through the power amplifier is a problem that urgently needs to be solved. Summary of the Invention

[0003] The present invention provides an amplifier with a harmonic filtering circuit to solve the above-mentioned problems.

[0004] This invention discloses an amplifier comprising: a signal input terminal for inputting an input signal; a voltage input terminal for inputting a power supply voltage; an amplification circuit for generating an amplified input signal based on the input signal, wherein the amplified input signal has a fundamental frequency, a first harmonic, and a second harmonic, wherein the first harmonic is the second harmonic of the fundamental frequency, and the second harmonic is the third harmonic of the fundamental frequency; a harmonic filter circuit coupled between the voltage input terminal and the amplification circuit for filtering the first harmonic and the second harmonic; and a signal output terminal coupled to the harmonic filter circuit for outputting an output signal based on the amplified input signal.

[0005] The present invention also discloses a harmonic filtering circuit, comprising a resonator circuit, including a first terminal coupled to a voltage input terminal; and a second terminal for receiving an input signal, wherein the input signal has a fundamental frequency, a first harmonic, and a second harmonic, and the first harmonic and the second harmonic have a first impedance value and a second impedance value in the resonator circuit that are less than the third impedance value of the fundamental frequency in the resonator circuit; and a bypass capacitor circuit, including a first terminal coupled to the voltage input terminal; and a second terminal coupled to a reference voltage terminal, wherein the first harmonic and the second harmonic have a fourth impedance value and a fifth impedance value in the bypass capacitor circuit that are less than the sixth impedance value of the fundamental frequency in the bypass capacitor circuit. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the amplifier in Embodiment 1 of the present invention.

[0007] Figure 2 This is a schematic diagram of the amplifier in Embodiment 1 of the present invention.

[0008] Figure 3 This is a schematic diagram of a harmonic filter circuit according to Embodiment 1 of the present invention.

[0009] Figure 4 This is a schematic diagram of the layout of the harmonic filter circuit in Embodiment 1 of the present invention.

[0010] Figure 5 This is a schematic diagram of the amplifier layout according to Embodiment 1 of the present invention.

[0011] Figure 6 This is a schematic diagram of the amplifier layout according to Embodiment 1 of the present invention.

[0012] Figure 7a This is a schematic diagram of the amplifier layout according to Embodiment 1 of the present invention.

[0013] Figure 7b This is a schematic diagram of the amplifier layout according to Embodiment 1 of the present invention.

[0014] Figure 8a This is a schematic diagram of the power performance of a power amplifier in the prior art.

[0015] Figure 8b This is a schematic diagram of the power performance of the amplifier in an embodiment of the present invention.

[0016] Figure 9 This is a comparison chart of the radio frequency output power of power amplifiers in the prior art and the amplifiers in the embodiments of the present invention.

[0017] [Symbol Explanation]

[0018] 10, 20, 50, 60, 70: Amplifier

[0019] 100: Amplifier Circuit

[0020] 110, 30, 40, 600, 700: Harmonic filter circuit

[0021] 120: Matching circuit

[0022] 300: Resonant Circuit

[0023] 302, 404, 604, 704: Inductor-capacitor parallel circuit

[0024] 310, 412: Bypass capacitor circuit

[0025] 400,606,S1,S2:Substrate

[0026] 402, 602, 702: Open-circuit residual capacitors

[0027] 406: Interdigitated edge capacitors

[0028] 408: Distribute Inductance

[0029] 410: Transmission line inductance

[0030] 90, 91, 92, 93, 94, 95: Simulation curves

[0031] C1, C2, Cshunt, Cp: Capacitors

[0032] E1, E2, E3, E4, E5, E6, E7, E8: Endpoints

[0033] Lmlin, Lwb, Lp: Inductance

[0034] P1, P2: Ports

[0035] Pin: Signal input terminal

[0036] Pout: Signal output terminal

[0037] S_in: Input signal

[0038] S_out, S_out': Output signals

[0039] SIG: Amplified input signal

[0040] VCC: Voltage input terminal

[0041] V_ref: Reference voltage terminal Detailed Implementation

[0042] Figure 1This is a schematic diagram of an amplifier 10 (e.g., a power amplifier) ​​according to an embodiment of the present invention. The amplifier 10 includes a signal input terminal Pin, a voltage input terminal VCC, an amplifier circuit 100, a harmonic filter circuit 110, and a signal output terminal Pout. The harmonic filter circuit 110 is coupled between the voltage input terminal VCC and the amplifier circuit 100, and the signal output terminal Pout is coupled between the harmonic filter circuit 110 and the amplifier circuit 100. Specifically, an input signal S_in is input through the signal input terminal Pin, and a power supply voltage is input through the voltage input terminal VCC and provided to the amplifier circuit 100 as its operating voltage. Based on the input signal S_in input to the input terminal of the amplifier circuit 100, the amplifier circuit 100 generates an amplified input signal SIG and outputs it to the output terminal of the amplifier circuit 100. The amplified input signal SIG has a fundamental frequency, a first harmonic, and a second harmonic. The first harmonic may be the second harmonic of the fundamental frequency, and the second harmonic may be the third harmonic of the fundamental frequency. Next, the harmonic filter circuit 110 filters the first and second harmonics of the amplified input signal SIG to suppress the first and second harmonics output to the signal output terminal Pout. Based on the amplified input signal SIG, the signal output terminal Pout outputs an output signal S_out.

[0043] Based on the foregoing description, the present invention provides an amplifier that includes a harmonic filtering circuit, which can be used to filter the second and third harmonics generated by the input signal in the circuit. Therefore, the problem of harmonics generated when the input signal passes through the power amplifier can be improved.

[0044] In one embodiment, the amplifier circuit 100 may be an amplifying transistor. In one embodiment, the amplifier circuit 100 may include a plurality of amplifying stages, and each amplifying stage may include an amplifying transistor. In one embodiment, the signal input terminal Pin may be coupled to the input terminal of the amplifying transistor, for example, the base. In one embodiment, the harmonic filter circuit 110 may be coupled to the output terminal of the amplifying transistor, for example, the collector. In one embodiment, the reference terminal of the amplifying transistor, for example, the emitter, may be coupled to a reference voltage terminal V_ref.

[0045] Please also refer to Figure 1 and Figure 4 In one embodiment, the amplifier 10 further includes a substrate S1, and the substrate S1 has a first surface S11 and a second surface S12, wherein at least a portion of the harmonic filter circuit 110 may be disposed on the first surface S11 of the substrate S1. Please also refer to Figure 1 , Figure 4 and Figure 7bIn one embodiment, the amplifier 10 further includes a substrate S2, and the substrate S2 has a first surface and a second surface. At least a portion of the harmonic filter circuit 110 may be disposed between the first surface of the substrate S1 and the second surface of the substrate S2, and the amplifier circuit 100 may be disposed on the first surface of the substrate S2. In one embodiment, in the amplifier 10, the substrate S1 may be a first metal-1 layer substrate, and the substrate S2 may be a second metal-2 layer substrate.

[0046] In one embodiment, the amplifier circuit 100 may further include a plurality of amplifier stages, and the harmonic filter circuit 110 may be coupled between the voltage input terminal VCC and the last amplifier stage of the plurality of amplifier stages.

[0047] In one embodiment, the power supply voltage VCC may be between 0 and 5V, but is not limited thereto. In one embodiment, the reference voltage terminal V_ref may be a ground voltage, but is not limited thereto.

[0048] Figure 2 This is a schematic diagram of an amplifier 20 (e.g., a power amplifier) ​​according to an embodiment of the present invention. Compared to amplifier 10, amplifier 20 further includes a matching network 120. The matching network 120 is coupled to the harmonic filter circuit 110 and the signal output terminal Pout, and can be an output matching network (OMN) to provide output impedance matching for amplifier 20. The operation and function of other circuit components can be referred to the foregoing and will not be repeated here. In one embodiment, the output signal S_out may include the fundamental frequency of the amplified input signal SIG. In one embodiment, after passing through the matching network 120, the output signal S_out' is output at the signal output terminal Pout.

[0049] It should be noted that the amplifier 10 provided by this invention filters the harmonics of the amplified input signal SIG in the harmonic filter circuit 110, while the matching circuit 120 provides output impedance matching. That is, the harmonic filter circuit 110 is set on the path from the amplifier circuit 100 to the voltage input terminal VCC for harmonic filtering, rather than on the path from the amplifier circuit 100 to the signal output terminal Pout for harmonic filtering.

[0050] Figure 3This is a schematic diagram of a harmonic filter circuit 30 according to an embodiment of the present invention. The harmonic filter circuit 30 can be used to implement a harmonic filter circuit 110. The harmonic filter circuit 30 includes a resonant circuit 300 and a bypass capacitor circuit 310. The resonant circuit 300 includes a first terminal E1 and a second terminal E2. The first terminal E1 of the resonant circuit 300 can be coupled to the voltage input terminal VCC, and the second terminal E2 of the resonant circuit 300 can be coupled to the amplifier circuit 100 to receive the amplified input signal SIG. The bypass capacitor circuit 310 includes a first terminal E3 and a second terminal E4. The first terminal E3 of the bypass capacitor circuit 310 can be coupled to the voltage input terminal VCC, and the second terminal E4 of the bypass capacitor circuit 310 can be coupled to the reference voltage terminal V_ref. Specifically, the amplified input signal SIG has a fundamental frequency, a first harmonic, and a second harmonic. The first harmonic can be the second harmonic of the fundamental frequency, and the second harmonic can be the third harmonic of the fundamental frequency. The impedance values ​​of the first harmonic and the second harmonic in the resonant circuit 300 are less than the impedance value of the fundamental frequency in the resonant circuit 300. The impedance values ​​of the first harmonic and the second harmonic in the bypass capacitor circuit 310 are also less than the impedance value of the fundamental frequency in the bypass capacitor circuit 310.

[0051] As described above, the harmonic filtering circuit of the present invention allows the second and third harmonics generated in the circuit by the input signal passing through the power amplifier to be input to a relatively low-impedance harmonic filtering circuit to filter the second and third harmonics. Furthermore, compared to existing technologies (e.g., λ / 4 transmission lines), the harmonic filtering circuit provided by the present invention can simultaneously filter the second and third harmonics and has a smaller circuit size, reducing the installation area or volume of the harmonic filtering circuit and thus reducing interference experienced by the harmonic filtering circuit. Therefore, the problem of harmonics generated when the signal passes through the power amplifier can be improved.

[0052] In one embodiment, the bypass capacitor circuit 310 may further include bypass capacitors C1 and C2, wherein bypass capacitors C1 and C2 are connected in parallel. In one embodiment, the impedance value of the first harmonic at bypass capacitor C1 is less than the impedance value of the fundamental wave at bypass capacitor C1. In one embodiment, the impedance value of the second harmonic at bypass capacitor C2 is less than the impedance value of the fundamental wave at bypass capacitor C2. That is, according to the resonant circuit 300 and bypass capacitor C1, the first harmonic can be filtered. According to the resonant circuit 300 and bypass capacitor C2, the second harmonic can be filtered. Therefore, the harmonic filtering circuit 30 can simultaneously filter the second and third harmonics generated by the amplified input signal SIG in the circuit, so as to reduce the influence caused by the above-mentioned harmonics.

[0053] In one embodiment, the resonant circuit 300 further includes an inductor-capacitor parallel circuit 302. The inductor-capacitor parallel circuit 302 includes at least one capacitor Cp and at least one inductor Lp, wherein the at least one capacitor Cp and the at least one inductor Lp are connected in parallel. The inductor-capacitor parallel circuit 302 has a first terminal E5 and a second terminal E6. The inductor-capacitor parallel circuit 302 is coupled between the first terminal E1 and the second terminal E2 of the resonant circuit 300. In one embodiment, the resonant circuit 300 further includes an inductor Lmlin and a capacitor Cshunt. The inductor Lmlin is coupled between the first terminal E5 of the inductor-capacitor parallel circuit 302 and the first terminal E1 of the resonant circuit 300. The capacitor Cshunt includes a first terminal E7 and a second terminal E8. The first terminal E7 of the capacitor Cshunt can be coupled between the second terminal E6 of the inductor-capacitor parallel circuit 302 and the second terminal E2 of the resonant circuit 300, and the second terminal E8 of the capacitor Cshunt can be coupled to a reference voltage terminal V_ref. In one embodiment, at least one capacitor Cp, at least one inductor Lp, inductor Lmlin, or capacitor Chaount may be formed by at least one microstrip line. In one embodiment, the first terminal of at least one capacitor Cp, at least one inductor Lp, inductor Lmlin, and capacitor Chaount may be disposed on a first surface of a substrate (e.g., substrate S1). In one embodiment, the second terminal of capacitor Chaount may be disposed on a second surface of the substrate.

[0054] In one embodiment, the capacitor Chaoshunt can be an open-stub capacitor. That is, the capacitor Chaoshunt can be generated based on a parasitic effect. In one embodiment, the capacitor Chaoshunt can be a capacitor generated based on the parasitic effect of a parallel-plate capacitor. In one embodiment, if the harmonic filter circuit 30 is disposed in an amplifier having a first substrate and a second substrate, the capacitor Chaoshunt can be a capacitor generated based on the parasitic effect of the first substrate and the second substrate. In one embodiment, at least one capacitor Cp can be at least one fringing-capacitance. In one embodiment, at least one capacitor Cp can be at least one interdigitated fringing-capacitance. In one embodiment, the capacitance value of at least one capacitor Cp is related to the number of fringing-capacitance units. For example, if at least one capacitor Cp has n fringing-capacitance units, the capacitance value of at least one capacitor Cp is n*ΔC, where ΔC is the capacitance value of a single fringing-capacitance unit.

[0055] In one embodiment, at least one inductor Lp may include a distribution inductance and a transmission line inductance. In one embodiment, the inductance value of the at least one inductor Lp is the sum of the inductance values ​​of the distribution inductance and the transmission line inductance. For example, if the inductance value of the distribution inductance is ΔL1 and the inductance value of the transmission line inductance is ΔL2, then the inductance value of the at least one inductor Lp is ΔL1 + ΔL2.

[0056] In one embodiment, the resonant circuit 300 may further include an inductor Lwb. The inductor Lwb may be coupled between a first terminal E7 of the capacitor Cshunt and a second terminal E2 of the resonant circuit 300. In one embodiment, the inductor Lwb may be a bondwire. That is, the material constituting the inductor Lwb may be different from that of at least one capacitor Cp, at least one inductor Lp, inductor Lmlin, and capacitor Cshunt. In other words, the material used for the inductor Lwb may be different from that of at least one capacitor Cp, at least one inductor Lp, inductor Lmlin, and capacitor Cshunt.

[0057] In one embodiment, the harmonic filter circuit 30 may be disposed on a printed circuit board (PCB) conforming to the FR-4 standard. In one embodiment, the harmonic filter circuit 30 may be disposed on a ceramic substrate. In one embodiment, the harmonic filter circuit 30 may be implemented inside or outside a package to reduce the size or volume of the harmonic filter circuit 30. In one embodiment, the harmonic filter circuit 30 may be applied to a multi-chip module (MCM) to reduce the size or volume of the harmonic filter circuit 30. Therefore, the harmonic filter circuit 30 provided by the present invention can have a smaller circuit size, reducing the size or volume of the harmonic filter circuit 30 and thus reducing the interference received by the harmonic filter circuit 30.

[0058] In one embodiment, the reference voltage terminal V_ref can be a ground voltage or a common voltage, but is not limited thereto. In one embodiment, the voltage at the voltage input terminal VCC can be between 0 and 5V, but is not limited thereto.

[0059] Figure 4This is a schematic diagram of the layout of a harmonic filter circuit 40 according to an embodiment of the present invention. The harmonic filter circuit 40 can be used to implement the harmonic filter circuit 30. The substrate S1 (400) has a first surface S11 and a second surface S12. The harmonic filter circuit 40 can be at least partially disposed on the first surface S11 of the substrate S1 (400), and a conductive layer is disposed on the second surface S12 to form a ground layer (not shown in the figure). The harmonic filter circuit 40 may include an open-circuit residual capacitor 402, an inductor-capacitor parallel circuit 404, a voltage input terminal VCC, and a bypass capacitor circuit 412. The open-circuit residual capacitor 402 can be disposed on the first surface S11, and a capacitor is generated by the parasitic effect of the parallel plate capacitor generated by the ground layer disposed on the second surface S12. The inductor-capacitor parallel circuit 404 can be disposed on the first surface S11, and may include at least one interdigitated edge capacitor 406, a distribution inductor 408, and a transmission line inductor 410. The inductor-capacitor parallel circuit 404 can be coupled to the open-circuit residual capacitor 402, and the voltage input terminal VCC can be coupled to the inductor-capacitor parallel circuit 404. The bypass capacitor circuit 412 can be disposed outside or inside the substrate S1 (400), and can be coupled between the voltage input terminal VCC and the reference voltage terminal V_ref. In the inductor-capacitor parallel circuit 404, the distribution inductor 408 can be connected in series with the transmission line inductor 410, and at least one interdigitated edge capacitor 406 can be connected in parallel with the distribution inductor 408 and the transmission line inductor 410. The bypass capacitor circuit 412 can be, but is not limited to, the bypass capacitor circuit 310. The harmonic filter circuit 40 can have a port P1 and a port P2. Port P1 can be disposed in the open-circuit residual capacitor 402, and port P2 can be disposed near the voltage input terminal VCC. Through a single wire, the first and second harmonics of the amplified input signal SIG can be input to the harmonic filter circuit 40 via port P1. It should be noted that, depending on different design requirements, the number of interdigitated edge capacitors 406, the length of the distribution inductor 408, and the transmission line inductor 410 can be adjusted accordingly to reduce design complexity and achieve a smaller circuit size. This reduces the installation area or volume of the harmonic filter circuit, thereby minimizing interference to the harmonic filter circuit.

[0060] The operation of the harmonic filter circuit 30 can be applied to the harmonic filter circuit 40, which will not be described in detail here.

[0061] Figure 5This is a schematic diagram of the layout of amplifier 50 according to an embodiment of the present invention. Amplifier 50 can be used to implement amplifier 10. Amplifier 50 includes a signal input terminal Pin, a voltage input terminal VCC, an amplification circuit 100, a harmonic filter circuit 40, and a signal output terminal Pout. The harmonic filter circuit 40 can be implemented on a circuit board outside the package, for example, on a substrate 400 disposed outside the amplification circuit 100, and the harmonic filter circuit 40 includes an open-circuit residual capacitor 402, an inductor-capacitor parallel circuit 404, and a bypass capacitor circuit 412. Amplification circuit 100 is coupled to harmonic filter circuit 40 through at least one bonding wire. The coupling methods of other circuit components can be referred to the foregoing description and will not be repeated here.

[0062] according to Figure 5 The input signal (e.g., input signal S_in) is input through the signal input terminal Pin and amplified in the amplifier circuit 100. Then, the second and third harmonics of the amplified input signal can be input to the harmonic filter circuit 40 through at least one pass. Therefore, the second and third harmonics generated in the circuit by the output signal (e.g., output signal S_out) at the signal output terminal Pout can be filtered. Furthermore, compared to the prior art, the layout area of ​​the harmonic filter circuit 40 is smaller than the layout area of ​​a λ / 4 transmission line, which reduces interference to the output signal.

[0063] The operation of the harmonic filter circuit 40 can be referred to the above content, and will not be repeated here.

[0064] In one embodiment, the harmonic filter circuit 40 may be disposed on the first surface of the substrate 400. In one embodiment, if the amplifier circuit 100 includes a plurality of amplification stages (in this figure, two amplification stages are used as an example), the harmonic filter circuit 40 may be coupled between the voltage input terminal VCC and the output terminal of the last amplification stage of the plurality of amplification stages of the amplifier circuit 100 (in this figure, two amplification stages are used as an example). In one embodiment, if the amplifier circuit 100 further includes an RF choke, the output terminals of the other amplification stages of the plurality of amplification stages of the amplifier circuit 100 (in this figure, the first amplification stage is used as an example) may be coupled to the voltage input terminal VCC through at least one circuit connection line (e.g., at least one microstrip line). In one embodiment, amplifier 50 may optionally include a matching circuit (not shown) to implement amplifier 20. The matching circuit is coupled to harmonic filter circuit 400 and signal output terminal Pout to provide output impedance matching for amplifier 100. Its operation and function can be referred to the foregoing and will not be repeated here.

[0065] Figure 6This is a schematic diagram of the layout of amplifier 60 according to an embodiment of the present invention. Amplifier 60 can be used to implement amplifier 10. Amplifier 60 includes a signal input terminal Pin, an amplification circuit 100, a harmonic filter circuit 600, and a signal output terminal Pout. The harmonic filter circuit 600 includes an open-circuit residual capacitor 602, an inductor-capacitor parallel circuit 604, a voltage input terminal VCC, and a bypass capacitor circuit 412. The harmonic filter circuit 600 can be implemented on a circuit board outside the package, for example, on a substrate 606 outside the amplification circuit 100. The amplification circuit 100 is coupled to the harmonic filter circuit 600 through at least one bonding wire. Compared to Figure 5 The open-circuit residual capacitor 602 and the open-circuit residual capacitor 402 have different layouts, as do the inductor-capacitor parallel circuit 604 and the inductor-capacitor parallel circuit 404. Furthermore, the layout area of ​​the harmonic filter circuit 600 is smaller than that of the λ / 4 transmission line, which reduces interference to the output signal. The operation of amplifier 50 can be applied to amplifier 60, and will not be elaborated here.

[0066] In one embodiment, amplifier 60 may optionally include a matching circuit (not shown) to implement amplifier 20. The matching circuit is coupled to harmonic filter circuit 600 and signal output terminal Pout to provide output impedance matching for amplifier 100. Its operation and function can be referred to the foregoing and will not be repeated here.

[0067] Figure 7a This is a schematic diagram of the layout of amplifier 70 according to an embodiment of the present invention. Amplifier 70 can be used to implement amplifier 10. Amplifier 70 can be implemented inside a package, for example, the harmonic filter circuit 700 and the amplifier circuit 100 are jointly disposed on the same side of the leadframe inside the same package. Amplifier 70 includes a signal input terminal Pin, a voltage input terminal VCC, amplifier circuit 100, harmonic filter circuit 700, and signal output terminal Pout. Harmonic filter circuit 700 may include an open-circuit residual capacitor 702, an inductor-capacitor parallel circuit 704, bypass capacitor C1, and bypass capacitor C2. Harmonic filter circuit 700 can be disposed on the first side of substrate S1.

[0068] In one embodiment, the harmonic filter circuit 700 may be a harmonic filter circuit 30, a harmonic filter circuit 40, or a harmonic filter circuit 600, but is not limited thereto. In one embodiment, the open-circuit residual capacitor 702 may be an open-circuit residual capacitor 402 or an open-circuit residual capacitor 602, but is not limited thereto. In one embodiment, the inductor-capacitor parallel circuit 704 may be an inductor-capacitor parallel circuit 404 or an inductor-capacitor parallel circuit 604, but is not limited thereto.

[0069] In one embodiment, amplifier 70 may optionally include a matching circuit (not shown) to implement amplifier 20. The matching circuit is coupled to harmonic filter circuit 700 and signal output terminal Pout to provide output impedance matching for amplifier 100. Its operation and function are as described above and will not be repeated here. The matching circuit may be housed in the same package as amplifier circuit 100. The operation of harmonic filter circuit 30 or harmonic filter circuit 40 can be applied to harmonic filter circuit 70, and will not be repeated here.

[0070] Figure 7b This is another schematic diagram of the layout of amplifier 70 according to an embodiment of the present invention, which can also be used to implement amplifier 10. Compared to Figure 7a The amplifier 70 further includes a substrate S2, and the substrate S2 has a first surface and a second surface. At least a portion of the harmonic filtering circuit may be disposed between the first surface of substrate S1 and the second surface of substrate S2, and the amplifier circuit 100 may be disposed on the first surface of substrate S2. In one embodiment, the amplifier 70 may optionally include a matching circuit (not shown) to implement the amplifier 20. The matching circuit may be disposed together with the amplifier circuit 100 on the first surface of substrate S2, and its operation and function are as described above, and will not be repeated here. For ease of explanation, the harmonic filtering circuit is drawn with solid lines, while other components are drawn with dashed lines.

[0071] according to Figure 7a and Figure 7b The amplifier of the present invention can be implemented inside a single package or on a multilayer substrate to reduce the size of its circuit layout area or volume, and further reduce the interference experienced by the circuit.

[0072] Figure 8a This is a schematic diagram of the power performance of a power amplifier using a λ / 4 transmission line in the prior art. Figure 8b This is a schematic diagram illustrating the power performance of the amplifier 10 with a harmonic filter circuit 110 in an embodiment of the present invention. Figure 8a and Figure 8b In the diagram, the horizontal axis represents frequency, and the vertical axis represents the power of the forward transmission parameter S21. The unit of frequency is GHz (GHz), and the unit of power of the forward transmission parameter S21 is dB (decibels). In this embodiment, a fundamental frequency of 5.5 GHz (i.e., f0 = 5.5 GHz) is used as an example. It should be noted that this invention can be applied to fundamental frequencies of any frequency, and is not limited thereto. In the case of the second harmonic (2f0), according to... Figure 8a In the 10GHz–12GHz frequency band, the signal exhibits better power filtering performance. Conversely, according to... Figure 8bIn the 9GHz–13GHz frequency band, the signal exhibits good power filtering performance. However, in the case of the third harmonic (3f0), the λ / 4 transmission line cannot filter the third harmonic. Therefore, power amplifiers using λ / 4 transmission lines have poor power filtering performance in the 3f0 frequency band and its adjacent bands. Figure 8a As shown at point 3f0. Relatively speaking, according to... Figure 8b The amplifier provided in this embodiment of the invention can still have good power filtering effect in the 3f0 frequency band and its adjacent frequency bands. Therefore, compared with the prior art, the amplifier 10 or 20 provided in this invention can have a larger signal bandwidth.

[0073] Figure 9 This is a comparison chart of the RF output power of a power amplifier that uses only an RF choke for filtering and an amplifier 10 or 20 with a harmonic filtering circuit 110 in this embodiment of the invention, under different RF input power conditions. Figure 9In this embodiment, the units for RF input power and RF output power are decibels per milliwatt (dBm). The power amplifier primarily using an RF choke for filtering has the same input signal as amplifier 10 or 20, and both have the same fundamental, second, and third harmonics in their amplified input signals. Simulation curve 90 represents the fundamental RF output power of amplifier 10 or 20 in this embodiment, and simulation curve 91 represents the fundamental RF output power of the power amplifier primarily using an RF choke for filtering. Simulation curve 92 represents the second harmonic RF output power of amplifier 10 or 20 in this embodiment, and simulation curve 93 represents the second harmonic RF output power of the power amplifier primarily using an RF choke for filtering. Simulation curve 94 represents the third harmonic RF output power of amplifier 10 or 20 in this embodiment, and simulation curve 95 represents the third harmonic RF output power of the power amplifier primarily using an RF choke for filtering. In detail, regarding the fundamental frequency, simulation curves 90 and 91 nearly overlap, indicating that the power amplifier primarily using an RF choke for filtering has a similar RF output power to amplifier 10 or 20 of the present invention. However, regarding the second harmonic, simulation curve 92 has a lower RF output power compared to simulation curve 93. That is, by filtering the second harmonic, amplifier 10 or 20 of the present invention can reduce the additional power generated by the second harmonic. Next, regarding the third harmonic, simulation curve 94 also has a lower RF output power compared to simulation curve 95. Therefore, amplifier 10 or 20 of the present invention can also reduce the additional power generated by the third harmonic. In summary, amplifier 10 or 20 provided by the present invention can reduce signal distortion caused by the aforementioned harmonics. When the second and third harmonics can be filtered, amplifier 10 or 20 provided by the present invention can reduce power loss. Therefore, amplifier 10 or 20 provided by the present invention can have lower intermodulation distortion (IMD).

[0074] In summary, this invention provides an amplifier for processing and filtering the second and third harmonics generated when an input signal passes through the amplifier. Therefore, the amplifier with harmonic filtering circuitry can have a larger signal bandwidth. Furthermore, this invention can reduce the area or volume of the circuitry, thereby reducing interference to the harmonic filtering circuitry and further improving the amplifier's performance and efficiency.

[0075] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention.

Claims

1. An amplifier, characterized in that, Includes: A signal input terminal, used to input an input signal; A voltage input terminal is used to input a power supply voltage; An amplifier circuit is used to generate an amplified input signal based on the input signal, and the amplified input signal has a fundamental wave, a first harmonic and a second harmonic, wherein the first harmonic is the first and second harmonic of the fundamental wave, and the second harmonic is the first and third harmonic of the fundamental wave. A harmonic filter circuit is coupled between the voltage input terminal and the amplifier circuit to filter the first harmonic and the second harmonic; the harmonic filter circuit includes a resonant circuit, which includes: A first terminal, coupled to the voltage input terminal; and A second terminal is coupled to the amplifier circuit, wherein the first harmonic and the second harmonic have a first impedance value and a second impedance value in the resonant circuit that are less than the third impedance value of the fundamental wave in the resonant circuit; and A bypass capacitor circuit includes: A first terminal, coupled to the voltage input terminal; and A second terminal is coupled to a reference voltage terminal, wherein the first harmonic and the second harmonic have a fourth impedance value and a fifth impedance value in the bypass capacitor circuit that are less than the fundamental wave has a sixth impedance value in the bypass capacitor circuit. as well as A signal output terminal is coupled to the harmonic filter circuit to output an output signal based on the amplified input signal.

2. The amplifier as claimed in claim 1, characterized in that, The bypass capacitor circuit also includes: A first bypass capacitor, wherein the seventh impedance value of the first harmonic at the first bypass capacitor is less than the eighth impedance value of the fundamental frequency at the first bypass capacitor; and A second bypass capacitor is connected in parallel with the first bypass capacitor, wherein the ninth impedance value of the second harmonic in the second bypass capacitor is less than the tenth impedance value of the fundamental wave in the second bypass capacitor.

3. The amplifier as claimed in claim 1, characterized in that, The resonant circuit further includes: An inductor-capacitor parallel circuit includes at least one first capacitor and at least one first inductor, wherein the at least one first capacitor and the at least one first inductor are connected in parallel, and the inductor-capacitor parallel circuit is coupled between the first terminal of the resonant circuit and the second terminal of the resonant circuit.

4. The amplifier as described in claim 3, characterized in that, The resonant circuit further includes: A second inductor is coupled between the inductor-capacitor parallel circuit and the first terminal of the resonant circuit; and A second capacitor, comprising: A first terminal is coupled between the second terminal of the inductor-capacitor parallel circuit and the resonant circuit; and The second terminal is coupled to the reference voltage terminal.

5. The amplifier as described in claim 4, characterized in that, The at least one first capacitor, the at least one first inductor, the second inductor, and the second capacitor are all composed of at least one microstrip line.

6. The amplifier as claimed in claim 5, characterized in that, The amplifier also includes: A first substrate has a first surface and a second surface, wherein the at least one first capacitor, the at least one first inductor, the first terminal of the second capacitor and the second inductor are disposed on the first surface of the first substrate.

7. The amplifier as claimed in claim 6, characterized in that, The second terminal of the second capacitor is disposed on the second surface of the first substrate.

8. The amplifier as claimed in claim 7, characterized in that, The second capacitor is an open-circuit residual capacitor generated according to a parasitic effect.

9. The amplifier as claimed in claim 6, characterized in that, The at least one first capacitor is at least one edge capacitor.

10. The amplifier as claimed in claim 6, characterized in that, The amplifier circuit and the harmonic filter circuit are housed together on a frame inside a package.

11. The amplifier as claimed in claim 6, characterized in that, The amplifier further includes a second substrate layer, which is disposed between the amplifier circuit and the first substrate layer.

12. The amplifier as claimed in claim 4, characterized in that, The resonant circuit further includes: A third inductor is coupled between the second capacitor and the second terminal of the resonant circuit.

13. The amplifier as claimed in claim 12, characterized in that, The third inductor is a multi-strand wire.

14. The amplifier as claimed in claim 1, characterized in that, The amplifier circuit further includes a plurality of amplifier stages, and the harmonic filter circuit is coupled between the voltage input terminal and the last amplifier stage of the plurality of amplifier stages.

15. The amplifier as claimed in claim 1, characterized in that, The amplifier also includes: A matching circuit, coupled to the amplifier circuit and the signal output terminal, is used to provide an output impedance match for the amplifier.

16. A harmonic filter circuit, characterized in that, Includes: A resonant circuit includes: A first terminal is coupled to a voltage input terminal; and A second terminal is used to receive an input signal, wherein the input signal has a fundamental frequency, a first harmonic, and a second harmonic, and the first harmonic and the second harmonic have a first impedance value and a second impedance value in the resonant circuit that are smaller than the third impedance value of the fundamental frequency in the resonant circuit; and A bypass capacitor circuit includes: A first terminal, coupled to the voltage input terminal; and A second terminal is coupled to a reference voltage terminal, wherein the first harmonic and the second harmonic have a fourth impedance value and a fifth impedance value in the bypass capacitor circuit that are less than the fundamental wave has a sixth impedance value in the bypass capacitor circuit.

17. The harmonic filter circuit as described in claim 16, characterized in that, The bypass capacitor circuit also includes: A first bypass capacitor, wherein the seventh impedance value of the first harmonic at the first bypass capacitor is less than the eighth impedance value of the fundamental frequency at the first bypass capacitor; and A second bypass capacitor is connected in parallel with the first bypass capacitor, wherein the ninth impedance value of the second harmonic in the second bypass capacitor is less than the tenth impedance value of the fundamental wave in the second bypass capacitor.

18. The harmonic filter circuit as described in claim 16, characterized in that, The resonant circuit further includes: An inductor-capacitor parallel circuit includes at least one first capacitor and at least one first inductor, wherein the at least one first capacitor and the at least one first inductor are connected in parallel, and the inductor-capacitor parallel circuit is coupled between the first terminal of the resonant circuit and the second terminal of the resonant circuit.

19. The harmonic filter circuit as described in claim 18, characterized in that, The resonant circuit further includes: A second inductor is coupled between the inductor-capacitor parallel circuit and the first terminal of the resonant circuit; and A second capacitor, comprising: A first terminal is coupled between the second terminal of the inductor-capacitor parallel circuit and the resonant circuit; and The second terminal is coupled to the reference voltage terminal.

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