Security defense method, coprocessor and processing device

Abstract

The present disclosure provides a security defense method, a coprocessor and a processing device. The security defense method is used for the coprocessor, and includes: receiving a jump destination encryption request for an operation task; performing first mask processing on a first jump destination address value using a mask configuration, removing data bits in the first jump destination address value that meet a first mode, and obtaining a first intermediate jump destination address value; performing verification operation based on the first jump destination storage address, a key reference value corresponding to the operation task and the first intermediate jump destination address value, and obtaining a first encryption result value; performing second mask processing on the first encryption result value using the mask configuration, and obtaining a first intermediate encryption result value; and performing verification operation on the first intermediate encryption result value and the first jump destination address value, and obtaining a first encrypted jump destination address value. The security defense method can be used to defend against buffer overflow attacks and the like.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a security defense method, a coprocessor, and a processing device. Background Technology

[0002] One of the most common vulnerabilities affecting computer system security in recent years is buffer overflow attacks. A successful buffer overflow attack can modify the control flow of a computer system. For example, it can modify the program's return address, the EBP of a function call, or modify function pointers and the GOT table, thereby redirecting the program to the attacker's pre-set malicious code to execute malicious code and cause the entire program to crash. Alternatively, it can allow the attacker to gain partial control of the system, causing a security crisis for the entire computer system. Therefore, defending against buffer overflow attacks is of extremely important practical significance.

[0003] In general, buffer overflow attacks can be divided into two modes: (i) directly tampering with critical program data such as EIP; (ii) indirectly tampering with critical data such as EBP and EIP by modifying pointer variables through buffer overflows.

[0004] To mitigate the threat of memory safety violations, several techniques have been proposed. One such technique is the ASLR mechanism, which increases the difficulty for attackers to jump to specific memory locations by adding a random offset before the starting address of memory segments such as the stack and heap where critical data is stored during program address space initialization. Another example is the DEP mechanism, which implements the W⊕X principle for addresses: writable addresses are not executable, and executable addresses are not writable. This mechanism prevents attackers from executing injected malicious program segments by setting flags in the address space of data segments to non-executable. Once the system fetches instructions from these address spaces, the CPU will report a memory violation exception, thereby killing the process. The stack space is also set to non-executable by the operating system, thus preventing ordinary shellcode injection.

[0005] The two prevention mechanisms mentioned above provide good protection for the operation of programs in computer systems to a certain extent. However, they are not very effective against more complex attack methods. For example, regarding ASLR protection, randomization only randomizes the library function loading address each time, while the relative addresses between library functions remain unchanged. Therefore, attackers can leak library function addresses through the GOT table and thus deduce the addresses of other functions in the running program. For example, regarding DEP protection, attackers can use dynamic link libraries or existing code segments in the program to construct return addresses and data in the stack to implement Ret2libc attacks.

[0006] Stack Canary was later proposed as a more effective prevention mechanism. The Stack Canary mechanism inserts a Canary Word between the buffer and the return address. When the buffer overflows, the Canary Word is overwritten before the return address is overwritten. By checking whether the Canary Word value has been modified, it can be determined whether an overflow attack has occurred. However, if the Canary Word value is inserted at the end of the buffer, some system functions allow writing to the Canary Word value, making overflow attacks still possible. Summary of the Invention

[0007] To address the issue of buffer overflow attacks, several embodiments of this disclosure provide a security defense method, a coprocessor, and a processing device.

[0008] At least one embodiment of this disclosure provides a security defense method for an operation task, used by a coprocessor, comprising: receiving a jump destination encryption request for the operation task, wherein the jump destination encryption request includes information for obtaining a first jump destination storage address and a first jump destination address value corresponding to the operation task; using a mask configuration, performing a first mask processing on the first jump destination address value to remove data bits conforming to a first pattern from the first jump destination address value to obtain a first intermediate jump destination address value; performing a verification operation based on the first jump destination storage address, a key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain a first encryption result value; using the mask configuration, performing a second mask processing on the first encryption result value to retain data bits conforming to the first pattern from the first encryption result value to obtain a first intermediate encryption result value; performing a verification operation on the first intermediate encryption result value and the first jump destination address value to obtain a first encrypted jump destination address value, and returning the first encrypted jump destination address value.

[0009] At least one embodiment of this disclosure provides a coprocessor for security defense of operational tasks, including: a decoder, a key register, a verification module, and a control module. The decoder is configured to decode operation instructions input to the coprocessor, wherein the operation instructions include a jump destination encryption instruction, wherein the jump destination encryption instruction includes information for obtaining a first jump destination storage address and a first jump destination address value corresponding to the operation task; the key register is configured to store a key reference value corresponding to the operation task; the control module is configured to use a mask configuration to perform a first masking process on the first jump destination address value, removing data bits that conform to a first pattern from the first jump destination address value to obtain a first intermediate jump destination address value; the verification module is configured to perform a verification operation based on the first jump destination storage address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain a first encryption result value; the control module is further configured to use the mask configuration to perform a second masking process on the first encryption result value, retaining data bits that conform to the first pattern from the first encryption result value to obtain a first intermediate encryption result value, perform a verification operation between the first intermediate encryption result value and the first jump destination address value to obtain a first encrypted jump destination address value, and return the first encrypted jump destination address value.

[0010] At least one embodiment of this disclosure provides a processing apparatus comprising: the aforementioned coprocessor and a main processor communicating with the coprocessor, wherein the main processor is configured to run the operation task and send the operation instructions to the coprocessor. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0012] Figure 1 A schematic diagram of a processing apparatus and its coprocessor provided according to at least one embodiment of the present disclosure is shown.

[0013] Figure 2A A schematic diagram showing at least a partial format of operating instructions according to at least one embodiment of the present disclosure is shown.

[0014] Figure 2B A schematic diagram showing an example of operating instructions according to at least one embodiment of the present disclosure is provided.

[0015] Figure 3 An example is shown of a reference address according to at least one embodiment of the present disclosure, which includes the base address's useless high bits and a portion of the valid high bits.

[0016] Figure 4A An example of encryption operation in a security defense method according to at least one embodiment of the present disclosure is shown.

[0017] Figure 4B An example of a verification / decryption operation in a security defense method according to at least one embodiment of the present disclosure is shown.

[0018] Figure 4C The verification / decryption operation in a security defense method according to at least one embodiment of the present disclosure is shown relative to... Figure 4A and Figure 4B Examples of variations.

[0019] Figure 5 A block diagram of a security defense method executed on a main processor according to at least one embodiment of the present disclosure is shown.

[0020] Figure 6 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0022] Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described objects changes.

[0023] At least one embodiment of this disclosure provides a security defense method and processing device for computer buffer overflow security issues using hardware co-processing, as well as a coprocessor included in the processing device. This method and processing device can mitigate the threat of computer buffer overflows. Compared with software-based pointer encryption designs, this security defense method and processing device, by using a coprocessor to assist in encryption and verification (decryption), can effectively avoid reduced system operating efficiency and does not generate additional memory overhead. While significantly improving security, the system performance loss is not significant, and it can efficiently solve the security defense problem of computer buffer overflows.

[0024] Figure 1 A processing apparatus and its included coprocessor are shown according to at least one embodiment of the present disclosure. Figure 1 As shown, the processing device 10 includes one or more main processors (or main processor cores) 100 and one or more coprocessors (or coprocessor cores) 200. The main processor 100 includes a communication interface 110 and communicates with the coprocessor 200 through the communication interface 110. The main processor 100 is configured to run at least one computer program, resulting in a process corresponding to the computer program. This process may include, for example, multiple parallel threads. During the execution of the computer program, the process or one of its threads may send operation instructions to the coprocessor 200 to configure the coprocessor 200 or invoke the coprocessor 200 to implement security defense functions. The computer program includes system programs and / or application programs, such as an operating system. This processing device, through coprocessor-assisted encryption and decryption, can efficiently solve the security defense problem of computer buffer overflows.

[0025] In this disclosure, the term "operation task" is used to refer to a process or thread. Here, a process describes the execution of a computer program; the operating system allocates independent address space and other resources to each process. A thread belongs to a process and executes within that process's address space. Within the operating system, multiple processes can execute in parallel and alternately. For each process, a Process Control Block (PCB) is created and maintained to describe the current state of the process and information controlling its execution. For the same process, multiple threads can execute in parallel and alternately. For each thread, a Thread Control Block (TCB) is created and maintained to describe the current state of the thread and information controlling its execution. The resource allocation information for these threads is already recorded in the PCB of their respective process (i.e., the thread's PCB is the same as the process's PCB), therefore the content of the TCB is less than that of the corresponding PCB. In the embodiments of this disclosure, there are instances of instruction sequence jumps or the use of function pointers during the execution of a process or thread.

[0026] like Figure 1As shown, in at least one embodiment, the coprocessor 200 for security defense of operational tasks includes a control module 201, a decoder 202, a verification module 203, and a key register 204.

[0027] Within the coprocessor 200, the control module 201 issues various operation control signals according to the operations to be performed as indicated by the operation instructions, thereby controlling the controlled object to execute the instructions. The control module 201 is communicatively connected to other components to provide operation control signals.

[0028] The decoder 202 is used to parse the operation instructions received by the coprocessor 200, determine what the operation code of the operation instruction is, and determine the nature and method of the operation. Thus, the control module 201 can issue various operation control signals (according to a certain timing sequence).

[0029] For example, the verification module 203 can employ an encryption algorithm or a verification algorithm, such as a symmetric encryption algorithm or a Message Authentication Code (MAC) algorithm, for both encryption and verification operations. The sender and receiver use the same key and the same algorithm to perform calculations on the received message to be encrypted and compare the results for verification.

[0030] When the verification module 203 is configured to use an encryption algorithm, it performs an encryption operation on the received message to be encrypted (plaintext) to obtain encrypted information (ciphertext). For example, the encryption module 203 is configured to perform an encryption operation on the message to be encrypted (plaintext) based on the received key and the message to be encrypted (plaintext) to obtain encrypted information (ciphertext). The obtained ciphertext can be used for subsequent decryption or verification operations. For example, in an embodiment of this disclosure, the message to be encrypted is a jump destination address value.

[0031] For example, the encryption module can employ a symmetric encryption algorithm, such as DES (Data Encryption Standard). In other words, the verification module could be a DES encryption module. The DES encryption algorithm is symmetric, using the same key for both encryption and decryption. The DES encryption module uses the same key for both encryption and decryption, employing block ciphers to encrypt plaintext in 64-bit blocks. The resulting data is then concatenated bit by bit to form the final ciphertext. The DES block size is, for example, 64 bits. If the length of the encrypted data is not a multiple of 64 bits, padding bits can be added according to a specific rule.

[0032] For example, when verification module 203 is configured to use a verification algorithm, it uses a key pair to perform a Message Authentication Code (MAC) algorithm operation on the received message to be encrypted (original message) to generate a MAC value. In this case, verification module 203 can be a MAC module. For example, the obtained MAC value is transmitted along with the original message. The receiver uses the same key and the same algorithm to generate a new MAC value, and then compares them. If the two MAC values ​​are the same, the MAC verification is successful; otherwise, the verification fails. For example, the MAC algorithm can be an HMAC (Hash-based Message Authentication Code) algorithm, which uses a hash algorithm as the encryption primitive.

[0033] Key register 204 is configured to store a key reference value and provide this key reference value for generating the key required by the verification module during the encryption or verification process. This key reference value is, for example, a random number, which may be obtained from the main processor 100 or generated locally within the coprocessor 200. An example of generating the key reference value locally within the coprocessor 200 is as follows: Figure 1 As shown, the coprocessor 200 may further include a random number generation module 207, which is configured to generate random numbers. For example, various available algorithms or principles can be used to generate the required random numbers. The number of bits of the obtained random numbers can be, for example, 64 bits, 128 bits, etc. The embodiments of this disclosure do not limit this.

[0034] As described below, a key reference value is one-to-one with a process running on the main processor (e.g., it is bound to a program) and is used to identify that process. For example, the key reference value corresponding to a program is randomly assigned each time the program is loaded into the system and run as a process, for example, stored in the process's PCB.

[0035] In at least another embodiment, the coprocessor 200 may further include a reference address register 205 for storing a reference address corresponding to the operation task, which is used to recover the return destination address during the decryption and verification phase (see the following description for details).

[0036] In at least another embodiment, the coprocessor 200 may further include a mask register 206 for storing a mask configuration, which is, for example, a binary value consisting of multiple bits corresponding to a certain mode (here referred to as "the first mode"). For example, a bit of 1 in the binary value of the mask configuration indicates that the corresponding bit in the processed binary value will be retained; conversely, a bit of 0 in the binary value of the mask configuration indicates that the corresponding bit in the processed binary value will be set to zero. The corresponding mask operation is, for example, an AND operation. For example, if the mask configuration is 8 bits (10100000) and the processed binary value is also 8 bits, then after performing a mask operation using the mask configuration, the 7th and 5th bits of the processed binary value will be retained, while the remaining bits will be set to zero. As another example, if the mask configuration is 32 bits (FF000000) and the processed binary value is also 32 bits, then after performing a mask operation using the mask configuration, the high 8 bits of the processed binary value will be retained, while the remaining bits will be set to zero.

[0037] For example, the values ​​of mask register 206 and reference address register 205 can only be modified by the MSET and BSET instructions related to data operations.

[0038] Communication interface 110 is used to handle communication between main processor 100 and coprocessor 200. This communication interface 110 may be, for example, a device or module independent of main processor 100 and coprocessor 200, communicating with both main processor 100 and coprocessor 200 respectively; or, this communication interface 110 may be, for example, part of main processor 100, communicating with other components or parts within processing device 10, including coprocessor 200. This communication interface 110 may be constructed according to a certain communication protocol, and may include one or more buffers to buffer one or more transmitted messages.

[0039] In addition to conventional value fetching units, decoding units, execution units, at least a level 1 cache, and a memory management unit (MMU), the main processor also maintains a process control block (PCB) corresponding to the process of a program during its execution. The PCB is a unique identifier of the existence of the corresponding process, and the system controls and schedules the process through the PCB.

[0040] During operation, the program (process) running on the main processor 100 operates the coprocessor 200 through at least one operation instruction. Figure 2A A schematic diagram showing at least a partial format of operating instructions according to at least one embodiment of the present disclosure is illustrated. Figure 2A As shown, this operation instruction may include the following fields / bits:

[0041] ● The opcode field indicates the operation that the instruction will perform;

[0042] ● Destination register (rd) field;

[0043] • The source register (rs) field may include one or more source registers as needed, such as a first source register (rs1) or a second source register (rs2);

[0044] • The register occupancy status field includes multiple bits, which correspond to the destination register and the source register (one or more). For example, in the case where the aforementioned registers rs1, rs2, and rd are present, the field includes three bits: xs1, xs2, and xd. The xs1 bit indicates whether the first source register is occupied, the xs2 bit indicates whether the coprocessor occupies the second source register, and the xd bit indicates whether the destination register is occupied, etc.

[0045] The size and order of the fields in this operation instruction can be changed accordingly based on different instruction sets, and the embodiments disclosed herein do not impose any limitations on this.

[0046] In at least one embodiment of this disclosure, six exemplary operation instructions are defined in the format above, thereby enabling control of the coprocessor to perform security defense operations to address the security defense problem of computer buffer overflows.

[0047] like Figure 1 As shown, the main processor 100 sends operation instructions (cmd) to the coprocessor 200 through the communication interface 110, and sends the values ​​of relevant registers (source register rs1 and / or source register rs2) to the coprocessor 200 according to the operation instructions sent to the coprocessor 200; the coprocessor 200 returns the operation result (including the register number of the destination register rd and the return value) to the main processor 100 through the communication interface 110. For example, the communication interface 110 can also mark the status of the coprocessor 200 (e.g., busy, idle, etc.), which the main processor 100 can read; for another example, the communication interface 110 can also have functions such as accessing the memory on the main processor 100 side and triggering interrupts as needed.

[0048] For example, the “jump destination memory address” described below can be the memory address of the current program address (the value of the program counter) saved before the program jumps when it calls a function, while the “jump destination address value” is the address value (i.e., the value of the program counter) stored at that memory address; as another example, the “jump destination memory address” can be the memory address of the function pointer value (i.e., the pointer address) when the program creates a function pointer, while the “jump destination address value” is the address value (i.e., the pointer value) stored at that memory address.

[0049] These operational instructions include:

[0050] Instruction 0 (INSTRUCTION_0): Key reference value loading instruction. For example, when the corresponding process starts working or during process intrusion, this instruction instructs the coprocessor to load the value (key reference value) stored in the first source register specified by the rs1 field of this instruction into the coprocessor's key register. Alternatively, this instruction instructs the coprocessor to generate a key reference value and store it in the coprocessor's key register. For example, before executing instruction 0, the key reference value is copied from the process control block (PCB) corresponding to the process to the first source register on the main processor side.

[0051] Instruction 1 (INSTRUCTION_1): Key reference value storage instruction. For example, when the corresponding process of the program is switched out or ends, this instruction is used to instruct the coprocessor to retrieve the key reference value stored in the key register and store it in the destination register specified by the rd field of the instruction. Thus, for example, the key reference value can be further stored in the process control block (PCB) on the main processor corresponding to the operation task (e.g., process or thread) and securely saved along with other critical information of the program.

[0052] The key reference value corresponds one-to-one with the program, and the key reference value stored in the coprocessor's key register at each moment is unique, thereby further improving security by using the key reference value.

[0053] Instruction 2 (INSTRUCTION_2): Mask configuration instruction. For example, when the corresponding process of the program starts working, this instruction is used to instruct the coprocessor to load the value stored in the first source register specified by the rs1 field of this instruction into the mask register to provide mask configuration. The mask configuration is used to specify which bits in the input jump destination address value will be used as the location of the verification value according to a certain pattern (first pattern). For example, the first pattern specifies that the high m bits of the jump destination address value (address value) are used to store the verification value, or n bits selected from the high m bits (e.g., odd bits or even bits) are used to store the verification value.

[0054] In some embodiments, the mask configuration is embedded in the coprocessor, in which case the coprocessor may not include a mask register, and correspondingly, the mask configuration instruction is not required.

[0055] Instruction 3: Reference address configuration instruction. For example, during the operation of the process corresponding to the program, such as at the start of operation, this instruction is used to instruct the coprocessor to load the value (reference address value) stored in the first source register specified by the rs1 field of this instruction into the coprocessor's reference address register. This is used to restore the jump destination address value (address value) after successful verification. For example, before executing instruction 3, the reference address value is copied from the process control block (PCB) corresponding to the process to the first source register on the main processor side.

[0056] For example, reference addresses used by different programs may differ from one another. This reference address could be the base address of a virtual address or the base address of a physical address within the address space allocated to the corresponding program (process) in the operating system, or a portion of that base address (e.g., a portion of its high-order bits). In a computer system, each virtual address consists of a virtual base address plus an offset value; similarly, each physical address consists of a physical base address plus an offset value. Typically, the operating system allocates different, non-overlapping address spaces to different processes, thus the base addresses of different processes are different. On the other hand, multiple threads belonging to the same process can have the same base address.

[0057] In at least some embodiments of this disclosure, the mask configuration and the reference address are used in conjunction with each other. For example, the mask configuration is used to process only the portion (bits) of the address corresponding to the reference address. For example, the mask configuration may be used to extract the base address portion of the address (i.e., set the offset portion to zero while leaving the base address portion unchanged) or remove the base address portion (i.e., set the base address portion to zero while leaving the offset portion unchanged).

[0058] For example, in a 64-bit architecture, the bit width is 64 bits; however, virtual addresses in computer systems typically do not use all 64 bits. For instance, virtual addresses in the RISC-V instruction set currently typically use three paging modes: sv32, sv39, and sv48. Therefore, the base address of the system's virtual address contains unused bits in the high-order bits (e.g., these unused bits are all 0). Thus, in at least one embodiment of this disclosure, only these unused high-order bits in the base address are used to store the verification value (verification code), or a portion of the valid high-order bits of the base address value can also be used to store the verification value (verification code). In the example where only the unused high-order bits are used, since the valid bits of the base address value are not modified, it is not necessary to consider the corresponding base address value used to restore the jump destination address value. For example, in a 32-bit architecture, the bit width is 32 bits. In this case, the system mostly uses physical addresses. Since system memory (or the address space allocated to processes) is usually relatively small (e.g., less than 4GB, e.g., 1GB), some useless high-order bits may still exist in the base address of the physical address. On the other hand, for a program, the valid high-order bits of the base address value usually do not change within the program's allocated address space. For example, when using a 4-level page table, the 0th and 1st level page tables may not change during program execution. Therefore, in at least one embodiment of this disclosure, the useless high-order bits of the base address and some or all of the valid high-order bits are used to store the verification value (verification code). In this case, it is necessary to consider the corresponding base address value used to recover the destination address. The base address value is maintained by the system (software) running on the main processor.

[0059] Figure 3 An example is shown where the reference address includes the base address's useless high bits and some of its valid high bits.

[0060] Instruction 4 (INSTRUCTION_4): Jump destination encryption instruction. The value stored in the first source register specified by the rs1 field of this instruction is the jump destination address value, such as the pointer to be encrypted; the value stored in the second source register specified by the rs2 field of this instruction is the jump destination memory address, such as the pointer address; the destination register specified by the rd field of this instruction is used to store the output encrypted jump destination address value.

[0061] Specifically, the value stored in the first source register specified by the rs1 field of the instruction (the jump destination address value, such as the pointer to be encrypted) is modified by removing a portion of the bits indicated by a predetermined mode (such as "first mode") according to the mask configuration to obtain a first intermediate value; a verification operation is performed based on the jump destination storage address, the key reference value corresponding to the current process or thread, and the first intermediate value to obtain an encrypted result value; the obtained encrypted result is modified by retaining the portion of the bits indicated by the aforementioned predetermined mode according to the mask configuration, and then a verification operation (such as an XOR operation) is performed with the jump destination address value to obtain an encrypted jump destination address value (such as an encrypted pointer), and then the encrypted jump destination address value is output to the destination register specified by the rd field of the instruction.

[0062] For example, in one instance, during the operation of the corresponding process or thread of the program, the above instruction is used to instruct the coprocessor to perform a calculation (e.g., XOR operation) on the value stored in the second source register specified by the rs2 field of the instruction with the key reference value in the key register to obtain the key; the first intermediate value is then input into the verification module as plaintext along with the above key for verification calculation to obtain the encrypted result value.

[0063] For example, in another example, during the operation of a process or thread, the above instruction is used to instruct the coprocessor to perform a calculation (e.g., XOR operation) on the value stored in the second source register specified by the rs2 field of the instruction (the jump destination memory address, such as a pointer address) with the first intermediate value to obtain the first intermediate calculation result value. The key is obtained from the key reference value in the key register. The first intermediate calculation result value is then used as plaintext and together with the above key is input into the verification module for verification calculation to obtain the encrypted result value.

[0064] Instruction 5 (INSTRUCTION_5): Jump destination verification instruction. The value stored in the second source register specified by the rs2 field of this instruction is the jump destination address, such as a pointer address; the value stored in the first source register specified by the rs1 field of this instruction is the encrypted jump destination address value, such as an encrypted pointer; the destination register specified by the rd field of this instruction is used to store the restored jump destination address value of the output.

[0065] Specifically, the value stored in the first source register specified by the rs1 field of the instruction (the encrypted jump destination address value, such as an encrypted pointer) is modified by removing a portion of the bits indicated by a predetermined mode (such as "first mode") according to the mask configuration to obtain a first intermediate value. A verification operation is then performed based on the jump destination storage address, the key reference value corresponding to the current process or thread, and the first intermediate value to obtain an encrypted result value. The obtained encrypted result is then modified according to the mask configuration, retaining the portion of the bits indicated by the aforementioned predetermined mode, to obtain a second intermediate value. This second intermediate value is then compared with the reference address value in the reference address register (such as an XOR operation) to obtain a third intermediate value for verification. If the third intermediate value is the same as the verification value (fourth intermediate value) included in the encrypted jump destination address value, the verification passes. If the verification passes, the restored (or decrypted) jump destination address value can be obtained using the reference address value and the encrypted jump destination address value. This restored jump destination address value is written into the destination register specified by the rd field of the instruction. Otherwise, an exception (alarm) is triggered, for example, by feeding back the exception information to the main processor. After retaining a portion of the bits indicated by the predetermined pattern according to the mask configuration of the encrypted jump destination address value, the aforementioned fourth intermediate value is obtained.

[0066] For example, in one instance, during the operation of the corresponding process or thread of the program, the above instruction is used to instruct the coprocessor to perform a calculation (e.g., XOR operation) on the value stored in the second source register specified by the rs2 field of the instruction with the key reference value in the key register to obtain the key; the first intermediate value is then input into the verification module as, for example, plaintext, together with the above key, for verification calculation to obtain the encrypted result value.

[0067] For example, in another example, during the process or the process's operation, the above instruction is used to instruct the coprocessor to perform a calculation (e.g., XOR operation) between the value stored in the second source register specified by the rs2 field of the instruction (the jump destination memory address, such as a pointer address) and the first intermediate value to obtain the first intermediate calculation result value. The key is obtained from the key reference value in the key register. The first intermediate calculation result value is then used as plaintext and together with the above key is input into the verification module for verification calculation to obtain the encrypted result value.

[0068] When the coprocessor receives one of the aforementioned operation instructions sent by the main processor, the coprocessor's decoder decodes the received operation instruction to determine the operation content of the instruction. The control module generates control signals based on the decoded operation content to perform the required operation. For example, it reads a value from a register of the main processor (e.g., the first source register or the second source register) and stores the read value in a processor of the coprocessor, or writes a value from the coprocessor to a register of the main processor (e.g., the destination register).

[0069] For example, at least the embodiments of this disclosure do not limit the specifications of the main processor 100, the coprocessor 200 and the communication interface 110. For example, the main processor 100 and the coprocessor 200 may be based on instruction set architectures such as x86, MIPS, ARM, RISC-V, etc., while the communication interface 110 is matched with the corresponding instruction set or architecture.

[0070] For example, in one embodiment, the main processor 100 and the coprocessor 200 are based on a RISC-V instruction set architecture. For instance, the main processor 100 may employ a Rocket core, a Boom core (e.g., a SonicBoom core), or a Freedom SOC core. For example, the communication interface 110 is a RoCC interface, and the communication protocol used by this RoCC interface is the DecoupledIO protocol defined in Chisel (Constructing Hardware in an Scala Embedded Language), a FIFO-based ready / valid protocol. Correspondingly, in this embodiment, the exemplary operation instructions used are as follows: Figure 2B As shown, this exemplary operation instruction conforms to the format requirements of custom instructions in the RISC-V standard, has 32 bits, and includes the following fields / bits:

[0071] The opcode field contains the opcode of the instruction.

[0072] The rd field is the destination register, located in the main processor;

[0073] ●The rs2 field is the second source register, located in the main processor;

[0074] ●The rs1 field is the first source register, located in the main processor;

[0075] The xs1 bit indicates whether the coprocessor reads the value from the first source register;

[0076] The xs2 bit indicates whether the coprocessor reads the value from the second source register;

[0077] The xd bit indicates whether the coprocessor writes back to the destination register;

[0078] The `funct7` field represents a 7-bit function code, which can be extended by the user to control the coprocessor to perform different operations.

[0079] Some embodiments of this disclosure also provide a security defense method based on the coprocessor or processing device of at least one of the above embodiments.

[0080] For example, in the processing apparatus of at least one embodiment of this disclosure, when compiling a program or loading and running a program, the source code or executable code of the program is analyzed to locate the code that needs to call a function and assign a value to the return address ra. Before the code that assigns the return address value (jump destination address value) ra, a jump destination encryption instruction for encrypting the return address value ra is inserted. When the process or thread corresponding to the program runs to this point, the coprocessor is called to encrypt the return address value and store it in the encrypted return address value at the corresponding storage address. Then, the code that uses the return address value ra is located, and a jump destination verification instruction for decrypting the encrypted return address value ra is inserted before the code that uses the jump destination address value ra. When the program runs to this point, the encrypted return address value is obtained from the corresponding storage address, and the coprocessor is called to verify the encrypted return address value. If the verification is successful, the required return address value ra is obtained from the coprocessor.

[0081] For example, in the processing apparatus of at least one embodiment of this disclosure, when compiling a program or loading and running a program, the source code or executable code of the program is analyzed to locate the code that creates a function pointer and assigns a function pointer value (jump destination address value) to the function pointer fp. Before the code that assigns a value to the function pointer fp, a jump destination encryption instruction for encrypting the function pointer value is inserted, so that when the process or thread corresponding to the program runs to this point, the coprocessor is called to encrypt the generated function pointer value and store the encrypted function pointer value at the corresponding storage address. Then, the code that uses the function pointer value fp is located, and a jump destination verification instruction for decrypting the encrypted function pointer value is inserted before the code that uses the function pointer value fp, so that when the program runs to this point, the encrypted function pointer value is obtained from the corresponding storage address, and then the coprocessor is called to verify the encrypted function pointer value. If the verification is successful, the required function pointer value fp is obtained from the coprocessor.

[0082] For example, in the processing apparatus of at least one embodiment of this disclosure, when compiling a program or loading and running a program, the source code or executable code of the program is analyzed, and a key reference value loading instruction is inserted at the beginning of the program. This causes the process or thread corresponding to the program to execute the key reference value loading instruction at this point, loading the key reference value corresponding to the program into the key register of the coprocessor. Alternatively, when the process corresponding to the operation task starts or switches out and then back in, the key reference value loading instruction is executed, causing the program to load the key reference value corresponding to the program into the key register of the coprocessor. For example, when starting to run a program, the key reference value loading instruction is executed to complete the initialization process.

[0083] For example, when the key reference value is obtained by calling a key reference value generation module (e.g., a random number generation module) in the system running on the main processor, the main processor generates the key reference value corresponding to the program before executing the key reference value loading instruction, stores the reference value in a register R1, modifies the rs1 register in the key reference value loading instruction to point to register R1, and then sends the key reference value loading instruction to the coprocessor for processing. The coprocessor can read the value of register R1. When the key reference value is generated in the coprocessor, the rs1 register in the key reference value loading instruction can be invalidated, and then the key reference value loading instruction can be sent to the coprocessor for processing. The coprocessor does not need to read the value from the main processor.

[0084] For example, in the processing apparatus of at least one embodiment of this disclosure, when a program is loaded and run, when the process corresponding to the program is switched out or terminated, the system can execute a key reference value storage instruction to read the key reference value corresponding to the program from the key register of the coprocessor and store it outside the coprocessor, such as in the process control block of the processor; or, when the program is terminated, the key reference value storage instruction is not executed, and the value of the key register of the coprocessor will subsequently overwrite the key reference value corresponding to the subsequent program.

[0085] For example, in the processing apparatus of at least one embodiment of this disclosure, when compiling a program or loading and running a program, the source code or executable code of the program is analyzed, and a mask configuration instruction is inserted at the beginning of the program, causing the program to load the mask configuration into the mask register of the coprocessor at this point. Alternatively, when the operating system running on the main processor starts, the mask configuration instruction is executed, causing the program to load the mask configuration into the mask register of the coprocessor at this point.

[0086] For example, in the processing apparatus of at least one embodiment of this disclosure, when compiling a program or running a program, the source code or executable code of the program is analyzed. For example, a reference address configuration instruction is inserted at the beginning of the program, causing the process or thread corresponding to the program to load the reference address into the reference address register of the coprocessor at this location. Alternatively, when the process corresponding to the program starts or switches out and then switches back in, the reference address configuration instruction is executed, causing the process or thread corresponding to the program to load the reference address into the reference address register of the coprocessor at this location. As described above, the reference address may only include the useless high-order bits of the base address of the virtual or physical address used by the system, or include part or all of the base address when there are no useless high-order bits, or include the useless high-order bits of the base address and some valid high-order bits.

[0087] A security defense method according to at least one embodiment of the present disclosure will be described, for example, the method of this embodiment is executed by a coprocessor.

[0088] First, let's illustrate the encryption operation with an example.

[0089] According to one embodiment of this disclosure, a coprocessor receives a jump destination encryption request for an operation task (e.g., a process or thread) of a program running on a main processor. The jump destination encryption request is sent from the main processor to the coprocessor as a jump destination encryption instruction. The jump destination encryption request includes information for obtaining a first jump destination memory address and a first jump destination address value corresponding to the program. For example, the first jump destination memory address and the first jump destination address value may be the memory address (return address) and return address value of the return address when the corresponding process or thread calls a function, or the memory address (pointer address) and function pointer value of a created function pointer.

[0090] Using mask configuration, the first jump destination address value is processed by the first mask, and the data bits that match the first pattern in the first jump destination address value are removed to obtain the first intermediate jump destination address value.

[0091] A verification operation is performed based on the first jump destination memory address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain the first encryption result value. For example, the key reference value is stored in the key reference value register in the coprocessor; in the case of threads, the key reference value corresponding to the thread is the same as the key reference value of the process to which the thread belongs.

[0092] Using a mask configuration, the first encrypted result value is processed by a second mask, and the data bits in the first encrypted result value that conform to the first pattern are retained to obtain the first intermediate encrypted result value.

[0093] The first intermediate encrypted result value is verified against the jump destination address value to obtain the first encrypted jump destination address value, which is then returned. For example, this can be used as a response to the jump destination encryption request.

[0094] For example, a verification operation is performed based on the first jump destination storage address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain the first encrypted result value, including the following cases:

[0095] For example, a first key is obtained using the first destination address and the key reference value corresponding to the operation task. Then, based on the first key, a verification operation is performed on the first intermediate destination address value to obtain a first encrypted result value. Alternatively, a first intermediate calculation result value is obtained using the first destination address and the first intermediate destination address value. Then, based on the key reference value corresponding to the operation task, a verification operation is performed on the first intermediate calculation result value to obtain a first encrypted result value.

[0096] Secondly, an example of the verification (decryption) operation is explained.

[0097] According to an example of the above embodiments of this disclosure, a coprocessor receives a jump destination verification request for an operational task (e.g., a process or thread) of a program running on a main processor. The jump destination verification request is sent from the main processor to the coprocessor as a jump destination verification instruction, wherein the jump destination verification request includes information for obtaining a second jump destination storage address and a second jump destination address value corresponding to the program. Here, the second jump destination value is an encrypted jump destination address value.

[0098] Using a mask configuration, the second jump destination address value is processed by the first mask, and the data bits that match the first pattern in the second jump destination address value are removed to obtain the second intermediate jump destination address value.

[0099] The second encryption result value is obtained by performing a verification operation based on the second jump destination memory address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value. Similarly, for example, the key reference value is stored in the key reference value register in the coprocessor; in the case of threads, the key reference value corresponding to the thread is the same as the key reference value of the process to which the thread belongs.

[0100] Using a mask configuration, the second encrypted result value is processed with a second mask, retaining the data bits in the second encrypted result value that conform to the first mode, to obtain the second intermediate encrypted result value.

[0101] The second intermediate encrypted result value is compared with the pre-stored reference address corresponding to the operation task and conforming to the first mode to perform message verification operation, thereby obtaining the third encrypted intermediate result value.

[0102] Using a mask configuration, the second jump destination address value is processed by a third mask, while retaining the data bits of the second jump destination address value that conform to the first pattern, to obtain the fourth encrypted intermediate result value.

[0103] The third and fourth encrypted intermediate result values ​​are compared, and the result of this comparison is used to determine whether the verification passes or fails.

[0104] For example, a verification operation is performed based on the second jump destination storage address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value to obtain the second encrypted result value, including the following cases:

[0105] The second key is obtained by using the second jump destination storage address and the key reference value corresponding to the operation task. Then, based on the second key, the second intermediate jump destination address value is verified to obtain the second encrypted result value. Alternatively, the second intermediate calculation result value is obtained by using the second jump destination storage address and the second intermediate jump destination address value. Then, based on the key reference value corresponding to the operation task, the second intermediate calculation result value is verified to obtain the second encrypted result value.

[0106] According to an example of the embodiments of this disclosure, in addition to the encryption and verification (decryption) processes described above, the security defense method may further include, for example, obtaining a key reference value. For example, obtaining a key reference value includes: receiving a key reference value loading instruction when the process corresponding to the program starts or is switched on the main processor; obtaining the key reference value from outside the coprocessor or generating the key reference value within the coprocessor according to the key reference value loading instruction, and storing the key reference value.

[0107] According to an example of the above embodiments of this disclosure, for example, the security defense method further includes: retrieving and storing the key reference value outside the coprocessor. Retrieving and storing the key reference value outside the coprocessor includes: receiving a key reference value storage instruction when the process corresponding to the operation task is switched out on the main processor; and storing the key reference value stored in the coprocessor outside the coprocessor according to the key reference value storage instruction.

[0108] According to an example of the embodiments of this disclosure, for example, the security defense method further includes: receiving a mask configuration and storing the mask configuration within a coprocessor. Receiving the mask configuration and storing it within a coprocessor includes: receiving a mask configuration instruction when the process corresponding to the program starts on the main processor; and storing the mask configuration within the coprocessor according to the mask configuration instruction.

[0109] According to an example of the above embodiments of this disclosure, the security defense method further includes: saving a reference address corresponding to an operation task that conforms to a first mode. Saving the reference address corresponding to the operation task of the program includes: receiving a reference address configuration instruction before performing message verification operations; and saving the reference address corresponding to the operation task that conforms to the first mode within the coprocessor according to the reference address configuration instruction. For example, the first mode is a first number of high-order data bits, and the reference address is the base address for the first number of high-order data bits.

[0110] According to an example of the above embodiments of this disclosure, for example, in the above security defense method, the verification operation includes symmetric encryption operation or message verification code (MAC) algorithm. For example, the symmetric encryption operation includes DES encryption operation, and the message verification code algorithm includes hash-based message verification code (HMAC) algorithm.

[0111] According to an example of the above embodiments of this disclosure, for example, in the above security defense method, the verification operation includes an XOR operation.

[0112] According to an example of the above embodiments of this disclosure, for example, in the above security defense method, the first jump destination storage address is the program return address or the function pointer address, and the first jump destination address value is the program return address value or the function pointer address value.

[0113] According to an example of the above embodiments of this disclosure, for example, in the above security defense method, in response to successful verification, a pending jump destination address value corresponding to the program is returned based on the second intermediate jump destination address value.

[0114] According to an example of the above embodiments of the present disclosure, for example, in the above security defense method, returning the pending jump destination address value corresponding to the program based on the second intermediate jump destination address value includes: in response to the reference address being the base address corresponding to the program, combining the second intermediate jump destination address value and the reference address to obtain the pending jump destination address value.

[0115] According to the embodiments described above in this disclosure, for example, taking the first jump destination storage address and the first jump destination address value as the storage address (pointer address) and function pointer value of the created function pointer value, respectively, and taking the first mask configuration mode as corresponding to all base addresses in the processed address as an example, refer to... Figure 4A The following is an example illustrating the encryption operation in the above security defense method.

[0116] like Figure 4AAs shown, the function pointer value (address value) includes a base address and an offset value. The first mode of mask configuration is: the mask has the same width as the function pointer value, with the portion corresponding to the base address being 1 and the portion corresponding to the offset value being 0. After receiving the jump destination encryption instruction, the coprocessor obtains the function pointer value through the source register rs1 recorded in the instruction, obtains the function pointer address (p_addr) through the source register rs2 recorded in the instruction, obtains the saved mask configuration from the mask register, and obtains the saved key reference value (Key) from the key reference value register.

[0117] The mask is inverted to obtain a new mask ~Mask. The function pointer value is then subjected to an AND operation with the inverted mask ~Mask to obtain a first intermediate value. This first intermediate value, compared to the input function pointer value, has its base address portion removed (i.e., the base address portion is set to zero), retaining only the offset portion. The function pointer address is then subjected to an XOR operation with the key reference value to obtain the key. This key and the first intermediate value (e.g., plaintext) are then used by the verification module to perform a verification operation to obtain a second intermediate value. The second intermediate value is the ciphertext (MAC). The second intermediate value is ANDed with the mask to obtain the third intermediate value. Compared with the second intermediate value, the third intermediate value removes the part corresponding to the offset value, that is, only the high-order part of the ciphertext corresponding to the base address is retained. The third intermediate value is XORed with the input function pointer value to obtain the encrypted function pointer value. The encrypted function pointer value includes the verification value (MAC') part obtained by encryption and verification operations in the high-order part corresponding to the base address, as well as the offset value included in the original function pointer value.

[0118] According to the above embodiments of this disclosure, for example, taking the first jump destination storage address and the first jump destination address value as the storage address (pointer address) of the created function pointer value and the function pointer value respectively, and taking the mask configuration as the first mode corresponding to all base addresses in the processing address as an example, refer to... Figure 4B The following is an example illustrating the verification / decryption operation in the aforementioned security defense method.

[0119] like Figure 4BAs shown, similarly, the function pointer value (address value) includes a base address and an offset. The first mask configuration mode is: the mask has the same width as the function pointer value, with the portion corresponding to the base address being 1 and the portion corresponding to the offset being 0. The encrypted function pointer value includes the verification value (MAC') obtained by encryption and verification operations in the high-order part corresponding to the base address and the offset value (Offset) from the original function pointer value. After receiving the jump destination verification instruction, the coprocessor obtains the encrypted function pointer value through the source register rs1 recorded in the instruction, obtains the function pointer address (p_addr) through the source register rs2 recorded in the instruction, obtains the saved mask configuration from the mask register, obtains the saved key reference value (Key) from the key reference value register, and obtains the saved base address (Base) used as the reference address from the reference address register.

[0120] The mask is inverted to obtain a new mask ~Mask. The encrypted function pointer value is then ANDed with the inverted mask ~Mask to obtain a first intermediate value. This first intermediate value, compared to the input encrypted function pointer value, removes the verification value (MAC') and retains only the offset value. The function pointer address is then XORed with the key reference value to obtain the key. This key and the first intermediate value are then verified using the verification module to obtain a second intermediate value, which is the ciphertext (MAC). This second intermediate value is then ANDed with the mask ~Mask to obtain a third intermediate value. Compared to the second intermediate value, the part corresponding to the offset value is removed, that is, only the high-order part of the obtained ciphertext corresponding to the base address is retained; the third intermediate value is XORed with the base address to obtain the fourth intermediate value. The high-order part of the fourth intermediate value corresponding to the base address is the calculated verification value (MAC”). The calculated verification value (MAC”) is compared with the verification value (MAC’) in the encrypted function pointer value. If they are the same, the verification is successful; otherwise, an exception (Interrupt) is triggered. That is, the (encrypted) function pointer value used for verification has been modified and is no longer the encrypted function pointer value returned during encryption.

[0121] If the verification is successful, the decrypted function pointer value is obtained by combining the base address with the offset value in the input encrypted function pointer value, that is, by combining the base address with the first intermediate value. The decrypted function pointer is then returned to the main processor (i.e., written into the destination register rd).

[0122] To perform the above comparison, a fifth intermediate value can be obtained by performing an AND operation between the encrypted function pointer value and the mask. This fifth intermediate value, relative to the input encrypted function pointer value, removes the offset value and retains only the input verification value (MAC'). Comparing the fourth and fifth intermediate values ​​then achieves the comparison between the calculated verification value (MAC') and the input verification value (MAC').

[0123] Figure 4C It shows that for Figure 4A and Figure 4B The variation of the example shown is similar to Figure 4A and Figure 4B The difference between the examples shown is that the inputs to the validation operation used to obtain the validation value are different. For example... Figure 4C As shown, after performing a mask operation (AND operation) on the function pointer value and the inverted mask ~Mask to obtain a first intermediate value, this first intermediate value is then subjected to an XOR operation, for example, with the function pointer address (p_addr) to obtain a first intermediate result value. Using the key reference value as the key, this first intermediate result value is then verified using the verification module to obtain a second intermediate value, which is, for example, ciphertext (MAC). The remainder of this variant example is similar to... Figure 4A and Figure 4B The examples shown are the same, so they will not be repeated.

[0124] Some embodiments of this disclosure also provide a coprocessor for performing the above-described security defense methods.

[0125] According to at least one embodiment of this disclosure, for example referring to Figure 1 As shown, the provided coprocessor is used for program security defense and includes a decoder, key register, verification module and control module.

[0126] The decoder is configured to decode operation instructions of the input coprocessor, wherein the operation instructions include jump destination encryption instructions, wherein the jump destination encryption instructions include information for obtaining a first jump destination storage address and a first jump destination address value corresponding to the operation task.

[0127] The key register is configured to store a key reference value corresponding to the operation task.

[0128] The control module is configured to use a mask configuration to process the first jump destination address value with a first mask, remove the data bits that conform to the first pattern from the first jump destination address value, and obtain the first intermediate jump destination address value.

[0129] The verification module is configured to perform verification operations based on the first jump destination storage address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain the first encrypted result value.

[0130] Correspondingly, the control module is also configured to use a mask configuration to perform a second mask processing on the first encrypted result value, retain the data bits in the first encrypted result value that conform to the first mode, obtain a first intermediate encrypted result value, perform a verification operation between the first intermediate encrypted result value and the jump destination address value to obtain a first encrypted jump destination address value, and return the first encrypted jump destination address value, for example, as a response to the jump destination encryption request.

[0131] Based on the first jump destination storage address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value, a verification operation is performed to obtain the first encrypted result value, including the following cases:

[0132] For example, a first key is obtained using the first destination address and the key reference value corresponding to the operation task. Then, based on the first key, a verification operation is performed on the first intermediate destination address value to obtain a first encrypted result value. Alternatively, for example, a first intermediate calculation result value is obtained using the first destination address and the first intermediate destination address value. Then, based on the key reference value corresponding to the operation task, a verification operation is performed on the first intermediate calculation result value to obtain a first encrypted result value.

[0133] According to an example of the above embodiments of the present disclosure, for example, the coprocessor further includes a reference address register, wherein the reference address register is configured to store a base address corresponding to an operation task.

[0134] The operation instructions also include a jump destination verification instruction, which includes information for obtaining the second jump destination storage address and the second jump destination address value corresponding to the program. Correspondingly, the control module is also configured to use a mask configuration to perform a first masking process on the second jump destination address value, removing data bits that conform to the first pattern from the second jump destination address value to obtain a second intermediate jump destination address value. The verification module is also configured to perform a verification operation based on the second jump destination storage address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value to obtain a second encrypted result value. Correspondingly, the control module is also configured to: use mask configuration to perform second mask processing on the second encrypted result value, retain the data bits in the second encrypted result value that conform to the first mode, to obtain a second intermediate encrypted result value; perform message verification operation on the second intermediate encrypted result value and the pre-stored reference address corresponding to the operation task that conforms to the first mode, to obtain a third encrypted intermediate result value; use mask configuration to perform third mask processing on the second jump destination address value, retain the data bits in the second jump destination address value that conform to the first mode, to obtain a fourth encrypted intermediate result value; and compare the third encrypted intermediate result value and the fourth encrypted intermediate result value, wherein the result of the comparison is used to determine whether the verification passes or fails.

[0135] The verification operation is performed based on the second jump destination storage address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value to obtain the second encryption result value, including the following cases:

[0136] For example, a second key is obtained using the second destination address and the key reference value corresponding to the operation task. Then, based on the second key, a verification operation is performed on the second intermediate destination address value to obtain the second encrypted result value. Alternatively, for example, a second intermediate calculation result value is obtained using the second destination address and the second intermediate destination address value. Then, based on the key reference value corresponding to the operation task, a verification operation is performed on the second intermediate calculation result value to obtain the second encrypted result value.

[0137] According to an example of the above embodiments of the present disclosure, for example, the operation instructions further include reference address configuration instructions. Correspondingly, the control module is further configured to save a reference address corresponding to the operation task and conforming to the first mode within the coprocessor according to the reference address configuration instructions.

[0138] According to an example of the above embodiments of the present disclosure, for example, the first mode is a first number of high-order data bits, and the reference address is the base address for the first number of high-order data bits.

[0139] According to an example of the above embodiments of the present disclosure, for example, the coprocessor further includes a mask register, wherein the mask register is configured to store a mask configuration.

[0140] According to an example of the above embodiments of the present disclosure, for example, the operation instruction further includes a mask configuration instruction. Correspondingly, the control module is further configured to obtain a mask configuration according to the mask configuration instruction and store the mask configuration in a mask register.

[0141] According to an example of the above embodiments of the present disclosure, for example, the operation instructions further include a key reference value loading instruction. Correspondingly, the control module is further configured to obtain a key reference value from outside the coprocessor or generate a key reference value within the coprocessor according to the key reference value loading instruction, and store the key reference value in the key reference value register.

[0142] According to an example of the above embodiments of the present disclosure, for example, the coprocessor further includes a random number generation module configured to generate a key reference value within the coprocessor and then store the key reference value in a key register.

[0143] According to an example of the above embodiments of the present disclosure, for example, the operation instructions further include a key reference value storage instruction. Correspondingly, the control module is further configured to save the key reference value stored in the coprocessor to outside the coprocessor according to the key reference value storage instruction.

[0144] According to an example of the above embodiments of the present disclosure, for example, the control module is further configured to return a pending jump destination address value corresponding to the program based on the second intermediate jump destination address value in response to successful verification.

[0145] According to an example of the above embodiments of the present disclosure, for example, the control module is further configured to obtain a jump destination address value to be used by combining the second intermediate jump destination address value and the reference address in response to the reference address being the base address corresponding to the program.

[0146] According to an example of the above embodiments of this disclosure, for example, the verification module is a DES verification module or a message verification module.

[0147] Next, a security defense method according to at least one embodiment of the present disclosure will be described, for example, the method of this embodiment is executed by the main processor. Figure 5 A block diagram of a security defense method executed on a main processor according to at least one embodiment of the present disclosure is shown. Figure 5 As shown, when a program runs, it will perform operations such as loading key reference values, storing key reference values, mask configuration, reference address configuration, encrypting destination address values, and decrypting destination address values ​​as needed. Specific examples are described below.

[0148] According to one embodiment of this disclosure, the main processor runs a program. During the execution of the program, it sends a mask configuration instruction to the coprocessor to save the mask configuration in the mask register of the coprocessor. The mask configuration is used by the coprocessor to mask the received destination address value during the encryption or verification process. The main processor also sends a reference address configuration instruction corresponding to the program to the coprocessor to save a reference address in the reference address register of the coprocessor. The reference address is used by the coprocessor to obtain the decrypted destination address value corresponding to the program during the verification process.

[0149] According to an example of the above embodiments of the present disclosure, for example, the security defense method further includes: when the process corresponding to the operation task starts or is switched on the main processor, sending a key reference value loading instruction to the coprocessor to save the key reference value in the key reference value register of the coprocessor, wherein the key reference value is used by the coprocessor to generate a key during the encryption process or the verification process.

[0150] According to an example of the above embodiments of the present disclosure, for example, the key reference value loading instruction includes a source register in the main processor that stores the key reference value, such that the coprocessor reads the key reference value from the source register, or the key reference value loading instruction instructs the coprocessor to generate the key reference value.

[0151] According to an example of the above embodiments of the present disclosure, for example, the security defense method further includes: generating a key reference value in the main processor and storing the key reference value in a source register.

[0152] According to one example of the above embodiments of this disclosure, for example, the key reference value is a random number.

[0153] According to an example of the above embodiments of this disclosure, for example, the security defense method further includes: when the process corresponding to the operation task is switched out on the main processor, sending a key reference value storage instruction to the coprocessor; receiving and saving the key reference value returned by the coprocessor according to the key reference value storage instruction.

[0154] According to an example of the above embodiments of the present disclosure, for example, a key reference value is stored in a process control block (PCB) corresponding to an operation task.

[0155] According to an example of the above embodiments of this disclosure, for example, the reference address conforms to a first pattern defined by the mask configuration.

[0156] According to an example of the above embodiments of the present disclosure, for example, the first mode is a first number of high-order data bits, and the reference address is the base address for the first number of high-order data bits.

[0157] According to an example of the above embodiments of this disclosure, for example, the security defense method further includes: sending a jump destination encryption instruction to a coprocessor, wherein the jump destination encryption instruction includes information for obtaining a first jump destination storage address and a first jump destination address value corresponding to the program, and the coprocessor performs an encryption operation based on the mask configuration, the first jump destination storage address and the first jump destination address value to obtain a first encrypted jump destination address value; and receiving the first encrypted jump destination address value from the coprocessor.

[0158] According to an example of the above embodiments of this disclosure, for example, the first jump destination storage address is the program return address or the function pointer address, and the first jump destination address value is the program return address value or the function pointer address value.

[0159] According to an example of the above embodiments of this disclosure, for example, the security defense method further includes: sending a jump destination verification instruction to a coprocessor, wherein the jump destination verification instruction includes information for obtaining a second jump destination storage address and a second jump destination address value corresponding to the program, the second jump destination address value being an encrypted jump destination address value, and the coprocessor performing a verification operation based on a mask configuration, the second jump destination storage address, and the second jump destination address value; in response to successful verification, receiving a decrypted pending jump destination address value corresponding to the program from the coprocessor, or in response to unsuccessful verification, receiving exception information from the coprocessor, wherein the coprocessor obtains the pending jump destination address value based on a reference address and the second jump destination address value.

[0160] According to at least some embodiments of the security defense method disclosed herein, the mechanism for encrypting the returned destination address value includes: combining the returned destination storage address (addr) and a key reference value corresponding to the process to encrypt and store the returned destination address value (e.g., return address ra, function pointer fp, etc.) to obtain ciphertext; and determining which bits of the encrypted destination address value (MAC) are placed in the mask configuration stored in the coprocessor. During program execution, when the returned destination address value is needed, a verification instruction is used to instruct the coprocessor to decrypt it. Possible attacks are defended by comparing whether the MAC value has changed. After successful verification, the decrypted destination address value is obtained and loaded into the main processor's register, making it point to the correct destination address, thereby realizing the decryption / verification process of the destination address value. Through the above mechanism, the returned destination address value can be encrypted and hidden. Even if an attacker changes the control flow direction of the program through various attack methods, they cannot actually change the location pointed to by the finally decrypted destination address value, thus making it impossible to locate the attack code. Therefore, the embodiments of this disclosure can defend against buffer overflow attacks.

[0161] Some embodiments of this disclosure also provide a processing apparatus, see [link to relevant documentation] Figure 1 As shown in the block diagram, the processing device includes any of the aforementioned coprocessors and a main processor, wherein the main processor is configured to run a program, generate an operation task, and send operation instructions to the coprocessor, and the coprocessor is configured to execute the aforementioned security defense method for the operation task.

[0162] Some embodiments of this disclosure also provide an electronic device including a main processor, a coprocessor, and a memory, wherein computer-executable code is stored in the memory, and the computer-executable code is executed by the main processor and the coprocessor to implement the above-described security defense method.

[0163] In the above embodiments, the main processor and the coprocessor communicate through a communication interface. For example, the main processor is a RISC-V processor, and the communication interface is a RoCC interface.

[0164] Figure 6 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 6 The electronic device 1000 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0165] For example, such as Figure 6 As shown, in some examples, electronic device 1000 includes a processing unit that may include the processing unit of any of the above embodiments, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. RAM 1003 also stores various programs and data required for the operation of the computer system. Processor 1001, ROM 1002, and RAM 1003 are connected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0166] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable storage media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 6 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0167] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0168] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, home appliance, communication base station, industrial controller, server, etc., or any combination of data processing device and hardware. The embodiments disclosed herein do not limit this.

[0169] The following points should be noted regarding this disclosure:

[0170] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0171] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0172] The above are merely exemplary embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A security defense method for operational tasks, used in a coprocessor, comprising: Receive a jump destination encryption request for the operation task, wherein the jump destination encryption request includes information for obtaining a first jump destination storage address and a first jump destination address value corresponding to the operation task; Using a mask configuration, the first jump destination address value is processed by a first mask, and the data bits that conform to the first pattern in the first jump destination address value are removed to obtain the first intermediate jump destination address value; A verification operation is performed based on the first jump destination storage address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain the first encryption result value; Using the mask configuration, the first encrypted result value is processed by the second mask, and the data bits in the first encrypted result value that conform to the first pattern are retained to obtain the first intermediate encrypted result value. The first intermediate encrypted result value is verified with the first jump destination address value to obtain the first encrypted jump destination address value, and the first encrypted jump destination address value is returned.

2. The security defense method according to claim 1, wherein, Based on the first destination storage address, the key reference value corresponding to the operation task, and the first intermediate destination address value, a verification operation is performed to obtain a first encryption result value, including: A first key is obtained using the first destination address and the key reference value corresponding to the operation task. Then, based on the first key, the verification operation is performed on the first intermediate destination address value to obtain the first encrypted result value; or... The first intermediate calculation result value is obtained by using the first jump destination storage address and the first intermediate jump destination address value. Then, based on the key reference value corresponding to the operation task, the first intermediate calculation result value is subjected to the verification operation to obtain the first encrypted result value.

3. The security defense method according to claim 1 further includes: Receive a jump destination verification request for the operation task, wherein the jump destination verification request includes information for obtaining a second jump destination storage address and a second jump destination address value corresponding to the operation task, wherein the second jump destination address value is an encrypted jump destination address value; Using the mask configuration, the second jump destination address value is processed by the first mask, and the data bits that conform to the first pattern in the second jump destination address value are removed to obtain the second intermediate jump destination address value; The verification operation is performed based on the second jump destination storage address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value to obtain the second encryption result value; Using the mask configuration, the second encrypted result value is processed by the second mask, and the data bits in the second encrypted result value that conform to the first mode are retained to obtain the second intermediate encrypted result value; The second intermediate encrypted result value is compared with the pre-stored reference address corresponding to the operation task and conforming to the first mode to perform message verification operation, so as to obtain the third encrypted intermediate result value. Using the mask configuration, the second jump destination address value is processed by the third mask, and the data bits of the second jump destination address value that conform to the first mode are retained to obtain the fourth encrypted intermediate result value; The third and fourth encrypted intermediate result values ​​are compared, and the result of the comparison is used to determine whether the verification passes or fails.

4. The security defense method according to claim 3, wherein, The verification operation is performed based on the second jump destination storage address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value to obtain a second encryption result value, including: A second key is obtained using the second destination address and the key reference value corresponding to the operation task. Then, based on the second key, the verification operation is performed on the second intermediate destination address value to obtain the second encrypted result value; or, The second intermediate calculation result value is obtained by using the second jump destination storage address and the second intermediate jump destination address value. Then, based on the key reference value corresponding to the operation task, the verification operation is performed on the second intermediate calculation result value to obtain the second encrypted result value.

5. The security defense method according to claim 1 further includes: Obtain the key reference value.

6. The security defense method according to claim 5, wherein, Obtaining the key reference value includes: When the process corresponding to the operation task starts or is switched on the main processor, a key reference value loading instruction is received. According to the key reference value loading instruction, the key reference value is obtained from outside the coprocessor or generated within the coprocessor, and the key reference value is stored.

7. The security defense method according to claim 5 further includes: The key reference value is retrieved and stored outside the coprocessor.

8. The security defense method according to claim 7, wherein, The step of retrieving and saving the key reference value outside the coprocessor includes: When the process corresponding to the operation task is switched out on the main processor, a key reference value storage instruction is received. According to the key reference value storage instruction, the key reference value stored in the coprocessor is saved outside the coprocessor.

9. The security defense method according to any one of claims 3-8, wherein, The key reference value is a random number.

10. The security defense method according to claim 1, further comprising: The mask configuration is received and stored within the coprocessor.

11. The security defense method according to claim 10, wherein, The step of receiving the mask configuration and storing the mask configuration within the coprocessor includes: When the process corresponding to the operation task starts on the main processor, a mask configuration instruction is received; The mask configuration is stored within the coprocessor according to the mask configuration instructions.

12. The security defense method according to claim 3 further includes: Save the reference address that corresponds to the operation task and conforms to the first mode.

13. The security defense method according to claim 12, wherein, Saving the reference address corresponding to the operation task includes: Before performing the message verification operation, a reference address configuration instruction is received; According to the reference address configuration instructions, the reference address corresponding to the operation task and conforming to the first mode is stored within the coprocessor.

14. The security defense method according to claim 13, wherein, The first mode is a first number of high-order data bits, and the reference address is the base address for the first number of high-order data bits.

15. The security defense method according to claim 1, wherein, The verification operation includes symmetric encryption operation or message verification code algorithm.

16. The security defense method according to claim 1, wherein, The verification operation includes an XOR operation.

17. The security defense method according to claim 1, wherein, The first jump destination storage address is the operation task return address or function pointer address, and the first jump destination address value is the operation task return address value or function pointer address value.

18. The security defense method according to claim 3, wherein, In response to the successful verification, the decrypted pending jump destination address value corresponding to the operation task is returned based on the second intermediate jump destination address value.

19. The security defense method according to claim 18, wherein, Based on the second intermediate jump destination address value, return the pending jump destination address value corresponding to the operation task, including: In response to the reference address being the base address corresponding to the operation task, the decrypted pending jump destination address value is obtained by combining the second intermediate jump destination address value and the reference address.

20. A coprocessor for security defense of operational tasks, comprising: The decoder, key register, verification module, and control module are included. The decoder is configured to decode operation instructions input to the coprocessor, wherein the operation instructions include jump destination encryption instructions, wherein the jump destination encryption instructions include information for obtaining a first jump destination storage address and a first jump destination address value corresponding to the operation task; The key register is configured to store a key reference value corresponding to the operation task; The control module is configured to use a mask configuration to perform a first mask processing on the first jump destination address value, remove the data bits that conform to the first pattern in the first jump destination address value, and obtain the first intermediate jump destination address value; The verification module is configured to perform verification operations based on the first jump destination storage address, the key reference value corresponding to the operation task, and the first intermediate jump destination address value to obtain a first encryption result value; The control module is further configured to use the mask configuration to perform a second mask processing on the first encrypted result value, retain the data bits in the first encrypted result value that conform to the first mode, obtain a first intermediate encrypted result value, perform a verification operation between the first intermediate encrypted result value and the first jump destination address value, obtain a first encrypted jump destination address value, and return the first encrypted jump destination address value.

21. The coprocessor of claim 20, further comprising a reference address register, wherein, The reference address register is configured to store the base address corresponding to the operation task; The operation instruction also includes a jump destination verification instruction, which includes information for obtaining a second jump destination storage address and a second jump destination address value corresponding to the operation task, wherein the second jump destination address value is an encrypted jump destination address value; The control module is further configured to use the mask configuration to process the second jump destination address value using the first mask, remove the data bits in the second jump destination address value that conform to the first pattern, and obtain the second intermediate jump destination address value; The verification module is further configured to perform the verification operation based on the second jump destination storage address, the key reference value corresponding to the operation task, and the second intermediate jump destination address value to obtain a second encryption result value; The control module is further configured to: use the mask configuration to perform the second mask processing on the second encrypted result value, retaining the data bits in the second encrypted result value that conform to the first pattern, to obtain a second intermediate encrypted result value; perform a message verification operation on the second intermediate encrypted result value and a pre-stored reference address corresponding to the operation task that conforms to the first pattern, to obtain a third encrypted intermediate result value; use the mask configuration to perform the third mask processing on the second jump destination address value, retaining the data bits in the second jump destination address value that conform to the first pattern, to obtain a fourth encrypted intermediate result value; and compare the third encrypted intermediate result value and the fourth encrypted intermediate result value, wherein the result of the comparison is used to determine whether the verification passes or fails.

22. The coprocessor according to claim 21, wherein, The operation instructions also include reference address configuration instructions. The control module is further configured to store, within the coprocessor, the reference address corresponding to the operation task and conforming to the first mode, according to the reference address configuration instruction.

23. The coprocessor according to claim 22, wherein, The first mode is a first number of high-order data bits, and the reference address is the base address for the first number of high-order data bits.

24. The coprocessor of claim 20, further comprising a mask register, wherein, The mask register is configured to store the mask configuration.

25. The coprocessor according to claim 24, wherein, The operation instructions also include mask configuration instructions. The control module is further configured to obtain the mask configuration according to the mask configuration instruction and store the mask configuration in the mask register.

26. The coprocessor according to claim 20, wherein, The operation instructions also include a key reference value loading instruction. The control module is further configured to obtain the key reference value from outside the coprocessor or generate the key reference value within the coprocessor according to the key reference value loading instruction, and store the key reference value in the key reference value register.

27. The coprocessor according to claim 26, further comprising a random number generation module, wherein, The random number generation module is configured to generate the key reference value within the coprocessor.

28. The coprocessor according to claim 26, wherein, The operation instructions also include key reference value storage instructions. The control module is further configured to save the key reference value stored in the coprocessor to a location outside the coprocessor according to the key reference value storage instruction.

29. The coprocessor according to claim 21, wherein, The control module is further configured to, in response to the successful verification, return a pending jump destination address value corresponding to the operation task based on the second intermediate jump destination address value.

30. The coprocessor according to claim 29, wherein, The control module is further configured to, in response to the reference address being the base address corresponding to the operation task, combine the second intermediate jump destination address value and the reference address to obtain the pending jump destination address value.

31. The coprocessor according to claim 20, wherein, The verification module is either a symmetric encryption module or a message verification code module.

32. A processing apparatus, comprising: The coprocessor as described in any one of claims 20-31, and The main processor that communicates with the coprocessor The main processor is configured to run the operation task and send the operation instructions to the coprocessor.

33. The processing apparatus according to claim 32, wherein, The main processor and the coprocessor communicate through a communication interface.

34. The processing apparatus according to claim 33, wherein, The main processor is a RISC-V processor, and the communication interface is a RoCC interface.

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