Bit processing system for digital ink-jet printing
By designing a bit processing system for digital inkjet printing, the core processor and coprocessor work together to achieve efficient bit operations, which solves the shortcomings of general-purpose processors in terms of efficiency, flexibility and power consumption, meets the high-efficiency bit operation requirements of digital inkjet printing, and improves the scalability and adaptability of the system.
Patent Information
- Application Number
- CN202520496712.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-03-20
AI Technical Summary
Existing general-purpose processors are insufficient in terms of execution efficiency, flexibility, versatility and power consumption, making it difficult to meet the high-efficiency bit operation requirements of the digital inkjet printing field.
A bit processing system for digital inkjet printing is designed, including a core processor, a coprocessor, external memory, and a printer. The core processor stores bit operation instructions through instruction-tightly coupled memory and sends them to the coprocessor. The coprocessor contains bit operation units to achieve efficient bit operations and control signal processing, meeting the timing requirements of the printer.
It significantly improves bit operation efficiency, reduces power consumption, increases hardware resource utilization, and enhances system scalability and adaptability, making it suitable for power-sensitive embedded systems and industrial equipment.
Smart Images
Figure CN223884010U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to bit processor design technical field especially is a kind of bit processing system for digital inkjet printing. BACKGROUND
[0002] Bit operation refers to the processing mode of directly operating the single bit of binary number in computer system. Common bit operations include bitwise AND, bitwise OR, bitwise XOR, bitwise NOT, logical left shift and right shift, etc. These operations are directly performed on each bit of binary number, and do not involve higher-level data structures. With the development of embedded systems, more and more application scenarios require efficient bit operation processing of data, for example, in the fields of cryptography algorithms, image processing, data compression, etc., bit operation occupies a major part of the calculation. However, the existing general-purpose processors have limited support for bit operations, which cannot fully meet the needs of these specific fields. The implementation of hardware circuit is difficult to meet the needs of generalization in different scenarios, and the traditional general-purpose processor and hardware implementation have the following disadvantages:
[0003] 1. Low execution efficiency: The instruction set of general-purpose processor is usually designed for general tasks, and lacks special optimization for complex bit operations. This leads to the fact that in scenarios requiring a large number of bit operations, the performance of general-purpose processor cannot meet the needs, and the operation often needs to be completed by multiple instructions, increasing the operation time.
[0004] 2. Limited instruction set support: The basic instruction set of general-purpose processor usually includes basic bit operation instructions, but lacks direct support for complex bit operations. For example, when performing specific bit operations, general-purpose processor may need to be implemented through a series of general-purpose instructions, and cannot provide efficient bit-level parallel processing.
[0005] 3. Low hardware resource utilization: The hardware design of general-purpose processor is to support a wide range of computing tasks, not specific bit operation optimization. This means that its hardware resources cannot be used specifically to accelerate bit operation calculation, resulting in that in applications requiring a large number of bit operations, the computing resources of the processor are not fully utilized.
[0006] 4. Poor scalability: The instruction set and architecture of general-purpose processor are usually fixed and cannot be customized according to the needs of specific application fields. This makes the performance and efficiency of general-purpose processor greatly limited in some fields that require special bit operation optimization, such as industrial digital printing.
[0007] 5. High power consumption: Since general-purpose processor usually needs to implement complex bit operations by executing multiple instructions, it will consume more clock cycles and increase power consumption. In embedded systems or power-sensitive scenarios, this increase in power consumption is very disadvantageous.
[0008] When a conventional general-purpose processor performs a timing conversion task of picture data in the field of digital inkjet printing, a large number of complex bit operations need to be calculated. Although the existing general-purpose processor and hardware implementation scheme have advantages in the feasibility of development, they have obvious deficiencies in execution efficiency, flexibility, versatility and the like, are difficult to provide efficient parallel processing capability, and lack flexible optimization for specific application scenarios, which leads to poor performance under the requirements of high performance and low power consumption, and is difficult to meet the different bit operation requirements of different printers in the industrial inkjet printing application. Utility model content
[0009] Therefore, the technical problem to be solved by the utility model lies in overcoming the problem that the instructions of the general-purpose processor in the prior art only include basic bit operations, which leads to obvious deficiencies in execution efficiency, flexibility, versatility and the like, and cannot meet the task requirements in the field of digital inkjet printing.
[0010] To solve the above technical problem, the utility model provides a bit processing system for digital inkjet printing, which comprises a host computer, a core processor, a coprocessor, an external memory and a printer, the core processor is connected with the host computer, the coprocessor and the external memory respectively, and the coprocessor is connected with the printer.
[0011] The core processor comprises an instruction tightly coupled memory (ITCM).
[0012] The coprocessor comprises a bit operation unit (BMU).
[0013] The host computer is used for generating image data and bit operation instructions; the external memory is used for receiving the image data from the host computer; the core processor is used for storing the bit operation instructions from the host computer through the instruction tightly coupled memory (ITCM) and sending the bit operation instructions to the coprocessor; the core processor is also used for acquiring the image data from the external memory and sending the image data to the coprocessor; the coprocessor is used for analyzing the bit operation instructions and determining the bit operation type corresponding to the bit operation instructions; the bit operation unit (BMU) performs bit operation on the image data according to the bit operation type corresponding to the bit operation instructions, so that the image data meets the timing requirements of the printer; the bit operation unit (BMU) sends the image data after bit operation to the printer; and the printer performs an inkjet printing task according to the image data after bit operation.
[0014] In an embodiment of the utility model, the host computer is also used to generate control instructions about the control signal, the core processor is also used to store the control instructions from the host computer through instruction tightly coupled memory ITCM and send the control instructions to the coprocessor, the coprocessor is also used to send the control instructions to the printer, and the printer executes inkjet printing task according to the image data after bit operation and the control instructions, wherein the control signal is a signal meeting the timing requirement of the printer.
[0015] In an embodiment of the utility model, the coprocessor further comprises a decoding unit connected with the instruction tightly coupled memory ITCM and the bit operation unit BMU respectively, and the decoding unit is used to receive and analyze the bit operation instructions and the control instructions from the instruction tightly coupled memory ITCM.
[0016] In an embodiment of the utility model, the host computer and the instruction tightly coupled memory ITCM of the core processor communicate through a RISC-V regulator, and the host computer transmits the generated bit operation instructions and control instructions to the instruction tightly coupled memory ITCM through the RISC-V regulator.
[0017] In an embodiment of the utility model, the core processor is provided with an ICB bus, and the core processor is connected with an external memory through the ICB bus and an AXI bus.
[0018] In an embodiment of the utility model, the core processor is a hummingbird E203 processor based on RISC-V instruction set architecture.
[0019] In an embodiment of the utility model, the external memory is a DDR memory.
[0020] In an embodiment of the utility model, the core processor is connected with the coprocessor through an NICE interface.
[0021] In an embodiment of the utility model, the coprocessor is a field programmable gate array FPGA.
[0022] In an embodiment of the utility model, the external memory receives image data from the host computer through an AXI bus.
[0023] The above technical solution of the utility model has the following advantages compared with the prior art:
[0024] Significant improvement in bit operation efficiency: By extending the RISC-V instruction set and designing a dedicated bit operation unit, the utility model greatly optimizes the execution efficiency of complex bit operations, especially in application scenarios such as inkjet printing systems, cryptography, data compression, and image processing, which require a large number of bit operations, achieving high-speed and efficient computing processing.
[0025] Reducing power consumption: The design of the dedicated bit processor reduces redundant calculations and instruction execution, enabling efficient execution of bit operations while reducing the overall system power consumption, especially suitable for power-sensitive embedded systems and industrial devices.
[0026] Efficient use of hardware resources: By optimizing the data path and instruction set, the utility model maximizes the use of hardware resources, reducing the performance bottleneck caused by resource waste when general-purpose processors handle bit operations, and improving the utilization rate of hardware resources.
[0027] Strong scalability: The modular design based on the RISC-V architecture allows the processor to be customized according to the needs of different application fields, flexibly configuring different bit operation units, enhancing the scalability and adaptability of the system, and meeting the computing needs in different scenarios.
[0028] Convenient development: Although the utility model is customized with a dedicated bit operation unit for a specific field, it still retains the versatility of the RISC-V architecture, allowing developers to easily implement application development and expansion on a standard platform, reducing development and maintenance costs. BRIEF DESCRIPTION OF DRAWINGS
[0029] In order to make the content of the utility model more easily understood, the following will be further explained according to the specific embodiments of the utility model and in conjunction with the drawings.
[0030] Figure 1 is the overall framework diagram of the bit processing system for digital inkjet printing of the utility model. DETAILED DESCRIPTION
[0031] The utility model will be further explained in conjunction with the drawings and specific embodiments to make those skilled in the art better understand the utility model and can be implemented, but the embodiments are not as a limitation of the utility model. Example one
[0032] Reference Figure 1The utility model relates to a kind of bit processing system for digital ink-jet printing, including: host computer, core processor, coprocessor, external memory and printer, the core processor is connected with host computer, coprocessor and external memory respectively, and the coprocessor is connected with printer;The core processor includes instruction tightly coupled memory ITCM;The coprocessor includes bit operation unit BMU;
[0033] The host computer is used to generate image data and bit operation instructions;The external memory is used to receive image data from the host computer;The core processor is used to store bit operation instructions from the host computer by instruction tightly coupled memory ITCM, and send bit operation instructions to the coprocessor;The core processor is also used to obtain image data from the external memory, and send image data to the coprocessor;The coprocessor is used to receive image data and bit operation instructions;The coprocessor is also used to parse bit operation instructions, determine the bit operation type corresponding to the bit operation instructions;The bit operation unit BMU performs bit operation on image data according to the bit operation type corresponding to the bit operation instructions, to meet the corresponding mapping relationship between each pixel in image data and each nozzle of the printer;The bit operation unit BMU sends image data after bit operation to the printer (ink-jet printer);The printer performs ink-jet printing task according to image data after bit operation.
[0034] The host computer is also used to generate control instructions about control signals (control instructions in the same printing task correspond to bit operation instructions), and the core processor is also used to store control instructions from the host computer by instruction tightly coupled memory ITCM, and send control instructions to the coprocessor;The coprocessor is also used to send control instructions to the printer, and the printer performs ink-jet printing task according to image data after bit operation and control instructions;Wherein, the control signal is a signal meeting the timing requirements of the printer.
[0035] The following will introduce this embodiment in detail:
[0036] Please refer to Figure 1 Developer writes assembly code (program instructions, including bit operation instructions and control instructions) related to image processing in Nuclei Studio of host computer (PC). The code written is transmitted to instruction tightly coupled memory ITCM of core processor (E203 core) by RISC-V debugger. E203 core reads program instructions from instruction tightly coupled memory ITCM and starts execution. According to task demand, E203 core allocates bit operation (the purpose of bit operation is to realize timing conversion) task to coprocessor, and coprocessor executes specific bit operation instructions, such as bit extraction, bit placement and bit sorting.
[0037] The E203 core obtains image data to be processed from the external memory (DDR memory) through the AXI bus and the ICB bus in turn, and sends the obtained image data to the coprocessor through the NICE interface. The specific bit operation task is performed by the bit operation unit BMU in the coprocessor. Specifically, the bit operation unit BMU re-performs bit extraction, bit sorting and bit placement on the image data to ensure that the image data meets the timing requirements of the printer. The processed image data is sent to the printer through the coprocessor. The coprocessor can ensure that the image data is transmitted in the correct timing and complete the timing conversion task.
[0038] Regarding the source of the image data, the external memory (DDR memory) receives the image data from the host computer through the AXI bus.
[0039] The bit processing system for digital inkjet printing in this embodiment mainly consists of the following modules:
[0040] (1) Core processor, which is a hummingbird E203 processor (referred to as E203 core) based on the RISC-V instruction set architecture: as the control core, it is responsible for receiving program instructions (including bit operation instructions and control instructions) and image data from the host computer (PC), storing the program instructions through the instruction tightly coupled memory ITCM, and storing the image data through the extended external memory (DDR memory). At the same time, the core processor is also responsible for task scheduling, which transmits the complex bit operation (corresponding to the timing conversion task) to the coprocessor through the NICE interface.
[0041] (2) Coprocessor (implemented through field programmable gate array FPGA): communicates with the E203 core through the NICE interface, and the coprocessor mainly includes:
[0042] (2.1) Decoding unit: responsible for receiving and analyzing program instructions (including bit operation instructions and control instructions) from the instruction tightly coupled memory ITCM in the E203 core, determining the type of bit operation to be performed through the analysis of the bit operation instructions, and sending the analyzed bit operation instructions to the BMU (bit operation unit), determining the timing requirements of the printer through the analysis of the control instructions, and sending the analyzed control instructions to the printer through the print driver unit.
[0043] (2.2) Bit operation unit BMU (Bit Manipulation Unit): specifically performs complex bit operation tasks such as bit extraction, bit sorting and bit placement on the image data sent through the NICE interface. This step involves rearranging each pixel data to meet the physical requirements of the inkjet printer head, wherein:
[0044] bit_extract (bit extraction): extracts certain specific bits from data according to a mask. Specifically, from the input image data, according to the physical correspondence between the image pixels and the nozzles, the specific bit segment required by the nozzles in a certain area is extracted. It can be simply understood as: in inkjet printing, the data required by the nozzles in a certain area is extracted from the entire image data.
[0045] bit_permute (bit permutation): reorders data according to a mask according to a preset order, and reorders the extracted data to meet the actual physical structure and timing requirements of the printhead, to ensure that each nozzle can receive correct data. It can be simply understood as: in inkjet printing, this means that the extracted image data is reordered to ensure that the nozzles can print the data of the corresponding pixels in the correct order.
[0046] bit_deposit (bit deposit): places certain data bits in the data to the specified location of the output register according to the mask. The output register is in the bit operation unit, which is specifically implemented by the FF hardware logic resource in the FPGA, for subsequent transmission and output.
[0047] Further, in addition to the above-mentioned bit extraction, bit ordering and bit placement, in other embodiments, the following complex bit operations can also be set up by themselves:
[0048] Bit count: count the number of data with value 1 in the data;
[0049] Bit truncation: truncate part of the bit width data from the low bit of the data;
[0050] Bit concatenation: concatenate multiple input data in order;
[0051] Bit distribution: distribute data according to address to each unit in turn;
[0052] Bit output: serially output data according to the output clock;
[0053] (2.3) Printer_Control (Printer_Control): According to the timing requirements of the print driver, the control instructions parsed by the decoding unit are sent to the printer through the print driver unit. The print driver unit is connected to the printer through the Dupont line. The print driver unit is used to send the clock signal (informing the printer at what time to print which image data, the image data and the clock are matched together) and the driving signal (the printer ignition pulse signal) to the printer according to the parsed control instructions. The clock signal and the driving signal are the above-mentioned control signals.
[0054] It should be noted that the decoding unit, the bit operation unit BMU and the print driving unit in the coprocessor are mainly implemented by the combination of CLB (Configurable Logic Block), FF (Flip-Flop) and LUT (Look-Up Table) hardware logic resources in the FPGA to realize specific functions. Specifically, the decoding unit, the bit operation unit BMU and the print driving unit in the FPGA can realize their respective functions through the vivado design environment.
[0055] (3) External memory (DDR memory): The DDR memory is used to store a large amount of image data and temporary data, to ensure the storage and scheduling of large-scale image data in the printing process. The E203 core reads the image data in the DDR memory through the ICB bus to AXI bus (specifically, the conversion of the two different buses is realized through the ICB2AXI interface conversion protocol), and sends the read image data to the coprocessor through the NICE interface. The coprocessor itself does not directly access the memory DDR.
[0056] (4) Printer (printhead): As an output device, it receives the processed image data and completes high-speed printing according to the control signal.
[0057] The core processor communicates with the coprocessor through the NICE interface, and the NICE interface is described in detail as follows:
[0058] The NICE interface includes:
[0059] nice_icb_cmd_wdata: This signal interface is used to transmit image data signals;
[0060] nice_req_inst: This interface is used to transmit program instructions (bit operation instructions and control instructions) from the E203 core. The instruction type is parsed by the decoding unit of the coprocessor to determine which bit operation or other print control task needs to be executed.
[0061] nice_icb_rsp_data: After the coprocessor finishes processing the task, it returns the result data to the E203 core through this interface, and notifies the E203 core that the corresponding instruction execution is completed.
[0062] nice_icb_cmd_addr: This signal interface is used to transmit the target address of the task or the specific address information of the operation, and is usually used to indicate where the coprocessor reads data and where the processing result is sent.
[0063] The decoding unit is described in detail as follows:
[0064] Function: The decoding unit is responsible for receiving program instructions from the E203 core, determining the operation type corresponding to the bit operation instruction, such as bit extraction, bit placement, or bit arrangement, by parsing the bit operation instruction in nice_req_inst, and of course determining the control signal corresponding to the control instruction.
[0065] First, the bit operation unit BMU of the coprocessor obtains image data from the DDR memory from nice_icb_cmd_wdata and parses the specific bit operation instruction type from nice_req_inst. Then, the decoding unit passes these bit operation instructions to the bit operation unit BMU to perform the corresponding bit operation task on the image data through the bit operation unit BMU. At the same time, the decoding unit is responsible for passing the parsed control instruction to the printer control unit (Printer_Control) to ensure that the coprocessor correctly controls the timing and data flow of the printing process.
[0066] Detailed introduction to the printer control unit (Printer_Control):
[0067] Function: The printer control unit controls the timing, synchronization signal, and print trigger signal of the print data to ensure that the inkjet printer can perform inkjet printing on the image data at the correct time.
[0068] The printer control unit (Printer_Control) includes the following signal interfaces:
[0069] print_clk: The print clock is sent to the clock input interface of the printer. The drive chip in the printer implements the transmission of image data to the corresponding nozzle for printing according to the frequency of the print clock.
[0070] print_fire: Trigger the actual printing process of the inkjet printer, instructing the nozzle to start inkjet operation.
[0071] The bit processing system for digital inkjet printing of the embodiment has good effects in bit operation throughput, timing conversion delay, and power consumption efficiency. The utility model can process a large number of bit operations in unit time, significantly shorten the timing conversion time, reduce power consumption, maintain stable performance under high parallelism, and have good expansion capability.
[0072] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0073] Obviously, the above embodiments are only examples for clearly illustrating the present application and are not intended to limit the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A bit processing system for digital inkjet printing, characterized by: The system comprises a host computer, a core processor, a coprocessor, an external memory and a printer, the core processor is connected with the host computer, the coprocessor and the external memory respectively, and the coprocessor is connected with the printer; The core processor comprises an instruction tightly coupled memory (ITCM); The coprocessor comprises a bit manipulation unit (BMU); The host computer is used to generate image data and bit manipulation instructions; the external memory is used to receive the image data from the host computer; the core processor is used to store the bit manipulation instructions from the host computer through the instruction tightly coupled memory (ITCM) and send the bit manipulation instructions to the coprocessor; the core processor is also used to obtain the image data from the external memory and send the image data to the coprocessor; the coprocessor is used to parse the bit manipulation instructions and determine the bit manipulation type corresponding to the bit manipulation instructions; the bit manipulation unit (BMU) performs bit manipulation on the image data according to the bit manipulation type corresponding to the bit manipulation instructions so that the image data meets the timing requirements of the printer; and the bit manipulation unit (BMU) sends the image data after bit manipulation to the printer; The printer performs an inkjet printing task according to the image data after bit manipulation.
2. A bit processing system for digital inkjet printing according to claim 1, characterized in that: The host computer is also used to generate control instructions about control signals, the core processor is also used to store the control instructions from the host computer through the instruction tightly coupled memory (ITCM) and send the control instructions to the coprocessor; the coprocessor is also used to send the control instructions to the printer, and the printer performs an inkjet printing task according to the image data after bit manipulation and the control instructions; wherein the control signals are signals meeting the timing requirements of the printer.
3. A bit processing system for digital inkjet printing according to claim 2, characterized in that: The coprocessor further comprises a decoding unit connected with the instruction tightly coupled memory (ITCM) and the bit manipulation unit (BMU) respectively; the decoding unit is used to receive and parse the bit manipulation instructions and the control instructions from the instruction tightly coupled memory (ITCM).
4. The bit processing system for digital inkjet printing of claim 2, wherein: The host computer communicates with the instruction tightly coupled memory (ITCM) of the core processor through a RISC-V debugger, and the host computer transmits the generated bit manipulation instructions and control instructions to the instruction tightly coupled memory (ITCM) through the RISC-V debugger.
5. The bit processing system for digital inkjet printing of claim 1, wherein: The core processor is provided with an ICB bus, and the core processor is connected with the external memory through the ICB bus and the AXI bus.
6. The bit processing system for digital inkjet printing of claim 1, wherein: The core processor is a hummingbird E203 processor based on the RISC-V instruction set architecture.
7. The bit processing system for digital inkjet printing of claim 1, wherein: The external memory is a DDR memory.
8. The bit processing system for digital inkjet printing of claim 1, wherein: The core processor is connected with the coprocessor through an NICE interface.
9. The bit processing system for digital inkjet printing of claim 1, wherein: The coprocessor is a field programmable gate array (FPGA).
10. The bit processing system for digital inkjet printing of claim 1, wherein: The external memory receives the image data from the host computer through the AXI bus.