Multi-protocol encoder communication interface circuit based on hardware configuration

Abstract

The invention relates to the technical field of encoder communication interface circuits, in particular to a multi-protocol encoder communication interface circuit based on hardware configuration, which comprises a core control and protocol processing module, a hardware configuration and mode recognition module, an RS-485 differential driving and receiving module and an interface protection circuit module. In the invention, the problems that the hardware cost is high, the PCB layout is complicated, the overall size of the system is increased, the types of connectors are diversified and the wiring difficulty is increased due to the fact that an independent physical interface circuit needs to be independently designed for each protocol such as BISS and Tamagawa or a special integrated chip with a solidified factory function is adopted in the existing scheme are thoroughly solved; and meanwhile, the problems that chips need to be replaced or hardware needs to be redesigned and the configuration flexibility is poor in the protocol updating of an existing scheme are solved, the time sequence conflict risk existing in software dynamic switching protocols is avoided, and the defects that a traditional circuit is poor in surge resistance, signal crosstalk is caused and debugging and maintenance are complex are overcome.

Description

Technical Field

[0001] This invention relates to the field of encoder communication interface circuit technology, and in particular to a multi-protocol encoder communication interface circuit based on hardware configuration. Background Technology

[0002] As a key component that converts mechanical displacement or rotational speed into electrical signals, encoders are widely used in industrial control, precision manufacturing and other fields. To meet the requirements of signal transmission accuracy, speed and anti-interference capability in different scenarios, the industry has developed a variety of encoder communication protocols, such as BISS-C and Tamagawa. These protocols differ in signal format, timing logic and data interaction methods. The main controller needs to communicate with the encoder through a specific interface to obtain key information such as position and speed to support the precise control of the system.

[0003] Existing main controller solutions that support multiple encoder protocols have significant limitations. One type of solution designs a separate physical interface circuit for each protocol, while another type uses a single vendor's dedicated application-specific integrated chip (ASIC). However, the ASIC's functions are fixed at the factory, resulting in high hardware costs. The PCB layout becomes complex due to multiple interface circuits, increasing the overall system size. At the same time, different protocols require different connectors, increasing wiring difficulty. More importantly, when new protocols need to be supported, the chip must be replaced or the hardware must be redesigned, resulting in poor configuration flexibility and difficulty in adapting to rapidly changing application requirements. Summary of the Invention

[0004] To overcome the problems of existing main controllers supporting multiple encoder protocols such as BISS-C and Tamagawa, which require designing independent physical interface circuits for each encoder protocol or using dedicated integrated chips (ASICs) from a single supplier with fixed factory functions, resulting in high hardware costs, complex PCB layouts, large system size, diverse connectors, difficult wiring, and the need to replace chips or redesign hardware for subsequent protocol updates, as well as poor configuration flexibility.

[0005] The technical solution of the present invention is as follows: a multi-protocol encoder communication interface circuit based on hardware configuration, including a core control and protocol processing module, a hardware configuration and pattern recognition module, an RS-485 differential drive and receiver module, and an interface protection circuit module. Each module is electrically connected in sequence, and the circuit connection relationship is changed through hardware configuration to achieve multi-protocol compatibility and adaptation.

[0006] Preferably, the core control and protocol processing module is composed of a microcontroller unit or a field-programmable gate array, and is electrically connected to the hardware configuration and pattern recognition module to receive its pattern signals.

[0007] Preferably, the hardware configuration and pattern recognition module configures the circuit connection relationship by soldering or not soldering a 10-ohm resistor; when adapting to the BISS protocol, resistors RD8 and RD13 are not soldered; when adapting to the Tamagawa protocol, resistor RD17 is not soldered; the hardware configuration and pattern recognition module includes a resistor configuration interface, which is electrically connected to the core control and protocol processing module and the RS-485 differential driver and receiver module.

[0008] Preferably, the RS-485 differential driver and receiver module consists of an RS-485 transceiver chip (model TPT75176B-DF6R) and peripheral circuits. When adapting to the BISS protocol, two 485 circuits are used as the BISS receiving signal circuit and the BISS transmitting signal circuit, respectively. When adapting to the Tamagawa protocol, one 485 circuit is used to realize the transmit and receive connection of the Tamagawa communication input and output signal terminals. The RS-485 differential driver and receiver module is electrically connected to the core control and protocol processing module, converting the internal single-ended signal into a differential signal for transmission, and simultaneously converting the received differential signal into a single-ended signal for transmission to the core control and protocol processing module.

[0009] Preferably, the peripheral circuit includes capacitors CD1-CD6 and resistors RD6-RD11, with capacitor specifications including 1nF 50V and 100nF 50V, and resistor specifications including 10Ω 1 / 16W and 120Ω 1 / 4W; when adapting to the Tamagawa protocol, the Tamagawa communication input / output signal terminals are connected to a differential signal conversion unit.

[0010] Preferably, the interface protection circuit module is composed of a bidirectional Zener diode (model WE12DF-B) connected in parallel with the signal input terminal of the RS-485 differential driver and receiver module; the interface protection circuit module includes a Zener diode protection unit.

[0011] Preferably, the RS-485 differential driver and receiver module includes a debug receiver section and a debug transmitter section, which are connected to external devices via a serial port.

[0012] The beneficial effects of this invention are: 1. Significantly reduced hardware and usage costs: The core control and protocol processing module is electrically connected to the signal output pins of the hardware configuration and pattern recognition module, and the control pins of the RS-485 differential driver and receiver module via PCB routing. The RS-485 differential driver and receiver module is then electrically connected to the Zener diode protection unit of the interface protection circuit module via PCB routing, forming a universal hardware platform. This platform reuses the TPT75176B-DF6R RS-485 transceiver chip and peripheral capacitors CD1-CD6 and resistors RD6-RD11, replacing the traditional multiple independent interface circuits, reducing the number of components, BOM costs, and PCB manufacturing costs. The unified circuit architecture simplifies PCB layout, reduces system size, reduces connector types, and reduces wiring difficulty and material management complexity. 2. Significantly Improved Reliability and Signal Quality: The resistor configuration interface pads of the hardware configuration and pattern recognition module are directly electrically connected to the signal input terminals of the core control and protocol processing module and the control input terminals of the RS-485 differential driver and receiver module. Mode signals are output through selective soldering of resistors. Upon receiving these signals, the core control and protocol processing module directly controls the switching circuit state of the RS-485 differential driver and receiver module, eliminating the timing delay risk associated with software dynamic switching. The WE12DF-B bidirectional Zener diode protection unit of the interface protection circuit module is electrically connected at both ends to the differential signal output pin and ground terminal of the RS-485 differential driver and receiver module, forming a parallel structure. This allows for rapid conduction and energy dissipation in the event of external surge voltage, preventing damage to the core control and protocol processing module and the RS-485 differential driver and receiver module. In the peripheral circuit of the RS-485 differential driver and receiver module, one end of the 1nF 50V capacitors CD3, CD4, and CD6 is electrically connected to the chip's power supply filter pin, and the other end is grounded. A 100nF... One end of 50V capacitors CD2 and CD5 is electrically connected to the chip's power input pin, and the other end is grounded. This dual-filter structure filters out high-frequency interference in the power supply and signal. The other ends of 120Ω 1 / 4W resistors RD6 and RD11 are electrically connected to the differential pins of the BISS receiving signal circuit and the BISS transmitting signal circuit, respectively, to match the differential signal transmission impedance and reduce signal reflection. One end of 10Ω 1 / 16W resistors RD8, RD13, and RD17 is electrically connected to the RS-485 differential drive and receiving module control pin, and the other end is selectively grounded to limit the control pin current and prevent chip overcurrent damage. This multi-structure collaborative approach ensures stable circuit operation and signal transmission integrity. 3. Flexible protocol adaptation and convenient operation: The resistor configuration interface of the hardware configuration and pattern recognition module reserves three corresponding solder pads for resistors RD8, RD13, and RD17. Different protocol adaptations can be achieved simply by changing the soldering combination of the resistors at the solder pads. When adapting to the BISS protocol, RD8 and RD13 are not soldered at the resistor configuration interface, and only RD17 is kept in the soldering state. The hardware configuration and pattern recognition module (102) outputs the BISS protocol mode signal. The UART0_DE pin of the core control and protocol processing module is pulled up through internal software configuration. The output control signal is electrically connected to the enable pin of the RS-485 differential drive and receiver module (103), controlling it to switch to two independent 485 circuits, which are used as the BISS receiving signal circuit and the BISS transmitting signal circuit, respectively. The differential input terminal of the BISS receiving signal circuit is electrically connected to the encoder BISS_DAT signal output terminal, and the single-ended output terminal is electrically connected to the signal receiving pin of the core control and protocol processing module (101). The single-ended input terminal of the BISS transmitting signal circuit is electrically connected to the core control and protocol processing module (101). The signal transmission pin of the control and protocol processing module is electrically connected, and the differential output terminal is electrically connected to the encoder BISS_CLK signal input terminal to realize bidirectional transmission of BISS protocol signals. When adapting to the Tamagawa protocol, RD17 is not soldered at the resistor configuration interface, and the soldering status of RD8 and RD13 is retained. The hardware configuration and mode recognition module outputs the Tamagawa protocol mode signal. The mode selection pin of the core control and protocol processing module outputs a low level and is electrically connected to the RS-485 differential drive and receiver module mode switching pin to control it to switch to a single-channel 485 circuit. It is electrically connected to the Tamagawa communication input and output signal terminal. The differential pin of the Tamagawa communication input and output signal terminal is electrically connected to the input terminal of the differential signal conversion unit. The single-ended output terminal of the differential signal conversion unit is electrically connected to the signal receiving pin of the core control and protocol processing module, and the single-ended input terminal is electrically connected to the signal transmission pin of the core control and protocol processing module to realize bidirectional transmission of Tamagawa protocol signals. The entire adaptation process does not require redesigning hardware or replacing chips. The operation is simple and fast, greatly improving the product's adaptability to different application scenarios. 4. Simplified Production Debugging and On-site Maintenance: The unified circuit architecture and standardized resistance soldering configuration allow the production line to quickly complete the adaptation operation of different protocols without adjusting the PCB layout or component installation position for different protocols, reducing the error rate of production operations. The signal input terminal of the debugging and receiving section of the RS-485 differential driver and receiver module is electrically connected to the TX pin of the external serial port debugging device, and the signal output terminal is electrically connected to the debugging and receiving pin of the core control and protocol processing module. The signal input terminal of the debugging and transmitting section is electrically connected to the debugging and transmitting pin of the core control and protocol processing module, and the signal output terminal is electrically connected to the RX pin of the external serial port debugging device. There is no need to build additional debugging circuits. Debugging command reception and feedback signal transmission can be realized through the serial port, directly checking the working status of the core control and protocol processing module and the RS-485 differential driver and receiver module, significantly reducing the complexity and difficulty of on-site maintenance. Attached Figure Description

[0013] Figure 1 This is the overall circuit schematic diagram of the present invention; Figure 2 This is a general functional block diagram of the present invention; Figure 3 This is a functional block diagram of the BISS protocol of the present invention; Figure 4 This is a functional block diagram of the Tamagawa protocol of the present invention.

[0014] In the attached diagram, the following are the reference numerals: 101, Core Control and Protocol Processing Module; 102, Hardware Configuration and Pattern Recognition Module; 103, RS-485 Differential Driver and Receiver Module; 104, Interface Protection Circuit Module; 201, BISS Receive Signal Circuit; 202, BISS Transmit Signal Circuit; 203, Debug Receiver Section; 204, Debug Transmitter Section; 301, Tamagawa Communication Input / Output Signal Terminal; 302, Differential Signal Conversion Unit; 303, Zener Diode Protection Unit; 304, Resistor Configuration Interface. Detailed Implementation

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0016] Example 1

[0017] refer to Figure 1-2 The structure shown is a hardware-configured multi-protocol encoder communication interface circuit, including a core control and protocol processing module 101, a hardware configuration and pattern recognition module 102, an RS-485 differential drive and receiver module 103, and an interface protection circuit module 104. Each module is electrically connected in sequence through PCB wiring.

[0018] The core control and protocol processing module 101 uses a microcontroller unit (MCU), whose pins are electrically connected to the signal output pins of the hardware configuration and pattern recognition module 102. The resistor configuration interface 304 of the hardware configuration and pattern recognition module 102 consists of three solder pads reserved on the PCB, corresponding to resistors RD8, RD13, and RD17 respectively. Its signal output terminals are electrically connected to the signal input terminals of the core control and protocol processing module 101 and the control input terminals of the RS-485 differential drive and receiver module 103, respectively. The core chip of the differential drive and receiver module 103 is TPT75176B-DF6R. Its power supply pin is electrically connected to one end of the external capacitors CD1 and CD2, and the other end of the capacitors CD1 and CD2 is grounded. The differential signal pin of the chip is electrically connected to one end of the resistors RD6 and RD11. The Zener diode protection unit 303 of the interface protection circuit module 104 is a WE12DF-B bidirectional Zener diode. Its two ends are electrically connected to the differential signal output pin and the ground terminal of the RS-485 differential drive and receiver module 103, respectively.

[0019] By selectively soldering or leaving unsoldered resistors RD8, RD13, and RD17 on the resistor configuration interface 304 pad of the hardware configuration and pattern recognition module 102, the target protocol (BISS or Tamagawa) is determined. The hardware configuration and pattern recognition module 102 outputs a mode signal corresponding to the protocol based on the resistor soldering status. This signal is transmitted via PCB routing to the signal input terminal of the core control and protocol processing module 101. After receiving the mode signal, the core control and protocol processing module 101 outputs a control signal to the control pin or mode switching pin of the RS-485 differential driver and receiver module 103 to control the internal circuitry of the RS-485 differential driver and receiver module 103. The structure is switched to adapt to the target protocol (when adapting to the BISS protocol, it switches to two independent 485 circuits, serving as the BISS receiving signal circuit 201 and the BISS transmitting signal circuit 202 respectively; when adapting to the Tamagawa protocol, it switches to a single 485 circuit paired with the Tamagawa communication input / output signal terminal 301 and the differential signal conversion unit 302). The differential signal output by the encoder is then received by the corresponding circuit of the RS-485 differential driver and receiver module 103 (via the BISS receiving signal circuit 201 under the BISS protocol, and via the Tamagawa communication input / output signal terminal 301 under the Tamagawa protocol) and converted into a single-ended signal, which is then transmitted to the core control and protocol processing unit. Module 101, along with the core control and protocol processing module 101, outputs a single-ended signal that is transmitted via the corresponding circuit of the RS-485 differential driver and receiver module 103 (BISS protocol via BISS transmit signal circuit 202), and then converted to a differential signal by the differential signal conversion unit 302 under the Tamagawa protocol. This differential signal is then transmitted to the encoder via the Tamagawa communication input / output signal terminal 301. During this process, the Zener diode protection unit 303 of the interface protection circuit module 104 is connected in parallel with the differential signal pin of the RS-485 differential driver and receiver module 103 to provide real-time protection against potential external surge voltages. When debugging or maintenance is required, external... The TX pin of the serial port debugging device is electrically connected to the signal input terminal of the debugging receiving section 203 of the RS-485 differential driver and receiver module 103. The signal output terminal of the debugging receiving section 203 is electrically connected to the debugging receiving pin of the core control and protocol processing module 101. The RX pin of the external serial port debugging device is electrically connected to the signal output terminal of the debugging transmitting section 204 of the RS-485 differential driver and receiver module 103. The signal input terminal of the debugging transmitting section 204 is electrically connected to the debugging transmitting pin of the core control and protocol processing module 101. Through this connection, the debugging command reception and feedback signal transmission are realized, the circuit working status detection and fault diagnosis are completed, and a complete workflow chain is formed.

[0020] Example 2

[0021] Based on the above embodiment 1, optimizations were made for the adaptation scenarios of the BISS protocol and the Tamagawa protocol, referring to... Figures 2-4 The structure shown; Furthermore, when adapting to the BISS protocol, at the resistor configuration interface 304 of the hardware configuration and pattern recognition module 102, the pads corresponding to RD8 and RD13 are not soldered, only the soldering state of RD17 is retained. The UART0_DE pin of the core control and protocol processing module 101 is pulled up through internal software configuration, and its output control signal is electrically connected to the enable pin of the RS-485 differential drive and receiver module 103.

[0022] The selective welding resistor structure of the resistor configuration interface 304 allows the hardware configuration and pattern recognition module 102 to output the mode signal corresponding to the BISS protocol. After receiving the signal, the core control and protocol processing module 101 controls the RS-485 module to switch to the BISS adaptation state. This structure does not require an additional control chip, which simplifies the hardware complexity. At the same time, the hardware configuration method avoids the timing risk of dynamic software switching and improves the reliability of protocol switching.

[0023] Furthermore, when adapting to the BISS protocol, the RS-485 differential drive and receiver module 103 is internally divided into two independent 485 circuits. One is the BISS receiving signal circuit 201, whose differential input terminal is electrically connected to the BISS_DAT signal output terminal of the encoder, and its single-ended output terminal is electrically connected to the signal receiving pin of the core control and protocol processing module 101. The other is the BISS transmitting signal circuit 202, whose single-ended input terminal is electrically connected to the signal transmitting pin of the core control and protocol processing module 101, and its differential output terminal is electrically connected to the BISS_CLK signal input terminal of the encoder.

[0024] The structure uses two independent 485 circuits as the BISS receiving and transmitting signal circuits respectively to achieve physical isolation of the receiving and transmitting signals under the BISS protocol, eliminating crosstalk problems. At the same time, the BISS receiving signal circuit 201 can convert the differential signal output by the encoder into a single-ended signal that can be recognized by the core control module, and the BISS transmitting signal circuit 202 can convert the single-ended signal output by the core control module into a differential signal that can be received by the encoder, ensuring the integrity of signal transmission and anti-interference capability.

[0025] Furthermore, when adapting to the BISS protocol, the signal input terminal of the debug receiving section 203 of the RS-485 differential driver and receiver module 103 is electrically connected to the TX pin of the external serial port debugging device, and the signal output terminal of the debug receiving section 203 is electrically connected to the debug receiving pin of the core control and protocol processing module 101; the signal input terminal of the debug transmitting section 204 is electrically connected to the debug transmitting pin of the core control and protocol processing module 101, and the signal output terminal of the debug transmitting section 204 is electrically connected to the RX pin of the external serial port debugging device.

[0026] The debugging receiving section 203 and the debugging transmitting section 204 are electrically connected to external devices and the core control module to realize the reception of debugging commands and the transmission of debugging feedback signals. No additional debugging circuit is required, which simplifies the debugging process and reduces the difficulty of on-site maintenance. At the same time, the serial port connection method is compatible with mainstream debugging equipment, improving versatility.

[0027] Furthermore, when adapting to the Tamagawa protocol, at the resistor configuration interface 304 of the hardware configuration and pattern recognition module 102, the pad corresponding to RD17 is not soldered, and only the soldering status of RD8 and RD13 is retained. The mode selection pin of the core control and protocol processing module 101 outputs a low level and is electrically connected to the mode switching pin of the RS-485 differential drive and receiver module 103.

[0028] The design of the resistor configuration interface 304 without soldering RD17 allows the hardware configuration and pattern recognition module 102 to output the mode signal of the Tamagawa protocol. After receiving the signal, the core control module controls the RS-485 module to switch to single-channel transceiver mode. This configuration method is consistent with the resistor configuration logic of the BISS protocol, which facilitates rapid operation on the production line, reduces the error rate, and eliminates the need to redesign the hardware, thus improving the product's flexibility in adapting to different protocols.

[0029] Furthermore, when adapting to the Tamagawa protocol, the single-channel 485 circuit of the RS-485 differential driver and receiver module 103 is electrically connected to the Tamagawa communication input / output signal terminal 301, the differential pin of the Tamagawa communication input / output signal terminal 301 is electrically connected to the input terminal of the differential signal conversion unit 302, the single-ended output terminal of the differential signal conversion unit 302 is electrically connected to the signal receiving pin of the core control and protocol processing module 101, and the single-ended input terminal of the differential signal conversion unit 302 is electrically connected to the signal transmitting pin of the core control and protocol processing module 101.

[0030] The single-channel 485 circuit, combined with the structure of the Tamagawa communication input / output signal terminal 301, enables multiplexing of transmit and receive signals under the Tamagawa protocol, reducing circuit space and the number of components, and lowering hardware costs. At the same time, the differential signal conversion unit 302 can perform bidirectional conversion between differential signals and single-ended signals, ensuring signal compatibility between the core control module and the encoder, and guaranteeing communication stability.

[0031] Furthermore, when adapting to the Tamagawa protocol, the Zener diode protection unit 303 of the interface protection circuit module 104 is electrically connected at both ends to the differential pin and ground terminal of the Tamagawa communication input / output signal terminal 301, respectively, forming a parallel connection with the signal input terminal of the RS-485 differential driver and receiver module 103.

[0032] The structure, in which the Zener diode protection unit 303 is connected in parallel with the Tamagawa communication input / output signal terminal 301, allows the bidirectional Zener diode to quickly conduct and discharge energy when an external surge voltage occurs, preventing the surge voltage from damaging the RS-485 module and the core control module. This protection structure requires no additional control logic and has a fast response speed. At the same time, the Zener diode of model WE12DF-B is compatible with the circuit's operating voltage, ensuring the protection effect without affecting normal signal transmission.

[0033] Furthermore, in the peripheral circuit of the RS-485 differential driver and receiver module 103, one end of capacitors CD3, CD4, and CD6 is electrically connected to the power supply filter pin of the chip, and the other end is grounded. The capacitor specifications are all 1nF 50V. One end of capacitors CD2 and CD5 is electrically connected to the power input pin of the chip, and the other end is grounded. The capacitor specifications are all 100nF 50V. The other end of resistors RD6 and RD11 is electrically connected to the differential pins of the BISS receiving signal circuit 201 and the BISS transmitting signal circuit 202, respectively. The resistor specifications are 120Ω 1 / 4W. The specifications of resistors RD8, RD13, and RD17 are all 10Ω 1 / 16W. One end of them is electrically connected to the control pin of the RS-485 differential driver and receiver module 103, and the other end is selectively grounded.

[0034] The filter structure using capacitors of different specifications (1nF 50V, 100nF 50V) can filter out high-frequency interference in the power supply and signal respectively, improving the stability of the circuit operation; the 120Ω terminating resistors (RD6, RD11) can match the differential signal transmission impedance, reduce signal reflection, and ensure signal integrity; the 10Ω resistors (RD8, RD13, RD17) can limit the current of the control pins to avoid overcurrent damage to the chip. The overall peripheral circuit design takes into account filtering, current limiting, and impedance matching functions, improving the working reliability and signal transmission quality of the RS-485 module.

[0035] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A hardware configuration based multi-protocol encoder communication interface circuit, characterized by: It comprises a core control and protocol processing module (101), a hardware configuration and mode recognition module (102), an RS-485 differential drive and receiving module (103) and an interface protection circuit module (104), and the modules are electrically connected in sequence through the hardware configuration to change the circuit connection relationship.

2. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 1, characterized in that: The core control and protocol processing module (101) is composed of one of a microcontroller unit and a field programmable gate array, and is electrically connected with the hardware configuration and mode recognition module (102) to receive the mode signal thereof.

3. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 1, wherein: The hardware configuration and mode recognition module (102) is configured by welding or not welding a 10-ohm resistor; when adapting to the BISS protocol, the resistors RD8 and RD13 are not welded; when adapting to the Tomihe protocol, the resistor RD17 is not welded; the hardware configuration and mode recognition module (102) comprises a resistor configuration interface (304) and is electrically connected with the core control and protocol processing module (101) and the RS-485 differential drive and receiving module (103).

4. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 1, wherein: The RS-485 differential drive and receiving module (103) is composed of an RS-485 transceiver chip and peripheral circuits; when adapting to the BISS protocol, two 485 circuits are used as a BISS receiving signal circuit (201) and a BISS sending signal circuit (202) respectively; when adapting to the Tomihe protocol, one 485 circuit is used to realize the transceiving connection of a Tomihe communication input and output signal end (301); the RS-485 differential drive and receiving module (103) is electrically connected with the core control and protocol processing module (101) to convert the internal single-end signal into a differential signal for sending and to convert the received differential signal into a single-end signal for transmission to the core control and protocol processing module (101).

5. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 4, wherein: The peripheral circuits comprise capacitors CD1-CD6 and resistors RD6-RD11; when adapting to the Tomihe protocol, the Tomihe communication input and output signal end (301) is connected with a differential signal conversion unit (302).

6. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 1, wherein: The interface protection circuit module (104) is composed of a bidirectional voltage stabilizing diode and is connected in parallel with the signal input end of the RS-485 differential drive and receiving module (103); the interface protection circuit module (104) comprises a voltage stabilizing diode protection unit (303).

7. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 4, wherein: The RS-485 differential drive and receiving module (103) comprises a debugging receiving part (203) and a debugging sending part (204) and is connected with external equipment through a serial port.

8. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 4, wherein: When adapting to the BISS protocol, the BISS receiving signal circuit (201) receives the BISS differential signal returned by an encoder and converts it into a single-end signal for transmission to the core control and protocol processing module (101); the BISS sending signal circuit (202) converts the BISS control signal output by the core control and protocol processing module (101) into a differential signal for sending to the encoder.

9. A hardware configuration based multi-protocol encoder communication interface circuit according to claim 5, wherein: When the Tomo River protocol is adapted, the Tomo River communication input and output signal end (301) realizes the input and output of the encoder signal under the Tomo River protocol, the differential signal conversion unit (302) converts the differential signal received by the Tomo River communication input and output signal end (301) into a single-ended signal and transmits it to the core control and protocol processing module (101), and at the same time, converts the single-ended signal output by the core control and protocol processing module (101) into a differential signal and sends it to the encoder through the Tomo River communication input and output signal end (301).

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