Multi-bus decoupling distributed embedded hardware rendering architecture, system and method

Abstract

The invention discloses a multi-bus decoupling distributed embedded hardware rendering architecture, system and method, and relates to the technical field of ultra-high-definition video hardware processing, and the key points of the technical scheme are that the architecture comprises a multi-bus decoupling module which comprises a plurality of hardware buses which are physically isolated from one another, each hardware bus is an exclusive hardware transmission link bearing a single-type manufacturing task; the modular processing unit is an independent hardware board card and is integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port; the plurality of modular processing units are cascaded in sequence through a hardware bus in the multi-bus decoupling module to form a distributed assembly line rendering link; when the modular processing units are newly added, the signal processing capability and the rendering synthesis capability are linearly improved along with the increase of the number of the modular processing units. According to the invention, the problem of performance bottleneck of the traditional architecture in processing 4K / 8K ultra-high-definition and multichannel rendering is fundamentally solved.

Description

Technical Field

[0001] This invention relates to the field of ultra-high-definition video hardware processing technology, and more specifically, to a multi-bus decoupled distributed embedded hardware rendering architecture, system, and method. Background Technology

[0002] Ultra-high definition (4K / 8K) technology is rapidly becoming widespread in the audiovisual industry. Key application scenarios such as live sports events, large-scale cultural performances, converged media studios, and command center large screens have widely adopted multi-source heterogeneous signal hybrid access modes such as SDI, ST2110, and NVI, which places extremely high demands on the performance, scalability, and reliability of hardware rendering architecture.

[0003] Currently, the mainstream industry adopts a centralized embedded hardware rendering architecture, which relies on a single chip or board to complete the entire signal processing process. Existing few improvement solutions only optimize the single bus bandwidth or general module splitting, failing to fundamentally solve the core problems of the hardware architecture. Specifically, the main problems include: (1) In the centralized architecture, the processing capacity of a single chip or board has an inherent upper limit, making it difficult to support multi-channel parallel rendering of ultra-high-definition signals, which easily leads to insufficient computing power and cannot meet the needs of multi-task parallel processing; (2) When adding signal input channels or production channels, the entire hardware equipment needs to be replaced, lacking modular stacking capabilities, resulting in high expansion costs, extended deployment cycles, and inability to adapt to dynamic changes in business; (3) The existing bus design adopts a single-bus multi-task sharing mode, with broadcast, pre-monitoring, and monitoring tasks competing for bus resources, and there is no physical isolation mechanism. A single point of failure may cause the entire system to be paralyzed, resulting in low reliability; (4) Existing hardware modules are only split based on general functions, lacking differentiated design for the large audiovisual industry, and modules cannot achieve seamless cascading. When adding modules, the system performance cannot be linearly improved, resulting in low hardware resource utilization.

[0004] The aforementioned hardware architecture deficiencies make traditional solutions ill-suited for the hardware demands of next-generation ultra-high-definition video production. Therefore, the industry urgently needs a distributed embedded hardware rendering architecture that can achieve performance stacking, possesses high reliability, and supports flexible scalability. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a distributed embedded hardware rendering architecture, system, and method with multi-bus decoupling. By adopting the physical isolation of multi-bus decoupling modules and the flexible cascading design of modular processing units, the centralized processing mode that relies on a single chip or single board is fundamentally abandoned. The overall processing task is decomposed into multiple independent modular processing units for parallel execution, and the addition of modular processing units can directly improve the overall computing power of the system.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: Firstly, a distributed embedded hardware rendering architecture with multi-bus decoupling is provided, including: The multi-bus decoupling module includes multiple physically isolated hardware buses, each of which is a dedicated hardware transmission link for carrying a single type of production task. Multiple modular processing units with different functions, each of which is an independent hardware board and integrates an external signal input port, an upstream bus signal input port and a downstream bus signal output port; The modular processing units are cascaded sequentially through the corresponding hardware buses in the multi-bus decoupling module to form a distributed pipeline rendering link. When a new modular processing unit is added, the overall signal processing capability and rendering compositing capability of the system increase linearly with the increase in the number of modular processing units.

[0007] Furthermore, the multiple hardware buses adopt an independent routing design in hardware, and there is no data interaction between the multiple hardware buses; Furthermore, each of the aforementioned hardware buses integrates a hardware synchronization calibration unit, which achieves multi-bus signal synchronization through hardware logic of same-source clock distribution and frame header alignment.

[0008] Furthermore, the multiple functionally differentiated modular processing units include at least two of the following: a basic input processing unit, a basic rendering processing unit, and a core professional rendering processing unit. The basic input processing unit is used to convert received external multi-source heterogeneous signals into a unified baseband signal within the architecture. The basic rendering processing unit is used to perform basic rendering processing on the received baseband signal; The core professional rendering processing unit is used to perform high-level professional rendering processing on the received baseband signal or file stream.

[0009] Furthermore, the basic input processing unit hardware integrates at least one of the following: SDI, ST2110, NVI, NDI and SRT signal input interfaces; The basic rendering processing unit hardware integrates at least one of SDI, NVI, NDI and SRT signal input interfaces, and is equipped with a basic rendering hardware module for realizing color space conversion, switching, digital video effects, mixing, cropping or multi-screen overlay. The core professional rendering processing unit hardware integrates at least one of SDI and audio / video file input interfaces, and is equipped with a professional rendering hardware module for signal switching, keying, downstream keying, digital video effects, mixing, cropping, or multi-screen overlay.

[0010] Furthermore, the hardware circuits and functional modules of the modular processing unit are designed differently according to their processing functions.

[0011] Furthermore, the architecture supports distributing the processed signal to multiple corresponding downstream hardware buses for parallel processing via a single signal input from the modular processing unit.

[0012] Furthermore, the multiple hardware buses mentioned include the broadcast PGM bus, the preview PVW bus, and the multi-view MV bus.

[0013] Secondly, a slow-motion and highlight replay system is provided, employing a multi-bus decoupled distributed embedded hardware rendering architecture as described in any one of the first aspects, including: At least one basic rendering processing unit has an external signal input port for receiving external camera signals, and its upstream bus signal input port and downstream bus signal output port are respectively connected to the MV bus to realize signal recording and MV bus multi-screen basic rendering. At least one first core professional rendering processing unit, which accesses file storage through a 10 Gigabit Ethernet interface, and whose upstream bus signal input port is connected to the PGM bus and MV bus, is used to realize video file decoding, speed processing and multi-screen overlay rendering. At least one second core professional rendering processing unit accesses file storage via a 10 Gigabit Ethernet interface. Its upstream bus signal input port is connected to the PGM bus and MV bus, and its downstream bus signal output port is connected to the PGM broadcast output interface and MV monitoring output interface. This unit is used to realize multi-screen decoding of files, multi-screen fusion rendering with MV bus signals, and final signal output.

[0014] Thirdly, a large-format multi-screen splicing system is provided, employing a multi-bus decoupled distributed embedded hardware rendering architecture as described in any one of the first aspects, including: Multiple basic input processing units are used to receive ST2110 signals; At least one basic rendering processing unit is used to receive SDI, NVI and network stream signals and perform image stitching processing; At least one core professional rendering processing unit is used to receive files and perform multi-channel multi-screen bus splicing and screen splicing output processing. The multi-bus decoupling module has four hardware buses.

[0015] Fourthly, a multi-bus decoupled distributed embedded hardware rendering method is provided, applied to a multi-bus decoupled distributed embedded hardware rendering architecture as described in any one of the first aspects, the method comprising: Signals are transmitted via multiple physically isolated hardware buses, each of which is dedicated to carrying a single type of production task. The signal is processed in a distributed pipeline manner through multiple modular processing units with different functions, wherein each modular processing unit is an independent hardware board that can be freely combined and cascaded. When a new modular processing unit is added, it is cascaded into a link composed of multiple hardware buses, thereby linearly improving the overall signal processing and rendering synthesis capabilities of the system.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention proposes a multi-bus decoupled distributed embedded hardware rendering architecture. This architecture, by adopting the physical isolation of multi-bus decoupling modules and the flexible cascading design of modular processing units, fundamentally abandons the centralized processing mode that relies on a single chip or single board. It decomposes the overall processing task into multiple independent modular processing units for parallel execution. The addition of modular processing units can directly improve the overall computing power of the system, thereby fundamentally solving the performance bottleneck problem of traditional architectures when processing 4K / 8K ultra-high definition and multi-channel rendering. This allows the system's processing power to be linearly and stacked according to business needs.

[0017] 2. This invention employs multiple physically isolated and independently routed hardware buses to ensure complete decoupling of data streams for different tasks such as broadcasting, pre-monitoring, and monitoring at the transport layer, avoiding resource contention. Simultaneously, each modular processing unit is designed as an independent hardware board. This design ensures that when a single hardware bus or modular processing unit fails, the fault can be strictly isolated, preventing impact on other tasks or modules. This solves the reliability problem of "single point of failure leading to complete system paralysis" in traditional shared bus architectures, guaranteeing the security and continuity of core services, especially the live broadcast link.

[0018] 3. This invention breaks down the system into modular processing units with differentiated functions (e.g., a basic input processing unit for input, a basic rendering processing unit for basic rendering, and a core professional rendering processing unit for professional rendering). Users can freely select and combine the required modules according to actual application scenarios (such as simple switching, complex graphic packaging, or slow-motion playback). When it is necessary to expand the number of signal channels or processing capabilities, only the corresponding hardware boards need to be added and cascaded into the system, without replacing or reconstructing the entire hardware platform. This design effectively solves the problems of poor scalability, high cost, and long cycle time of traditional architecture.

[0019] 4. This invention supports the replication and distribution of a single signal input to multiple different downstream hardware buses after passing through the processing unit, enabling subsequent parallel processing. This avoids the waste of interface and internal processing resources caused by repeated acquisition and access of the same source signal. At the same time, each modular processing unit integrates multiple industry standard interfaces such as SDI, ST2110, NVI, NDI, and SRT, solving the adaptation problem in mixed access scenarios of multi-source heterogeneous signals, thereby achieving efficient utilization of hardware resources and broad compatibility.

[0020] 5. This invention can be specifically applied to optimized systems for complex scenarios such as slow-motion playback and ultra-high resolution splicing. For example, by decomposing the recording, playback, and broadcasting processes into parallel execution on basic rendering processing units and core professional rendering processing units connected by different buses, safe and efficient collaboration between multi-channel high bitrate recording and real-time slow-motion processing is achieved, solving the hardware implementation problems required for high performance, high reliability, and complex concurrent processes in professional scenarios. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings: Figure 1 This is an overall hardware structure diagram of Embodiment 1 of the present invention; Figure 2 This is an overall hardware structure diagram of Embodiment 2 of the present invention; Figure 3 This is an overall hardware structure diagram of Embodiment 3 of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0023] Example 1: A distributed embedded hardware rendering architecture with multi-bus decoupling, such as Figure 1As shown, the architecture includes a multi-bus decoupling module and multiple modular processing units with differentiated functions. The core technical features of the architecture are multi-bus physical isolation and modular cascading performance stacking. The number of modular processing units can be flexibly expanded, unrestricted by hardware architecture. Each modular processing unit achieves signal-isolated cascading transmission through the multi-bus decoupling module to complete distributed pipelined rendering processing. Each modular processing unit integrates external signal input ports, upstream bus signal input ports, and downstream bus signal output ports, supporting unlimited cascading expansion at the hardware level. This ensures the system has high scalability and stability when facing high concurrency and multi-task rendering requirements.

[0024] The multi-bus decoupling module comprises multiple physically isolated hardware buses, each serving as a dedicated hardware transmission link for a single type of production task. This module employs an independent wiring design, utilizing shielding isolation and differential signal transmission techniques to effectively avoid crosstalk and resource contention between buses, ensuring that various tasks operate independently without interference. For example, the three-bus architecture for slow-motion and highlight replay applications includes: a program bus (PGM) for broadcasters, a preview bus (PVW), and a multi-view bus (MV). Each bus can be independently configured with bandwidth and protocol to adapt to the real-time requirements of different production scenarios.

[0025] like Figure 1 As shown, the system includes multiple modular processing units such as A0, A1, R0, R1, and M0. Each modular processing unit with different functions is an independent hardware board. Each board integrates external signal input ports, upstream bus signal input ports, and downstream bus signal output ports. The hardware circuits and functional modules of each board are designed differently according to processing requirements, and can be selected and combined as needed. Different levels of modular processing units can be selected according to the complexity of live broadcast production to achieve an optimized balance between cost and performance.

[0026] It should be noted that AMD cards can use graphics cards with dedicated graphics chips, NVIDIA cards can use RTX series graphics cards, and AMD cards can use mobile graphics cards.

[0027] Multiple modular processing units are cascaded sequentially through corresponding hardware buses in a multi-bus decoupling module, forming a distributed pipeline rendering link. When a new modular processing unit is added, the overall signal processing and rendering / compositing capabilities of the system increase linearly with the number of units. The hardware cascading and performance stacking logic manifests as follows: multiple sets of basic input processing units, basic rendering processing units, and core professional rendering processing units are cascaded in parallel through hardware buses. New units are directly connected to the link through expansion ports, resulting in a linearly stacked increase in system processing capacity with no performance ceiling. This logic is adaptable to complex scenarios such as live broadcasts of large-scale sports events and multi-channel program production, effectively overcoming the performance bottlenecks of traditional centralized architectures while reducing system latency and single-point-of-failure risks.

[0028] Traditional modular cascading relies on external interfaces for signal transmission. Each additional unit introduces signal conversion loss, leading to increased latency and performance degradation with each cascaded unit, making linear performance stacking impossible. To address this, this invention achieves hardware cascading of modular processing units through a multi-bus decoupling module, overcoming the performance loss challenges of cascading. Units utilize direct bus connection hardware logic, eliminating the need for external interface conversion and resolving the performance degradation problem inherent in traditional cascading.

[0029] Multiple hardware buses employ independent routing at the physical layer, with no data exchange between them. This ensures complete decoupling of various production tasks during transmission, avoiding performance degradation or signal conflicts caused by bus contention. Furthermore, considering the potential for inconsistent signal delays between different buses in a physically isolated multi-bus design (e.g., the PGM broadcast signal and the PVW preview signal being out of sync), a hardware synchronization calibration unit is integrated into each hardware bus. Through clock distribution from the same source and frame header alignment hardware logic, multi-bus signal synchronization is achieved, resolving the core contradiction between physical isolation and synchronization.

[0030] The modular processing units with multiple functional differences include at least two of the following: basic input processing unit, basic rendering processing unit, and core professional rendering processing unit.

[0031] The basic input processing unit is used to convert received external multi-source heterogeneous signals into a unified baseband signal within the architecture. For example, the A card's basic input processing unit is a pure hardware input conversion board, integrating multiple signal input interfaces such as SDI (Serial Digital Interface), ST2110 (IP-based Real-Time Media Transfer Protocol), NVI (Network Video Interface), NDI (Network Device Interface), and SRT (Secure and Reliable Transmission Protocol). Its core hardware circuitry completes the conversion of various input signals into an internally unified format baseband signal, serving as the basic input hardware of the architecture. This unit can support emerging signal protocols through firmware upgrades, ensuring input compatibility and future scalability.

[0032] The basic rendering processing unit is used to perform basic rendering processing on the received baseband signals. It is a basic hardware rendering board that integrates SDI, NVI, NDI, and SRT input interfaces. It is equipped with basic rendering hardware modules such as signal color space conversion and switching, DVE (Digital Video Effects), MIX (mixing), cropping, and multi-screen overlay. It can receive upstream bus baseband signals, complete basic rendering according to the corresponding bus requirements through hardware logic, and then distribute them to the corresponding downstream bus links. It supports real-time processing of low-latency rendering tasks, such as simple image and text overlay and scene switching.

[0033] The core professional rendering processing unit performs high-level professional rendering processing on received baseband signals or file streams. It is a core hardware rendering board, integrating SDI and audio / video file input interfaces. It features advanced professional rendering hardware modules such as signal switching, MIX (mixing), DVE (digital video effects), KEY (keying), DSK (downstream keying), cropping, and multi-screen overlay. This dedicated core hardware for high-complexity live broadcast production can receive upstream bus baseband signals, perform professional-grade rendering according to the corresponding bus requirements through hardware logic, and then distribute the rendering to the corresponding downstream bus links. This unit supports advanced effects such as 3D transitions, real-time keying, and dynamic graphics rendering, meeting the needs of professional broadcast-grade production.

[0034] The hardware circuits and functional modules of the modular processing unit are designed differently according to their processing functions. For example, power consumption and performance are optimized through application-specific integrated circuits or programmable logic devices to ensure that each unit works efficiently and collaboratively in the cascaded system.

[0035] This architecture supports distributing the processed signal to multiple downstream corresponding hardware buses for parallel processing through a single signal input from a modular processing unit, thereby achieving multi-output synchronous rendering and improving production efficiency.

[0036] Multiple hardware buses include the PGM bus for broadcasters, the PVW bus for previewers, and the MV bus for multi-view monitors. Auxiliary buses, such as recording buses or streaming media output buses, can also be added as needed to support more complex multi-tasking parallel production workflows.

[0037] Example 2: A slow-motion and highlight replay system based on a multi-bus decoupled distributed embedded hardware rendering architecture as described in Example 1. Figure 2 As shown, the system includes a basic rendering processing unit, a first core professional rendering processing unit, and a second core professional rendering processing unit.

[0038] The basic rendering processing unit is equipped with an external signal input port for receiving signals from external cameras; its upstream bus signal input port and downstream bus signal output port are respectively connected to the MV bus to realize signal recording and MV bus multi-screen basic rendering functions.

[0039] The first core professional rendering processing unit accesses the file storage system through a 10 Gigabit network interface. Its upstream bus signal input port is connected to the PGM bus and MV bus, and it is responsible for video file decoding, speed processing, and multi-screen overlay rendering.

[0040] The second core professional rendering processing unit also accesses the file storage system through a 10 Gigabit network interface. Its upstream bus signal input port is connected to the PGM bus and MV bus, while its downstream bus signal output port is connected to the PGM broadcast output interface and MV monitoring output interface. This is used to realize multi-screen decoding of files, multi-screen fusion rendering with MV bus signals, and to complete the final signal output.

[0041] This system employs a dual-channel slow-motion and highlight playback processing workflow: R cards handle signal recording and basic rendering processing such as multi-screen stitching; each processing group contains multiple R cards (R0, R1, R2, R3) and one M card. For example, the first processing group, Group0, is configured with R0, R1, R2, R3, and M0 cards, while the second processing group, Group1, is configured with R0, R1, R2, R3, and M1 cards. ch0-F and ch1-F are the two inputs to the slow-motion / fast-motion video compression streams, respectively, while ch0-MV-F and ch1-MV-F are the two inputs to the multi-screen compression streams, respectively. The M0 card is responsible for dual-channel file decoding and playback, slow-motion algorithm processing, and multi-screen stitching; the M1 card performs multi-screen file decoding, multi-screen fusion with the signal, and bus output functions. The entire system works in coordination based on three hardware buses: MV, PGM0, and PGM1. ch0-MV and ch1-MV are the two outputs of the MV hardware bus, ch0-PGM is the output of the PGM0 hardware bus, and ch1-PGM is the output of the PGM1 hardware bus.

[0042] Multiple signals from external cameras are connected to the external signal input port of the R card via a hardware SDI interface. Numbers ①-⑧ in the diagram represent hardware SDI interfaces. Both the M0 and M1 cards access the file storage system via a 10 Gigabit network interface. The downstream bus signal output port of the M1 card is hardware-connected to the PGM0 and PGM1 broadcast output interfaces and the MV monitoring output interface, respectively. The processing cards are interconnected via the MV, PGM0, and PGM1 hardware buses.

[0043] R-card functions: It completes the baseband format unification and synchronization calibration of camera signals through hardware circuitry; it realizes high and low bit rate signal recording using a hardware recording module; it completes the basic rendering of MV bus multi-screen overlay through a basic rendering hardware module, and uses the hardware bus to copy and transmit MV bus signals to the next-level processing card.

[0044] M0 card functions: It decodes dual-channel video files through a hardware decoding module; it uses a variable-speed rendering hardware module to achieve fast and slow playback speed processing; it transmits the processed signal to the subsequent processing unit through the PGM0 and PGM1 hardware buses; it overlays multiple screens according to the screen layout and copies the MV bus signal to the next-level processing card through the MV hardware bus.

[0045] M1 Card Functions: It completes multi-screen decoding of dual-channel files through the hardware decoding module, and performs multi-screen fusion with the MV bus signal according to application instructions. The fusion rendering module realizes high-level rendering of dual-channel multi-screen fusion. Finally, it outputs standardized MV monitoring signals and PGM0 and PGM1 broadcast signals through the hardware output interface.

[0046] The system has good scalability: if more camera access signals are needed, only an R-card hardware board needs to be added, and the overall hardware processing capability of the system can be synchronously and linearly improved.

[0047] Example 3: An ultra-large format multi-screen splicing system, based on a multi-bus decoupled distributed embedded hardware rendering architecture as described in Example 1, such as... Figure 3 As shown, it mainly consists of a basic input processing unit, a basic rendering processing unit, and a core professional rendering processing unit.

[0048] The basic input processing unit is responsible for receiving ST2110 signals; the basic rendering processing unit is used to receive SDI, NVI, and network stream signals, and perform image stitching processing; the core professional rendering processing unit is used to receive files, and perform multi-channel multi-screen bus stitching and image stitching output processing. The multi-bus decoupling module contains four hardware buses.

[0049] The system uses multiple A cards to achieve basic ST2110 signal access, R cards for SDI, NVI and network stream signal access and video splicing, and M cards for file access, multi-channel multi-screen bus splicing and video splicing output.

[0050] Taking the first processing group Group0 as an example, A card is A0, R card consists of three cards: R0, R1, and R2, and M card is M0.

[0051] The system supports stitching together four 4K images or stitching together a single 8K image.

[0052] Example 4: A distributed embedded hardware rendering method based on multi-bus decoupling. This method is applied to a multi-bus decoupling distributed embedded hardware rendering architecture as described in Example 1, and includes the following steps: (1) Signal transmission is carried out through multiple physically isolated hardware buses, each of which is dedicated to carrying a single type of rendering task data; (2) The signal is processed in a distributed pipeline by using multiple modular processing units with heterogeneous functions. Each modular processing unit is an independent hardware board that can be flexibly combined and cascaded. (3) When it is necessary to expand the system's processing capacity, the overall signal processing and rendering synthesis capabilities of the system can be linearly improved by connecting and cascading the newly added modular processing units into the transmission link composed of multiple hardware buses.

[0053] Working principle: This invention, by adopting the physical isolation of multi-bus decoupling modules and the flexible cascading design of modular processing units, fundamentally abandons the centralized processing mode that relies on a single chip or single board. It decomposes the overall processing task into multiple independent modular processing units for parallel execution. The addition of modular processing units can directly improve the overall computing power of the system, thereby fundamentally solving the performance bottleneck problem of traditional architecture in processing 4K / 8K ultra-high definition and multi-channel rendering. This allows the system's processing power to be improved linearly and in a stacked manner according to business needs.

[0054] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0055] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0056] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0057] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0058] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A distributed embedded hardware rendering architecture with multi-bus decoupling, characterized in that, include: The multi-bus decoupling module includes multiple physically isolated hardware buses, each of which is a dedicated hardware transmission link for carrying a single type of production task. Multiple modular processing units with different functions, each of which is an independent hardware board and integrates an external signal input port, an upstream bus signal input port and a downstream bus signal output port; The modular processing units are cascaded sequentially through the corresponding hardware buses in the multi-bus decoupling module to form a distributed pipeline rendering link. When a new modular processing unit is added, the overall signal processing capability and rendering and compositing capability of the system increase linearly with the increase in the number of the modular processing units.

2. The distributed embedded hardware rendering architecture with multi-bus decoupling according to claim 1, characterized in that, The multiple hardware buses are designed with independent wiring in the hardware, and there is no data interaction between the multiple hardware buses; Furthermore, each of the aforementioned hardware buses integrates a hardware synchronization calibration unit, which achieves multi-bus signal synchronization through hardware logic of same-source clock distribution and frame header alignment.

3. The distributed embedded hardware rendering architecture with multi-bus decoupling according to claim 1, characterized in that, The multiple functionally differentiated modular processing units include at least two of the following: basic input processing unit, basic rendering processing unit, and core professional rendering processing unit; The basic input processing unit is used to convert received external multi-source heterogeneous signals into a unified baseband signal within the architecture. The basic rendering processing unit is used to perform basic rendering processing on the received baseband signal; The core professional rendering processing unit is used to perform high-level professional rendering processing on the received baseband signal or file stream.

4. The distributed embedded hardware rendering architecture with multi-bus decoupling according to claim 3, characterized in that, The basic input processing unit hardware integrates at least one of the following: SDI, ST2110, NVI, NDI and SRT signal input interfaces; The basic rendering processing unit hardware integrates at least one of SDI, NVI, NDI and SRT signal input interfaces, and is equipped with a basic rendering hardware module for realizing color space conversion, switching, digital video effects, mixing, cropping or multi-screen overlay. The core professional rendering processing unit hardware integrates at least one of SDI and audio / video file input interfaces, and is equipped with a professional rendering hardware module for signal switching, keying, downstream keying, digital video effects, mixing, cropping, or multi-screen overlay.

5. The distributed embedded hardware rendering architecture with multi-bus decoupling according to claim 1, characterized in that, The hardware circuits and functional modules of the modular processing unit are designed differently according to their processing functions.

6. The distributed embedded hardware rendering architecture with multi-bus decoupling according to claim 1, characterized in that, The architecture supports distributing the processed signal to multiple corresponding downstream hardware buses for parallel processing through a single signal input from the modular processing unit.

7. A multi-bus decoupled distributed embedded hardware rendering architecture according to any one of claims 1-6, characterized in that, The aforementioned hardware buses include the broadcast PGM bus, the preview PVW bus, and the multi-view MV bus.

8. A slow-motion and highlight replay system, characterized in that, The application of a multi-bus decoupled distributed embedded hardware rendering architecture as described in any one of claims 1-7 includes: At least one basic rendering processing unit has an external signal input port for receiving external camera signals, and its upstream bus signal input port and downstream bus signal output port are respectively connected to the MV bus to realize signal recording and MV bus multi-screen basic rendering. At least one first core professional rendering processing unit, which accesses file storage through a 10 Gigabit Ethernet interface, and whose upstream bus signal input port is connected to the PGM bus and MV bus, is used to realize video file decoding, speed processing and multi-screen overlay rendering. At least one second core professional rendering processing unit accesses file storage via a 10 Gigabit Ethernet interface. Its upstream bus signal input port is connected to the PGM bus and MV bus, and its downstream bus signal output port is connected to the PGM broadcast output interface and MV monitoring output interface. This unit is used to realize multi-screen decoding of files, multi-screen fusion rendering with MV bus signals, and final signal output.

9. A large-format multi-screen splicing system, characterized in that, The application of a multi-bus decoupled distributed embedded hardware rendering architecture as described in any one of claims 1-7 includes: Multiple basic input processing units are used to receive ST2110 signals; At least one basic rendering processing unit is used to receive SDI, NVI and network stream signals and perform image stitching processing; At least one core professional rendering processing unit is used to receive files and perform multi-channel multi-screen bus splicing and screen splicing output processing. The multi-bus decoupling module has four hardware buses.

10. A distributed embedded hardware rendering method with multi-bus decoupling, characterized in that, Applied to a multi-bus decoupled distributed embedded hardware rendering architecture as described in any one of claims 1-7, the method includes: Signals are transmitted via multiple physically isolated hardware buses, each of which is dedicated to carrying a single type of production task. The signal is processed in a distributed pipeline manner through multiple modular processing units with different functions, wherein each modular processing unit is an independent hardware board that can be freely combined and cascaded. When a new modular processing unit is added, it is cascaded into a link composed of multiple hardware buses, thereby linearly improving the overall signal processing and rendering synthesis capabilities of the system.

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