Chip visualization method, apparatus, device, and storage medium

Abstract

The application discloses a chip visualization method, device, equipment and storage medium. The method comprises the following steps: acquiring internal resources of a chip; drawing graphics corresponding to the internal resources of the chip in turn according to the sizes of the internal resources of the chip from large to small; updating the number of the internal resources of the chip that have been drawn after drawing the graphics corresponding to one internal resource of the chip; and stopping drawing the graphics corresponding to the internal resources of the chip when the number of drawing elements of the internal resources of the chip that have been drawn exceeds a preset threshold value, so as to obtain a GUI corresponding to the chip. By giving priority to the resources with large sizes, the performance bottleneck in the existing drawing method is overcome when drawing very complex internal resources of the chip, the GUI drawing of the chip is prevented from being stuck without affecting the user experience, the GUI is quickly drawn, and the efficiency of drawing the GUI of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of image visualization technology, and in particular to a chip visualization method, device, equipment and storage medium. Background Art

[0002] Chip visualization can be used for chip browsing and resource constraints. As development demands, devices are becoming larger and larger, and the internal resources of chips are becoming increasingly abundant. However, with the increase in internal chip resources, existing chip visualization methods can cause lag when operating the chip's GUI when drawing internal chip resources, and the chip's GUI drawing is inefficient. Summary of the Invention

[0003] Based on this, the present invention provides a chip visualization method, device, equipment and storage medium, which solve the problems of interface freeze and low efficiency of drawing chip GUI during chip visualization.

[0004] The present invention provides a chip visualization method, comprising:

[0005] Obtain chip internal resources;

[0006] Draw graphics corresponding to the chip internal resources in descending order according to the sizes of the chip internal resources;

[0007] After each graphic corresponding to a chip's internal resources is drawn, the number of currently drawn chip internal resources is updated;

[0008] When the number of drawing elements of the currently drawn chip internal resources exceeds a preset threshold, the drawing of the graphics corresponding to the chip internal resources is stopped, and the GUI corresponding to the chip is obtained; wherein, the drawing elements include the number of times the resource shape is drawn, the number of times the resource name is drawn, and the background color of the filled resource.

[0009] Furthermore, after the step of acquiring the chip internal resources and before the step of drawing graphics corresponding to the chip internal resources in descending order of size, the method further includes:

[0010] Sort the internal resources of the chip in descending order according to size;

[0011] The sorted chip internal resources are stored in the data structure.

[0012] Furthermore, before the step of sorting the internal resources of the chip in descending order of size, the method further includes:

[0013] Modeling a chip and classifying internal resources of the chip;

[0014] According to the classification results, obtain the resource quantity, name and distribution of each type of resources;

[0015] Determine the text length of each resource in each resource type based on the name of the resource type, and obtain the size and distribution of each resource in each resource type.

[0016] Furthermore, the step of drawing graphics corresponding to the chip internal resources in descending order of size of the chip internal resources includes:

[0017] Determine the proportion of each resource type in the canvas based on the number of resources in that resource type;

[0018] Determine the location of each type of resource in the canvas based on its distribution;

[0019] Determine the size of each resource in the resource canvas of each resource type according to the size of each resource in the resource type;

[0020] Determine the position of each resource in the resource canvas of each category according to the distribution of each resource in the category;

[0021] Use the drawing tools to draw graphics corresponding to the size of each resource's canvas based on the shape, text, and background color of each resource at the canvas location where each resource is located.

[0022] Furthermore, the chip modeling and chip resource classification according to the modeling results include:

[0023] Convert the chip into data that can be recognized by the drawing tool according to preset rules;

[0024] The internal resources of the chip are classified according to their functions.

[0025] Furthermore, the drawing tool is based on QPainter in the Qt library.

[0026] Furthermore, the preset threshold is determined by the following method:

[0027] Get historical chip internal resource information;

[0028] Draw the internal resources of historical chips in descending order of their size. When the GUI of the drawn historical chip freezes, record the number of internal resources drawn.

[0029] A preset threshold is determined according to the drawing element of the drawn internal resource quantity.

[0030] The present invention also provides a chip visualization device, comprising:

[0031] Acquisition module, used to obtain internal resources of the chip;

[0032] A graphics drawing module, configured to draw graphics corresponding to the chip internal resources in descending order of size;

[0033] The quantity update module is used to update the quantity of the currently drawn chip internal resources after each graphic corresponding to the chip internal resources is drawn;

[0034] A detection module is used to stop drawing the graphics corresponding to the chip internal resources when the number of drawing elements of the currently drawn chip internal resources exceeds a preset threshold, thereby obtaining a GUI corresponding to the chip; wherein the drawing elements are the number of times the resource shape is drawn, the number of times the resource name is drawn, and the background color of the filled resource.

[0035] The present invention also provides a chip visualization device, comprising:

[0036] processor;

[0037] a memory comprising one or more computer program modules;

[0038] The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include modules for implementing any of the above-mentioned methods.

[0039] The present invention also provides a storage medium for storing non-transitory computer-readable instructions, which can implement any of the above-mentioned methods when executed by a computer.

[0040] The chip visualization method disclosed in the present invention updates the number of currently drawn chip internal resources by drawing graphics corresponding to the chip internal resources in order from large to small according to the size of the chip internal resources; then compares the drawing elements of the currently drawn number of chip internal resources with a preset threshold. If the drawing elements of the currently drawn number of chip internal resources exceed the preset threshold, the drawing of the graphics corresponding to the chip internal resources is stopped, and the GUI corresponding to the chip is obtained. If it does not exceed the preset threshold, the next chip internal resource is drawn. The above method overcomes the performance bottleneck of the existing drawing method when drawing very complex chip internal resources by giving priority to resources with large resource sizes. Without affecting the user experience, it avoids the occurrence of freezes when drawing the chip GUI, realizes fast GUI drawing, and improves the efficiency of drawing the chip GUI. The present invention also provides a chip visualization device, equipment and storage medium, which can also achieve the above effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A schematic diagram of a chip visualization method according to an embodiment of the present invention;

[0043] Figure 2 A structural block diagram of a chip visualization device provided by an embodiment of the present invention;

[0044] Figure 3 A schematic structural diagram of a chip visualization device provided by an embodiment of the present invention;

[0045] Figure 4 A computer storage medium is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0047] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] In order to make the purpose, technical solutions and advantages of this application more clear, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] In the following description, use of suffixes such as “module,” “part,” or “unit” to refer to elements is merely for facilitating description of the present application, and has no specific meaning by itself.

[0050] like Figure 1 FIG. 1 is a flow chart of a chip visualization method provided by an embodiment of the present invention, wherein the method includes:

[0051] Step S1: Obtain chip internal resources;

[0052] The present application uses an FPGA as an example to illustrate the various internal resources available for user configuration, including: ① Programmable Input / Output Blocks (IOBs). To facilitate management and adapt to various electrical standards, FPGA IOBs are divided into several groups (banks). The interface standard of each bank is determined by its interface voltage (VCCO). A bank can only have one VCCO, but different banks can have different VCCOs. Only interfaces with the same electrical standard can be connected together. ② Configurable Logic Blocks (CLBs). CLBs are the basic logic units within an FPGA. The actual number and characteristics of CLBs vary depending on the device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, some selection circuits (MUXs), and flip-flops. ③ Digital Clock Management Modules (DCMs). DCMs can divide and multiply clock frequencies and maintain the phase relationship between clocks, i.e., zero clock skew. ④ Embedded Block RAM (BRAM). BRAMs offer high flexibility and can be configured as common storage structures such as single-port RAM, dual-port RAM, content-addressable memory (CAM), and FIFO. ⑤ Abundant wiring resources. These resources connect all units within the FPGA, and the length and process of the wiring determine the signal driving capability and transmission speed along the wiring. ⑥ Low-level embedded functional units. These embedded functional modules primarily refer to soft processing cores such as DLLs (Delay Locked Loops), PLLs (Phase Locked Loops), DSPs, and CPUs. ⑦ Embedded dedicated hard cores. These are equivalent to ASIC circuits, as opposed to the soft cores migrated into the low-level architecture. To improve FPGA performance, chip manufacturers integrate specialized hard cores within their chips.

[0053] When obtaining the internal resources of the chip, you can directly obtain them from the chip design and production party, or read them directly from the chip.

[0054] In some embodiments, the method further includes: modeling the chip and classifying internal resources of the chip;

[0055] Specifically, the chip is converted into data that can be recognized by the drawing tool according to the preset rules; and the chip's internal resources are classified according to their functions. In actual applications, after obtaining the chip's internal resources, a script is designed according to the set conversion rules to convert the chip's internal resources into data that can be recognized by the drawing tool. And the converted data is divided into different types according to the functions of the chip's internal resources, such as APM, CLMA, CLMS, DRM36K and IO. At the same time, the number of resources, resource names and resource distribution in each type of resource in the classification results are obtained, the text length of each resource in each type of resource is determined according to the name of each type of resource, and the size and distribution of each resource in each type of resource are obtained. The following table is a resource comparison table for chip 1 and chip 2, where "30->11520" in the number of resources indicates the change in the number of resources from chip 1 to chip 2:

[0056] Resource Type Number of resources Resource size APM 30->11520 (140#900)->(140#900) CLMA 3274->138240 (160#320)->(160#320) CLMS 2220->136800 (160#320)->(160#320) DRM36K 0->1080 (140#1200) IO 300->1180 (160#320)->(160#320)

[0057] Furthermore, the method further includes: sorting the chip internal resources in descending order according to size; and storing the sorted chip internal resources in a data structure.

[0058] Specifically, after obtaining the internal resources of the chip, they are sorted from large to small according to their sizes, that is, they are sorted in descending order according to their sizes, with the largest size at the front and the smallest size at the end, and then the modeled data corresponding to the internal resources of the chip are stored in a data structure, such as in a sequence.

[0059] Resources are sorted by size. This takes advantage of the difference in scaling between the logical window and the viewport. When the viewport size remains unchanged, the larger the scaling ratio, the larger the resources within the viewport, and the fewer resources there are within the viewport. Conversely, when the viewport size remains unchanged, the scaling ratio constrains the smaller the resources within the viewport, and the more resources there are within the viewport. Therefore, in this application, when the number of drawing resources is fixed and the viewport remains unchanged, resources with larger drawing resource sizes are prioritized, so as not to affect the overall GUI diagram of the chip.

[0060] Step S2: drawing graphics corresponding to the chip internal resources in descending order according to the sizes of the chip internal resources;

[0061] Preferably, the drawing tool used in the embodiment of the present application to draw graphics corresponding to internal chip resources is QPainter based on the Qt library. Qt provides a powerful 2D drawing system that can use the same API to draw on the screen and drawing devices. It is mainly based on the three classes of QPainter, QPaintDevice and QPaintEngine. QPainter is used to perform drawing operations, and the API it provides displays graphics (lines, shapes, gradients, etc.), text and images in the GUI or QImage, QOpenGLPaintDevice, QWidget and QPaintDevice. QPaintDevice does not directly draw the physical display screen, but uses the intermediary of the logical interface. For example, when drawing a rectangular graphic, in order to draw the object between multiple interfaces such as QWidget, QGLPixelBuffer, QImage, QPixmap, QPicture, etc., QPaintDevice must be used. QPaintEngine provides some interfaces that can be used by QPainter to draw on different devices. The drawing system uses QPainter to complete specific drawing operations, and the QPainter class provides a large number of highly optimized functions to complete most of the drawing work required for GUI programming. It can draw all the graphics you want, from the simplest straight line to any other complex graphics, such as: points, lines, rectangles, arcs, pie charts, polygons, Bezier arcs, etc. In addition, QPainter also supports some advanced features, such as anti-aliasing (for text and graphic edges), pixel blending, gradient fills and vector paths, etc. QPainter also supports linear transformations, such as translation, rotation, and scaling.

[0062] When drawing a graph, an index is taken from the end of the data structure where the chip internal resource size is larger, and a graph corresponding to the chip internal resource is drawn.

[0063] Specifically, step S2 includes:

[0064] Determine the proportion of each type of resources in the canvas based on the number of resources in that type of resources; determine the position of each type of resources in the canvas based on the distribution of each type of resources; determine the size of each resource in the canvas of that type of resources based on the size of each resource in each type of resources; determine the position of each resource in the canvas of that type of resources based on the distribution of each resource in each type of resources; use drawing tools to draw graphics corresponding to the size of each resource canvas based on the shape, text and background color of each resource at the canvas location where each resource is located.

[0065] Specifically, after obtaining the chip's internal resources, the total number of resources is known. Then, based on the classification results, the number of resources in each resource category is determined. During drawing, the total canvas size is known, and the proportion of each resource category's resources in the canvas is calculated as the proportion of the total number of resources in each resource category. Based on the distribution of each resource category and the correspondence between the set resource distribution and the position on the canvas, the position of each resource category in the canvas is determined. Through these steps, the size and distribution of each resource category in the canvas are determined. Drawing each resource is then performed, and the size of each resource in the canvas is determined based on the size of each resource in that category. That is, once the number of resources in each resource category is known, the size of all resources in that category is known. The size of the canvas corresponding to each resource in that category is determined based on the proportion of the resource's size to the size of all resources in that category. The position of each resource in the canvas is then determined based on the distribution of each resource in the category. QPainter is then used to draw a graphic corresponding to the size of each resource's canvas, based on the resource's shape, text, and background color. For example, the number of times a CLMA resource is drawn is 148 edges, 88 letters, and the background color.

[0066] Step S3: After each graphic corresponding to a chip internal resource is drawn, the number of currently drawn chip internal resources is updated;

[0067] Specifically, after drawing a chip internal resource, the number of currently drawn chip internal resources is updated.

[0068] Step S4: When the number of drawing elements of the currently drawn chip internal resources exceeds a preset threshold, stop drawing the graphics corresponding to the chip internal resources and obtain the GUI corresponding to the chip; wherein the drawing elements include the number of times the resource shape is drawn, the number of times the resource name is drawn, and the background color of the filled resource.

[0069] Specifically, each time the internal resources of a chip are drawn, the number of the internal resources of the chip that have been drawn is updated, and then the drawing elements of the internal resources of the chip, including the number of times the shapes of these resources are drawn, the number of times the names of these resources are drawn, and the background color of these resources is updated to see whether they have exceeded the preset threshold. If not, the internal resources of the next chip are drawn. If so, the drawing is stopped to obtain the GUI corresponding to the chip.

[0070] In some embodiments, the preset threshold is determined by the following method:

[0071] Obtain internal resource information of the historical chip; draw the internal resources of the historical chip from large to small according to the size of the internal resources of the historical chip, and when the GUI of the drawn historical chip freezes, record the number of internal resources that have been drawn; determine a preset threshold value based on the drawing elements of the number of internal resources that have been drawn.

[0072] Specifically, in practical applications, whether the chip GUI is stuck can be determined based on the user's requirements for the smoothness of the GUI, and the preset threshold can be flexibly adjusted.

[0073] The chip visualization method disclosed in an embodiment of the present invention updates the number of currently drawn chip internal resources by drawing graphics corresponding to the chip internal resources in order from large to small according to the size of the chip internal resources; then compares the drawing elements of the currently drawn number of chip internal resources with a preset threshold. If the drawing elements of the currently drawn number of chip internal resources exceed the preset threshold, the drawing of the graphics corresponding to the chip internal resources is stopped, and the GUI corresponding to the chip is obtained. If it does not exceed the preset threshold, the next chip internal resource is drawn. The above method overcomes the performance bottleneck of existing drawing methods when drawing very complex chip internal resources by giving priority to resources with large resource sizes. Without affecting the user experience, it avoids the occurrence of freezes when drawing the chip GUI, realizes fast GUI drawing, and improves the efficiency of drawing chip GUI.

[0074] like Figure 2 FIG. 2 is a block diagram of a chip visualization apparatus 200 according to an embodiment of the present invention. The apparatus 200 includes:

[0075] An acquisition module 201 is used to acquire chip internal resources; a graphics drawing module 202 is used to draw graphics corresponding to chip internal resources in sequence according to the sizes of the chip internal resources from large to small; a quantity update module 203 is used to update the number of currently drawn chip internal resources each time a graphic corresponding to a chip internal resource is drawn; a detection module 204 is used to stop drawing graphics corresponding to chip internal resources when the number of drawing elements of the currently drawn chip internal resources exceeds a preset threshold, and obtain a GUI corresponding to the chip; wherein the drawing elements are the number of times the resource shape is drawn, the number of times the resource name is drawn, and the background color of the fill resource.

[0076] In some embodiments, the apparatus 200 further includes:

[0077] The sorting module is used to sort the internal resources of the chip in descending order according to size; and store the sorted internal resources of the chip in a data structure.

[0078] In some embodiments, the apparatus 200 further includes:

[0079] The modeling module is used to model the chip and classify the internal resources of the chip; based on the classification results, the resource quantity, name and distribution of each type of resources are obtained; based on the name of each type of resources, the text length of each resource in the resource class is determined, and the size and distribution of each resource in each type of resources are obtained.

[0080] In some embodiments, the graphics drawing module 202 is also used to determine the proportion of resources of each type in the canvas based on the number of resources in each type of resource; determine the position of resources of each type in the canvas based on the distribution of resources of each type; determine the size of each resource in the canvas of resources of this type based on the size of each resource in each type of resource; determine the position of each resource in the canvas of resources of this type based on the distribution of each resource in each type of resource; use a drawing tool to draw a graphic corresponding to the size of each resource canvas based on the shape, text and background color of each resource at the canvas position where each resource is located.

[0081] In some embodiments, the modeling module is further used to convert the chip into data that can be recognized by the drawing tool according to preset rules; and classify the internal resources of the chip according to their functions.

[0082] In some embodiments, the apparatus 200 further includes:

[0083] A threshold setting module is used to obtain internal resource information of historical chips; draw the internal resources of historical chips from large to small according to the size of the internal resources of historical chips, and when the GUI of the drawn historical chips freezes, record the number of internal resources that have been drawn; and determine the preset threshold based on the drawing elements of the number of internal resources that have been drawn.

[0084] See also Figure 3 , Figure 3 FIG. 3 is a schematic diagram of the structure of a chip visualization device 300 disclosed in an embodiment of the present invention. Figure 3 As shown, the chip visualization device may include:

[0085] Processor 301;

[0086] Memory 302, including one or more computer program modules;

[0087] The one or more computer program modules are stored in the memory 302 and configured to be executed by the processor 301 , and the one or more computer program modules include modules for implementing any of the above-mentioned methods.

[0088] See also Figure 4 , an embodiment of the present invention discloses a computer storage medium 401 for storing non-transitory computer-readable instructions, which can implement any of the above-mentioned methods when executed by a computer.

[0089] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0090] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip visualization method, characterized in that: The method comprises: Obtain chip internal resources; Draw graphics corresponding to the chip internal resources in descending order according to the sizes of the chip internal resources; After each graphic corresponding to a chip's internal resources is drawn, the number of currently drawn chip internal resources is updated; When the number of drawing elements of the currently drawn chip internal resources exceeds a preset threshold, the drawing of the graphics corresponding to the chip internal resources is stopped, and the GUI corresponding to the chip is obtained; wherein, the drawing elements include the number of times the resource shape is drawn, the number of times the resource name is drawn, and the number of times the background color of the resource is filled is drawn.

2. The chip visualization method according to claim 1, characterized in that After the step of acquiring the chip internal resources and before the step of drawing graphics corresponding to the chip internal resources in descending order of size, the method further includes: Sort the internal resources of the chip in descending order according to size; The sorted chip internal resources are stored in the data structure.

3. The chip visualization method according to claim 2, characterized in that: Before the step of sorting the internal resources of the chip in descending order of size, the method further includes: Modeling a chip and classifying internal resources of the chip; According to the classification results, obtain the resource quantity, name and distribution of each type of resources; Determine the text length of each resource in each resource type based on the name of the resource type, and obtain the size and distribution of each resource in each resource type.

4. The chip visualization method according to claim 3, characterized in that: Drawing graphics corresponding to the chip internal resources in descending order of size of the chip internal resources includes: Determine the proportion of each resource type in the canvas based on the number of resources in that resource type; Determine the location of each type of resource in the canvas based on its distribution; Determine the size of each resource in the resource canvas of each resource type according to the size of each resource in the resource type; Determine the position of each resource in the resource canvas of each category according to the distribution of each resource in the category; Use the drawing tools to draw graphics corresponding to the size of each resource's canvas based on the shape, text, and background color of each resource at the canvas location where each resource is located.

5. The chip visualization method according to claim 3, characterized in that: Modeling the chip and classifying chip resources according to the modeling results include: Convert the chip into data that can be recognized by the drawing tool according to preset rules; The internal resources of the chip are classified according to their functions.

6. The chip visualization method according to any one of claims 4-5, characterized in that: The drawing tool is based on QPainter in the Qt library.

7. The chip visualization method according to claim 1, characterized in that: The preset threshold is determined by the following method: Get historical chip internal resource information; Draw the internal resources of historical chips in descending order of their size. When the GUI of the drawn historical chip freezes, record the number of internal resources drawn. A preset threshold is determined according to the drawing element of the drawn internal resource quantity.

8. A chip visualization device, characterized in that: The device comprises: Acquisition module, used to obtain internal resources of the chip; A graphics drawing module, configured to draw graphics corresponding to the chip internal resources in descending order of size; The quantity update module is used to update the quantity of the currently drawn chip internal resources after each graphic corresponding to the chip internal resources is drawn; A detection module is used to stop drawing the graphics corresponding to the chip internal resources when the number of drawing elements of the currently drawn chip internal resources exceeds a preset threshold, thereby obtaining a GUI corresponding to the chip; wherein the drawing elements are the number of times the resource shape is drawn, the number of times the resource name is drawn, and the number of times the background color of the fill resource is drawn.

9. A chip visualization device comprising: processor; a memory comprising one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include modules for implementing the method according to any one of claims 1 to 7.

10. A storage medium for storing non-transitory computer-readable instructions, wherein when the non-transitory computer-readable instructions are executed by a computer, the method according to any one of claims 1 to 7 can be implemented.

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