Pixel circuit, display panel and display device

Abstract

The present invention discloses a pixel circuit, a display panel and a display device, including a data writing circuit and a driving transistor; the data writing circuit includes: a first data writing transistor, a second data writing transistor and a distributed capacitor; the gate of the first data writing transistor is coupled to the first scanning signal end, the gate of the second data writing transistor is coupled to the second scanning signal end, the first electrode of the first data writing transistor is coupled to the data line, the second electrode of the first data writing transistor is coupled to the first electrode of the second data writing transistor, and the second electrode of the second data writing transistor is coupled to the first electrode of the driving transistor; the first electrode of the distributed capacitor is coupled to the second electrode of the first data writing transistor, and the second electrode of the distributed capacitor is coupled to the fixed voltage signal end.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] Electroluminescent diodes (ELDs), such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), and micro-LEDs, offer advantages such as self-luminescence and low energy consumption, making them a hot topic in current research on the application of ELDs. Pixel circuits are typically used in ELDs to drive ELDs to emit light. Summary of the Invention

[0003] The pixel circuit provided by the embodiment of the present invention includes a data writing circuit and a driving transistor;

[0004] The data writing circuit includes: a first data writing transistor, a second data writing transistor and a distributed capacitor;

[0005] The gate of the first data writing transistor is coupled to the first scan signal terminal, the gate of the second data writing transistor is coupled to the second scan signal terminal, the first electrode of the first data writing transistor is coupled to the data line, the second electrode of the first data writing transistor is coupled to the first electrode of the second data writing transistor, and the second electrode of the second data writing transistor is coupled to the first electrode of the driving transistor;

[0006] A first electrode of the distributed capacitor is coupled to the second electrode of the first data writing transistor, and a second electrode of the distributed capacitor is coupled to a fixed voltage signal terminal.

[0007] In some possible implementations, the first scan signal terminal transmits a first scan signal, the second scan signal terminal transmits a second scan signal, and an effective level of the first scan signal does not overlap with an effective level of the second scan signal.

[0008] In some possible implementations, the duration of the effective level of the first scanning signal is longer than the duration of the effective level of the second scanning signal.

[0009] In some possible implementations, the pixel circuit further includes an initialization circuit, a threshold compensation circuit, and a light emitting control circuit;

[0010] The initialization circuit is configured to initialize the gate of the driving transistor under the control of the signal of the first reset signal terminal, and initialize the anode of the light emitting device under the control of the signal of the second reset signal terminal;

[0011] The threshold compensation circuit is configured to compensate the threshold voltage of the driving transistor under the control of the signal of the third scanning signal terminal;

[0012] The light emitting control circuit is configured to connect the first power supply terminal to the first electrode of the driving transistor and connect the second electrode of the driving transistor to the anode of the light emitting device under the control of the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

[0013] In some possible implementations, the initialization circuit includes: a first transistor, a second transistor;

[0014] The gate of the first transistor is coupled to the first reset signal terminal, the first electrode of the first transistor is coupled to the first initial voltage signal terminal, and the second electrode of the first transistor is coupled to the gate of the driving transistor;

[0015] The gate of the second transistor is coupled to the second reset signal terminal, the first electrode of the second transistor is coupled to the second initial voltage signal terminal, and the second electrode of the second transistor is coupled to the anode of the light emitting device.

[0016] In some possible implementations, the first reset signal terminal and the second reset signal terminal are different signal terminals;

[0017] The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

[0018] In some possible implementations, the threshold compensation circuit includes: a storage capacitor and a third transistor;

[0019] A first electrode of the storage capacitor is coupled to the gate of the driving transistor, and a second electrode of the storage capacitor is coupled to the first power supply terminal;

[0020] The gate of the third transistor is coupled to the third scan signal terminal, the first electrode of the third transistor is coupled to the second electrode of the driving transistor, and the second electrode of the third transistor is coupled to the gate of the driving transistor.

[0021] The light emitting control circuit includes: a first light emitting transistor and a second light emitting transistor;

[0022] The gate of the first light emitting transistor is coupled to the light emitting control signal terminal, the first electrode of the first light emitting transistor is coupled to the first power supply terminal, and the second electrode of the first light emitting transistor is coupled to the first electrode of the driving transistor;

[0023] The gate of the second light emitting transistor is coupled to the light emitting control signal terminal, the first electrode of the second light emitting transistor is coupled to the second electrode of the driving transistor, and the second electrode of the second light emitting transistor is coupled to the anode of the light emitting device.

[0024] In some possible implementations, in the above-mentioned pixel circuit, the third scanning signal terminal transmits a third scanning signal, and a duration of an effective level of the third scanning signal is greater than a duration of an effective level of the second scanning signal.

[0025] In some possible implementations, the pixel circuit further includes: a noise reduction circuit;

[0026] The noise reduction circuit is configured to provide the signal of the fixed voltage signal terminal to the first electrode of the driving transistor under the control of the signal of the noise reduction signal terminal.

[0027] In some possible implementations, the noise reduction circuit includes a fourth transistor;

[0028] A gate of the fourth transistor is coupled to the noise reduction signal terminal, a first electrode of the fourth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the fixed voltage signal terminal.

[0029] In some possible implementations, the noise reduction signal terminal and the second reset signal terminal are the same signal terminal.

[0030] An embodiment of the present invention further provides a display panel including the above-mentioned pixel circuit.

[0031] In some possible implementations, the display panel includes a plurality of sub-pixels and a plurality of data lines;

[0032] Each of the sub-pixels includes the pixel circuit;

[0033] One column of sub-pixels corresponds to two data lines;

[0034] The pixel circuits of the sub-pixels in the odd-numbered rows in a column are coupled to one of the corresponding two data lines, and the pixel circuits of the sub-pixels in the even-numbered rows are coupled to the other of the corresponding two data lines.

[0035] An embodiment of the present invention further provides a display device including the above-mentioned display panel.

[0036] In some possible implementations, the driving method of the pixel circuit includes: a data writing stage, an initialization stage, a threshold compensation stage, and a light emitting stage;

[0037] In the data writing phase, the first data writing transistor inputs the data voltage on the coupled data line into the distributed capacitor;

[0038] In the initialization phase, the initialization circuit initializes the gate of the driving transistor under the control of the signal of the first reset signal terminal, and initializes the anode of the light-emitting device under the control of the signal of the second reset signal terminal;

[0039] In the threshold compensation stage, the second data writing transistor inputs the data voltage stored in the distributed capacitance into the gate of the driving transistor and compensates for the threshold voltage of the driving transistor;

[0040] In the light-emitting stage, the light-emitting control circuit, under the control of the signal of the light-emitting control signal terminal, connects the first power supply terminal to the first electrode of the driving transistor, and connects the second electrode of the driving transistor to the anode of the light-emitting device, thereby driving the light-emitting device to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagrams of some structures of pixel circuits in embodiments of the present invention;

[0042] Figure 2a are other structural schematic diagrams of pixel circuits in embodiments of the present invention;

[0043] Figure 2b 1 are further structural schematic diagrams of pixel circuits in embodiments of the present invention;

[0044] Figure 3a are further structural schematic diagrams of display panels in embodiments of the present invention;

[0045] Figure 3b are further structural schematic diagrams of display panels in embodiments of the present invention;

[0046] Figure 4 is a flow chart of a driving method of a pixel circuit in an embodiment of the present invention;

[0047] Figure 5 are some signal timing diagrams in embodiments of the present invention;

[0048] Figure 6 are other signal timing diagrams according to embodiments of the present invention;

[0049] Figure 7 Some signal timing diagrams in the embodiments of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0052] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0053] The display device provided by the embodiment of the present invention may include a display panel. The display panel may include a substrate. The substrate may include a display area and a non-display area (i.e., an area in the substrate except for the area surrounded by the display area). The display area may include a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0054] In an embodiment of the present invention, each sub-pixel may include a pixel circuit and a light-emitting device coupled to the pixel circuit. The pixel circuit may include a driving transistor to control the light-emitting device to emit light, thereby enabling the display panel to display images. Due to factors such as process and aging, the threshold voltage Vth of the driving transistor may drift, affecting the generated drive current and resulting in poor display quality. Therefore, compensation for the threshold voltage Vth of the driving transistor is required. However, existing technologies employ compensation for the threshold voltage Vth simultaneously with data charging, resulting in slow compensation and charging speeds, making it unsuitable for high-frequency circuits.

[0055] Based on this, an embodiment of the present invention provides a pixel circuit, such as Figure 1 As shown, the device includes a driving transistor M0 and a data write circuit 10. The data write circuit 10 is coupled to the driving transistor M0, a fixed voltage signal terminal REF, a data voltage terminal DA, a first scan signal terminal SS1, and a second scan signal terminal SS2. The driving transistor M0 can be configured to generate a current that drives the light-emitting device L to emit light based on the data voltage. The data write circuit 10 can be configured to input the data voltage in response to a loaded signal.

[0056] In the embodiment of the present invention, Figure 1 As shown, the data write circuit 10 includes: a first data write transistor M1, a second data write transistor M2 and a distributed capacitor C1; wherein, the gate of the first data write transistor M1 is coupled to the first scan signal terminal SS1, the gate of the second data write transistor M2 is coupled to the second scan signal terminal SS2, the first electrode of the first data write transistor M1 is coupled to the data voltage terminal DA, the second electrode of the first data write transistor M1 is coupled to the first electrode of the second data write transistor M2, and the second electrode of the second data write transistor M2 is coupled to the first electrode of the driving transistor M0; the first electrode of the distributed capacitor C1 is coupled to the second electrode of the first data write transistor M1, and the second electrode of the distributed capacitor C1 is coupled to the fixed voltage signal terminal REF.

[0057] Exemplarily, the first data write transistor M1 can be turned on under the control of the effective level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the ineffective level of the first scan signal. For example, the first data write transistor M1 can be set as a P-type transistor, then the effective level of the first scan signal is a low level, and the ineffective level of the first scan signal is a high level. Alternatively, the first data write transistor M1 can also be set as an N-type transistor, then the effective level of the first scan signal is a high level, and the ineffective level of the first scan signal is a low level. And the first electrode of the first data write transistor M1 can be its source, and the second electrode of the first data write transistor M1 can be its drain, or the first electrode of the first data write transistor M1 can be its drain, and the second electrode of the first data write transistor M1 can be its source.

[0058] Exemplarily, the second data write transistor M2 can be turned on under the control of the effective level of the second scan signal transmitted on the second scan signal terminal SS2, and can be turned off under the control of the ineffective level of the second scan signal. For example, the second data write transistor M2 can be set as a P-type transistor, then the effective level of the second scan signal is a low level, and the ineffective level of the second scan signal is a high level. Alternatively, the second data write transistor M2 can also be set as an N-type transistor, then the effective level of the second scan signal is a high level, and the ineffective level of the second scan signal is a low level. And the first electrode of the second data write transistor M2 can be its source, and the second electrode of the second data write transistor M2 can be its drain, or the first electrode of the second data write transistor M2 can be its drain, and the second electrode of the second data write transistor M2 can be its source.

[0059] For example, within the refresh range of a display frame, the effective level of the first scanning signal and the effective level of the second scanning signal do not overlap. Non-overlapping means that the first data write transistor M1 and the second data write transistor M2 are not turned on at the same time, thereby further improving compensation and charging speeds.

[0060] For example, within the refresh range of a display frame, the duration of the effective level of the first scanning signal is greater than the duration of the effective level of the second scanning signal, that is, the conduction time of the first data writing transistor M1 is greater than the conduction time of the second data writing transistor M2, so that the data signal can be fully written and stored in the distributed capacitor C1.

[0061] The pixel circuit provided by an embodiment of the present invention, by providing a first data write transistor, a second data write transistor, and a distributed capacitor in the data write circuit, can first input the data voltage on the data line into the distributed capacitor before compensating the threshold voltage Vth of the drive transistor, charge the distributed capacitor with data, and store the data voltage in the distributed capacitor. Subsequently, the threshold voltage Vth compensation process is performed using the data voltage stored in the distributed capacitor, achieving time-sharing of threshold voltage Vth compensation and data charging. This eliminates the need for threshold voltage Vth compensation, allowing more time for compensation, improving the compensation effect, and enhancing the display quality at low grayscales.

[0062] In some embodiments of the present invention, Figure 1 As shown, the driving transistor M0 can be configured as a P-type transistor; wherein the first electrode of the driving transistor M0 can be its source, the second electrode of the driving transistor M0 can be its drain, and when the driving transistor M0 is in a saturated state, current flows from the source of the driving transistor M0 to its drain. Of course, the driving transistor M0 can also be configured as an N-type transistor, which is not limited here.

[0063] Furthermore, the light-emitting device L generally emits light under the action of the current when the driving crystal M0 is in a saturated state. Of course, in the embodiments of the present invention, the driving crystal M0 is only described as a P-type transistor. If the driving crystal M0 is an N-type transistor, the design principle is the same as the present invention and also falls within the scope of protection of the present invention.

[0064] In the pixel circuit provided by the embodiment of the present invention, Figure 1 As shown, the pixel circuit further includes: an initialization circuit 20, a threshold compensation circuit 30, and a light emitting control circuit 40;

[0065] The initialization circuit 20 is respectively coupled to the first reset signal terminal CS1, the first initial voltage signal terminal VINIT1, the second reset signal terminal CS2, the second initial voltage signal terminal VINIT2, the gate of the driving transistor M0, and the anode of the light-emitting device L. The initialization circuit 20 is configured to be coupled to the first reset signal terminal CS1 and initialize the gate of the driving transistor M0 under the control of the signal of the first reset signal terminal CS1; and to be coupled to the second reset signal terminal CS2 and initialize the anode of the light-emitting device L under the control of the signal of the second reset signal terminal CS2.

[0066] The threshold compensation circuit 30 is coupled to the third scan signal terminal SS3, the first power supply terminal VDD, and the gate and second electrodes of the driving transistor M0. The threshold compensation circuit 30 is configured to be coupled to the third scan signal terminal SS3 and, under the control of the signal at the third scan signal terminal SS3, compensate the threshold voltage Vth of the driving transistor M0.

[0067] The light emitting control circuit 40 is respectively coupled to the first power supply terminal VDD, the first electrode and the second electrode of the driving transistor M0, and the light emitting device L. The light emitting control circuit 40 is configured to be coupled to the light emitting signal terminal EM. Under the control of the signal of the light emitting control signal terminal EM, the first power supply terminal VDD is electrically connected to the first electrode of the driving transistor M0, and the second electrode of the driving transistor M0 is electrically connected to the anode of the light emitting device L, thereby driving the light emitting device L to emit light.

[0068] In some embodiments of the present invention, Figure 2a and 2b As shown, the initialization circuit 20 includes: a first transistor M3 and a second transistor M4; wherein, the gate of the first transistor M3 is coupled to the first reset signal terminal CS1, the first electrode of the first transistor M3 is coupled to the first initial voltage signal terminal VINIT1, and the second electrode of the first transistor M3 is coupled to the gate of the driving transistor M0; the gate of the second transistor M4 is coupled to the second reset signal terminal CS2, the first electrode of the second transistor M4 is coupled to the second initial voltage signal terminal VINIT2, and the second electrode of the second transistor M4 is coupled to the anode of the light-emitting device L.

[0069] For example, the first transistor M3 can be turned on under the control of the active level of the first reset signal transmitted on the first reset signal terminal CS1, and can be turned off under the control of the inactive level of the first reset signal. For example, the first transistor M3 is configured as an N-type transistor, and the active level of the first reset signal is a high level, and the inactive level of the first reset signal is a low level.

[0070] For example, the second transistor M4 can be turned on under the control of the active level of the second reset signal transmitted on the second reset signal terminal CS2, and can be turned off under the control of the inactive level of the second reset signal. For example, the second transistor M4 is configured as a P-type transistor, and the active level of the second reset signal is a low level, and the inactive level of the second reset signal is a high level.

[0071] In some embodiments of the present invention, Figure 2a and 2b As shown, the first reset signal terminal CS1 coupled to the first transistor M3 and the second reset signal terminal CS2 coupled to the second transistor M4 can be different signal terminals. For example, the first reset signal terminal CS1 and the second reset signal terminal CS2 can be loaded with different signals.

[0072] In specific implementation, in the embodiment of the present invention, as Figure 2a and 2b As shown, the first transistor M3 is configured as an N-type transistor, wherein the first electrode of the first transistor M3 serves as its drain and the second electrode of the first transistor M3 serves as its source, or the first electrode of the first transistor M3 serves as its source and the second electrode of the first transistor M3 serves as its drain.

[0073] The second transistor M4 is configured as a P-type transistor, wherein the first electrode of the second transistor M4 serves as its drain and the second electrode of the second transistor M4 serves as its source, or the first electrode of the second transistor M4 serves as its source and the second electrode of the second transistor M4 serves as its drain.

[0074] In some embodiments of the present invention, Figure 2a and 2b As shown, the threshold compensation circuit 30 includes: a storage capacitor C2 and a third transistor M5; wherein, the first electrode of the storage capacitor C2 is coupled to the gate of the driving transistor M0, and the second electrode of the storage capacitor C2 is coupled to the first power supply terminal VDD; the gate of the third transistor M5 is coupled to the third scan signal terminal SS3, the first electrode of the third transistor M5 is coupled to the second electrode of the driving transistor M0, and the second electrode of the third transistor M5 is coupled to the gate of the driving transistor M0.

[0075] Exemplarily, the third transistor M5 can be turned on under the control of the effective level of the third scan signal transmitted on the third scan signal terminal SS3, and can be turned off under the control of the inactive level of the third scan signal. For example, the third transistor M5 can be set as a P-type transistor, then the effective level of the third scan signal is a low level, and the inactive level of the third scan signal is a high level. Alternatively, the third transistor M5 can also be set as an N-type transistor, then the effective level of the third scan signal is a high level, and the inactive level of the third scan signal is a low level. Wherein, the first electrode of the third transistor M5 serves as its drain, and the second electrode of the third transistor M5 serves as its source, or the first electrode of the third transistor M5 serves as its source, and the second electrode of the third transistor M5 serves as its drain.

[0076] Exemplarily, the duration of the effective level of the third scan signal is longer than the duration of the effective level of the second scan signal, that is, the on-time of the third transistor M5 is longer than the on-time of the second data writing transistor M2.

[0077] In some embodiments of the present invention, Figure 2a and 2bAs shown, the light-emitting control circuit 40 includes: a first light-emitting transistor M6 and a second light-emitting transistor M7; wherein, the gate of the first light-emitting transistor M6 is coupled to the light-emitting control signal terminal EM, the first electrode of the first light-emitting transistor M6 is coupled to the first power supply terminal VDD, and the second electrode of the first light-emitting transistor M6 is coupled to the first electrode of the driving transistor M0; the gate of the second light-emitting transistor M7 is coupled to the light-emitting control signal terminal EM, the first electrode of the second light-emitting transistor M7 is coupled to the second electrode of the driving transistor M0, and the second electrode of the second light-emitting transistor M7 is coupled to the anode of the light-emitting device L.

[0078] For example, the first light-emitting transistor M6 and the second light-emitting transistor M7 can be turned on under the control of the active level of the light-emitting control signal transmitted on the light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the first light-emitting transistor M6 and the second light-emitting transistor M7 can be configured as P-type transistors, in which case the active level of the light-emitting control signal is a low level, and the inactive level of the light-emitting control signal is a high level. Alternatively, the first light-emitting transistor M6 and the second light-emitting transistor M7 can be configured as N-type transistors, in which case the active level of the light-emitting control signal is a high level, and the inactive level of the light-emitting control signal is a low level.

[0079] The first electrode of the first light-emitting transistor M6 serves as its drain, and the second electrode of the first light-emitting transistor M6 serves as its source, or the first electrode of the first light-emitting transistor M6 serves as its source, and the second electrode of the first light-emitting transistor M6 serves as its drain. The first electrode of the second light-emitting transistor M7 serves as its drain, and the second electrode of the second light-emitting transistor M7 serves as its source, or the first electrode of the second light-emitting transistor M7 serves as its source, and the second electrode of the second light-emitting transistor M7 serves as its drain.

[0080] In some embodiments of the present invention, the anode of the light-emitting device L can be coupled to the second electrode of the second light-emitting transistor M7, and the cathode of the light-emitting device L can be coupled to the second power supply terminal VSS. Exemplarily, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L can include: a micro light-emitting diode (Micro Light Emitting Diode, MicroLED), an organic electroluminescent diode (Organic Light Emitting Diode, OLED) and a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED) at least one. Exemplarily, the light-emitting device L can include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application, and is not limited here.

[0081] The embodiments of the present invention provide some pixel circuits, such as Figure 2b As shown, the present invention further includes a noise reduction circuit 50, wherein the noise reduction circuit 50 is coupled to the driving transistor M0, the fixed voltage signal terminal REF, and the noise reduction signal terminal CS3. The noise reduction circuit 50 is configured to provide the signal of the fixed voltage signal terminal REF to the first electrode of the driving transistor M0 under the control of the signal of the noise reduction signal terminal CS3.

[0082] In some embodiments of the present invention, Figure 2b As shown, the noise reduction circuit 50 includes a fourth transistor M8; wherein the gate of the fourth transistor M8 is coupled to the noise reduction signal terminal CS3, the first electrode of the fourth transistor M8 is coupled to the first electrode of the driving transistor M0, and the second electrode of the fourth transistor M8 is coupled to the fixed voltage signal terminal REF. Exemplarily, the first electrode of the fourth transistor M8 serves as its drain and the second electrode of the fourth transistor M8 serves as its source, or the first electrode of the fourth transistor M8 serves as its source and the second electrode of the fourth transistor M8 serves as its drain.

[0083] Exemplarily, the noise reduction signal terminal CS3 and the second reset signal terminal CS2 may be the same signal terminal, so as to reduce the number of signal terminals and reduce the difficulty of signal line layout.

[0084] Of course, the noise reduction signal terminal CS3 and the second reset signal terminal CS2 may also be independent signal terminals, which is not limited here.

[0085] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0086] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, in order to reduce leakage current, in some embodiments of the present invention, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0087] For example, all transistors can be set as LTPS transistors. Alternatively, all transistors can be set as oxide transistors. Alternatively, some transistors can be set as oxide transistors, and the remaining transistors can be set as LTPS transistors. By combining the two processes for preparing transistors, LTPS transistors and oxide transistors, to prepare an LTPO pixel circuit of low-temperature polysilicon oxide, the leakage current of the gate of the driving transistor M0 can be reduced, and the power consumption can be lowered. Thus, the pixel circuit is applied to a display panel, and when the display panel reduces the refresh frequency for display, the uniformity of the display can be guaranteed.

[0088] Illustratively, in an embodiment of the present invention, N-type transistors (e.g., the first transistor M3, the third transistor M5) can be set as LTPS-type transistors, and P-type transistors (e.g., the first data write transistor M1, the second data write transistor M2, the second transistor M4, the first light-emitting transistor M6, the second light-emitting transistor M7, the fourth transistor M8) can be set as oxide-type transistors.

[0089] In some embodiments of the present invention, the first power supply terminal VDD can be configured to load a constant first power supply voltage, and the first power supply voltage is generally positive. And the second power supply terminal VSS can be configured to load a constant second power supply voltage, and the second power supply voltage is generally a ground voltage or a negative value. For example, Figure 1 In the illustrated embodiment, the first power supply terminal VDD can be loaded with a constant first power supply voltage Vdd, which is a positive voltage. The second power supply terminal VSS can be loaded with a constant second power supply voltage Vss, which is a negative voltage or grounded. In actual applications, the specific values ​​of the first power supply voltage and the second power supply voltage can be designed and determined based on the actual application environment and are not limited here.

[0090] The above is merely an example to illustrate the specific structure of each circuit in the pixel circuit provided by the embodiment of the present invention. In specific implementation, the specific structure of the above circuit is not limited to the above structure provided by the embodiment of the present invention, and can also be other structures known to those skilled in the art. These are all within the scope of protection of the present invention and are not specifically limited here.

[0091] In an embodiment of the present invention, a display panel provided by the embodiment of the present invention includes a plurality of sub-pixels and a plurality of data lines, each sub-pixel includes a pixel circuit, a column of sub-pixels corresponds to at least two data lines, and the pixel circuit of some sub-pixels in a column is coupled to one of the corresponding at least two data lines. Exemplarily, a column of sub-pixels corresponds to two data lines; the pixel circuits of the sub-pixels in odd-numbered rows in a column are coupled to one of the corresponding two data lines, and the pixel circuits of the sub-pixels in even-numbered rows are coupled to the other of the corresponding two data lines.

[0092] In the embodiment of the present invention, Figure 3a and 3b As shown, the pixel circuits of the odd-numbered rows of sub-pixels (such as Figure 3a and 3b The data voltage terminal of Row1 (or the first electrode of the first data writing transistor M1) is coupled to the data line DA1, and the pixel circuits of the even-numbered sub-pixels (such as Figure 3a and 3b The data voltage terminal of Row2 (or the first electrode of the first data writing transistor M1) is coupled to the data line DA2. It should be noted that Row1 and Row2 represent the pixel circuits of the first and second rows of sub-pixels in the same column.

[0093] The above-mentioned display panel provided by the embodiment of the present application can realize a refresh process with a high refresh frequency. Especially for large-size display panels. For example, a 32-inch 6K display panel with a refresh frequency of 240Hz has as many as 3000 rows of sub-pixels, and the refresh time of 1 row of sub-pixels is 1H=1 / 240 / 3000=1.38us. Taking into account the RC delay on the data line (i.e. RC Delay), the display panel in the prior art is difficult to meet the 240Hz data charging. In order to solve this problem, the embodiment of the present invention combines the pixel circuit of the present invention with the dual data lines to realize 2H charging, which increases the charging time from the original 1.38us to 2.76us. Moreover, the pre-charging method of the pixel circuit provided by the embodiment of the present invention is further combined to enable 240Hz to be achieved.

[0094] In the embodiment of the present invention, Figure 4 As shown, the driving method of the pixel circuit provided by the embodiment of the present invention may include the following steps:

[0095] S100, data writing stage, the first data writing transistor inputs the data voltage on the coupled data line into the distributed capacitor;

[0096] S200, in an initialization stage, the initialization circuit initializes the gate of the driving transistor under the control of the signal of the first reset signal terminal, and initializes the anode of the light-emitting device under the control of the signal of the second reset signal terminal;

[0097] S300, threshold compensation stage: the second data writing transistor inputs the data voltage stored in the distributed capacitor into the gate of the driving transistor and compensates for the threshold voltage of the driving transistor;

[0098] S400, light-emitting stage, the light-emitting control circuit, under the control of the signal of the light-emitting control signal terminal, connects the first power supply terminal to the first electrode of the driving transistor, and connects the second electrode of the driving transistor to the anode of the light-emitting device, driving the light-emitting device to emit light.

[0099] Below is Figure 2b As an example, the pixel circuit shown in the figure is combined with Figure 5 The signal timing diagram shown in FIG. 1 describes the working process of the pixel circuit provided by the embodiment of the present invention.

[0100] Among them, such as Figure 5 As shown, em represents the light-emitting control signal of the light-emitting control signal terminal EM, ss1 represents the first scanning signal of the first scanning signal terminal SS1, ss2 represents the second scanning signal of the second scanning signal terminal SS2, ss3 represents the third scanning signal of the third scanning signal terminal SS3, cs1 represents the first reset signal of the first reset signal terminal CS1, cs2 represents the second reset signal of the second reset signal terminal CS2, and cs3 represents the noise reduction signal of the noise reduction signal terminal CS3.

[0101] Furthermore, a data writing phase T1 , an initialization phase T2 , a threshold compensation phase T3 and a light emitting phase T4 in a display frame are selected.

[0102] During the data writing phase T1, the first data writing transistor M1 is turned on by the low level of the first scanning signal ss1. The second data writing transistor M2 is turned off by the high level of the second scanning signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned off by the low level of the third scanning signal ss3. The first light-emitting transistor M6 is turned on by the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on by the low level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. The turned-on first data writing transistor M1 inputs the data voltage Vda applied to the data voltage terminal DA into the first electrode of the distributed capacitor C1, thereby charging the distributed capacitor C1.

[0103] During the initialization phase T2, the first data write transistor M1 is turned off in response to the high level of the first scan signal ss1. The second data write transistor M2 is turned off in response to the high level of the second scan signal ss2. The first transistor M3 is turned on in response to the high level of the first reset signal cs1. The second transistor M4 is turned on in response to the low level of the second reset signal cs2. The third transistor M5 is turned off in response to the low level of the third scan signal ss3. The first light-emitting transistor M6 is turned off in response to the high level of the light-emitting control signal em. The second light-emitting transistor M7 is turned off in response to the high level of the light-emitting control signal em. The fourth transistor M8 is turned on in response to the low level of the noise reduction signal cs3. The turned-on first transistor M3 inputs the first initialization voltage of the first initialization voltage signal terminal VINIT1 to the gate of the driving transistor M0, thereby initializing the gate of the driving transistor M0. The turned-on second transistor M4 inputs the second initialization voltage of the second initialization voltage signal terminal VINIT2 to the anode of the light-emitting device L, thereby initializing the anode of the light-emitting device L. The turned-on fourth transistor M8 provides the signal of the fixed voltage signal terminal REF to the first electrode of the driving transistor M0 , thereby initializing the first electrode of the driving transistor M0 .

[0104] During the threshold compensation phase T3, the first data write transistor M1 is turned off by the high level of the first scan signal ss1. The second data write transistor M2 is turned on by the low level of the second scan signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned on by the high level of the third scan signal ss3. The first light-emitting transistor M6 is turned off by the high level of the light-emitting control signal em. The second light-emitting transistor M7 is turned off by the high level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. The turned-on second data write transistor M2 inputs the data voltage Vda stored in the distributed capacitor C1 into the first electrode of the drive transistor M0. Since the third transistor M5 is turned on, the driving transistor M0 can be connected in a diode manner. Therefore, the data voltage Vda input to the first electrode of the driving transistor M0 can pass through the driving transistor M0 in a diode-connected manner and be input to the gate of the driving transistor M0, and the threshold voltage Vth of the driving transistor M0 can be compensated so that the gate voltage of the driving transistor M0 is Vda+Vth.

[0105] In the light-emitting stage T4, the first data writing transistor M1 is turned off under the control of the high level of the first scanning signal ss1. The second data writing transistor M2 is turned off under the control of the high level of the second scanning signal ss2. The first transistor M3 is turned off under the control of the low level of the first reset signal cs1. The second transistor M4 is turned off under the control of the high level of the second reset signal cs2. The third transistor M5 is turned off under the control of the low level of the third scanning signal ss3. The first light-emitting transistor M6 is turned on under the control of the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on under the control of the low level of the light-emitting control signal em. The fourth transistor M8 is turned off under the control of the high level of the noise reduction signal cs3. The turned-on first light-emitting transistor M6 connects the first power supply terminal VDD to the first electrode of the driving transistor M0. The driving transistor M0 is in a saturated state and generates a current I that drives the light-emitting device to emit light, I=k(Vdd-Vda) 2 The turned-on second light emitting transistor M7 connects the second electrode of the driving transistor M0 to the anode of the light emitting device L, and the current I is input into the light emitting device L, driving the light emitting device L to emit light.

[0106] Below is Figure 3b As an example, the pixel circuit shown in the figure is combined with Figure 6 The signal timing diagram shown in FIG. 1 illustrates the operation of the pixel circuit according to an embodiment of the present invention. It should be noted that a sub-pixel scan method can be used to first input data voltages to all sub-pixels in the display panel, and then scan the sub-pixels row by row to achieve threshold compensation for the threshold voltage Vth.

[0107] like Figure 6 As shown, em represents the light emission control signal of the light emission control signal terminal EM coupled to the pixel circuit Row1, ss1-1 represents the first scan signal of the first scan signal terminal SS1 coupled to the pixel circuit Row1, ss2 represents the second scan signal of the second scan signal terminal SS2 coupled to the pixel circuit Row1, ss3 represents the third scan signal of the third scan signal terminal SS3 coupled to the pixel circuit Row1, cs1 represents the first reset signal of the first reset signal terminal CS1 coupled to the pixel circuit Row1, cs2 represents the second reset signal of the second reset signal terminal CS2 coupled to the pixel circuit Row1, and cs3 represents the noise reduction signal of the noise reduction signal terminal CS3 coupled to the pixel circuit Row1. ss1-2 represents the first scan signal of the first scan signal terminal SS1 coupled to the pixel circuit Row2. It should be noted that the signals of the light emission control signal terminal EM, the second scan signal terminal SS2, the third scan signal terminal SS3, the first reset signal terminal CS1, the second reset signal terminal CS2, and the noise reduction signal terminal CS3 corresponding to the pixel circuit Row2 can be referred to the above description and are not repeated here.

[0108] During the data write phase T1, for the Row 1 subpixel, the first data write transistor M1 is turned on by the low level of the first scan signal ss1-1. The second data write transistor M2 is turned off by the high level of the second scan signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned off by the low level of the third scan signal ss3. The first light-emitting transistor M6 is turned on by the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on by the low level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. The turned-on first data write transistor M1 inputs the data voltage Vda1 applied to the data line DA1 to the first electrode of the distributed capacitor C1, charging the distributed capacitor C1. Furthermore, for the Row 2 subpixel, the first data write transistor M1 is turned off by the high level of the first scan signal ss1-2. The second data write transistor M2 is turned off by the high level of the second scan signal ss2.

[0109] Subsequently, for the Row 1 subpixel, the first data write transistor M1 is turned on by the low level of the first scan signal ss1-1. The second data write transistor M2 is turned off by the high level of the second scan signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned off by the low level of the third scan signal ss3. The first light-emitting transistor M6 is turned on by the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on by the low level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. The turned-on first data write transistor M1 inputs the data voltage Vda1 applied to the data line DA1 to the first electrode of the distributed capacitor C1, charging the distributed capacitor C1. Furthermore, for the Row 2 subpixel, the first data write transistor M1 is turned on by the low level of the first scan signal ss1-2. The second data write transistor M2 is turned off by the high level of the second scan signal ss2. The turned-on first data writing transistor M1 inputs the data voltage Vda2 loaded on the data line DA2 into the first electrode of the distributed capacitor C1 to charge the distributed capacitor C1.

[0110] Then, for the Row1 subpixel, the first data write transistor M1 is turned off by the high level of the first scan signal ss1-1. The second data write transistor M2 is turned off by the high level of the second scan signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned off by the low level of the third scan signal ss3. The first light-emitting transistor M6 is turned on by the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on by the low level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. Furthermore, for the Row2 subpixel, the first data write transistor M1 is turned on by the low level of the first scan signal ss1-2. The second data write transistor M2 is turned off by the high level of the second scan signal. The turned-on first data write transistor M1 inputs the data voltage Vda2 applied to the data line DA2 into the first electrode of the distributed capacitor C1, charging the distributed capacitor C1.

[0111] The working processes in the initialization stage T2, the threshold compensation stage T3, and the light emitting stage T4 can refer to the above description and are not described in detail here.

[0112] Below is Figure 3b As an example, the pixel circuit shown in the figure is combined with Figure 7 The signal timing diagram shown in FIG. 1 illustrates the operation of the pixel circuit according to an embodiment of the present invention. It should be noted that a mode of simultaneously scanning two adjacent rows of sub-pixels can be employed to first input data voltages to all sub-pixels in the display panel, and then scan the sub-pixels row by row to achieve threshold compensation for the threshold voltage Vth.

[0113] like Figure 7As shown, em represents the light emission control signal of the light emission control signal terminal EM coupled to the pixel circuit Row1, ss1-1 represents the first scan signal of the first scan signal terminal SS1 coupled to the pixel circuit Row1, ss2 represents the second scan signal of the second scan signal terminal SS2 coupled to the pixel circuit Row1, ss3 represents the third scan signal of the third scan signal terminal SS3 coupled to the pixel circuit Row1, cs1 represents the first reset signal of the first reset signal terminal CS1 coupled to the pixel circuit Row1, cs2 represents the second reset signal of the second reset signal terminal CS2 coupled to the pixel circuit Row1, and cs3 represents the noise reduction signal of the noise reduction signal terminal CS3 coupled to the pixel circuit Row1. ss1-2 represents the first scan signal of the first scan signal terminal SS1 coupled to the pixel circuit Row2. It should be noted that the signals of the light emission control signal terminal EM, the second scan signal terminal SS2, the third scan signal terminal SS3, the first reset signal terminal CS1, the second reset signal terminal CS2, and the noise reduction signal terminal CS3 corresponding to the pixel circuit Row2 can be referred to the above description and are not repeated here.

[0114] During the data write phase T1, for the Row1 subpixel, the first data write transistor M1 is turned on by the low level of the first scan signal ss1-1. The second data write transistor M2 is turned off by the high level of the second scan signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned off by the low level of the third scan signal ss3. The first light-emitting transistor M6 is turned on by the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on by the low level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. The turned-on first data write transistor M1 inputs the data voltage Vda1 applied to the data line DA1 into the first electrode of the distributed capacitor C1, thereby charging the distributed capacitor C1.

[0115] Furthermore, for the Row2 sub-pixel, the first data write transistor M1 is turned on by the low level of the first scan signal ss1-2. The second data write transistor M2 is turned off by the high level of the second scan signal ss2. The first transistor M3 is turned off by the low level of the first reset signal cs1. The second transistor M4 is turned off by the high level of the second reset signal cs2. The third transistor M5 is turned off by the low level of the third scan signal ss3. The first light-emitting transistor M6 is turned on by the low level of the light-emitting control signal em. The second light-emitting transistor M7 is turned on by the low level of the light-emitting control signal em. The fourth transistor M8 is turned off by the high level of the noise reduction signal cs3. The turned-on first data write transistor M1 inputs the data voltage Vda2 loaded on the data line DA2 into the first electrode of the distributed capacitor C1, thereby charging the distributed capacitor C1.

[0116] The working processes in the initialization stage T2, the threshold compensation stage T3, and the light emitting stage T4 can refer to the above description and are not described in detail here.

[0117] Based on the same inventive concept, embodiments of the present invention further provide a display panel, including the display panel provided by the embodiments of the present invention. The principles of the display panel are similar to those of the aforementioned pixel circuit. Therefore, the implementation of the display panel can refer to the implementation of the aforementioned pixel circuit, and the repeated parts will not be repeated here.

[0118] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel described above. The principles of this display device are similar to those of the aforementioned display panel, and thus the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated here.

[0119] In specific implementations, in embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present invention.

[0120] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0121] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A pixel circuit, characterized in that: including a data writing circuit and a driving transistor; The data writing circuit includes: a first data writing transistor, a second data writing transistor and a distributed capacitor; The gate of the first data writing transistor is coupled to the first scan signal terminal, the gate of the second data writing transistor is coupled to the second scan signal terminal, the first electrode of the first data writing transistor is coupled to the data line, the second electrode of the first data writing transistor is coupled to the first electrode of the second data writing transistor, and the second electrode of the second data writing transistor is coupled to the first electrode of the driving transistor; A first electrode of the distributed capacitor is coupled to the second electrode of the first data writing transistor, and a second electrode of the distributed capacitor is coupled to a fixed voltage signal terminal; The first scanning signal terminal transmits a first scanning signal, the second scanning signal terminal transmits a second scanning signal, and an effective level of the first scanning signal does not overlap with an effective level of the second scanning signal; The duration of the effective level of the first scanning signal is longer than the duration of the effective level of the second scanning signal.

2. The pixel circuit according to claim 1, wherein: It also includes an initialization circuit, a threshold compensation circuit, and a light emitting control circuit; The initialization circuit is configured to initialize the gate of the driving transistor under the control of the signal of the first reset signal terminal, and initialize the anode of the light emitting device under the control of the signal of the second reset signal terminal; The threshold compensation circuit is configured to compensate the threshold voltage of the driving transistor under the control of the signal of the third scanning signal terminal; The light emitting control circuit is configured to connect the first power supply terminal to the first electrode of the driving transistor and connect the second electrode of the driving transistor to the anode of the light emitting device under the control of the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

3. The pixel circuit according to claim 2, wherein: The initialization circuit includes: a first transistor and a second transistor; The gate of the first transistor is coupled to the first reset signal terminal, the first electrode of the first transistor is coupled to the first initial voltage signal terminal, and the second electrode of the first transistor is coupled to the gate of the driving transistor; The gate of the second transistor is coupled to the second reset signal terminal, the first electrode of the second transistor is coupled to the second initial voltage signal terminal, and the second electrode of the second transistor is coupled to the anode of the light emitting device.

4. The pixel circuit according to claim 3, wherein: The first reset signal terminal and the second reset signal terminal are different signal terminals; The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

5. The pixel circuit according to claim 2, wherein: The threshold compensation circuit includes: a storage capacitor and a third transistor; a first electrode of the storage capacitor is coupled to the gate of the driving transistor, and a second electrode of the storage capacitor is coupled to the first power supply terminal; the gate of the third transistor is coupled to the third scan signal terminal, a first electrode of the third transistor is coupled to the second electrode of the driving transistor, and a second electrode of the third transistor is coupled to the gate of the driving transistor; The light-emitting control circuit includes: a first light-emitting transistor and a second light-emitting transistor; the gate of the first light-emitting transistor is coupled to the light-emitting control signal terminal, the first electrode of the first light-emitting transistor is coupled to the first power supply terminal, and the second electrode of the first light-emitting transistor is coupled to the first electrode of the driving transistor; the gate of the second light-emitting transistor is coupled to the light-emitting control signal terminal, the first electrode of the second light-emitting transistor is coupled to the second electrode of the driving transistor, and the second electrode of the second light-emitting transistor is coupled to the anode of the light-emitting device.

6. The pixel circuit according to any one of claims 2 to 5, wherein: The third scanning signal terminal transmits a third scanning signal, and a duration of an effective level of the third scanning signal is longer than a duration of an effective level of the second scanning signal.

7. The pixel circuit according to any one of claims 2 to 5, wherein: The pixel circuit further includes: a noise reduction circuit; The noise reduction circuit is configured to provide the signal of the fixed voltage signal terminal to the first electrode of the driving transistor under the control of the signal of the noise reduction signal terminal.

8. The pixel circuit according to claim 7, wherein: The noise reduction circuit includes a fourth transistor; A gate of the fourth transistor is coupled to the noise reduction signal terminal, a first electrode of the fourth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the fixed voltage signal terminal.

9. The pixel circuit according to claim 7, wherein: The noise reduction signal terminal and the second reset signal terminal are the same signal terminal.

10. A display panel, characterized in that: The method comprises the pixel circuit according to any one of claims 1 to 9.

11. The display panel according to claim 10, wherein: The display panel includes a plurality of sub-pixels and a plurality of data lines; Each of the sub-pixels includes the pixel circuit; One column of sub-pixels corresponds to two data lines; The pixel circuits of the sub-pixels in the odd-numbered rows in a column are coupled to one of the corresponding two data lines, and the pixel circuits of the sub-pixels in the even-numbered rows are coupled to the other of the corresponding two data lines.

12. A display device, characterized in that: Comprising the display panel according to claim 10 or 11.

13. A method for driving the pixel circuit according to any one of claims 1 to 9, characterized in that: include: Data writing stage, initialization stage, threshold compensation stage and light emitting stage; In the data writing phase, the first data writing transistor inputs the data voltage on the coupled data line into the distributed capacitor; In the initialization phase, the initialization circuit initializes the gate of the driving transistor under the control of the signal of the first reset signal terminal, and initializes the anode of the light-emitting device under the control of the signal of the second reset signal terminal; In the threshold compensation stage, the second data writing transistor inputs the data voltage stored in the distributed capacitance into the gate of the driving transistor and compensates for the threshold voltage of the driving transistor; In the light-emitting stage, the light-emitting control circuit, under the control of the signal of the light-emitting control signal terminal, connects the first power supply terminal to the first electrode of the driving transistor, and connects the second electrode of the driving transistor to the anode of the light-emitting device, thereby driving the light-emitting device to emit light.

Images