Method of manufacturing a semiconductor device, semiconductor device, and electronic apparatus

Abstract

The present application provides a manufacturing method of a semiconductor device, a semiconductor device, and an electronic device. After the Schottky contact hole etching is completed, an intrinsic polysilicon layer covering the gate oxide layer and the trench polysilicon is formed. After the Schottky barrier metal layer is formed subsequently, the Schottky barrier metal layer can react with the intrinsic polysilicon layer covering the gate oxide layer, so that a barrier metal silicide layer is also generated on the gate oxide layer. Thus, after the contact metal layer is formed subsequently, the contact metal layer does not contact the epitaxial layer. Therefore, when the depth of the contact hole etching, the in-chip uniformity of the etching rate, and the barrier thickness are accurately controlled, the risk of direct contact between the contact metal layer and the epitaxial layer in the trench Schottky diode can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing. Specifically, it relates to a manufacturing method of a semiconductor device, a semiconductor device, and an electronic device. Background Art

[0002] The trench Schottky diode is a common semiconductor power device, which is invented by utilizing the MOS effect of metal-semiconductor silicon. Its main feature is that as the reverse voltage increases, the trenches are pinched off in advance through the MOS effect, and the electric field strength drops to zero before reaching the silicon surface, avoiding surface breakdown and improving the blocking ability.

[0003] Since a barrier metal silicide layer is not formed on the gate oxide after the barrier alloying, it is very easy for the contact metal to directly contact the epitaxial layer, resulting in leakage. Therefore, in the manufacturing process of the existing trench Schottky diode, it is very difficult to accurately control the depth of the contact hole etching, the in-chip uniformity of the etching rate, and the barrier thickness, leading to a low product yield. Summary of the Invention

[0004] In order to overcome the above deficiencies in the prior art, the purpose of this application is to provide a manufacturing method of a semiconductor device, and the method includes:

[0005] Providing an epitaxial layer, the epitaxial layer including opposite first and second surfaces;

[0006] Forming trenches on the first surface of the epitaxial layer;

[0007] Forming a gate oxide layer in the trenches;

[0008] Filling trench polysilicon in the trenches;

[0009] Forming Schottky contact holes exposing the first surface of the epitaxial layer;

[0010] Providing an intrinsic polysilicon layer on the first surface of the epitaxial layer, such that the intrinsic polysilicon layer covers the exposed epitaxial layer, the trench polysilicon, and the gate oxide layer;

[0011] Forming a Schottky barrier metal layer on the intrinsic polysilicon layer;

[0012] Performing a barrier metal alloy reaction on the Schottky barrier metal layer, such that the Schottky barrier metal layer reacts with the intrinsic polysilicon layer to form a barrier metal silicide layer;

[0013] Forming a contact metal layer on a side of the barrier metal silicide layer away from the epitaxial layer;

[0014] Forming a back metal layer on the second surface of the epitaxial layer.

[0015] In a possible implementation, the step of performing a barrier metal alloy reaction on the Schottky barrier metal layer includes:

[0016] Performing a barrier metal alloy reaction on the Schottky barrier metal layer to cause an alloy reaction between the Schottky barrier metal layer, the intrinsic polysilicon layer, and at least a part of the epitaxial layer to form a barrier metal silicide layer.

[0017] In a possible implementation, the step of performing a barrier metal alloy reaction on the Schottky barrier metal layer includes:

[0018] Performing a barrier metal alloy reaction on the Schottky barrier metal layer for 10 to 100 seconds in an environment with a temperature of 300 to 800 °C.

[0019] In a possible implementation, the step of disposing an intrinsic polysilicon layer on the first surface of the epitaxial layer includes:

[0020] Depositing and forming an intrinsic polysilicon layer with a thickness of 500 to 2000 angstroms on one side of the epitaxial layer by low-pressure chemical vapor deposition.

[0021] In a possible implementation, the step of forming a trench on the first surface of the epitaxial layer includes:

[0022] Forming a surface oxide layer on the first surface;

[0023] Performing photolithography on the surface oxide layer to form a first opening;

[0024] Etching the epitaxial layer from the first opening to form a trench;

[0025] Removing the surface oxide layer.

[0026] In a possible implementation, after the step of filling the trench with trench polysilicon, the method further includes:

[0027] Performing back etching on the trench polysilicon to make the trench polysilicon in the trench lower than the first surface of the epitaxial layer.

[0028] In a possible implementation, the step of forming a Schottky contact hole exposing the first surface of the epitaxial layer includes:

[0029] Forming a silicon dioxide layer on the side of the surface oxide layer away from the epitaxial layer;

[0030] Performing photolithography on the silicon dioxide layer to form a second opening;

[0031] Etch the Schottky contact hole from the second opening to expose the epitaxial layer.

[0032] In a possible implementation, after the step of performing a barrier metal alloy reaction on the Schottky barrier metal layer, the method further includes:

[0033] Remove the unreacted Schottky barrier metal layer.

[0034] Another object of the present application is to provide a semiconductor device, which is manufactured by the semiconductor device manufacturing method provided by the present application.

[0035] Another object of the present application is to provide an electronic device, which includes the semiconductor device provided by the present application.

[0036] Compared with the prior art, the present application has the following beneficial effects:

[0037] The present application provides a manufacturing method of a semiconductor device, a semiconductor device and an electronic device. After completing the etching of the Schottky contact hole, an intrinsic polysilicon layer covering the gate oxide layer and the trench polysilicon is formed. After forming the Schottky barrier metal layer subsequently, the Schottky barrier metal layer can react with the intrinsic polysilicon layer covering the gate oxide layer, so that a barrier metal silicide layer is also generated on the gate oxide layer. Thus, after forming the contact metal layer subsequently, the contact metal layer will not contact the epitaxial layer, so that the risk of direct contact between the contact metal layer and the epitaxial layer in the trench Schottky diode can be reduced while accurately controlling the depth of the contact hole etching, the in-chip uniformity of the etching rate, and the barrier thickness. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 One of the schematic diagrams of the semiconductor device manufacturing process in the prior art;

[0040] Figure 2 Another schematic diagram of the semiconductor device manufacturing process in the prior art;

[0041] Figure 3 Another schematic diagram of the semiconductor device manufacturing process in the prior art;

[0042] Figure 4 It is the fourth schematic diagram of the semiconductor device manufacturing process in the prior art;

[0043] Figure 5 It is the schematic flow diagram of the manufacturing method of the semiconductor device provided in this embodiment;

[0044] Figure 6 It is one of the schematic diagrams of the manufacturing process of the semiconductor device provided in this embodiment;

[0045] Figure 7 It is the second schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0046] Figure 8 It is the third schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0047] Figure 9 It is the fourth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0048] Figure 10 It is the fifth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0049] Figure 11 It is the sixth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0050] Figure 12 It is the seventh schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0051] Figure 13 It is the eighth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0052] Figure 14 It is the ninth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0053] Figure 15 It is the tenth schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment;

[0054] Figure 16 It is the eleventh schematic diagram of the manufacturing process of the semiconductor device provided in this embodiment. Detailed implementation manners

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. Usually, the components of the embodiments of this application described and illustrated herein can be arranged and designed in various different configurations.

[0056] Accordingly, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0057] It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0058] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0059] In addition, terms such as "horizontal", "vertical", "overhanging", etc. do not mean that the components are required to be absolutely horizontal or overhanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but may be slightly inclined.

[0060] In the description of the present application, it should also be noted that unless otherwise clearly specified and defined, the terms "arranged", "installed", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0061] In the manufacturing process of the existing trench Schottky diode, processes such as forming a trench on the epitaxial layer 110, then forming a gate oxide layer 120 in the trench, and then filling the trench with trench polysilicon 130 are usually performed to form a structure as Figure 1 shown.

[0062] After that, please refer to Figure 2, a Schottky barrier metal layer 140 is formed on the epitaxial layer 110 on one side of the trench opening, and then the Schottky barrier metal layer 140 reacts with the epitaxial layer 110 and the trench polysilicon 130 in a high-temperature environment to form a barrier metal silicide layer 150.

[0063] However, the gate oxide layer 120 exposed through the Schottky contact hole will not react with the Schottky barrier metal layer 140. Therefore, a barrier metal silicide layer 150 will not be formed above the exposed gate oxide layer 120, resulting in a notch exposing the gate oxide layer 120 on the barrier metal silicide layer 150, as Figure 3 shown.

[0064] On this basis, when forming the contact metal layer 160 on the barrier metal silicide layer 150, please refer to Figure 4 , the contact metal layer 160 at the notch is likely to be in direct contact with the epitaxial layer 110, resulting in leakage. Therefore, in the existing manufacturing process of trench Schottky diodes, it is necessary to accurately control the depth of the Schottky contact hole etching and the in-chip uniformity of the etching rate, as well as the barrier thickness, resulting in a low product yield.

[0065] In view of this, this embodiment provides a solution that can reduce the risk of direct contact between the contact metal layer and the epitaxial layer in trench Schottky diodes. The solution provided in this embodiment will be elaborated in detail below.

[0066] Please refer to Figure 5 , Figure 5 is a manufacturing method of a semiconductor device provided in this embodiment. This method can be used to manufacture trench Schottky diode devices, and this method may include the following steps.

[0067] Step S111, providing an epitaxial layer 110, the epitaxial layer 110 including opposite first and second surfaces.

[0068] Step S112, forming a trench on the first surface of the epitaxial layer 110.

[0069] Optionally, please refer to Figure 6 , in this embodiment, a surface oxide layer 101 can be formed on the first surface. For example, through a furnace tube device, in an environment with a temperature of 900 - 1100 °C, a surface oxide layer 101 with a thickness of 1000 - 5000 angstroms can be grown on the first surface of the epitaxial layer 110.

[0070] Next, please refer to Figure 7 , and perform photolithography on the surface oxide layer 101 to form a first opening.

[0071] Then, please refer to Figure 8, using the surface oxide layer 101 as a mask, etching is performed on the epitaxial layer 110 from the first opening to form a trench. The width of the trench can be 0.3 - 0.6 um, and the depth can be 0.8 - 2.7 um. After the etching of the trench is completed, the surface oxide layer can be removed.

[0072] It should be noted that in this embodiment, multiple trenches can be formed simultaneously. For the convenience of description Figures 6 to 8 and the subsequent views only show the processing process of some of the trenches, and the processing processes of other trenches will not be shown one by one.

[0073] Step S113, forming a gate oxide layer 120 in the trench.

[0074] Optionally, please refer to Figure 9 , in this embodiment, in a furnace tube equipment, in an environment where the temperature is 900 - 1100 °C and the oxygen flow rate is 4 - 12 L / min, a gate oxide layer 120 with a thickness of 600 - 4000 angstroms is grown on the inner wall of the trench.

[0075] Step S114, filling trench polysilicon 130 in the trench.

[0076] Optionally, please refer to Figure 10 , in this embodiment, after filling the trench polysilicon 130 in the trench, the trench polysilicon 130 can be etched back so that the trench polysilicon 130 located in the trench is lower than the first surface of the epitaxial layer 110.

[0077] Step S115, forming a Schottky contact hole exposing the first surface of the epitaxial layer 110.

[0078] Optionally, please refer to Figure 11 , in this embodiment, a silicon dioxide layer 102 can be first formed on the side of the surface oxide layer 101 away from the epitaxial layer 110. For example, silicon dioxide is deposited by atmospheric pressure chemical vapor deposition, and at the same time, boron element B and phosphorus element P are doped to form a silicon dioxide layer 102 with a thickness of 4000 - 15000 angstroms.

[0079] Then, photolithography is performed on the silicon dioxide layer 102 to form a second opening. Then, etching of the Schottky contact hole is performed from the second opening to expose the epitaxial layer 110, forming a structure as Figure 1 shown. It should be noted that in this embodiment, the Schottky contact hole can cover multiple trenches, and the gate oxide layer 120 on the first surface of the epitaxial layer 110 within the coverage of the Schottky contact hole can be removed during the etching process.

[0080] Step S116, an intrinsic polysilicon layer 170 is disposed on the first surface of the epitaxial layer 110, such that the intrinsic polysilicon layer 170 covers the exposed epitaxial layer 110, the trench polysilicon 130, and the gate oxide layer 120.

[0081] Optionally, please refer to Figure 12 , in this embodiment, the intrinsic polysilicon layer 170 with a thickness of 500 to 2000 angstroms can be deposited on one side of the epitaxial layer 110 by low-pressure chemical vapor deposition (LPCVD). Wherein, the intrinsic polysilicon layer 170 can cover the gate oxide layer 120 and the trench polysilicon 130 exposed in the trench.

[0082] Step S117, a Schottky barrier metal layer 140 is formed on the intrinsic polysilicon layer 170.

[0083] Optionally, please refer to Figure 13 , in this embodiment, the Schottky barrier metal layer 140 can be formed on the intrinsic polysilicon layer by sputtering.

[0084] Step S118, a barrier metal alloy reaction is performed on the Schottky barrier metal layer 140, such that the Schottky barrier metal layer 140 reacts with the intrinsic polysilicon layer 170 to form a barrier metal silicide layer 150.

[0085] Optionally, in this embodiment, a barrier metal alloy reaction can be performed on the Schottky barrier metal layer 140, such that the Schottky barrier metal layer 140 reacts with the intrinsic polysilicon layer 170 and at least a part of the epitaxial layer 110 to form a barrier metal silicide layer 150. That is, it is necessary to ensure that after the complete reaction between the intrinsic polysilicon layer 170 and the Schottky barrier metal layer 140, at least a part of the epitaxial layer 110 reacts with the Schottky barrier metal layer 140 to form a structure as shown in Figure 14 .

[0086] Further, in this embodiment, the barrier metal alloy reaction can be performed on the Schottky barrier metal layer 140 in an environment with a temperature of 300 to 800 °C for 10 to 100 seconds.

[0087] It should be noted that since the intrinsic polysilicon layer 170 covering the gate oxide layer 120 and the trench polysilicon 130 is formed in step S116, in step S118, the Schottky barrier metal layer 140 can react with the intrinsic polysilicon layer 170 covering the gate oxide layer 120, and a barrier metal silicide layer 150 is also formed on the gate oxide layer 120. Compared with the prior art, the situation that the barrier metal silicide layer 150 exposes the gate oxide layer 120 will not occur.

[0088] Further, after step S118, the Schottky barrier metal layer 140 that has not participated in the reaction can also be removed.

[0089] Step S119: Form a contact metal layer 160 on the side of the barrier metal silicide layer 150 away from the epitaxial layer 110.

[0090] Optionally, please refer to Figure 15 , in this embodiment, the contact metal layer 160 can be formed on the side of the barrier metal silicide layer 150 away from the epitaxial layer 110 by sputtering.

[0091] It should be noted that since the formed barrier metal silicide layer 150 in step S118 completely covers the gate oxide layer 120, the contact metal layer 160 formed in step S119 will not contact the epitaxial layer 110.

[0092] Step S120: Form a back metal layer 180 on the second surface of the epitaxial layer 110.

[0093] Optionally, in step S120, after sputtering to form the back metal layer 180, photolithography, etching, and thinning can be performed on the back metal layer 180 to finally form a Schottky diode device.

[0094] Based on the same inventive concept, this embodiment also provides a semiconductor device, which can be manufactured by the semiconductor device manufacturing method provided in this embodiment, and the semiconductor device can be a trench Schottky diode device.

[0095] This embodiment also provides an electronic device, which includes the semiconductor device provided in this embodiment.

[0096] In summary, this application provides a manufacturing method of a semiconductor device, a semiconductor device, and an electronic device. After completing the etching of the Schottky contact hole, an intrinsic polysilicon layer covering the gate oxide layer and the trench polysilicon is formed. After subsequently forming the Schottky barrier metal layer, the Schottky barrier metal layer can react with the intrinsic polysilicon layer covering the gate oxide layer, so that a barrier metal silicide layer is also generated on the gate oxide layer. In this way, after subsequently forming the contact metal layer, the contact metal layer will not contact the epitaxial layer, so that the risk of direct contact between the contact metal layer and the epitaxial layer in the trench Schottky diode can be reduced while accurately controlling the depth of the contact hole etching, the in-chip uniformity of the etching rate, and the barrier thickness.

[0097] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0098] As described above, the above are only various embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: providing an epitaxial layer, the epitaxial layer including opposite first and second surfaces; forming a trench in the first surface of the epitaxial layer; forming a gate oxide layer in the trench; filling the trench with trench polysilicon; forming a Schottky contact hole exposing the first surface of the epitaxial layer; providing an intrinsic polysilicon layer on the first surface of the epitaxial layer, such that the intrinsic polysilicon layer covers the exposed epitaxial layer, the trench polysilicon, and the gate oxide layer; forming a Schottky barrier metal layer on the intrinsic polysilicon layer; performing a barrier metal alloy reaction on the Schottky barrier metal layer, such that the Schottky barrier metal layer reacts with the intrinsic polysilicon layer to form a barrier metal silicide layer; forming a contact metal layer on a side of the barrier metal silicide layer away from the epitaxial layer; forming a back metal layer on the second surface of the epitaxial layer.

2. The method according to claim 1, characterized in that, The step of performing a barrier metal alloy reaction on the Schottky barrier metal layer includes: performing a barrier metal alloy reaction on the Schottky barrier metal layer, such that the Schottky barrier metal layer reacts with the intrinsic polysilicon layer and at least part of the epitaxial layer to form a barrier metal silicide layer.

3. The method according to claim 2, characterized in that The step of performing a barrier metal alloy reaction on the Schottky barrier metal layer includes: performing a barrier metal alloy reaction on the Schottky barrier metal layer for 10 to 100 seconds in an environment at a temperature of 300 to 800 °C.

4. The method according to claim 1, characterized in that, The step of providing an intrinsic polysilicon layer on the first surface of the epitaxial layer includes: depositing and forming an intrinsic polysilicon layer with a thickness of 500 to 2000 angstroms on one side of the epitaxial layer by low-pressure chemical vapor deposition.

5. The method according to claim 1, wherein The step of forming a trench in the first surface of the epitaxial layer includes: forming a surface oxide layer on the first surface; performing photolithography on the surface oxide layer to form a first opening; etching the epitaxial layer from the first opening to form a trench; removing the surface oxide layer.

6. The method according to claim 5, characterized in that, After the step of filling the trench with trench polysilicon, the method further includes: etching back the trench polysilicon, such that the trench polysilicon in the trench is lower than the first surface of the epitaxial layer.

7. The method according to claim 5, wherein The step of forming a Schottky contact hole exposing the first surface of the epitaxial layer includes: forming a silicon dioxide layer on a side of the surface oxide layer away from the epitaxial layer; performing photolithography on the silicon dioxide layer to form a second opening; etching the Schottky contact hole from the second opening to expose the epitaxial layer.

8. The method according to claim 1, wherein After the step of performing a barrier metal alloy reaction on the Schottky barrier metal layer, the method further includes: removing the unreacted Schottky barrier metal layer.

9. A semiconductor device, characterized in that, The semiconductor device is fabricated by the semiconductor device manufacturing method according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device according to claim 9.

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