Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the semiconductor device provided by the present invention. The semiconductor device includes a substrate, a GaN and a barrier layer formed sequentially on the substrate, a first groove formed by etching the GaN layer and the barrier layer, and an n-type heavily doped GaN material formed on the upper surface of the first groove and the barrier layer adjacent to the first groove. In the present invention, the first groove is filled with the n-type heavily doped GaN material and extends to the upper surface of the barrier layer, improving the ohmic contact between the n-type heavily doped GaN material and the sidewall of the GaN heterojunction and reducing the contact resistance between the n-type heavily doped GaN material and the sidewall of the GaN heterojunction. After the secondary epitaxial growth of the n-type heavily doped GaN material in the first groove, the growth continues laterally on the upper side of the barrier layer, which is beneficial to improving the problem of rough surface of the n-type heavily doped GaN material and further reducing the contact resistance between the n-type heavily doped GaN material and the metal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] An enhanced high electron mobility transistor structure and implementation method for forming an ohmic contact by secondary regrowth of n-type heavily doped GaN in a source / drain ohmic contact region using metal organic chemical vapor deposition technology, which are mainly used for manufacturing high-performance electronic devices in the fields of high-voltage power switches and digital circuits.

[0003] AlGaN / GaN-based high electron mobility transistors (HEMTs) have attracted wide attention due to their excellent material properties such as a large bandgap width, a high critical breakdown field strength, a high electron saturation drift velocity, and a two-dimensional electron gas (2DEG) with superior transport characteristics generated by strong spontaneous and piezoelectric polarization effects, and have unique advantages in the application of high-temperature, high-voltage, high-frequency high-power microwave electronic devices.

[0004] In the manufacturing process of GaN-based HEMT devices, the source / drain ohmic contact process is one of the key technologies, which directly affects the frequency and power performance of the devices. Secondary epitaxial growth of n-type heavily doped GaN in the ohmic contact region to reduce the ohmic contact resistivity and improve the surface morphology has become a new process internationally in recent years. This process can achieve non-alloy ohmic contacts, greatly improving the surface and edge morphology of the ohmic contacts, and can also achieve self-alignment processes for the source / drain / gate. Secondary epitaxial growth of n-type heavily doped GaN is mostly realized by molecular beam epitaxy (MBE), but some people also use metal organic chemical vapor deposition (MOCVD). The ohmic contact resistance achieved by this method mainly includes the contact resistance between the metal and n-type heavily doped GaN, the bulk resistance of n-type heavily doped GaN, and the contact resistance between the sidewalls of the n-type heavily doped GaN and GaN heterojunction. The quality of the contact between the sidewalls of the n-type heavily doped GaN and GaN heterojunction directly affects the contact resistance between the sidewalls of the n-type heavily doped GaN and GaN heterojunction, and this contact resistance has the greatest impact on the overall ohmic contact. Figures 1a to 1c Schematic diagram of the preparation process of secondary epitaxial growth of heavily doped GaN material for the prior art, as Figures 1a to 1c shown, using a patterned SiO2 layer as a mask to etch the exposed GaN channel layer 3 and barrier layer 4, etching to a depth below the GaN heterojunction interface, as Figure 1b shown, in the actual operation process, due to the problem of etching accuracy, it is easy to over-etch the GaN heterojunction. The side position of the GaN heterojunction is retracted by a certain distance relative to the mask layer SiO2 above it, as Figure 1cAs shown in the figure, when re-doped GaN material is grown by secondary epitaxy, due to the existence of over-etching, the side of the re-doped GaN material has poor contact with the GaN heterojunction, resulting in a significant increase in the contact resistance between the n-type re-doped GaN and the sidewall of the GaN heterojunction.

[0005] Therefore, effectively reducing the contact resistance between the n-type re-doped GaN and the sidewall of the GaN heterojunction is of great significance for reducing the overall ohmic contact.

[0006] In summary, the existing technologies cannot effectively reduce the ohmic contact resistance in the source-drain region. In addition, the device fabrication process has complex steps, great difficulty in controlling process precision, and expensive equipment, which cannot meet the requirements of market-oriented commodity production. Summary of the Invention

[0007] The purpose of the present invention is to provide a semiconductor device and a preparation method thereof with simple process and small ohmic contact resistance, which can reduce the contact resistance between the n-type re-doped GaN and the sidewall of the GaN heterojunction, reduce the difficulty of device manufacturing, improve the repeatability and controllability of the device manufacturing process, and enable the device to be better applied in high-voltage power switches and digital circuits.

[0008] To achieve the above object, the present invention provides a method for preparing a semiconductor device, including the following steps:

[0009] Form a GaN layer and a barrier layer on the substrate in sequence;

[0010] Grow a SiO2 dielectric layer on the upper surface of the barrier layer;

[0011] Use the first etching of the SiO2 layer in the source-drain ohmic contact region to the upper surface of the barrier layer to form a first window area;

[0012] Etch the GaN layer and the barrier layer in the first window area, etch to below the heterojunction interface of the GaN layer and the barrier layer to form a first groove, and then perform annealing treatment using a high-temperature annealing furnace;

[0013] Continue the second etching of the SiO2 layer on the basis of the first etching of the SiO2 layer to obtain a second window area with an enlarged horizontal projection area on the basis of the first window area;

[0014] Re-epitaxially grow n-type re-doped GaN material in the second window area.

[0015] As an optional technical solution, the horizontal distance from the edge of the second window area obtained by the second etching of the SiO2 layer to the edge of the first window area obtained by the first etching of the SiO2 layer is between 0-100 nm.

[0016] As an alternative technical solution, continuing the second etching of the SiO2 layer on the basis of the first etching of the SiO2 layer means continuing the second etching of the SiO2 layer to the upper surface of the barrier layer on the basis of the first etching of the SiO2 layer; the second window region exposes the first groove and a part of the upper surface of the barrier layer.

[0017] As an alternative technical solution, the thickness of the n-type heavily doped GaN material exceeds the upper surface of the barrier layer.

[0018] As an alternative technical solution, secondarily epitaxially growing the n-type heavily doped GaN material in the second window region means secondarily epitaxially growing the n-type heavily doped GaN material in the first groove and on the upper surface of a part of the barrier layer outside the first groove.

[0019] As an alternative technical solution, the SiO2 layer that defines the second window region has an inclined side surface.

[0020] As an alternative technical solution, the material used for the barrier layer is AlGaN, InAlN or AlN.

[0021] As an alternative technical solution, the thickness of the SiO2 layer is 20 - 300 nm.

[0022] As an alternative technical solution, the present invention provides a method for manufacturing a semiconductor device, further comprising:

[0023] Etching away the SiO2 layer on the barrier layer, fabricating a gate electrode on the barrier layer, and respectively disposing a source electrode and a drain electrode on the n-type heavily doped GaN material, wherein the gate electrode is insulated from the source electrode and the drain electrode.

[0024] As an alternative technical solution, the present invention provides a method for manufacturing a semiconductor device, further comprising:

[0025] Selectively etching the SiO2 layer in the gate region to the upper surface of the barrier layer to form a gate growth region;

[0026] Disposing a gate electrode in Schottky contact with the barrier layer in the gate growth region and respectively disposing a source electrode and a drain electrode on the n-type heavily doped GaN material.

[0027] On the other hand, the present invention further provides a semiconductor device, comprising:

[0028] A substrate;

[0029] A GaN layer and a barrier layer sequentially formed on the substrate;

[0030] A first groove, which is formed by etching the GaN layer and the barrier layer, and the bottom surface of the first groove is below the heterointerface of the GaN layer and the barrier layer;

[0031] An n-type heavily doped GaN material, which is formed on the upper surface of the first groove and the barrier layer adjacent to the first groove;

[0032] A gate electrode, which is formed on the barrier layer;

[0033] A source electrode and a drain electrode, which are formed on the n-type heavily doped GaN material.

[0034] As an optional technical solution, the horizontal distance between the edge position of the first groove and the edge position of the adjacent n-type heavily doped GaN material on the barrier layer is between 0 - 100 nm.

[0035] As an optional technical solution, the thickness of the n-type heavily doped GaN material exceeds the upper surface of the barrier layer.

[0036] As an optional technical solution, a semiconductor device provided by the present invention further includes:

[0037] An SiO2 layer, which is formed on the upper surface of the barrier layer and is located between the gate electrode and the n-type heavily doped GaN material.

[0038] As an optional technical solution, the side of the SiO2 layer close to the n-type heavily doped GaN material has an inclined side surface.

[0039] As an optional technical solution, the material used for the barrier layer is AlGaN, InAlN or AlN.

[0040] As an optional technical solution, the thickness of the SiO2 layer is 20 - 300 nm.

[0041] In summary, the present invention provides a method for fabricating a semiconductor device. The method includes first etching the SiO2 layer in the source-drain ohmic contact region to the upper surface of the barrier layer to form a first window region; etching the GaN layer and the barrier layer in the first window region, etching to form a first groove below the heterojunction interface of the GaN layer and the barrier layer, and then performing an annealing treatment using a high-temperature annealing furnace; continuously performing a second etching of the SiO2 layer on the basis of the first etching of the SiO2 layer to obtain a second window region with an enlarged horizontal projection area on the basis of the first window region; and epitaxially growing an n-type heavily doped GaN material in the second window region. In the method for fabricating a semiconductor device according to the present invention, by etching the SiO2 layer twice, the horizontal projection area of the second window region is enlarged, preventing the SiO2 layer from causing poor contact between the n-type heavily doped GaN material and the sidewall of the GaN heterojunction when the n-type heavily doped GaN material is epitaxially grown for the second time with the SiO2 layer as a mask layer.

[0042] The semiconductor device provided by the present invention includes a substrate, a GaN and a barrier layer sequentially formed on the substrate, a first groove formed by etching the GaN layer and the barrier layer, and an n-type heavily doped GaN material formed on the upper surface of the first groove and the barrier layer connected to the first groove. In the present invention, the first groove is filled with the n-type heavily doped GaN material and extends to the upper surface of the barrier layer, improving the ohmic contact between the n-type heavily doped GaN material and the sidewall of the GaN heterojunction and reducing the contact resistance between the n-type heavily doped GaN material and the sidewall of the GaN heterojunction.

[0043] On the other hand, after the n-type heavily doped GaN material is grown in the first groove during the second epitaxial growth, it continues to grow epitaxially on the upper side of the barrier layer, which is beneficial to improving the problem of rough surface of the n-type heavily doped GaN material and further reducing the contact resistance between the n-type heavily doped GaN material and the metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0045] Figures 1a - 1c is a schematic diagram of the preparation process of epitaxially growing a heavily doped GaN material in the prior art for the second time;

[0046] Figures 2a - 2f is a schematic diagram of the intermediate process and the structure of the final device in the method for fabricating a semiconductor device according to Embodiment 1 of the present invention;

[0047] Figure 3 is a schematic diagram of the structure of a semiconductor device according to Embodiment 2 of the present invention;

[0048] Figure 4 is a schematic diagram of the structure of a semiconductor device according to Embodiment 3 of the present invention.

[0049] Description of reference numerals: 1, substrate; 2, buffer layer; 3, GaN layer; 4, barrier layer; 5, SiO2 layer; 6, n-type heavily doped GaN material; 7, source electrode; 8, drain electrode; 9, gate electrode; T, first groove; 100, 200, 300, semiconductor device; S1, first window region; S2, second window region; d, horizontal distance from the edge of the second window region to the edge of the first window region. Detailed implementation manners

[0050] Here, the exemplary implementation manners will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The implementation manners described in the following exemplary implementation manners do not represent all implementation manners consistent with the present invention. On the contrary, they are merely examples of devices consistent with some aspects of the present invention as detailed in the appended claims.

[0051] Example 1

[0052] Figures 2a - 2e is a schematic structural diagram of an intermediate process in the manufacturing method of the semiconductor device according to Example 1 of the present invention. Figure 2f is a schematic structural diagram of the semiconductor device according to Example 1 of the present invention. As Figures 2a - 2f shown, the semiconductor device 100 according to Example 1 of the present invention includes: a substrate 1, a buffer layer 2, a GaN layer 3, a barrier layer 4, a first groove T, an n-type heavily doped GaN material 6, a source electrode 7, a drain electrode 8, and a gate electrode 9. The GaN layer 3 and the barrier layer 4 are sequentially formed above the substrate 1. Specifically, the GaN layer 3 and the barrier layer 4 are sequentially formed on the buffer layer 2, and the GaN layer 3 and the barrier layer 4 constitute a GaN heterojunction; the first groove T is formed by etching the GaN layer 3 and the barrier layer 4, and the bottom surface of the first groove T is located below the heterojunction interface of the GaN layer 3 and the barrier layer 4; the n-type heavily doped GaN material is formed on the upper surface of the first groove T and the barrier layer 4 adjacent to the first groove T; the gate electrode 9 is formed on the upper surface of the barrier layer 4; the source electrode 7 and the drain electrode 8 are formed on the n-type heavily doped GaN material 6. By filling the first groove T with the n-type heavily doped GaN material 6 and extending it to the upper surface of the barrier layer 4, the present invention improves the ohmic contact between the n-type heavily doped GaN material 6 and the sidewalls of the GaN heterojunction, and reduces the contact resistance between the n-type heavily doped GaN material 6 and the sidewalls of the GaN heterojunction.

[0053] On the other hand, after the n-type heavily doped GaN material 6 is grown epitaxially in the first groove T by secondary epitaxy, it continues to grow epitaxially on the upper side of the barrier layer 4, which is beneficial to improving the problem of rough surface of the n-type heavily doped GaN material 6, improving the crystal quality of the n-type heavily doped GaN material 6, and further reducing the contact resistance between the n-type heavily doped GaN material 6 and the metal electrode.

[0054] Preferably, in the semiconductor device 100 of Embodiment 1, the horizontal distance from the edge position of the first groove T to the edge position of the adjacent n-type heavily doped GaN material 6 located on the barrier layer is between 0 and 100 nm, that is, the n-type heavily doped GaN material 6 grows epitaxially for the second time in the first groove T. After filling the first groove T, it continues to grow epitaxially outside the first groove T, that is, it continues to grow epitaxially on the upper side of the barrier layer 4 outside the first groove T. The horizontal distance from the edge position of the extended-grown n-type heavily doped GaN material 6 on the barrier layer to the first groove T is between 0 and 100 nm.

[0055] Preferably, in the semiconductor device 100 of Embodiment 1, the thickness of the n-type heavily doped GaN material 6 exceeds the upper surface of the barrier layer 4.

[0056] The manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present invention includes the following steps:

[0057] As Figure 2a shown, a buffer layer 2, a GaN layer 3, and a barrier layer 4 are sequentially formed on the substrate 1. The material used for the barrier layer 4 is AlGaN, InAlN, or AlN;

[0058] As Figure 2b shown, a SiO2 dielectric layer 5 is grown on the upper surface of the barrier layer 4. The thickness of the SiO2 layer 5 is 20 - 300 nm. The SiO2 layer 5 is etched for the first time in the source-drain ohmic contact region to the upper surface of the barrier layer 4 to form a first window area S1;

[0059] As Figure 2c shown, the GaN layer and the barrier layer are etched in the first window area, and etched to below the heterojunction interface of the GaN layer and the barrier layer to form a first groove T, and then annealed using a high-temperature annealing furnace;

[0060] As Figure 2d shown, on the basis of the first etching of the SiO2 layer 5, the SiO2 layer 5 is etched for the second time to obtain a second window area S2 with an enlarged horizontal projection area on the basis of the first window area S1. Specifically, the horizontal distance d from the edge of the second window area S obtained by the second etching of the SiO2 layer to the edge of the first window area obtained by the first etching of the SiO2 layer is between 0 and 100 nm;

[0061] Preferably, on the basis of the first etching of the SiO2 layer 5, a second etching of the SiO2 layer 5 is continued, which is to continue the second etching of the SiO2 layer 5 to the upper surface of the barrier layer 4; the second window region S2 exposes the first groove T and a part of the upper surface of the barrier layer 4. It should be noted that the horizontal distance from the edge of the second window region S obtained by the second etching of the SiO2 layer to the edge of the first window region obtained by the first etching of the SiO2 layer is greater than or equal to the distance from the edge of the second window region S2 to the edge of the first groove T.

[0062] As Figure 2e shown, a second epitaxial growth of an n-type heavily doped GaN material 6 is performed in the second window region S2; preferably, the thickness of the second epitaxial growth of the n-type heavily doped GaN material 6 exceeds the upper surface of the barrier layer 4; preferably, the second epitaxial growth of the n-type heavily doped GaN material 6 in the second window region S2 is to perform a second epitaxial growth of the n-type heavily doped GaN material in the first groove T and a part of the upper surface of the barrier layer 4.

[0063] As Figure 2f shown, the SiO2 layer 5 on the barrier layer 4 is etched away, a gate electrode 9 is fabricated on the barrier layer 4, and a source electrode 7 and a drain electrode 8 are respectively disposed on the n-type heavily doped GaN material 6, wherein the gate electrode 9 is insulated from the source electrode 7 and the drain electrode 8.

[0064] Embodiment 2

[0065] Figure 3 FIG. is a schematic structural diagram of a semiconductor device 200 according to Embodiment 2 of the present invention. The semiconductor device 200 according to Embodiment 2 of the present invention and the manufacturing method of the semiconductor device 200 are substantially the same as those of the semiconductor device 100 according to Embodiment 1 of the present invention. The difference between the semiconductor device 200 according to Embodiment 2 and the semiconductor device 100 according to Embodiment 1 is that, as Figure 3 shown, the semiconductor device 200 according to Embodiment 2 further includes an SiO2 layer formed on the upper surface of the barrier layer 4 and located between the gate electrode 9 and the n-type heavily doped GaN material 6. The difference between the manufacturing method of the semiconductor device 200 according to Embodiment 2 and the manufacturing method of the semiconductor device 100 according to Embodiment 1 is that: the SiO2 layer 5 on the upper surface of the barrier layer 4 is not completely etched away, but the SiO2 layer 5 is etched in the gate region to the upper surface of the barrier layer 4 to form a gate growth region; a gate electrode 9 in Schottky contact with the barrier layer 4 is disposed in the gate growth region, and a source electrode 7 and a drain electrode 8 are respectively disposed on the n-type heavily doped GaN material. In Embodiment 2, the semiconductor device 200 retains the SiO2 layer 5, and the retained SiO2 layer 5 serves as an insulating medium between the gate electrode 9 and the n-type heavily doped GaN material. On the other hand, the retained SiO2 layer 5 also serves as a mask for the growth of the gate electrode 9 and the n-type heavily doped GaN material 6.

[0066] Embodiment III

[0067] Figure 4 is a schematic structural diagram of a semiconductor device 300 according to Embodiment III of the present invention. The semiconductor device 300 and the manufacturing method of the semiconductor device 300 according to Embodiment III of the present invention are substantially the same as those of the semiconductor device 200 and the manufacturing method of the semiconductor device 200 according to Embodiment II of the present invention. The only difference is that, as Figure 4 shown, the SiO2 layer 5 that defines the second window region S2 has an inclined side surface, that is, the side surface of the SiO2 layer 5 close to the n-type heavily doped GaN material 6 has an inclined side surface. The opening size defined by the SiO2 layer 5 gradually increases from bottom to top. The advantage of such a design is that when the n-type heavily doped GaN material 6 is epitaxially grown for the second time, the crystal quality of the n-type heavily doped GaN material 6 is improved. The SiO2 layer 5 has an inclined side surface. When the n-type heavily doped GaN material 6 continues to grow epitaxially outside the first groove T, the inclined side surface of the SiO2 layer 5 provides a better contact interface, reduces the growth defects of the n-type heavily doped GaN material 6, improves the crystal quality of the n-type heavily doped GaN material 6, and further reduces the contact resistance between the n-type heavily doped GaN material 6 and the metal electrode.

[0068] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including the following steps: Successively form a GaN layer and a barrier layer on a substrate; Grow an SiO2 layer on the upper surface of the barrier layer; Use a first etching of the SiO2 layer in the source-drain ohmic contact region to the upper surface of the barrier layer to form a first window region; Etch the GaN layer and the barrier layer in the first window region, etch to below the heterojunction interface of the GaN layer and the barrier layer to form a first groove, and then perform an annealing treatment using a high-temperature annealing furnace; Based on the first etching of the SiO2 layer, continue a second etching of the SiO2 layer to obtain a second window region with an enlarged horizontal projection area based on the first window region; Secondarily epitaxially grow an n-type heavily doped GaN material in the second window region; Selectively etch the SiO2 layer in the gate region to the upper surface of the barrier layer to form a gate growth region and retain a part of the SiO2 layer, wherein the inner edge of the second window region is closer to the gate growth region than the inner edge of the first window region; And Set a gate electrode in Schottky contact with the barrier layer in the gate growth region and respectively set a source electrode and a drain electrode on the n-type heavily doped GaN material, such that the retained part of the SiO2 layer serves as a mask during the growth of the gate electrode and serves as an insulating medium between the gate electrode and the n-type heavily doped GaN material.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The horizontal distance from the edge of the second window region obtained by the second etching of the SiO2 layer to the edge of the first window region obtained by the first etching of the SiO2 layer is between 0 - 100 nm.

3. The method for manufacturing a semiconductor device according to claim 1, wherein The continuing the second etching of the SiO2 layer based on the first etching of the SiO2 layer is to continue the second etching of the SiO2 layer to the upper surface of the barrier layer based on the first etching of the SiO2 layer; the second window region exposes the first groove and a part of the upper surface of the barrier layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein The thickness of the n-type heavily doped GaN material exceeds the upper surface of the barrier layer.

5. The method for manufacturing a semiconductor device according to claim 3, wherein, The secondarily epitaxially growing the n-type heavily doped GaN material in the second window region is to secondarily epitaxially grow the n-type heavily doped GaN material in the first groove and on a part of the upper surface of the barrier layer outside the first groove.

6. The method for manufacturing a semiconductor device according to claim 1, wherein, The SiO2 layer that defines the second window region has an inclined side surface.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, The material used for the barrier layer is AlGaN, InAlN, or AlN.

8. The method for manufacturing a semiconductor device according to claim 1, wherein, The thickness of the SiO2 layer is 20 - 300 nm.

9. A semiconductor device, which is obtained by the semiconductor device manufacturing method according to any one of claims 1 to 8, characterized in that, Including: A substrate; A GaN layer and a barrier layer successively formed on the substrate; A first groove, the first groove is formed by etching the GaN layer and the barrier layer, and the bottom surface of the first groove is located below the heterojunction interface of the GaN layer and the barrier layer; An n-type heavily doped GaN material, the n-type heavily doped GaN material is formed in the first groove and on the upper surface of the barrier layer adjacent to the first groove; A gate electrode, the gate electrode is formed on the barrier layer; A source electrode and a drain electrode, the source electrode and the drain electrode are formed on the n-type heavily doped GaN material; and The SiO2 layer is formed on the upper surface of the barrier layer, defining a second window region with a horizontally projected area larger than that of the first groove, and defining a gate growth region. Part of the n-type heavily doped GaN material is formed on the upper surface of the barrier layer in the second window region. The gate electrode is formed in the gate growth region, and the SiO2 layer is located between the gate electrode and the n-type heavily doped GaN material, serving as the insulating medium between the gate electrode and the n-type heavily doped GaN.

10. The semiconductor device according to claim 9, wherein The horizontal distance from the edge position of the first groove to the edge position of the adjacent n-type heavily doped GaN material on the barrier layer is between 0 and 100 nm.

11. The semiconductor device according to claim 9, characterized in that, The thickness of the n-type heavily doped GaN material exceeds the upper surface of the barrier layer.

12. The semiconductor device according to claim 9, wherein, The side of the SiO2 layer close to the n-type heavily doped GaN material has an inclined side surface.

13. The semiconductor device according to claim 9, wherein, The material used for the barrier layer is AlGaN, InAlN or AlN.

14. The semiconductor device according to claim 9, characterized in that, The thickness of the SiO2 layer is 20 - 300 nm.

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