A method for manufacturing a semiconductor structure

Abstract

This invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate having a plurality of shallow trench isolation structures, and having a first barrier oxide layer, an anti-reflection layer, and a photoresist layer sequentially covering the substrate and the shallow trench isolation structures; removing the photoresist layer, the anti-reflection layer, and a portion of the first barrier oxide layer using an anisotropic etching process, the remaining first barrier oxide layer constituting a second barrier oxide layer, the thickness of the second barrier oxide layer being less than half the thickness of the first barrier oxide layer; removing the second barrier oxide layer using an isotropic etching process; and forming a memory gate structure on the substrate. By removing most of the thickness of the first barrier oxide layer using anisotropic etching, the process time of the isotropic etching process is shortened, thereby reducing the size of the sidewall gaps in the shallow trench isolation structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory devices feature small cell size, good memory retention, low operating voltage, and compatibility with CMOS processes. Figure 1 A schematic diagram of the existing SONOS flash memory, such as Figure 1 As shown, a conventional SONOS flash memory device includes a substrate 20 and a memory gate structure located on the substrate 20. The substrate 20 has a plurality of shallow trench isolation structures 21 extending along a first direction x and distributed along a second direction y. The memory gate structure includes an ONO layer 23 covering the substrate 20 and the shallow trench isolation structures 21, and memory gates 22 extending along the second direction y and distributed along the first direction x. (See reference...) Figure 1 During the removal of each film layer on the substrate 20, lateral erosion of the shallow trench isolation structure 21 is inevitable. This leads to large lateral gaps at the interface between the shallow trench isolation structure 21 and the substrate 20, reducing the top surface area of ​​the shallow trench isolation structure 21. Consequently, the ONO layer 23 on the shallow trench isolation structure 21 is more susceptible to erosion in subsequent fabrication processes (e.g., ...). Figure 1 (As shown in the middle circle), in severe cases, it can even cause the storage gate 22 to detach, adversely affecting the performance of the SONOS flash memory. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure to solve the problem of large lateral gaps in the shallow trench isolation structure during the fabrication of existing SONOS flash memory.

[0004] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising:

[0005] A substrate is provided, wherein the substrate has a plurality of shallow trench isolation structures, and the substrate has a first barrier oxide layer, an anti-reflection layer and a photoresist layer that sequentially cover the substrate and the shallow trench isolation structures;

[0006] An anisotropic etching process is used to remove the photoresist layer, the antireflection layer, and a portion of the first barrier oxide layer. The remaining first barrier oxide layer constitutes the second barrier oxide layer, and the thickness of the second barrier oxide layer is less than half the thickness of the first barrier oxide layer.

[0007] The second barrier oxide layer is removed using an isotropic etching process;

[0008] A storage gate structure is formed on the substrate.

[0009] Optionally, the step of forming the memory gate structure on the substrate includes:

[0010] A stacked gate dielectric layer, a memory gate material layer, and a hard mask layer are formed, wherein the gate dielectric layer, the memory gate material layer, and the hard mask layer sequentially cover the substrate and the shallow trench isolation structure;

[0011] After removing the hard mask layer and the memory gate material layer on the shallow trench isolation structure, the remaining memory gate material layer covers a portion of the gate dielectric layer on the substrate to form a memory gate, and the memory gate and the gate dielectric layer it covers constitute the memory gate structure.

[0012] Optionally, after forming the memory gate structure, the method further includes:

[0013] Using the remaining hard mask layer as a mask, a first ion implantation process is performed on the substrates on both sides of the gate structure to form source / drain regions within the substrates.

[0014] Remove the hard mask layer.

[0015] Optionally, prior to the anisotropic etching process, the top surface of the shallow trench isolation structure is higher than the top surface of the substrate.

[0016] Optionally, while removing the photoresist layer, the antireflective layer, and a portion of the first barrier oxide layer using an anisotropic etching process, the second barrier oxide layer on the shallow trench isolation structure is also removed, along with a portion of the thickness of the shallow trench isolation structure, leaving the top surface of the remaining shallow trench isolation structure higher than the top surface of the second barrier oxide layer.

[0017] Optionally, while removing the remaining second barrier oxide layer using an isotropic etching process, a portion of the thickness of the shallow trench isolation structure is also removed, leaving the top surface of the remaining shallow trench isolation structure higher than the top surface of the substrate.

[0018] Optionally, the thickness of the second barrier oxide layer is

[0019] Optionally, the thickness of the first barrier oxide layer is

[0020] Optionally, the substrate has a storage region and a selection region, the storage gate structure is located on the storage region, and the storage gate structure is formed on the storage region while the selection gate structure is formed on the selection region.

[0021] Optionally, the first barrier oxide layer, the anti-reflection layer, and the photoresist layer cover the substrate of the storage region and the selection region. After removing a portion of the thickness of the photoresist layer, the anti-reflection layer, and the first barrier oxide layer on the storage region using an anisotropic etching process, the substrate further includes:

[0022] A second ion implantation process is performed on the substrate of the storage region to form a well region within the substrate of the storage region.

[0023] In the semiconductor structure fabrication method provided by this invention, the photoresist layer and anti-reflection layer on the substrate can provide protection for the substrate during early processes such as ion implantation, preventing high-energy doping ions from damaging the substrate. While removing the photoresist layer and the anti-reflection layer through anisotropic etching, a large portion of the thickness of the first barrier oxide layer is also removed. The remaining first barrier oxide layer constitutes a second barrier oxide layer, with the thickness of the second barrier oxide layer being less than half the thickness of the first barrier oxide layer. Since the anisotropic etching process only etches the film layer in a fixed direction, lateral erosion at the interface between the shallow trench isolation structure and the substrate can be avoided during the etching process, thereby preventing lateral gaps in the shallow trench isolation structure. The second barrier oxide layer can also prevent anisotropic etching from damaging the substrate. Then, the second barrier oxide layer is removed by isotropic etching. Since the anisotropic etching process has already removed more than half the thickness of the first barrier oxide layer, the remaining second barrier oxide layer can be completely removed in a shorter time. This shortens the process time of the isotropic etching process, reduces the lateral etching of the shallow trench isolation structure by the isotropic etching process, and thus reduces the size of the lateral gaps in the shallow trench isolation structure, reducing the impact of the lateral gaps on the memory gate structure and improving the performance of the flash memory device. Furthermore, isotropic etching generally has good selectivity, which can reduce damage to the substrate during etching. Attached Figure Description

[0024] Figure 1 A schematic diagram of the structure of a SONOS flash memory.

[0025] Figure 2 A flowchart of a method for fabricating a semiconductor structure is provided for embodiments of the present invention;

[0026] Figures 3-10 A schematic diagram of the corresponding steps in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0027] The attached figures are labeled as follows:

[0028] x - First direction; y - Second direction;

[0029] 20, 100 - Substrate; 21, 101 - Shallow trench isolation structure; 102 - First barrier oxide layer; 103 - Anti-reflection layer; 104 - Photoresist layer; 105 - Second barrier oxide layer; 106 - Lateral notch; 23, 107 - Gate dielectric layer; 108 - Storage gate material layer; 109 - Hard mask layer; 22, 110 - Storage gate; 111 - Source / drain region. Detailed Implementation

[0030] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0031] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the steps presented herein are not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described in the text may be added to the method.

[0032] This embodiment provides a method for fabricating a semiconductor structure. Figure 2 This is a flowchart of the method for fabricating the semiconductor structure. Figure 2 As shown, the method for fabricating the semiconductor structure includes:

[0033] Step S1: Provide a substrate having a plurality of shallow trench isolation structures, and the substrate having a first barrier oxide layer, an anti-reflection layer and a photoresist layer that sequentially cover the substrate and the shallow trench isolation structures;

[0034] Step S2: The photoresist layer, the antireflection layer, and a portion of the first barrier oxide layer are removed using an anisotropic etching process. The remaining first barrier oxide layer constitutes the second barrier oxide layer, and the thickness of the second barrier oxide layer is less than half the thickness of the first barrier oxide layer.

[0035] Step S3: Remove the second barrier oxide layer using an isotropic etching process;

[0036] Step S4: Form a plurality of memory gate structures on the substrate.

[0037] Figures 3-10 This is a schematic diagram of the corresponding steps in the method for fabricating the semiconductor structure provided in this embodiment. Next, we will combine... Figures 3-10 The method for preparing the semiconductor structure is described in detail.

[0038] like Figure 3 As shown, a substrate 100 is provided, the substrate 100 having a selection area (not shown) and a storage area, and the substrate 100 having a plurality of shallow trench isolation structures 101, the top surface of the shallow trench isolation structures 101 being higher than the top surface of the substrate 100.

[0039] like Figure 4 As shown, a first barrier oxide layer 102, an anti-reflection layer 103, and a photoresist layer 104 are stacked on the substrate 100. The first barrier oxide layer 102 conformally covers the substrate 100 and the shallow trench isolation structure 101. The anti-reflection layer 103 covers the first barrier oxide layer 102. The photoresist layer 104 covers the anti-reflection layer 103, and the upper surface of the photoresist layer 104 is flat.

[0040] Generally, the photoresist layer 104 and the anti-reflection layer 103 are used as barrier layers to perform ion implantation on the implantation region on the substrate 100 so that the substrate 100 has a specific conductivity type.

[0041] like Figures 4-5 As shown, an anisotropic etching process is used to remove the photoresist layer 104, the antireflection layer 103, and a portion of the first barrier oxide layer 102 on the storage area. The remaining first barrier oxide layer 102 constitutes the second barrier oxide layer 105, and the thickness of the second barrier oxide layer 105 is less than half the thickness of the first barrier oxide layer 102.

[0042] Since the top surface of the shallow trench isolation structure 101 in this embodiment is higher than the top surface of the substrate 100, and the film thickness on the shallow trench isolation structure 101 is less than the film thickness on the substrate 100, when the anisotropic etching process is performed, the first barrier oxide layer 102 on the top surface of the shallow trench isolation structure 101 will be etched first. When part of the thickness of the first barrier oxide layer 102 on the substrate 100 is removed, the first barrier oxide layer 102 on the shallow trench isolation structure 101 will be completely removed, and part of the thickness of the shallow trench isolation structure 101 will also be removed. Therefore, in this embodiment, the second barrier oxide layer 105 only covers the surface of the substrate 100.

[0043] In other alternative embodiments, the top surface of the shallow trench isolation structure 101 may be flush with the top surface of the substrate 100, and the second barrier oxide layer 105 simultaneously covers the substrate 100 and the shallow trench isolation structure 101.

[0044] Since the anisotropic etching process only etches the film layer in a fixed direction, it will not cause lateral erosion at the junction of the shallow trench isolation structure 101 and the substrate 100, which can effectively avoid the shallow trench isolation structure 101 from generating lateral gaps in the anisotropic etching process; at the same time, the second barrier oxide layer 105 can prevent the anisotropic etching process from damaging the substrate 100 and ensure device performance.

[0045] In this embodiment, the anisotropic etching process is dry etching; the thickness of the first barrier oxide layer 102 is... The thickness of the second barrier oxide layer 105 is

[0046] Then, a second ion implantation process is performed on the substrate 100 in the storage region to form a well region within the substrate 100 in the storage region. The second barrier oxide layer 105 protects the substrate 100 from damage by high-energy dopant ions during the second ion implantation process.

[0047] Finally, after removing a portion of the thickness of the photoresist layer 104, the anti-reflection layer 103, and the first barrier oxide layer 102 on the selected area, the remaining first barrier oxide layer 102 on the selected area constitutes the second barrier oxide layer 105.

[0048] like Figures 5-6 As shown, the second barrier oxide layer 105 on the storage region and the selection region is removed by an isotropic etching process. The isotropic etching process is a wet etching process, and a wet etchant with good selectivity for the oxide layer is used to avoid damage to the substrate 100 during the etching process.

[0049] Since the thickness on both sides of the shallow trench isolation structure 101 is less than the thickness in the middle, and etchant is easily deposited at the junction of the substrate 100 and the shallow trench isolation structure 101, lateral etching will inevitably occur at the junction of the shallow trench isolation structure 101 and the substrate 100 during the isotropic etching process, thereby forming a lateral notch 106 in the shallow trench isolation structure 101.

[0050] In this embodiment, an anisotropic etching process removes most of the thickness of the first barrier oxide layer 102, making the thickness of the second barrier layer 105 less than half the thickness of the first barrier layer 102. The thickness of the second barrier oxide layer 105 to be removed is relatively thin. The isotropic etching process can remove the second barrier oxide layer 105 in a shorter time, shortening the process time of the isotropic etching process and reducing the lateral etching of the shallow trench isolation structure 101 by the isotropic etching process. This reduces the size of the lateral notch 106 in the shallow trench isolation structure 101 and ensures the top surface area of ​​the shallow trench isolation structure 101.

[0051] Furthermore, in this embodiment, after the anisotropic etching process, a portion of the top surface of the shallow trench isolation structure 101 is higher than the height of the second barrier oxide layer 105, and the lowest height of the top surface of the shallow trench isolation structure 101 is still higher than the top surface of the substrate 100. When the isotropic etching process is performed, the thickness of a portion of the shallow trench isolation structure 101 is further reduced. The portion of the shallow trench isolation structure 101 higher than the substrate 100 can reduce the erosion of the shallow trench isolation structure 101 at the interface with the substrate 100 by the isotropic etching process, reduce the size of the lateral notch 106, and at the same time ensure the thickness of the shallow trench isolation structure 101, which is beneficial to ensuring the isolation effect of the shallow trench isolation structure 101 on the substrate 100, thereby ensuring device performance.

[0052] like Figures 7-8 As shown, a stacked gate dielectric layer 107, a storage gate material layer 108, and a hard mask layer 109 are formed on the substrate 100 of the storage region. The gate dielectric layer 107 covers the substrate 100 and the shallow trench isolation structure 101, the storage gate material layer 108 covers the gate dielectric layer 107, and the hard mask layer 109 covers the storage gate material layer 108.

[0053] The gate dielectric layer 107 is an ONO layer. Generally, the thickness of the gate dielectric layer 107 is small, so that after the gate dielectric layer 107 fills the lateral notch 106, a corresponding depression will also be formed on the gate dielectric layer 107.

[0054] like Figure 9 As shown, after removing part of the hard mask layer 109 and the memory gate material layer 108, the remaining memory gate material layer 108 constitutes the memory gate 110. The memory gate 110 is located on the substrate 100 between the shallow trench isolation structures 101. The memory gate 110 and the gate dielectric layer 107 constitute the memory gate structure.

[0055] like Figure 10As shown, using the remaining hard mask layer 109 as a mask, a first ion implantation process is performed on the substrate 100 on both sides of the storage gate 110 to form source / drain regions 111; then the hard mask layer 109 is removed.

[0056] During the removal of the hard mask layer 109, the gate dielectric layers 107 on both sides of the memory gate 110 will be damaged. However, due to the small size of the lateral notch 106 in the shallow trench isolation structure 101, the large and relatively flat area of ​​the top surface of the shallow trench isolation structure 101, and the small depression on the gate dielectric layer 107, the etching process will not cause triaxial erosion of the gate dielectric layer 107 on the top surface of the shallow trench isolation structure 101 and the surface of the substrate 100. This greatly reduces the erosion rate of the gate dielectric layer 107, reduces the damage to the gate dielectric layer 107, and effectively avoids lateral erosion of the gate dielectric layer 107 at the bottom of the memory gate 110, thereby preventing the memory gate 110 from falling off and ensuring the reliability of the device.

[0057] It should be noted that when the storage gate structure is formed on the storage area, a selection gate structure is also formed on the selection area. The method for forming the selection gate structure is a conventional procedure and will not be described in detail in this embodiment.

[0058] In summary, in the semiconductor structure fabrication method provided by the embodiments of the present invention, the photoresist layer and anti-reflection layer on the substrate can provide protection for the substrate during early processes such as ion implantation, preventing high-energy doping ions from damaging the substrate. While removing the photoresist layer and the anti-reflection layer through anisotropic etching, most of the thickness of the first barrier oxide layer is also removed. The remaining first barrier oxide layer constitutes the second barrier oxide layer, making the thickness of the second barrier oxide layer less than half the thickness of the first barrier oxide layer. Since the anisotropic etching process only etches the film layer in a fixed direction, lateral erosion at the interface between the shallow trench isolation structure and the substrate can be avoided during the etching process, thereby preventing lateral gaps in the shallow trench isolation structure. The second barrier oxide layer can also prevent anisotropic etching from damaging the substrate. Then, the second barrier oxide layer is removed by isotropic etching. Since the anisotropic etching process has already removed more than half of the thickness of the first barrier oxide layer, the remaining second barrier oxide layer can be completely removed in a short time, shortening the process time of the isotropic etching process, reducing the lateral etching of the shallow trench isolation structure by the isotropic etching process, thereby reducing the size of the lateral gap in the shallow trench isolation structure, reducing the impact of the lateral gap on the memory gate structure, improving the performance of the flash memory device, and the isotropic etching process generally has good selectivity, which can reduce the damage to the substrate during the etching process.

[0059] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a plurality of shallow trench isolation structures, the top surface of the shallow trench isolation structures is higher than the top surface of the substrate, and the substrate has a first barrier oxide layer, an anti-reflection layer and a photoresist layer that sequentially cover the substrate and the shallow trench isolation structures. An anisotropic etching process is used to remove the photoresist layer, the antireflection layer, and a portion of the first barrier oxide layer. The remaining first barrier oxide layer constitutes the second barrier oxide layer, and the thickness of the second barrier oxide layer is less than half the thickness of the first barrier oxide layer. The second barrier oxide layer is removed using an isotropic etching process; A storage gate structure is formed on the substrate.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The step of forming the memory gate structure on the substrate includes: A stacked gate dielectric layer, a memory gate material layer, and a hard mask layer are formed, wherein the gate dielectric layer, the memory gate material layer, and the hard mask layer sequentially cover the substrate and the shallow trench isolation structure; After removing the hard mask layer and the memory gate material layer on the shallow trench isolation structure, the remaining memory gate material layer covers a portion of the gate dielectric layer on the substrate to form a memory gate, and the memory gate and the gate dielectric layer it covers constitute the memory gate structure.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, After forming the memory gate structure, the method further includes: Using the remaining hard mask layer as a mask, a first ion implantation process is performed on the substrates on both sides of the memory gate structure to form source / drain regions within the substrates; Remove the hard mask layer.

4. The method for preparing the semiconductor structure according to claim 1, characterized in that, Before the anisotropic etching process is performed, the top surface of the shallow trench isolation structure is higher than the top surface of the substrate.

5. The method for preparing the semiconductor structure as described in claim 4, characterized in that, While removing the photoresist layer, the antireflective layer, and a portion of the first barrier oxide layer using an anisotropic etching process, the second barrier oxide layer on the shallow trench isolation structure is also removed, along with a portion of the thickness of the shallow trench isolation structure. The top surface of the remaining shallow trench isolation structure is higher than the top surface of the second barrier oxide layer.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, While removing the remaining second barrier oxide layer using an isotropic etching process, a portion of the thickness of the shallow trench isolation structure is also removed, leaving the top surface of the remaining shallow trench isolation structure higher than the top surface of the substrate.

7. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The thickness of the second barrier oxide layer is 30 Å to 20 Å.

8. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The thickness of the first barrier oxide layer is 150 Å to 130 Å.

9. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The substrate has a storage region and a selection region, and the storage gate structure is located on the storage region. The storage gate structure is formed on the storage region, and the selection gate structure is formed on the selection region at the same time.

10. The method for preparing the semiconductor structure according to claim 9, characterized in that, The substrate covering the storage region and the selection region, consisting of the first barrier oxide layer, the anti-reflection layer, and the photoresist layer, after a portion of the thickness of the photoresist layer, the anti-reflection layer, and the first barrier oxide layer on the storage region is removed using an anisotropic etching process, further comprising: A second ion implantation process is performed on the substrate of the storage region to form a well region within the substrate of the storage region.

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