High power dissipation double-sided plastic package aiP system-in-package structure and method

Abstract

The application relates to a high-power double-face plastic-sealed AiP system-level packaging structure and method, which comprises a substrate, a main-face first plastic-sealed unit and a main-face second plastic-sealed unit, wherein the main-face first plastic-sealed unit comprises a plurality of first main-face chip bodies, a first main-face plastic-sealed layer and a heat dissipation fin; the main-face second plastic-sealed unit comprises a plurality of second main-face chip bodies, a second main-face plastic-sealed layer, an antenna unit and a packaging lead-out body unit for leading out the system packaging structure; the packaging lead-out body unit comprises a switching unit body in the second main-face plastic-sealed layer and a packaging lead-out connecting body outside the second main-face plastic-sealed layer, the packaging lead-out connecting body is located on the switching unit body and is interconnected with the substrate through the switching unit body to lead out the formed system packaging structure after the interconnection. The application can effectively realize high-integration packaging, integrate the antenna in the packaging, effectively avoid signal interference, has high heat dissipation performance and is safe and reliable.

Description

Technical Field

[0001] This invention relates to a system-in-package (SIP) structure and method, and more particularly to a high-power double-sided plastic-encapsulated AiP (AIP) system-in-package structure and method. Background Technology

[0002] As the number of system I / O (input / output) components continues to increase, traditional two-dimensional packaging structures can no longer meet the requirements, necessitating higher-density packaging to satisfy the needs of practical applications. In existing three-dimensional packaging structures, chips and passive components are typically soldered on the front side, while I / O outputs are located on the back. This packaging structure results in a relatively low integration density within the effective area, failing to meet the requirements of small, thin, and lightweight designs in consumer electronics and other similar applications.

[0003] Currently, in applications requiring antennas, chips and antennas are typically placed separately. This separate placement increases the overall system area and also increases interconnection losses between the chip and antenna, hindering product miniaturization and high-performance requirements. For consumer applications, especially wearable devices, it is generally required that chips and the chip and antenna do not interfere with each other. However, system-in-package (SoC) typically uses a monolithic plastic encapsulation, which cannot effectively achieve electromagnetic shielding between chips and between the chip and antenna, resulting in signal quality that fails to meet system requirements.

[0004] Traditional system-in-package (SoC) structures encapsulate chips within EMC (Epoxy Molding Compound) for protection. However, EMC materials have limited thermal conductivity. This is particularly problematic for high-power systems, where effective heat dissipation of the system structure is inadequate. As package structures become increasingly integrated, heat dissipation must be considered, especially for high-power chip systems, to prevent inefficient heat dissipation from impacting the package's operation. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a high-power double-sided plastic-encapsulated AiP system-in-package structure and method, which can effectively achieve high integration packaging, integrate antennas in the package, effectively avoid signal interference, have high heat dissipation performance, and be safe and reliable.

[0006] According to the technical solution provided by the present invention, the high-power double-sided molded AiP system-in-package structure includes a substrate having a first main surface and a second main surface, a first main surface molding unit disposed on the first main surface of the substrate, and a second main surface molding unit disposed on the second main surface of the substrate, wherein...

[0007] The first main surface of the substrate corresponds to the second main surface of the substrate. The first molding unit of the main surface includes a plurality of first main surface chip bodies interconnected with the substrate, a first main surface molding layer for molding the first main surface chip bodies on the first main surface of the substrate, and a heat sink for dissipating heat from the first main surface chip bodies.

[0008] The second molding unit on the main surface includes a plurality of second main surface chip bodies interconnected with the substrate, a second main surface molding layer for molding the second main surface chip bodies on the second main surface of the substrate, an antenna unit for interconnecting with the substrate, and a packaging lead-out unit for leading out the system packaging structure.

[0009] The encapsulation lead unit includes a transition unit located within the second main surface molding layer and an encapsulation lead connector located outside the second main surface molding layer. The encapsulation lead connector is located on the transition unit and interconnects with the substrate as required through the transition unit to lead out the system encapsulation structure formed after interconnection.

[0010] The first main surface chip body and the second main surface chip body include functional chips;

[0011] When the functional chip used in the second main surface chip body is a signal-sensitive chip, it also includes a cavity shielding body for cavitating the signal-sensitive chip, so as to use the cavity shielding body to shield the signal-sensitive chip and the antenna unit from each other.

[0012] The cavity shielding body includes cavity shielding connecting posts embedded in the second main surface molding layer and a shielding surrounding layer electrically connected to the cavity shielding connecting posts, wherein...

[0013] The shielding surround layer surrounds the substrate, the first molding unit on the main surface, and the second molding unit on the main surface. The shielding surround layer is electrically connected to the grounding line layer in the substrate, and the shielding surround layer is electrically connected to the signal sensitive chip adapter through the cavity shielding connection post, so as to form a shielding cavity for shielding and isolating the signal sensitive chip from the antenna unit by using the cavity shielding connection post and the shielding surround layer.

[0014] The adapter unit includes an adapter plate and a plurality of adapter lead-out connecting posts located within the adapter plate, wherein...

[0015] The adapter lead-out connection post passes through the adapter board. One end of the adapter lead-out connection post is electrically connected to the corresponding substrate, and the other end of the adapter lead-out connection post is electrically connected to the corresponding package lead-out connection body.

[0016] The adapter board includes a silicon adapter board, and the encapsulated lead-out connector includes lead-out connection pads and lead-out connection solder balls disposed on the lead-out connection pads, wherein...

[0017] Lead-out connection pads cover the adapter board. The lead-out connection pads correspond one-to-one with the adapter lead-out connection posts in the adapter board. The lead-out connection solder balls correspond one-to-one with the lead-out connection pads. A lead-out connection solder ball is interconnected with the substrate through the corresponding lead-out connection pad and the adapter lead-out connection post.

[0018] The antenna unit includes an antenna unit layer disposed on the second main surface molding layer and an antenna unit connecting post disposed in the adapter plate. The antenna unit layer is interconnected with the substrate as required through the antenna unit connecting post.

[0019] The antenna unit connecting post is embedded in the adapter plate.

[0020] A plurality of substrate first main surface connection pads are provided on the first main surface of the substrate for leading out the substrate internal circuit layers from the first main surface, and a plurality of substrate second main surface connection pads are provided on the second main surface of the substrate for leading out the substrate internal circuit layers from the second main surface, wherein...

[0021] The first main surface chip body is connected to the circuit layer inside the substrate by leading out a connection pad on the corresponding first main surface of the substrate, so as to perform the required interconnection with the substrate.

[0022] The second main surface chip body, antenna unit, and package lead-out body unit are electrically connected to the circuit layer adapter in the substrate through the corresponding lead-out connection pads on the second main surface of the substrate, so as to perform the required interconnection with the substrate.

[0023] The heat sink covers the first main surface molding layer and is in direct contact with the first main surface chip body inside the first main surface molding layer.

[0024] When the heat sink is larger than the first main surface molding layer, and the shielding surrounding layer surrounds the substrate, the first main surface molding unit, and the corresponding side of the second main surface molding unit, the shielding surrounding layer contacts the corresponding outer edge of the substrate adjacent to the heat sink.

[0025] A method for fabricating a high-power double-sided molded AiP system-in-package (AIP) structure includes:

[0026] A substrate is provided having a first main surface and a second main surface, wherein the first main surface of the substrate corresponds directly to the first main surface of the substrate;

[0027] A first molding compound unit is fabricated on a first main surface of the provided substrate, and a second molding compound unit is fabricated on a second main surface of the substrate, wherein...

[0028] The prepared main surface first molding unit includes a plurality of first main surface chip bodies interconnected with the substrate, a first main surface molding layer for molding the first main surface chip bodies on the first main surface of the substrate, and a heat sink for dissipating heat from the first main surface chip bodies.

[0029] The prepared second molding unit on the main surface includes a plurality of second main surface chip bodies interconnected with the substrate, a second main surface molding layer for molding the second main surface chip bodies on the second main surface of the substrate, an antenna unit for interconnecting with the substrate, and a packaging lead-out unit for leading out the system packaging structure.

[0030] The encapsulation lead unit includes a transition unit located within the second main surface molding layer and an encapsulation lead connector located outside the second main surface molding layer. The encapsulation lead connector is located on the transition unit and interconnects with the substrate as required through the transition unit to lead out the system encapsulation structure formed after interconnection.

[0031] When fabricating the first molding unit on the main surface, a first main surface chip body is provided, and the provided first main surface chip body includes a first main surface chip body pad.

[0032] After aligning the corresponding first main surface chip pads with the first main surface lead-out connection pads on the first main surface of the substrate, the first main surface chip body is soldered and fixed so that the first main surface chip body and the substrate can be interconnected as required.

[0033] A molding process is performed on the first main surface of the substrate to obtain a first main surface molding layer, wherein the first main surface chip body is molded on the first main surface of the substrate using the first main surface molding layer, and the back side of the first main surface chip body is exposed from the first main surface molding layer.

[0034] The heat sink is attached to the first main surface molding layer, and the heat sink is in direct contact with the back of the first main surface chip.

[0035] When fabricating the second molding unit on the main surface, the required second main surface chip body and the adapter unit body are provided. The provided second main surface chip body includes the second main surface chip body pads, and the provided adapter unit body includes the adapter unit body pads.

[0036] The corresponding second main surface chip pads and the transition unit pads of the transition unit are aligned with the lead-out connection pads on the second main surface of the substrate and then soldered to fix them so that the second main surface chip and the transition unit can be interconnected with the substrate as required.

[0037] A molding process is performed on the second main surface of the substrate to obtain a second main surface molding layer, wherein the second main surface chip body and the adapter unit body are molded on the second main surface of the substrate using the second main surface molding layer, and the adapter unit body is exposed from the second main surface molding layer.

[0038] An antenna unit interconnected with a substrate and a packaged lead-out connector adapted to electrically connect to an adapter unit body are fabricated.

[0039] The adapter unit includes an adapter plate, an antenna unit connecting post located within the adapter plate, and several adapter lead-out connecting posts located within the adapter plate.

[0040] When fabricating the antenna element, an antenna element layer is fabricated on the second main surface molding layer, and the antenna element layer is interconnected with the substrate through antenna element connecting posts;

[0041] When fabricating the packaged lead-out connector, lead-out connection pads and lead-out connection solder balls are fabricated on the adapter board, wherein...

[0042] Lead-out connection pads cover the adapter board. The lead-out connection pads correspond one-to-one with the adapter lead-out connection posts in the adapter board. The lead-out connection solder balls correspond one-to-one with the lead-out connection pads. A lead-out connection solder ball is interconnected with the substrate through the corresponding lead-out connection pad and the adapter lead-out connection post.

[0043] The adapter plate is made of silicon;

[0044] Before the second main surface molding layer is prepared, the adapter body plate used to form the adapter plate is interconnected with the substrate as required.

[0045] After performing a molding process on the second main surface of the substrate, a second main surface molded body is obtained. The second main surface molded body is then thinned to obtain the required second main surface molding layer. While the second main surface molded body is being thinned, the adapter body is also being thinned simultaneously to form an adapter plate using the thinned adapter body.

[0046] The antenna unit layer and lead-out connection pads are fabricated using RDL technology, and the thickness of the adapter board is greater than the thickness of the second main surface chip body.

[0047] The second main surface chip body includes a functional chip and / or a signal-sensitive chip. When the second main surface chip body is a signal-sensitive chip, it also includes a cavity shield for cavitary shielding of the signal-sensitive chip, so as to use the cavity shield to shield the signal-sensitive chip and the antenna unit from each other.

[0048] The cavity shielding body includes cavity shielding connecting posts embedded in the second main surface molding layer and a shielding surrounding layer electrically connected to the cavity shielding connecting posts, wherein...

[0049] The shielding surround layer surrounds the substrate, the first molding unit on the main surface, and the corresponding sides of the second molding unit on the main surface. The shielding surround layer is electrically connected to the grounding line layer in the substrate, and the shielding surround layer is electrically connected to the signal sensitive chip adapter through the cavity shielding connection post, so as to form a shielding cavity for shielding and isolating the signal sensitive chip from the antenna unit by using the cavity shielding connection post and the shielding surround layer.

[0050] After the second main surface molding body is prepared, a cavity shielding connection groove is formed in the second main surface molding body using a laser grooving process;

[0051] The cavity shielding connector is obtained by filling the cavity shielding connector groove. When the second main surface encapsulation is thinned, the cavity shielding connector is cut to obtain the cavity shielding connector.

[0052] The process methods for preparing the shielding surrounding layer include magnetron sputtering.

[0053] Advantages of the present invention: A first molding unit is provided on the first main surface of the substrate, and a second molding unit is provided on the second main surface of the substrate. The first main surface chip body in the first molding unit is cooled by a heat sink mounted on the first main surface molding layer, which ensures effective heat dissipation of the high-power chip and guarantees the thermal performance of the system.

[0054] The second molding unit on the main surface integrates the second main surface chip body, the antenna unit, and the package lead-out connector. When the second main surface chip body is a signal-sensitive chip, the cavity shielding body is used to shield and isolate the signal-sensitive chip and the antenna unit, effectively avoiding signal interference. When the package lead-out connector is connected by an adapter board, the integration and reliability of the package can be improved. Attached Figure Description

[0055] Figure 1 This is a schematic diagram illustrating the system-level packaging of the present invention.

[0056] Figures 2 to 14 This is a cross-sectional view of a specific process implementation step of the present invention, wherein...

[0057] Figure 2 This provides a cross-sectional view of the first main surface chip body and the substrate for the present invention.

[0058] Figure 3 This is a cross-sectional view of the first main surface chip body interconnected with the substrate according to the present invention.

[0059] Figure 4 This is a cross-sectional view of the first main surface encapsulated body prepared according to the present invention.

[0060] Figure 5 This is a cross-sectional view of the first main surface encapsulant after thinning to form the first main surface encapsulant layer according to the present invention.

[0061] Figure 6 This is a cross-sectional view of the heat sink after it has been prepared according to the present invention.

[0062] Figure 7 This is a schematic diagram of the substrate after it has been flipped according to the present invention.

[0063] Figure 8 This is a cross-sectional view of the second main surface chip body and the adapter board and substrate after interconnection according to the present invention.

[0064] Figure 9 This is a cross-sectional view of the second main surface encapsulated body prepared according to the present invention.

[0065] Figure 10 This is a cross-sectional view of the cavity shielded connector prepared according to the present invention.

[0066] Figure 11 This is a cross-sectional view of the second main surface encapsulant after thinning to form the second main surface encapsulant layer according to the present invention.

[0067] Figure 12 This is a cross-sectional view of the antenna unit layer prepared according to the present invention, after the lead-out connection pads are exposed.

[0068] Figure 13 This is a cross-sectional view of the shielding surrounding layer prepared for the present invention.

[0069] Figure 14 This is a cross-sectional view of the solder balls after they have been brought out for this invention.

[0070] Explanation of reference numerals in the attached drawings: 1-Substrate, 2-Inner circuit layer of substrate, 3-First main surface molding layer, 4-Second main surface molding layer, 5-Heat sink, 6-Shielding first unit, 7-First functional chip, 8-Second functional chip, 9-Third functional chip, 10-Shielding second unit, 11-Signal sensitive chip, 12-Cavity shield, 13-Antenna unit, 14-Adapter board, 15-Lead-out connection solder ball, 16-Lead-out chip connection pad on the first main surface of the substrate, 17-First main surface chip body pad, 18-Lead-out connection pad, 19- Antenna unit pad, 20-Second main surface lead-out chip connection first pad, 21-Second main surface lead-out chip connection second pad, 22-First main surface molding compound, 23-Shielding support edge, 24-Sensitive chip pad, 25-Adapter main board, 26-Adapter lead-out connection post, 27-Antenna unit connection post, 28-Antenna unit connection post pad, 29-Adapter lead-out connection post pad, 30-Second main surface molding compound, 31-Cavity shielding connector, 32-Cavity shielding connection post, 33-Antenna unit layer, and 34-Lead-out connection pad. Detailed Implementation

[0071] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0072] like Figure 1 and Figure 14 As shown: In order to effectively achieve high integration packaging and improve heat dissipation, the high-power double-sided plastic-encapsulated AiP (Antenna-in-package) system-in-package structure of the present invention specifically includes: a substrate 1 having a first main surface and a second main surface, a first main surface plastic-encapsulating unit disposed on the first main surface of the substrate 1, and a second main surface plastic-encapsulating unit disposed on the second main surface of the substrate 1, wherein,

[0073] The first main surface of the substrate 1 corresponds to the second main surface of the substrate 1. The first molding unit of the main surface includes a plurality of first main surface chip bodies interconnected with the substrate 1, a first main surface molding layer 3 for molding the first main surface chip bodies on the first main surface of the substrate 1, and a heat sink 5 for dissipating heat from the first main surface chip bodies.

[0074] The second molding unit on the main surface includes a plurality of second main surface chip bodies interconnected with the substrate 1, a second main surface molding layer 4 for molding the second main surface chip bodies on the second main surface of the substrate 1, an antenna unit 13 for interconnecting with the substrate 1, and a packaging lead-out unit for leading out the system packaging structure.

[0075] The encapsulation lead-out unit includes a transition unit located within the second main surface molding layer 4 and an encapsulation lead-out connector located outside the second main surface molding layer 4. The encapsulation lead-out connector is located on the transition unit and interconnects with the substrate 1 as required through the transition unit, so as to lead out the system encapsulation structure formed after interconnection.

[0076] Specifically, the substrate 1 can adopt a commonly used form. An internal circuit layer 2 is provided within the substrate 1. The specific details of the internal circuit layer 2 can be selected according to actual needs to meet the requirements of the actual application. The substrate 1 can be plate-shaped and has a first main surface and a second main surface. The first main surface and the second main surface correspond to each other. Generally, the first main surface and the second main surface are two corresponding surfaces of the substrate 1. In specific implementation, the corresponding surface of the substrate 1 can be selected as the first main surface or the second main surface according to the actual situation. After selecting the first main surface, the other surface forms the second main surface.

[0077] A first molding unit is provided on the first main surface of the substrate 1, and a second molding unit is provided on the second main surface of the substrate 1. That is, the first molding unit corresponds to the first main surface of the substrate 1, and the second molding unit corresponds to the second main surface of the substrate 1, thereby forming a double-sided molding package.

[0078] The first molding unit on the main surface may specifically include a first main surface chip body, a first main surface molding layer 3, and a heat sink 5. The first main surface chip body is located within the first main surface molding layer 3. The first main surface chip body is used for interconnection with the substrate 1. The first main surface chip body can be a high-power functional chip in actual applications. The number and specific type of the first main surface chip body can be selected according to actual needs to meet the actual application requirements.

[0079] Figure 1 and Figure 14 The diagram illustrates a configuration where three first-main-surface chips are housed within the first-main-surface molding layer 3. These three chips are specifically a first functional chip 7, a second functional chip 8, and a third functional chip 9. The first functional chip 7, the second functional chip 8, and the third functional chip 9 are interconnected with the substrate 1. This interconnection specifically refers to the ability to perform necessary data interaction with the substrate 1. The type of data interaction during interconnection can be selected and determined as needed, and will not be elaborated here. A heat sink 5 is disposed on the first-main-surface molding layer 3. The heat sink 5 can directly dissipate heat from the first-main-surface chips, effectively improving heat dissipation capacity. The heat sink 5 can adopt commonly used heat dissipation methods, specifically designed to meet the heat dissipation requirements of the first-main-surface chips.

[0080] The second molding unit on the main surface may specifically include a second main surface chip body, a second main surface molding layer 4, an antenna unit 13, and a package lead-out unit. The second main surface chip body is located inside the second main surface molding layer 4. The specific situation of the second main surface chip body can be similar to that of the first main surface chip body. For details, please refer to the above description. Figure 1 The diagram illustrates a second main surface chip body disposed within the second main surface molding layer 4. The antenna unit 13 is interconnected with the substrate 1 to achieve coupling or signal transmission. The specific interconnection between the antenna unit 13 and the substrate 1 can be selected and determined as needed, and will not be elaborated here. The antenna unit 13 is integrated on the second main surface of the substrate 1, thus achieving a double-sided molding AiP system-in-package.

[0081] The system-level packaging structure is brought out through the packaging lead-out unit. Specifically, the system-level packaging structure refers to the packaging structure formed by the substrate 1, the first molding unit on the main surface, and the second molding unit on the main surface. After the system-level packaging structure is brought out through the packaging lead-out unit, the required connection or processing can be performed. The specific function and purpose of the lead-out can be consistent with the existing ones.

[0082] To further improve the integration of the package, the package lead unit includes a transition unit and a package lead connector. The transition unit is located within the second main surface molding layer 4, and the package lead connector is located on the transition unit. The package lead connector is interconnected with the substrate 1 through the transition unit, thus achieving interconnection and lead-out with the system-in-package structure. In specific implementation, the density of packaging and lead-out can be achieved through the transition of the transition unit.

[0083] Furthermore, the first main surface chip body and the second main surface chip body include a functional chip 11;

[0084] When the functional chip used in the second main surface chip body is a signal sensitive chip 11, it also includes a cavity shielding body 12 for cavity shielding of the signal sensitive chip 11, so as to use the cavity shielding body 12 to shield the signal sensitive chip 11 and the antenna unit 13 from each other.

[0085] As explained above, the first and second main surface chip bodies can be functional chips, such as signal amplification and analog-to-digital conversion chips. When the antenna unit 13 is disposed within the second plastic-encapsulated unit on the main surface, if the functional chip used in the second main surface chip body is a signal-sensitive chip 11, in order to improve the stability and reliability of the signal-sensitive chip 11, it is necessary to use a cavity shield 12 for cavity shielding. This cavity shielding achieves mutual shielding between the signal-sensitive chip 11 and the antenna unit 13, preventing mutual interference between them. The signal-sensitive chip 11 can adopt existing signal-sensitive types; signal sensitivity specifically refers to susceptibility to external signal interference. Using the cavity shield 12 for cavity shielding of the signal-sensitive chip 11 provides electromagnetic shielding between the signal-sensitive chip 11 and the antenna unit 13.

[0086] Furthermore, the cavity shielding body 12 includes a cavity shielding connecting post 32 embedded in the second main surface molding layer 4 and a shielding surrounding layer electrically connected to the cavity shielding connecting post 32, wherein,

[0087] The shielding surround layer surrounds the substrate 1, the first molding unit on the main surface, and the second molding unit on the main surface. The shielding surround layer is electrically connected to the grounding line layer in the substrate 1, and the shielding surround layer is adapted to be electrically connected to the signal sensitive chip 11 through the cavity shielding connection post 32, so as to form a shielding cavity for shielding and isolating the signal sensitive chip 11 and the antenna unit 13 by using the cavity shielding connection post 32 and the shielding surround layer.

[0088] To achieve cavity shielding, the cavity shielding body 12 includes cavity shielding connecting posts 32 and a shielding surrounding layer. The cavity shielding connecting posts 32 are located within the second main surface molding layer 4, and the length direction of the cavity shielding connecting posts 32 is perpendicular to the second main surface of the substrate 1. The shielding surrounding layer surrounds the substrate 1, the first molding unit of the main surface, and the second molding unit of the main surface, and the shielding surrounding layer is electrically connected to the grounding line layer in the substrate 1 to form a complete cavity shielding structure.

[0089] Figure 1 and Figure 14 In the cross-section of the system-in-package structure, the shielding surround layer includes a first shielding unit 6 and a second shielding unit 10. The first shielding unit 6 and the second shielding unit 10 are formed through the same process step and are interconnected as a single unit. The shielding surround layer surrounds the substrate 1, the first molding unit on the main surface, and the second molding unit on the main surface. Of course, in order to achieve connection with the cavity shielding connection post 32, Figure 1 and Figure 14 In this configuration, the first shielding unit 6 extends onto the second main surface molding layer 4, so that it makes contact with the cavity shielding connection post 32 after extension and then becomes electrically connected. That is, in cross-section, one end of the cavity shielding connection post 32 makes contact with the shielding surrounding layer on the second main surface molding layer 4 and becomes electrically connected. The cavity shielding connection post 32 is adapted to be electrically connected to the signal sensitive chip 11, and the cavity shielding connection post 32 is located between the signal sensitive chip 11 and the antenna unit 13.

[0090] Furthermore, a plurality of substrate first main surface connection pads are provided on the first main surface of the substrate 1 for leading out the substrate internal circuit layer 2 from the first main surface of the substrate 1, and a plurality of substrate second main surface connection pads are provided on the second main surface of the substrate 1 for leading out the substrate internal circuit layer 2 from the second main surface of the substrate 1, wherein,

[0091] The first main surface chip body is connected to the circuit layer 2 inside the substrate by a corresponding first main surface of the substrate through a connection pad, so as to perform the required interconnection with the substrate 1.

[0092] The second main surface chip body, antenna unit 13, and package lead-out body unit are electrically connected to the circuit layer 2 inside the substrate through the corresponding lead-out connection pads on the second main surface of the substrate, so as to perform the required interconnection with the substrate 1.

[0093] As explained above, the internal circuit layer 2 is located within the substrate 1. When interconnected with the substrate 1, it interconnects with the internal circuit layer 2 within the substrate 1 as required. To achieve this interconnection, a first main surface lead-out connection pad is provided on the first main surface of the substrate 1, and a second main surface lead-out connection pad is provided on the second main surface of the substrate 1. The first main surface lead-out connection pad is mainly used to bring out the corresponding circuit functions of the internal circuit layer 2 to the first main surface of the substrate 1, and the second main surface lead-out connection pad is used to bring out the corresponding circuit functions of the internal circuit layer 2 to the second main surface of the substrate 1. The specific circuit functions of the internal circuit layer 2 can be selected as needed to ensure that the chip body on the first main surface is adapted and connected to the internal circuit layer 2 through the corresponding first main surface lead-out connection pad, and that the chip body, antenna unit 13, and package lead-out unit on the second main surface are adapted and electrically connected to the internal circuit layer 2 through the corresponding second main surface lead-out connection pad.

[0094] Furthermore, the heat sink 5 covers the first main surface molding layer 3 and is in direct contact with the first main surface chip body inside the first main surface molding layer 3;

[0095] When the heat sink 5 is larger than the first main surface molding layer 3, and the shielding surrounding layer surrounds the substrate 1, the first molding unit on the main surface, and the second molding unit on the main surface, the shielding surrounding layer contacts the corresponding outer edge of the substrate 1 adjacent to the heat sink 5.

[0096] In this embodiment of the invention, the heat sink 5 can adopt a commonly used heat dissipation method. The heat sink 5 covers the first main surface molding layer 3, that is, the first main surface molding layer 3 is located between the heat sink 5 and the substrate 1. In order to improve the heat dissipation effect, the heat sink 5 is in direct contact with the back of the first main surface chip body.

[0097] The heat sink 5 is larger than the first main surface molding layer 3. Specifically, the size of the heat sink 5 is larger than the size of the first main surface molding layer 3. In this case, the outer ring of the heat sink 5 is located at the outer ring of the first main surface molding layer 3, and the outer ring of the heat sink 5 and the outer ring edge of the first main surface molding layer 3 form a shielding support edge 23. That is, the shielding support edge 23 can support the shielding surround layer.

[0098] Furthermore, the adapter unit includes an adapter plate 14 and a plurality of adapter lead-out connecting posts 26 located within the adapter plate 14, wherein,

[0099] The adapter lead-out connection post 26 passes through the adapter plate 14. One end of the adapter lead-out connection post 26 is electrically connected to the substrate 1, and the other end of the adapter lead-out connection post 26 is electrically connected to the package lead-out connection body.

[0100] In this embodiment of the invention, the adapter unit includes a plate-shaped adapter plate 14 located within the second main surface molding layer 4. To enable the adapter connection, a plurality of adapter lead-out connection posts 26 are provided within the adapter plate 14, and the adapter lead-out connection posts 26 penetrate the adapter plate 14, forming a through-type distribution. After the adapter plate 14 is molded onto the second main surface of the substrate 1, one end of the adapter lead-out connection post 26 is electrically connected to the substrate 1, and the other end of the adapter lead-out connection post 26 is electrically connected to the encapsulation lead-out connector.

[0101] Furthermore, the adapter board 14 includes a silicon adapter board, and the packaged lead-out connector includes lead-out connector pads 34 and lead-out connector solder balls 15 disposed on the lead-out connector pads 34, wherein,

[0102] Lead-out connection pads 34 cover the adapter plate 14. The lead-out connection pads 34 correspond one-to-one with the adapter lead-out connection posts 26 in the adapter plate 14. Lead-out connection solder balls 15 correspond one-to-one with the lead-out connection pads 34. A lead-out connection solder ball 15 is interconnected with the substrate 1 as required through the corresponding lead-out connection pads 34 and adapter lead-out connection posts 26.

[0103] Specifically, the material of the adapter board 14 includes silicon, thus forming a silicon adapter board. The packaged lead-out connector includes lead-out connection pads 34, which cover the adapter board 14. Lead-out connection balls 15 can be disposed on the lead-out connection pads 34 by means of soldering or other methods. Each lead-out connection ball 15 corresponds one-to-one with the lead-out connection pads 34, and each lead-out connection pad 34 corresponds one-to-one with the transition lead-out connection post 26. Thus, for any lead-out connection ball 15, the required interconnection with the substrate 1 is achieved through the corresponding lead-out connection pad 34 and the transition lead-out connection post 26.

[0104] Figure 1 and Figure 14 The diagram illustrates a configuration where two adapter lead-out connectors 26 are provided within the adapter plate 14. Specifically, the adapter plate 14 has two lead-out connector pads 34 and two lead-out connector solder balls 15. However, in practice, the number of lead-out connector solder balls 15 and adapter lead-out connectors 26 can be selected according to actual needs, ensuring sufficient lead-out and interconnection with the substrate 1. In practice, the adapter lead-out connectors 26 are pre-embedded within the adapter plate 14.

[0105] Furthermore, the antenna unit 13 includes an antenna unit layer 33 disposed on the second main surface molding layer 4 and an antenna unit connecting post 27 disposed in the adapter plate 14. The antenna unit layer 33 is interconnected with the substrate 1 as required through the antenna unit connecting post 27.

[0106] To form the required antenna element 13, specifically, an antenna element layer 33 needs to be provided on the second main surface molding layer 4. The specific details of the antenna element layer 33 can be selected as needed to form the required antenna configuration. To achieve interconnection between the antenna element layer 33 and the substrate 1, an antenna element connecting post 27 is provided within the adapter plate 14, wherein the antenna element connecting post 27 is pre-embedded within the adapter plate 14. The antenna element layer 33 is interconnected with the substrate 1 as required through the antenna element connecting post 27.

[0107] Figure 1 and Figure 14 The diagram illustrates the case where an antenna element layer 33 is installed on the second main surface molding layer 4. In this case, an antenna element connecting post 27 is installed within the adapter plate 14. When multiple antenna elements 13 need to be installed, multiple antenna element layers 33 and a corresponding number of antenna element connecting posts 27 are required. The specific configuration can be selected as needed and will not be elaborated here. In specific implementation, the length direction of the antenna element connecting post 27 is parallel to the length direction of the adapter lead-out connecting post 26 and the corresponding length direction of the cavity shielding connecting post 32.

[0108] like Figures 2 to 14 As shown, the above-mentioned double-sided plastic-encapsulated AiP system-in-package structure can be prepared by the following high-power double-sided plastic-encapsulated AiP system-in-package method. Specifically, the specific process of the packaging method includes:

[0109] A substrate 1 is provided having a first main surface and a second main surface, wherein the first main surface of the substrate 1 corresponds directly to the first main surface of the substrate 1;

[0110] A first molding compound unit is fabricated on the first main surface of the provided substrate 1, and a second molding compound unit is fabricated on the second main surface of the substrate 1, wherein...

[0111] The prepared main surface first molding unit includes a plurality of first main surface chip bodies interconnected with the substrate 1, a first main surface molding layer 3 for molding the first main surface chip bodies on the first main surface of the substrate 1, and a heat sink 5 for dissipating heat from the first main surface chip bodies.

[0112] The prepared second molding unit on the main surface includes a plurality of second main surface chip bodies interconnected with the substrate 1, a second main surface molding layer 4 for molding the second main surface chip bodies on the second main surface of the substrate 1, an antenna unit 13 for interconnecting with the substrate 1, and a packaging lead-out unit for leading out the system packaging structure.

[0113] The encapsulation lead-out unit includes a transition unit located within the second main surface molding layer 4 and an encapsulation lead-out connector located outside the second main surface molding layer 4. The encapsulation lead-out connector is located on the transition unit and interconnects with the substrate 1 as required through the transition unit, so as to lead out the system encapsulation structure formed after interconnection.

[0114] Specifically, the details of substrate 1, the first molding unit on the main surface, and the second molding unit on the main surface can be found in the above description. Figures 2 to 14 The diagram illustrates the specific process steps of first fabricating a first molding compound unit on the first main surface of substrate 1, and then fabricating a second molding compound unit on the second main surface of substrate 1. Of course, in practice, the second molding compound unit can be fabricated first, and then the required first molding compound unit can be fabricated. The specific fabrication order can be selected as needed, based on the requirement of obtaining the system-in-package structure.

[0115] like Figures 2-6 As shown, the specific process of fabricating the first molding compound unit on the main surface is illustrated. Specifically, when fabricating the first molding compound unit on the main surface, a first main surface chip body is provided, which includes a first main surface chip body pad 17.

[0116] After aligning the first main surface chip body corresponding first main surface chip body pad 17 with the substrate first main surface lead-out connection pad on the first main surface of the substrate 1, the chip body is soldered and fixed so that the first main surface chip body and the substrate 1 can be interconnected as required.

[0117] A molding process is performed on the first main surface of the substrate 1 to obtain a first main surface molding layer 3, wherein the first main surface chip body is molded on the first main surface of the substrate 1 using the first main surface molding layer 3, and the back side of the first main surface chip body is exposed from the first main surface molding layer 3.

[0118] The heat sink 5 is attached to the first main surface molding layer 3, and the heat sink 5 is in direct contact with the back of the first main surface chip body.

[0119] Figure 2The diagram shows three first main surface chip bodies, namely a first functional chip 7, a second functional chip 8, and a third functional chip 9. Each of the first functional chip 7, the second functional chip 8, and the third functional chip 9 has a corresponding first main surface chip pad 17. The number of first main surface chip pads 17 and their corresponding connections with the first functional chip 7, the second functional chip 8, and the third functional chip 9 are consistent with existing designs, so as to meet the requirements of leading out the first functional chip 7, the second functional chip 8, and the third functional chip 9 and interconnecting them with the substrate 1.

[0120] In order to enable interconnection and cooperation with the first functional chip 7, the second functional chip body 8, and the third functional chip body 9, the substrate first main surface lead-out connection pads of the substrate 1 are substrate first main surface lead-out chip connection pads 16. The distribution of the substrate first main surface lead-out chip connection pads 16 on the first main surface of the substrate 1 can be selected as needed to meet the interconnection and cooperation with the first functional chip 7, the second functional chip body 8, and the third functional chip body 9. This will not be elaborated here.

[0121] After determining the correspondence between substrate 1 and the first main surface chip body, the corresponding first main surface chip body pad 17 is aligned with the substrate first main surface lead-out connection pad on the first main surface of substrate 1 and then soldered and fixed to enable the first main surface chip body and substrate 1 to achieve the required interconnection. Figure 3 As shown. Figure 3 In the process, the first functional chip 7, the second functional chip body 8, and the third functional chip body 9 are aligned and soldered to the corresponding first main surface chip body pads 17 and the corresponding first main surface chip lead-out pads 16 on the first main surface of the substrate 1, thereby achieving interconnection with the substrate 1.

[0122] To achieve Figure 3 After interconnection, molding is performed to obtain the first main surface molded body 22. The specific molding process and procedures are consistent with existing methods and are well known to those skilled in the art. The first main surface chip body is located within the first main surface molded body 22, such as... Figure 4 As shown.

[0123] The first main surface molding compound 22 prepared above is thinned so that the corresponding back surfaces of the first functional chip 7, the second functional chip body 8, and the third functional chip body 9 are exposed. Figure 5 As shown. Thinning methods may include masking, etc. After thinning, the first main surface molding compound 22 forms the first main surface molding layer 3, and the back sides of the first functional chip 7, the second functional chip body 8, and the third functional chip body 9 are flush with the surface of the first main surface molding layer 3.

[0124] After the first main surface molding layer 3 is prepared, the heat sink 5 is attached to the first main surface molding layer 3 so that the heat sink 5 is in direct contact with the back of the first functional chip 7, the second functional chip body 8, and the third functional chip body 9. Figure 6 As shown, the size of the heat sink 5 is larger than the size of the first main surface molding layer 3, so that a shielding support edge 23 is formed between the outer edge of the heat sink 5 and the outer edge of the first main surface molding layer 3.

[0125] like Figures 7-14 The diagram shows a cross-sectional view of the specific process steps for fabricating the second molding compound unit on the main surface. Specifically, when fabricating the second molding compound unit on the main surface, a second main surface chip body and a transition unit body are provided. The provided second main surface chip body includes a second main surface chip body pad, and the provided transition unit body includes a transition unit body pad.

[0126] The corresponding second main surface chip pads and the transition unit pads of the transition unit are aligned with the lead-out connection pads on the second main surface of the substrate 1 and then soldered and fixed so that the second main surface chip and the transition unit can be interconnected with the substrate 1 as required.

[0127] A molding process is performed on the second main surface of the substrate 1 to obtain a second main surface molding layer 4, wherein the second main surface chip body and the adapter unit body are molded on the second main surface of the substrate 1 using the second main surface molding layer 4, and the adapter unit body is exposed from the second main surface molding layer 4.

[0128] An antenna unit 13 interconnected with a substrate 1 and a packaged lead-out connector adapted to be electrically connected to an adapter unit body are prepared.

[0129] In specific implementation, a second main surface lead-out connection pad is provided on the second main surface of substrate 1. Figure 2 The diagram illustrates the specific configuration of the lead-out connection pads on the second main surface of the substrate when it mates with a second main surface chip body, an antenna unit 13, and an adapter unit body. Specifically, the lead-out connection pads on the second main surface of the substrate 1 include lead-out connection pads 18, antenna unit pads 19, second main surface lead-out chip connection first pads 20, and second main surface lead-out chip connection second pads 21. There are two lead-out connection pads 18, which mate with the adapter unit body. The antenna unit pad 19 mates with the antenna unit 13. The second main surface lead-out chip connection first pad 20 and the second main surface lead-out chip connection second pad 21 are used to mate with the second main surface chip body.

[0130] Figure 7 In the above, the substrate 1 is flipped so that the second main surface of the substrate 1 faces upward, in order to carry out subsequent processes.

[0131] Figure 8In this example, the second main surface chip body using the signal-sensitive chip 11 and the adapter board 25 are respectively assembled on the second main surface of the substrate 1. Specifically, the sensitive chip pad 24 of the signal-sensitive chip 11 is aligned and soldered to the first and second main surface lead-out chip connection pads 20 and 21. The antenna unit connection post pads 28 and 19 of the adapter board 25 are aligned and soldered to each other. The adapter lead-out connection post pads 29 and 18 of the adapter board 25 are aligned and soldered to each other. For cases where there are multiple signal-sensitive chips 11, multiple adapter boards 25, or the adapter board 25 has more antenna unit connection post pads 28 and adapter lead-out connection post pads 29, please refer to [the relevant documentation]. Figure 8 In addition to the above description, the specific requirements are based on whether it can achieve interconnection with substrate 1.

[0132] Figure 8 In the adapter main board 25, adapter lead-out connection posts 26 and antenna unit connection posts 27 are pre-embedded. Specifically, the adapter main board 25 has two adapter lead-out connection posts 26 and one antenna unit connection post 27. The adapter lead-out connection posts 26 are electrically connected to the adapter lead-out connection post pads 29 in a one-to-one correspondence, and the antenna unit connection post 27 is electrically connected to the antenna unit connection post pads 28 in a one-to-one correspondence. The lengths of both the adapter lead-out connection posts 26 and the antenna unit connection post 27 are less than the thickness of the adapter main board 25, and the adapter lead-out connection posts 26 and the antenna unit connection post 27 are parallel to each other.

[0133] like Figure 9 As shown, after performing a molding process on the second main surface of substrate 1, a second main surface molded body 30 is obtained. Figure 9 In this case, the thickness of the second main surface molding compound 30 is greater than the height of the adapter motherboard body 25 on the second main surface of the substrate 1, that is, the adapter motherboard body 25 is completely located within the second main surface molding compound 30; in addition, the height of the signal sensitive chip 11 on the second main surface of the substrate 1 is less than the height of the adapter motherboard body 25 on the second main surface of the substrate 1.

[0134] As can be seen from the above description, when the second main surface chip body adopts the signal sensitive chip 11, it is necessary to prepare a cavity shield 12 so as to shield and isolate the signal sensitive chip 11 from the antenna unit 13.

[0135] To fabricate the cavity-splitting shield 12, a cavity-splitting shield connector 31 is prepared within the second main surface molding compound 30. Specifically, a laser grooving process is used to form a cavity-splitting shield connector groove within the second main surface molding compound 30; the cavity-splitting shield connector 31 is then filled into the groove. Figure 10 As shown. Of course, in specific implementation, other technical means can also be used to prepare the required cavity shielding connector 31. Figure 10In the middle, after the cavity shielding connector 31 is filled in the second main surface molding compound 30, the lower end of the cavity shielding connector 31 is electrically connected to the first bonding pad 20 of the chip lead-out on the second main surface, and the upper end of the cavity shielding connector 31 is flush with the end face of the second main surface molding compound 30.

[0136] In specific implementation, since the cavity shielding connector 31 is electrically connected to the grounding line layer of the basic inner circuit layer 2 through the shielding surround, the second main surface lead-out chip connects the first pad 20 and the grounding pad of the signal sensitive chip 11 to be electrically connected.

[0137] In order to achieve subsequent connection and fit, the second main surface molding body 30 needs to be thinned to obtain the required second main surface molding layer 4; and when the second main surface molding body 30 is thinned, the adapter body plate 25 is thinned simultaneously so as to form the adapter plate 14 using the thinned adapter body plate 25.

[0138] In specific implementation, when thinning the second main surface encapsulation 30, the cavity shielding connector 31 is also reduced to obtain the cavity shielding connector 32, such as... Figure 11 As shown. During thinning, commonly used techniques in this field can be employed, such as grinding. The specific thinning technique can be selected as needed to meet the actual thinning objective. Alternatively, in practice, the second main surface molding compound 30 can be thinned first to form the second main surface molding layer 4. After forming the second main surface molding layer 4, the cavity shielding connection post 32 can be prepared using laser grooving or similar methods. The specific method for preparing the cavity shielding connection post 32 can be selected as needed, ensuring the required cavity shielding connection post 32 is prepared.

[0139] After thinning, the upper surface of the adapter plate 14 is flush with the surface of the second main surface molding layer 4, and the signal sensitive chip 11 is completely located within the second main surface molding layer 4. Within the adapter plate 14, the upper ends of the antenna unit connecting post 27 and the adapter lead-out connecting post 26 are exposed from within the adapter plate 14, as shown below. Figure 11 As shown. Figure 11 In the middle, the upper end of the cavity shielding connection post 32 is located above the back of the signal sensitive chip 11. In specific implementation, the thickness of the adapter plate 14 is greater than the thickness of the second main surface chip body.

[0140] like Figure 12The antenna element layer 33 is fabricated on the second main surface molding layer 4 using the RDL (Redistributed Layer) process, and lead-out connection pads 34 are fabricated on the adapter board 14. The lead-out connection pads 34 are flush with the surface of the adapter board 14 and the second main surface molding layer 4. The antenna element layer 33 and the lead-out connection pads 34 can be fabricated in the same process step, and the specific details of the antenna element layer 33 and the lead-out connection pads 34 can be selected as needed.

[0141] Specifically, the antenna element layer 33 is electrically connected to the antenna element connecting post 27. As described above, the antenna element layer 33 can be interconnected with the substrate 1 through the antenna element connecting post 27, thus fabricating the antenna element 13. The lead-out connection pads 34 correspond one-to-one with the transition lead-out connection posts 26 in the adapter board 14. The lead-out connection pads 34 and the transition lead-out connection posts 26 are electrically connected, that is, the lead-out connection pads 34 are interconnected with the substrate 1 as required through the transition lead-out connection posts 26.

[0142] like Figure 13 As shown, in order to form the cavity shield 12, a shielding surround layer also needs to be prepared. The shielding surround layer surrounds the substrate 1, the first molding unit on the main surface and the second molding unit on the main surface. The shielding surround layer is electrically connected to the grounding line layer in the substrate 1, and the shielding surround layer is adapted to be electrically connected to the signal sensitive chip 11 through the cavity shielding connection post 32, so as to form a shielding cavity for shielding and isolating the signal sensitive chip 11 and the antenna unit 13 by using the cavity shielding connection post 32 and the shielding surround layer.

[0143] In practice, the process for fabricating the shielding wrapping layer includes magnetron sputtering. When using magnetron sputtering to form the shielding metal layer used to form the shielding wrapping layer, it is necessary to ensure that the antenna element layer 33 and the lead-out connection pads 34 are not sputtered. This requires applying a protective film to the antenna element layer 33 and the lead-out connection pads 34, which is then removed after sputtering. The process conditions and procedures for magnetron sputtering can be selected according to actual needs, ensuring the desired shielding wrapping layer is obtained.

[0144] After the shielding wrapping layer surrounds the substrate 1, the first molding unit on the main surface, and the second molding unit on the main surface, the shielding wrapping layer can fill the shielding support edge 23. When the shielding wrapping layer surrounds the substrate 1, it can achieve electrical connection with the grounding line layer in the substrate 1. The grounding line layer in the substrate 1 is generally used for grounding. The specific situation of the grounding line layer in the substrate 1 can be consistent with the existing ones, and will not be described in detail here.

[0145] Of course, during magnetron sputtering, it is also necessary to ensure that the shielding surrounding layer covers the signal sensitive chip 11 and contacts the cavity shielding connection post 32, so that the cavity shielding connection post 32 and the shielding surrounding layer can form a shielding cavity, thereby improving the reliability of shielding between the shielding and the antenna unit 13.

[0146] like Figure 14 As shown, using a technique commonly used in this field, lead-out solder balls 15 are provided on the lead-out solder pads 34. The lead-out solder balls 15 correspond one-to-one with the lead-out solder pads 34, so that any lead-out solder ball 15 is interconnected with the substrate 1 through the corresponding lead-out solder pad 34 and the transition lead-out post 26.

[0147] In this embodiment of the invention, the lead-out connection solder balls 15 and the corresponding lead-out connections of the antenna unit layer 33 are realized through the adapter board 14, which can reduce the spacing during packaging and improve the integration and reliability of the packaging. The lead-out connection balls 15 can be easily adapted and connected to external FPCs (Flexible Printed Circuits), which can expand the scope of application, such as making it more suitable for wearable products.

Claims

1. A high-power double-sided plastic-encapsulated AiP system-in-package structure, characterized in that: The substrate (1) includes a substrate having a first main surface and a second main surface, a first main surface molding unit disposed on the first main surface of the substrate (1), and a second main surface molding unit disposed on the second main surface of the substrate (1), wherein, The first main surface of the substrate (1) corresponds to the second main surface of the substrate (1). The first main surface molding unit includes a plurality of first main surface chip bodies interconnected with the substrate (1), a first main surface molding layer (3) for molding the first main surface chip bodies on the first main surface of the substrate (1), and a heat sink (5) covering the first main surface molding layer (3) to dissipate heat from the first main surface chip bodies. The second molding unit on the main surface includes several second main surface chip bodies interconnected with the substrate (1), a second main surface molding layer (4) for molding the second main surface chip bodies on the second main surface of the substrate (1), an antenna unit (13) for interconnecting with the substrate (1), and a packaging lead-out unit for leading out the system-in-package structure. The encapsulation lead unit includes a transition unit located within the second main surface molding layer (4) and an encapsulation lead connector located outside the second main surface molding layer (4). The encapsulation lead connector is located on the transition unit and interconnects with the substrate (1) as required through the transition unit, so as to lead out the system-in-package structure formed after interconnection; wherein, The adapter unit includes an adapter plate (14), and the antenna unit (13) includes an antenna unit connecting post (27) disposed within the adapter plate (14).

2. The high-power double-sided molded AiP system-in-package structure according to claim 1, characterized in that: The first main surface chip body and the second main surface chip body include functional chips; When the functional chip used in the second main surface chip body is a signal sensitive chip (11), it also includes a cavity shield (12) for cavity shielding of the signal sensitive chip (11), so as to use the cavity shield (12) to shield the signal sensitive chip (11) and the antenna unit (13) from each other.

3. The high-power double-sided molded AiP system-in-package structure according to claim 2, characterized in that: The cavity shielding body (12) includes a cavity shielding connecting post (32) embedded in the second main surface plastic sealing layer (4) and a shielding surrounding layer electrically connected to the cavity shielding connecting post (32), wherein, The shielding surround layer surrounds the substrate (1), the first molding unit on the main surface and the second molding unit on the main surface. The shielding surround layer is electrically connected to the grounding line layer in the substrate (1), and the shielding surround layer is electrically connected to the signal sensitive chip (11) through the cavity shielding connection post (32) to form a shielding cavity for shielding and isolating the signal sensitive chip (11) and the antenna unit (13) by using the cavity shielding connection post (32) and the shielding surround layer.

4. The high-power double-sided molded AiP system-in-package structure according to any one of claims 1 to 3, characterized in that: The adapter unit also includes several adapter lead-out connecting posts (26) located within the adapter plate (14), wherein, The adapter lead-out connection post (26) passes through the adapter plate (14). One end of the adapter lead-out connection post (26) is electrically connected to the substrate (1), and the other end of the adapter lead-out connection post (26) is electrically connected to the package lead-out connection body.

5. The high-power double-sided molded AiP system-in-package structure according to claim 4, characterized in that: The adapter board (14) includes a silicon adapter board, and the encapsulated lead-out connector includes lead-out connector pads (34) and lead-out connector solder balls (15) disposed on the lead-out connector pads (34), wherein, Lead-out connection pads (34) cover the adapter plate (14). The lead-out connection pads (34) correspond one-to-one with the adapter lead-out connection posts (26) in the adapter plate (14). Lead-out connection solder balls (15) correspond one-to-one with the lead-out connection pads (34). A lead-out connection solder ball (15) is interconnected with the substrate (1) through the corresponding lead-out connection pads (34) and adapter lead-out connection posts (26).

6. The high-power double-sided plastic-encapsulated AiP system-in-package structure according to claim 4, characterized in that: The antenna unit (13) includes an antenna unit layer (33) disposed on the second main surface molding layer (4), and the antenna unit layer (33) is interconnected with the substrate (1) as required through the antenna unit connecting post (27).

7. The high-power double-sided molded AiP system-in-package structure according to claim 1, characterized in that: The antenna unit connecting post (27) is embedded in the adapter plate (14).

8. The high-power double-sided molded AiP system-in-package structure according to any one of claims 1 to 3, characterized in that: A plurality of substrate first main surface connection pads are provided on the first main surface of the substrate (1) for leading out the substrate internal circuit layer (2) of the substrate (1) from the first main surface, and a plurality of substrate second main surface connection pads are provided on the second main surface of the substrate (1) for leading out the substrate internal circuit layer (2) of the substrate (1) from the second main surface, wherein, The first main surface chip body is connected to the circuit layer (2) inside the substrate through the corresponding substrate first main surface lead-out connection pads to perform the required interconnection with the substrate (1). The second main surface chip body, antenna unit (13) and package lead-out unit are electrically connected to the circuit layer (2) inside the substrate through the corresponding substrate second main surface lead-out connection pads to perform the required interconnection with the substrate (1).

9. The high-power double-sided plastic-encapsulated AiP system-in-package structure according to claim 3, characterized in that: The heat sink (5) is in direct contact with the first main surface chip body inside the first main surface molding layer (3); When the heat sink (5) is larger than the first main surface molding layer (3), and the shielding surrounding layer surrounds the substrate (1), the first molding unit of the main surface and the second molding unit of the main surface, the shielding surrounding layer contacts the corresponding outer edge of the heat sink (5) adjacent to the substrate (1).

10. A high-power double-sided plastic-encapsulated AiP system-in-package method, characterized in that: The method for fabricating the high-power double-sided molded AiP system-in-package structure of claim 1 includes: A substrate (1) having a first main surface and a second main surface is provided, wherein the first main surface of the substrate (1) is directly opposite to the first main surface of the substrate (1); A first molding unit for the required main surface is fabricated on the first main surface of the provided substrate (1), and a second molding unit for the required main surface is fabricated on the second main surface of the substrate (1), wherein, The first molding unit of the main surface is prepared includes a plurality of first main surface chip bodies interconnected with the substrate (1), a first main surface molding layer (3) for molding the first main surface chip bodies on the first main surface of the substrate (1), and a heat sink (5) covering the first main surface molding layer (3) to dissipate heat from the first main surface chip bodies. The prepared main surface second molding unit includes a plurality of second main surface chip bodies interconnected with the substrate (1), a second main surface molding layer (4) for molding the second main surface chip bodies on the second main surface of the substrate (1), an antenna unit (13) for interconnecting with the substrate (1), and a packaging lead-out unit for leading out the system-in-package structure. The encapsulation lead unit includes a transition unit located within the second main surface molding layer (4) and an encapsulation lead connector located outside the second main surface molding layer (4). The encapsulation lead connector is located on the transition unit and interconnects with the substrate (1) as required through the transition unit, so as to lead out the system-in-package structure formed after interconnection; wherein, The adapter unit includes an adapter plate (14), and the antenna unit (13) includes an antenna unit connecting post (27) disposed within the adapter plate (14).

11. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 10, characterized in that: in When fabricating the first molding unit on the main surface, the required first main surface chip body is provided, and the provided first main surface chip body includes the first main surface chip body pad (17). The first main surface chip body corresponding first main surface chip body pad (17) is aligned with the first main surface lead-out connection pad on the first main surface of the substrate (1) and then soldered and fixed so that the first main surface chip body and the substrate (1) can be interconnected as required. A molding process is performed on the first main surface of the substrate (1) to obtain a first main surface molding layer (3), wherein the first main surface chip body is molded on the first main surface of the substrate (1) using the first main surface molding layer (3), and the back side of the first main surface chip body is exposed from the first main surface molding layer (3). The heat sink (5) is attached to the first main surface molding layer (3) and the heat sink (5) is in direct contact with the back of the first main surface chip body.

12. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 10, characterized in that: When fabricating the second molding unit on the main surface, the required second main surface chip body and the adapter unit body are provided. The provided second main surface chip body includes the second main surface chip body pads, and the provided adapter unit body includes the adapter unit body pads. The corresponding second main surface chip pads and the transition unit pads of the transition unit are aligned with the lead-out connection pads of the substrate on the second main surface of the substrate (1) and then soldered and fixed so that the second main surface chip and the transition unit are interconnected with the substrate (1) as required. A molding process is performed on the second main surface of the substrate (1) to obtain a second main surface molding layer (4), wherein the second main surface chip body and the adapter unit body are molded on the second main surface of the substrate (1) using the second main surface molding layer (4), and the adapter unit body is exposed from the second main surface molding layer (4). An antenna unit (13) interconnected with a substrate (1) and a packaged lead-out connector adapted to be electrically connected to the adapter unit body are prepared.

13. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 12, characterized in that: The adapter unit includes a plurality of adapter lead-out connecting posts (26) located within the adapter plate (14). When fabricating the antenna unit (13), an antenna unit layer (33) is fabricated on the second main surface molding layer (4), and the antenna unit layer (33) is interconnected with the substrate (1) through the antenna unit connecting post (27); When fabricating the packaged lead-out connector, lead-out connector pads (34) and lead-out connector solder balls (15) are fabricated on the adapter board (14), wherein, Lead-out connection pads (34) cover the adapter plate (14). The lead-out connection pads (34) correspond one-to-one with the adapter lead-out connection posts (26) in the adapter plate (14). Lead-out connection solder balls (15) correspond one-to-one with the lead-out connection pads (34). A lead-out connection solder ball (15) is interconnected with the substrate (1) through the corresponding lead-out connection pads (34) and the adapter lead-out connection posts (26).

14. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 13, characterized in that: The material of the adapter plate (14) includes silicon; Before the second main surface molding layer (4) is prepared, the adapter body plate (25) used to form the adapter plate (14) is interconnected with the substrate (1) as required. After the second main surface of the substrate (1) is encapsulated, a second main surface encapsulated body (30) is obtained. The second main surface encapsulated body (30) is thinned to obtain the required second main surface encapsulated layer (4). When the second main surface encapsulated body (30) is thinned, the adapter body plate (25) is simultaneously thinned to form an adapter plate (14) using the thinned adapter body plate (25).

15. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 14, characterized in that: The antenna unit layer (33) and the lead-out connection pad (34) are prepared using RDL process, and the thickness of the adapter board (14) is greater than the thickness of the second main surface chip body.

16. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 14, characterized in that: The second main surface chip body includes a functional chip, and when the functional chip is a signal sensitive chip (11), it also includes a cavity shield (12) for cavity shielding of the signal sensitive chip (11), so as to use the cavity shield (12) to shield the signal sensitive chip (11) and the antenna unit (13) from each other.

17. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 16, characterized in that: The cavity shielding body (12) includes a cavity shielding connecting post (32) embedded in the second main surface plastic sealing layer (4) and a shielding surrounding layer electrically connected to the cavity shielding connecting post (32), wherein, The shielding surround layer surrounds the substrate (1), the first molding unit on the main surface and the second molding unit on the main surface. The shielding surround layer is electrically connected to the grounding line layer in the substrate (1), and the shielding surround layer is electrically connected to the signal sensitive chip (11) through the cavity shielding connection post (32) to form a shielding cavity for shielding and isolating the signal sensitive chip (11) and the antenna unit (13) by using the cavity shielding connection post (32) and the shielding surround layer.

18. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 17, characterized in that: in After the second main surface molding body (30) is prepared, a cavity shielding connection groove is formed in the second main surface molding body (30) using a laser grooving process; The cavity shielding connector (31) is obtained by filling the cavity shielding connector groove. When the second main surface encapsulation body (30) is thinned, the cavity shielding connector (31) is cut to obtain the cavity shielding connector (32).

19. The high-power double-sided plastic-encapsulated AiP system-in-package method according to claim 17 or 18, characterized in that: The process methods for preparing the shielding surrounding layer include magnetron sputtering.

Images