A semiconductor structure and a method for manufacturing the same
By forming spaced conductive posts and grooves in the semiconductor layer, and forming a memory cell and a third conductive post thereon, the problem of the through-hole stacking process in the semiconductor chip is solved, and higher product yield and performance stability are achieved.
Patent Information
- Application Number
- CN202211139514.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-19
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2042-09-19
AI Technical Summary
In the prior art, semiconductor chips need to use two through-hole stacking in the back-end process to achieve interconnection of functional areas and non-functional areas, resulting in lithography alignment process problems and penetration risks brought about by through-hole etching at different depths, affecting the performance of the chip.
By forming horizontally spaced first and second conductive posts in the semiconductor layer and forming grooves on the first conductive posts, the top surface of the second conductive posts is lower than the top surface of the first conductive posts, a memory cell is then formed on the second conductive posts, and a third conductive posts are formed on the memory cell, and finally a second metal layer is formed on the first and third conductive posts to achieve electrical connection.
The two-layer through-hole stacking process without forming the memory cell area is avoided, the inscribed alignment process window is increased, the penetration risk brought about by through-hole etching at different depths is avoided, the product yield is improved, and the performance stability and use safety of the semiconductor structure are improved.
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Figure CN115332258B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of integrated circuits and relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] As integrated circuits develop towards high density and low power consumption, the area of semiconductor chips is getting smaller and smaller. Therefore, it is necessary to continuously improve the integration of chips and integrate billions of transistors and other electronic components within a limited chip area. Since the conductivity of semiconductors is between conductors and insulators, it is necessary to connect the independent components inside the same chip in a certain way to form a circuit module with specific functions. Since integrated circuits are mainly prepared layer by layer by planar processes, multi-layer wiring technology is usually used, that is, to establish several layers of conductive metal wires, and different layers of metal wires are connected by columnar metals to improve circuit integration, increase circuit functions without increasing circuit area, and increase added value.
[0003] At present, when integrating various functional units in the back-end of line (BEOL) process of semiconductor production, the interconnection between functional areas and non-functional areas needs to be achieved through via stacking. Figures 1 to 4 , which is a schematic diagram of the structure presented by the above four steps of the method for manufacturing a semiconductor structure in the prior art, the conventional metal layer and the interconnection steps of the functional elements between the metal layers include: 1) Figure 1 As shown, a first through hole 33 is formed in the dielectric layer 22 on the first metal layer 11 and filled with a conductive material; 2) as shown in FIG. Figure 2 As shown, a functional element 44 is formed on the surface of the first through hole 33 in the functional area and an etching protection layer 55 is formed on the surface of the functional element 44 and the dielectric layer 22; 3) as shown Figure 3 As shown, a dielectric layer 22 is deposited on the silicon nitride layer 55, and a second through hole 66 is formed in the dielectric layer 22 by etching and filled with a conductive material; 4) as shown in FIG. Figure 4 As shown, a second metal layer 77 is generated on the surface of the second through hole 66. In the entire process, the non-functional area needs to be stacked with through holes twice, and there will be process problems of photolithography alignment in this process. In addition, when etching to form the second through hole, due to the different etching depths of the functional area and the non-functional area, the etching process window may be narrow in the process of forming the second through hole, that is, completing the etching of through holes of different depths in one etching process will bring about the risk of punch-through, destroying the structure of the functional element and thus affecting the performance of the chip.
[0004] Therefore, how to provide a semiconductor structure and a manufacturing method thereof to achieve a process that avoids the stacking of two layers of through holes in non-functional areas, increase the overlay (OVL) process window and at the same time avoid the risk of penetration caused by completing through-hole etching of different depths at one time, and improve product yield, has become an important technical problem that technical personnel in this field need to solve urgently.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor structure and a method for preparing the same, so as to solve the problem in the prior art that a non-functional area may have a process problem of lithography alignment after two through-hole stacking, and the risk of penetration caused by completing through-hole etching of different depths at one time, which may damage the structure of the functional element and affect the performance of the chip.
[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0008] Providing a semiconductor layer, the semiconductor layer comprising a first interlayer dielectric layer and a first metal layer located in the first interlayer dielectric layer;
[0009] Forming at least one first contact hole and at least one second contact hole in the first interlayer dielectric layer, wherein the first contact hole and the second contact hole are spaced apart in a horizontal direction, and both the first contact hole and the second contact hole open from the top surface of the first interlayer dielectric layer and extend to the upper surface of the first metal layer;
[0010] Filling the first contact hole and the second contact hole with a conductive material to obtain a first conductive column in the first contact hole and a second conductive column in the second contact hole;
[0011] forming a mask layer on the first interlayer dielectric layer and patterning it to obtain an opening penetrating the mask layer, wherein the opening exposes the second conductive pillar and at least a portion of the interlayer dielectric layer;
[0012] Based on the mask layer having the opening, the first interlayer dielectric layer and the second conductive pillar are etched to obtain a groove, and the top surface of the second conductive pillar is lower than the top surface of the first conductive pillar by a preset length;
[0013] forming a memory cell above the second conductive pillar, wherein the memory cell is electrically connected to the second conductive pillar;
[0014] forming a third conductive column above the memory cell, wherein the third conductive column is electrically connected to the memory cell;
[0015] A second metal layer is formed above the first conductive column and the third conductive column, and the second metal layer is electrically connected to the first conductive column and the third conductive column.
[0016] Optionally, the semiconductor layer further includes a lower conductive column and a gate structure located in the first interlayer dielectric layer, the lower conductive column and the gate structure are both located below the first metal layer, and the top of the lower conductive column is electrically connected to the first metal layer.
[0017] Optionally, the forming of the third conductive pillar above the memory cell comprises the following steps:
[0018] After forming the memory cell above the second conductive pillar, forming an insulating protection layer, the insulating protection layer covers the first interlayer dielectric layer, the first conductive pillar and the exposed surface of the memory cell;
[0019] forming a second interlayer dielectric layer on the insulating protection layer, wherein the second interlayer dielectric layer is also filled into the groove;
[0020] planarizing the second interlayer dielectric layer to remove the second interlayer dielectric layer outside the groove;
[0021] forming a third contact hole, wherein the third contact hole sequentially penetrates the second interlayer dielectric layer and the insulating protection layer;
[0022] A conductive material is filled into the third contact hole to obtain the third conductive column.
[0023] Optionally, chemical mechanical polishing is performed after forming the first conductive pillar, the method of planarizing the second interlayer dielectric layer to remove the second interlayer dielectric layer outside the groove includes chemical mechanical polishing, and chemical mechanical polishing is performed after forming the third conductive pillar.
[0024] Optionally, the photolithography mask used when forming the third contact hole and the photolithography mask used when forming the second contact hole are the same photolithography mask.
[0025] Optionally, a method of forming the memory cell comprises an atomic layer deposition method.
[0026] Optionally, the memory cell includes a ferroelectric memory or a phase change memory.
[0027] Optionally, the ferroelectric memory includes an upper electrode, a lower electrode and a ferroelectric material between the upper electrode and the lower electrode; the phase change memory includes an upper electrode, a lower electrode and a phase change material between the upper electrode and the lower electrode.
[0028] Optionally, the conductive material includes at least one of Al, Cu, W, Co, Ru and CNT, the material of the first metal layer includes at least one of Al, Cu, W, Co, Ru and CNT, and the material of the second metal layer includes at least one of Al, Cu, W, Co, Ru and CNT.
[0029] The present invention also provides a semiconductor structure, comprising:
[0030] A semiconductor layer, wherein the semiconductor layer includes a first interlayer dielectric layer and a first metal layer located in the first interlayer dielectric layer;
[0031] At least one first conductive column and at least one second conductive column are located in the first interlayer dielectric layer and are spaced apart in the horizontal direction, the bottom ends of the first conductive column and the second conductive column are both in contact with the upper surface of the first metal layer, and the top surface of the second conductive column is lower than the top surface of the first conductive column by a preset length;
[0032] A groove, located in the first interlayer dielectric layer and above the second conductive pillar, wherein a bottom width of the groove is greater than a width of the second conductive pillar;
[0033] a storage unit, located in the groove and above the second conductive pillar, the storage unit being electrically connected to the second conductive pillar;
[0034] An insulating protective layer, covering the sidewalls of the groove, the portion of the bottom surface of the groove not covered by the storage unit, and the storage unit;
[0035] A third conductive column, located above the memory cell and penetrating the insulating protection layer to be electrically connected to the memory cell;
[0036] The second metal layer is located above the first conductive column and the third conductive column, and the second metal layer is electrically connected to the first conductive column and the third conductive column.
[0037] As described above, the manufacturing method of the semiconductor structure of the present invention includes the following steps: providing a semiconductor layer including a first interlayer dielectric layer and a first metal layer located in the first interlayer dielectric layer; forming at least one first conductive column and at least one second conductive column spaced in the horizontal direction in the first interlayer dielectric layer; forming a groove in the first interlayer dielectric layer so that the top surface of the second conductive column is lower than the top surface of the first conductive column; forming a storage unit above the second conductive column based on the groove; forming a third conductive column above the storage unit; forming a second metal layer above the first conductive column and the third conductive column. The manufacturing method of the present invention can realize a process of avoiding the stacking of two layers of through holes in the area where the storage unit is not formed, and can increase the overlay alignment process window while avoiding the risk of penetration caused by completing through-hole etching of different depths at one time, thereby improving the product yield. In addition, the present invention also provides a semiconductor structure, which has good performance stability and safety in use. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 to Figure 4 It is a schematic cross-sectional structure diagram showing various steps in a method for manufacturing a semiconductor structure in the prior art.
[0039] Figure 5 It is a schematic diagram of a cross-sectional structure obtained after executing step S1 in the first embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0040] Figure 6 It is a schematic diagram of a cross-sectional structure obtained after executing step S2 in the first embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0041] Figure 7 It is a schematic diagram of a cross-sectional structure obtained after executing step S3 in the first embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0042] Figure 8 It is a schematic diagram of a cross-sectional structure obtained after executing step S4 in the first embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0043] Fig. 9 It is a schematic diagram of a cross-sectional structure obtained after executing step S5 in the first embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0044] Fig.10 It is a schematic diagram of a cross-sectional structure obtained after executing step S6 in the first embodiment of the method for manufacturing the semiconductor structure of the present invention.
[0045] Fig.11 It is a schematic diagram of a cross-sectional structure obtained after executing step S7 - 1 in the first embodiment of the method for manufacturing a semiconductor structure of the present invention.
[0046] Fig.12It is a schematic diagram of a cross-sectional structure obtained after executing step S7-2 in the first embodiment of the method for manufacturing the semiconductor structure of the present invention.
[0047] Fig.13 It is a schematic diagram of a cross-sectional structure obtained after executing step S7-3 in the first embodiment of the manufacturing method of the semiconductor structure of the present invention.
[0048] Fig.14 It is a schematic diagram of a cross-sectional structure obtained after executing step S7 - 4 in the first embodiment of the method for manufacturing the semiconductor structure of the present invention.
[0049] Fig.15 It is a schematic diagram of a cross-sectional structure obtained after executing step S7-5 in the first embodiment of the method for manufacturing the semiconductor structure of the present invention.
[0050] Fig.16 It is a schematic diagram of a cross-sectional structure obtained after executing step S8 in the first embodiment of the manufacturing method of the semiconductor structure of the present invention, and it is also a schematic diagram of a cross-sectional structure of the semiconductor structure of the present invention in the second embodiment.
[0051] Component number description
[0052] 11. First Metal Layer
[0053] 22 Dielectric layer
[0054] 33 First through hole
[0055] 44 Functional elements
[0056] 55 Silicon nitride layer
[0057] 66 Second through hole
[0058] 77 Second Metal Layer
[0059] 1 Semiconductor layer
[0060] 2. First interlayer dielectric layer
[0061] 3. First Metal Layer
[0062] 4 Lower conductive column
[0063] 5. Gate structure
[0064] 6 First contact hole
[0065] 7 Second contact hole
[0066] 8 First conductive column
[0067] 9 Second conductive column
[0068] 10 Mask layer
[0069] 11 Opening
[0070] 12 Grooves
[0071] 13 Storage Unit
[0072] 14 The third conductive column
[0073] 15 Insulation protective layer
[0074] 16 Second interlayer dielectric layer
[0075] 17 Third contact hole
[0076] 18 Second Metal Layer
[0077] Steps S1 to S8, S7-1 to S7-5 DETAILED DESCRIPTION
[0078] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0079] See also Figures 5 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0080] Embodiment 1
[0081] This embodiment provides a method for manufacturing a semiconductor structure. Figures 5 to 16 , execute steps S1 to S8. ,
[0082] First, see Figure 5 , perform step S1 to provide a semiconductor layer 1 , wherein the semiconductor layer 1 includes a first interlayer dielectric layer 2 and a first metal layer 3 located in the first interlayer dielectric layer 2 .
[0083] As an example, the semiconductor layer 1 also includes a lower conductive column 4 and a gate structure 5 located in the first interlayer dielectric layer 2, the lower conductive column 4 and the gate structure 5 are both located below the first metal layer 3, and the top of the lower conductive column 4 is electrically connected to the first metal layer 3.
[0084] As an example, the material of the first metal layer 3 includes at least one of Al, Cu, W, Co, Ru and CNT.
[0085] See also Figure 6 , performing step S2, forming at least one first contact hole 6 and at least one second contact hole 7 in the first interlayer dielectric layer 2, wherein the first contact hole 6 and the second contact hole 7 are arranged at intervals in the horizontal direction, and the first contact hole 6 and the second contact hole 7 are both opened from the top surface 11 of the first interlayer dielectric layer 2 and extend to the upper surface of the first metal layer 3
[0086] As an example, the first contact hole 6 and the second contact hole 7 are formed by using a photolithography mask and an etching method, and the lengths of the first contact hole 6 and the second contact hole 7 can be reasonably designed according to the sum of the lengths of two stacked through holes in the prior art.
[0087] See also Figure 7 , perform step S3 to fill the first contact hole 6 and the second contact hole 7 with a conductive material to obtain a first conductive column 8 located in the first contact hole 6 and a second conductive column 9 located in the second contact hole 7 .
[0088] As an example, the method of filling the conductive material includes atomic layer deposition or chemical vapor deposition. In this embodiment, atomic layer deposition is preferred. The first conductive column 8 and the second conductive column 9 have the following functions.
[0089] As an example, after obtaining the first conductive pillar 8 , a first chemical mechanical polishing is performed to remove the conductive material deposited in the area other than the first conductive pillar 8 , so as to flatten the surface of the first conductive pillar 8 to avoid affecting the electrical performance of the device later.
[0090] See also Figure 8 , performing step S4, forming a mask layer 10 on the first interlayer dielectric layer 2 and patterning it to obtain an opening 11 penetrating the mask layer 10, wherein the opening 11 exposes the second conductive pillar 9 and at least a portion of the interlayer dielectric layer.
[0091] See also Fig. 9 , executing step S5, etching the first interlayer dielectric layer 2 and the second conductive pillar 9 based on the mask layer 10 having the opening 11 to obtain a groove 12, and making the top surface of the second conductive pillar 9 lower than the top surface of the first conductive pillar 8 by a preset length.
[0092] As an example, the width of the groove 12 is one-third to three-half of the designed width of the storage unit 13 , and the depth of the groove 12 is also reasonably selected based on the designed height of the storage unit 13 .
[0093] See also Fig.10 , executing step S6 to form a storage unit 13 above the second conductive column 9 , wherein the storage unit 13 is electrically connected to the second conductive column 9 .
[0094] As an example, the method for forming the storage unit 13 includes an atomic layer deposition (ALD) method, which can well control the thickness and flatness of the materials of each structural layer of the storage unit 13, and can effectively control the performance stability of the product. Of course, the method for forming the storage unit 13 can also be physical vapor deposition or chemical vapor deposition, which can be reasonably selected according to the actual production needs.
[0095] As an example, the method for forming the storage unit 13 includes sequentially depositing the structural layer material of the storage unit 13 in the groove 12, and then etching away the structural layer material outside the storage unit 13 area based on the designed specification size of the storage unit 13 to obtain the storage unit 13.
[0096] As an example, the storage unit 13 includes a ferroelectric memory or a phase change memory, the ferroelectric memory includes an upper electrode, a lower electrode and a ferroelectric material located between the upper electrode and the lower electrode, the phase change memory includes an upper electrode, a lower electrode and a phase change material located between the upper electrode and the lower electrode, and the layer-out unit 13 is not limited to a storage unit, and may also include other functional elements.
[0097] See also Figures 11 to 15 , executing step S7 to form a third conductive column 14 above the storage unit 13 , wherein the third conductive column 14 is electrically connected to the storage unit 13 .
[0098] Specifically, Fig.11 As shown, step S7 - 1 is first performed to form the memory cell 13 above the second conductive pillar 9 , and then form an insulating protection layer 15 , which covers the first interlayer dielectric layer 2 , the first conductive pillar 8 and the exposed surface of the memory cell 13 .
[0099] As an example, the material of the insulating protection layer 15 includes silicon nitride (SiN). The insulating protection layer 15 protects the functional unit on the one hand, and can serve as a stop layer for chemical mechanical polishing after the second interlayer dielectric layer 16 is subsequently formed on the other hand.
[0100] like Fig.12 As shown, step S7 - 2 is then performed to form a second interlayer dielectric layer 16 on the insulating protection layer 15 , and the second interlayer dielectric layer 16 is also filled into the groove 12 .
[0101] like Fig.13As shown, step S7 - 3 is then performed to planarize the second interlayer dielectric layer 16 to remove the second interlayer dielectric layer 16 outside the groove 12 .
[0102] As an example, the method for planarizing the second interlayer dielectric layer 16 to remove the second interlayer dielectric layer 16 outside the groove 12 includes chemical mechanical polishing, that is, performing a second chemical mechanical polishing after forming the second interlayer dielectric layer 16, and the second chemical mechanical polishing is used to remove excess dielectric materials in other surface areas after forming the second interlayer dielectric layer 16 to obtain a flat, scratch-free and impurity-free surface to avoid the influence of impurity residues and rough surfaces on the performance of subsequent devices. In addition, during the second chemical mechanical polishing, the polishing of the area outside the groove 12 stops at the upper surface of the insulating protection layer 15, and the groove 12 area stops at a position flush with the upper surface of the first interlayer dielectric layer 2 so that the subsequent formation of the second metal layer 18 can maintain flush consistency.
[0103] like Fig.14 As shown, step S7 - 4 is then performed to form a third contact hole 17 , wherein the third contact hole 17 sequentially penetrates the second interlayer dielectric layer 16 and the insulating protection layer 15 .
[0104] As an example, the photolithography mask used to form the third contact hole 17 is the same photolithography mask used to form the first contact hole 6. In this embodiment, preferably, the third contact hole 17 is aligned with the second contact hole 7, so as to reduce the size of the components inside the semiconductor, thereby reducing the size of the chip.
[0105] like Fig.15 As shown, step S7 - 5 is then performed to fill the third contact hole 17 with a conductive material to obtain the third conductive column 14 .
[0106] As an example, after the third conductive column 14 is formed, a third chemical mechanical polishing is performed. The purpose of the third chemical mechanical polishing is to remove the conductive material deposited outside the third conductive column 14 area to avoid its influence on the subsequent performance of the device, and to remove the insulating protection layer 15 on the surface of the first conductive column 8, the first interlayer dielectric layer 2 and the second interlayer dielectric layer 16 so that when the second metal layer 18 is subsequently formed, it can be electrically connected to the first conductive column 8 and the third conductive column 14.
[0107] See also Fig.16 , perform step S8 to form a second metal layer 18 above the first conductive column 8 and the third conductive column 14 , and the second metal layer 18 is electrically connected to the first conductive column 8 and the third conductive column 14 .
[0108] As an example, the material of the second metal layer 18 includes at least one of Al, Cu, W, Co, Ru and CNT.
[0109] The manufacturing method of the present invention can achieve a process of avoiding the stacking of two layers of through holes in the area where no storage unit is formed, increase the overlay alignment process window, and avoid the risk of penetration caused by completing through hole etching of different depths at one time, thereby improving product yield.
[0110] Embodiment 2
[0111] This embodiment provides a semiconductor structure. Fig.16 , which is a schematic diagram of the structure of the semiconductor structure, comprising: a semiconductor layer 1, a first conductive column 8, a second conductive column 9, a groove 12, a storage unit 13, an insulating protection layer 15, a third conductive column 14 and a second metal layer 18, wherein the semiconductor layer 1 comprises a first interlayer dielectric layer 2 and a first metal layer 3 located in the first interlayer dielectric layer 2; the first conductive column 8 and the second conductive column 9 each comprise at least one, the first conductive column 8 and the second conductive column 9 are both located in the first interlayer dielectric layer 2 and are spaced apart in the horizontal direction, the bottom ends of the first conductive column 8 and the second conductive column 9 are both in contact with the upper surface of the first metal layer 3, and the top surface of the second conductive column 9 is lower than the top surface of the first conductive column 8 by a preset length; the groove 12 is located in the first interlayer dielectric layer 2; the second conductive column 9 and the third conductive column 14 are both located in the first interlayer dielectric layer 2 and are spaced apart in the horizontal direction; the first conductive column 8 and the second conductive column 9 are both located in the first interlayer dielectric layer 2 and are spaced apart in the horizontal direction; the bottom ends of the first conductive column 8 and the second conductive column 9 are both in contact with the upper surface of the first metal layer 3, and the top surface of the second conductive column 9 is lower than the top surface of the first conductive column 8 by a preset length; the groove 12 is located in the first interlayer dielectric layer 2; the second conductive column 9 and the third conductive column 14 are both ... An interlayer dielectric layer 2 is located above the second conductive pillar 9, and the bottom width of the groove 12 is greater than the width of the second conductive pillar 9; the storage unit 13 is located in the groove 12 and above the second conductive pillar 9, and the storage unit 13 is electrically connected to the second conductive pillar 9; the insulating protection layer 15 covers the sidewall of the groove 12, the bottom of the groove 12 not covered by the storage unit 13, and the storage unit 13; the third conductive pillar 14 is located above the storage unit 13 and penetrates the insulating protection layer 15 to be electrically connected to the storage unit 13; the second metal layer 18 is located above the first conductive pillar 8 and the third conductive pillar 14, and the second metal layer 18 is electrically connected to the first conductive pillar 8 and the third conductive pillar 14.
[0112] As an example, the semiconductor layer 1 also includes a lower conductive column 4 and a gate structure 5 located in the first interlayer dielectric layer 2, the lower conductive column 4 and the gate structure 5 are both located below the first metal layer 3, and the top of the lower conductive column 4 is electrically connected to the first metal layer 3.
[0113] Specifically, in the semiconductor structure, the first metal layer 3 and the second metal layer 18 function to realize the lateral electrical connection of the device having the semiconductor structure, and the first conductive column 8, the second conductive column 9 and the third conductive column 14 function to realize the vertical circuit connection; the first interlayer dielectric layer 2 and the second interlayer dielectric layer both play an insulating role to realize the electrical isolation of the circuit in the device; the storage unit 13 gives the device specific functional requirements; the insulating protection layer 15 can realize the protection of the storage unit 13.
[0114] Compared with the semiconductor structure with similar effects and functions formed by the two-hole stacking technology in the prior art, the semiconductor structure of this embodiment has better performance stability and use safety.
[0115] In summary, the manufacturing method of the semiconductor structure of the present invention includes the following steps: providing a semiconductor layer including a first interlayer dielectric layer and a first metal layer located in the first interlayer dielectric layer; forming at least one first conductive column and at least one second conductive column spaced in the horizontal direction in the first interlayer dielectric layer; forming a groove in the first interlayer dielectric layer so that the top surface of the second conductive column is lower than the top surface of the first conductive column; forming a storage unit above the second conductive column based on the groove; forming a third conductive column above the storage unit; forming a second metal layer above the first conductive column and the third conductive column. The manufacturing method of the present invention can realize the process of avoiding the stacking of two layers of through holes in the area where the storage unit is not formed, and can increase the overlay alignment process window while avoiding the penetration risk caused by completing the through hole etching of different depths at one time, thereby improving the product yield. In addition, the present invention also provides a semiconductor structure, which has good performance stability and safety in use. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0116] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a semiconductor layer, the semiconductor layer comprising a first interlayer dielectric layer and a first metal layer located in the first interlayer dielectric layer; Forming at least one first contact hole and at least one second contact hole in the first interlayer dielectric layer, wherein the first contact hole and the second contact hole are spaced apart in a horizontal direction, and both the first contact hole and the second contact hole open from the top surface of the first interlayer dielectric layer and extend to the upper surface of the first metal layer; Filling the first contact hole and the second contact hole with a conductive material to obtain a first conductive column in the first contact hole and a second conductive column in the second contact hole; forming a mask layer on the first interlayer dielectric layer and patterning it to obtain an opening penetrating the mask layer, wherein the opening exposes the second conductive pillar and at least a portion of the interlayer dielectric layer; Based on the mask layer having the opening, the first interlayer dielectric layer and the second conductive pillar are etched to obtain a groove, and the top surface of the second conductive pillar is lower than the top surface of the first conductive pillar by a preset length; forming a memory cell above the second conductive pillar, wherein the memory cell is electrically connected to the second conductive pillar; Forming a third conductive pillar above the memory cell, the third conductive pillar being electrically connected to the memory cell, comprises the following steps: forming an insulating protection layer, the insulating protection layer covering the first interlayer dielectric layer, the first conductive pillar and the exposed surface of the memory cell; forming a second interlayer dielectric layer on the insulating protection layer, the second interlayer dielectric layer also filling the groove; planarizing the second interlayer dielectric layer to remove the second interlayer dielectric layer outside the groove; forming a third contact hole, the third contact hole sequentially penetrating the second interlayer dielectric layer and the insulating protection layer; Filling the third contact hole with a conductive material to obtain the third conductive column; A second metal layer is formed above the first conductive column and the third conductive column, and the second metal layer is electrically connected to the first conductive column and the third conductive column.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The semiconductor layer further includes a lower conductive column and a gate structure located in the first interlayer dielectric layer. The lower conductive column and the gate structure are both located below the first metal layer. The top of the lower conductive column is electrically connected to the first metal layer.
3. The method for manufacturing a semiconductor structure according to claim 1, wherein: Chemical mechanical polishing is performed after forming the first conductive pillar, the method of planarizing the second interlayer dielectric layer to remove the second interlayer dielectric layer outside the groove includes chemical mechanical polishing, and chemical mechanical polishing is performed after forming the third conductive pillar.
4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The photolithography mask used when forming the third contact hole and the photolithography mask used when forming the second contact hole are the same photolithography mask.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method of forming the memory cell includes an atomic layer deposition method.
6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The memory cell includes a ferroelectric memory or a phase change memory.
7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The ferroelectric memory comprises an upper electrode, a lower electrode and a ferroelectric material between the upper electrode and the lower electrode; the phase change memory comprises an upper electrode, a lower electrode and a phase change material between the upper electrode and the lower electrode.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The conductive material includes at least one of Al, Cu, W, Co, Ru and CNT, the material of the first metal layer includes at least one of Al, Cu, W, Co, Ru and CNT, and the material of the second metal layer includes at least one of Al, Cu, W, Co, Ru and CNT.
9. A semiconductor structure, characterized in that: include: A semiconductor layer, wherein the semiconductor layer includes a first interlayer dielectric layer and a first metal layer located in the first interlayer dielectric layer; At least one first conductive column and at least one second conductive column are located in the first interlayer dielectric layer and are spaced apart in the horizontal direction, the bottom ends of the first conductive column and the second conductive column are both in contact with the upper surface of the first metal layer, and the top surface of the second conductive column is lower than the top surface of the first conductive column by a preset length; A groove, located in the first interlayer dielectric layer and above the second conductive pillar, wherein a bottom width of the groove is greater than a width of the second conductive pillar; a storage unit, located in the groove and above the second conductive pillar, the storage unit being electrically connected to the second conductive pillar; An insulating protective layer, covering the sidewalls of the groove, the portion of the bottom surface of the groove not covered by the storage unit, and the storage unit; A third conductive column, located above the memory cell and penetrating the insulating protection layer to be electrically connected to the memory cell; The second metal layer is located above the first conductive column and the third conductive column, and the second metal layer is electrically connected to the first conductive column and the third conductive column.
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