Display panel and display device

Abstract

The embodiments of the present disclosure provide a display panel and a display device, which relate to the field of display technology and are used to improve the failure of light-emitting devices caused by contact between the source and drain metal layers and the etching solution. The display panel includes a substrate, a first metal pattern layer, an organic insulation pattern layer and a first electrode pattern layer. The first metal pattern layer includes a voltage lead-out line, which is located in the lead-out area; the voltage lead-out line includes a stacked first sub-metal layer and a second sub-metal layer, and the activity of the first sub-metal layer is higher than that of the second sub-metal layer. The organic insulation pattern layer has a hollow portion at least in the lead-out area, and the hollow portion exposes at least part of the side surface of the first sub-metal layer. The first electrode pattern layer is located on the side of the organic insulation pattern layer away from the substrate; the first electrode pattern layer includes a protective portion, which at least covers the side surface of the first sub-metal layer exposed by the hollow portion. The above-mentioned display panel is used to display images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) has been widely used in the display field due to its advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed and flexible display. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide a display panel and a display device, which are used to improve the problem of light-emitting device failure caused by contact between the source and drain metal layers and the etching solution.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display panel is provided. The display panel comprises a display area and a lead-out area, the lead-out area being located on one side of the display area. The display panel comprises a substrate, a first metal pattern layer, an organic insulation pattern layer, and a first electrode pattern layer. The first metal pattern layer is located on one side of the substrate; the first metal pattern layer includes a voltage lead-out line, which is located in the lead-out area. The voltage lead-out line comprises a stacked first sub-metal layer and a second sub-metal layer; the first sub-metal layer is located between the substrate and the second sub-metal layer, and the activity of the first sub-metal layer is higher than that of the second sub-metal layer. The organic insulation pattern layer is located on the side of the first metal pattern layer away from the substrate; the organic insulation pattern layer has a hollow portion at least within the lead-out area, the hollow portion exposing at least a portion of the side surface of the first sub-metal layer. The first electrode pattern layer is located on the side of the organic insulation pattern layer away from the substrate; the first electrode pattern layer includes a protective portion, which covers at least the side surface of the first sub-metal layer exposed by the hollow portion.

[0006] In the above-mentioned display panel, the protective part can protect the side surface of the first sub-metal layer. Therefore, the etching solution used to etch the first electrode pattern layer cannot contact the side surface of the first sub-metal layer, and thus the etching solution will not contact the first sub-metal layer, thereby reducing the phenomenon of the first sub-metal layer being corroded to form a concave surface. Therefore, when forming the encapsulation layer, the film forming stress of the encapsulation layer near the side surface of the first sub-metal layer can be avoided to be too large, thereby improving the problem of cracks in the encapsulation layer, thereby improving the effect of the encapsulation layer in blocking water and oxygen, and improving the problem of water and oxygen invading the display area, resulting in water and oxygen failure of the light-emitting pattern layer in the display area, thereby improving the problem of failure of the light-emitting device, and thereby reducing the formation of dark spots.

[0007] In some embodiments, the voltage lead further includes a third sub-metal layer; the third sub-metal layer is located between the first sub-metal layer and the substrate; the activity of the first sub-metal layer is higher than that of the third sub-metal layer;

[0008] The protective portion covers the side surface of the voltage lead wire exposed by the hollow portion; the side surface of the voltage lead wire exposed by the hollow portion includes the side surfaces of the first sub-metal layer, the second sub-metal layer and the third sub-metal layer exposed by the hollow portion.

[0009] In some embodiments, the protection portion extends to a surface of the voltage lead away from the substrate; and / or the protection portion extends beyond an orthographic projection of the voltage lead on the substrate.

[0010] In some embodiments, a direction from the display area to the lead-out area is a first direction. The voltage lead-out line includes a first routing segment extending along the first direction. The hollow portion extends along an edge of the display area, and the hollow portion exposes a portion of a side surface of the first routing segment. The protective portion covers the side surface of the first routing segment exposed by the hollow portion, and the protective portion extends beyond the hollow portion along the first direction and covers the organic insulation pattern layer.

[0011] In some embodiments, the number of the hollow portions is at least two, and the at least two hollow portions are sequentially spaced away from the display area to form at least one circle of blocking portions between all the hollow portions. The protective portion extends along the first direction; the protective portion covers the at least two hollow portions and the blocking portions it passes through.

[0012] In some embodiments, there are multiple voltage lead lines and multiple protection portions. For any voltage lead line, the side surface of the first sub-metal layer exposed by the hollow portion is covered by at least one protection portion. At least one voltage lead line is used to transmit a VDD signal, and the remaining voltage lead lines are used to transmit a VSS signal.

[0013] In some embodiments, the first electrode pattern layer further includes a plurality of first electrodes, and the plurality of first electrodes are located in the display area.

[0014] In some embodiments, the display panel further comprises: a light-emitting pattern layer, a second electrode pattern layer, and an encapsulation layer. The light-emitting pattern layer is located on a side of the first electrode pattern layer away from the substrate. The second electrode pattern layer is located on a side of the light-emitting pattern layer away from the substrate; the second electrode pattern layer is electrically connected to the voltage lead for transmitting a VSS signal. The encapsulation layer is located on a side of the second electrode pattern layer away from the substrate, and the encapsulation layer contacts a side of the protective portion away from the substrate.

[0015] In some embodiments, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence, and the first inorganic encapsulation layer is in contact with a side of the protection portion away from the substrate.

[0016] In another aspect, a display device is provided. The display device comprises: a display panel according to any of the above embodiments, a flexible printed circuit board, and a main control printed circuit board. The display panel comprises a display area, a lead-out area, and a binding area. The binding area is located on a side of the lead-out area away from the display area, and the voltage lead line extends from the lead-out area to the binding area. One end of the flexible printed circuit board is bonded to the binding area, and the main control printed circuit board is electrically connected to the other end of the flexible printed circuit board.

[0017] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0019] Figure 1 is a structural diagram of a display device according to some embodiments;

[0020] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0021] Figure 3 is a structural diagram of a display panel according to some embodiments;

[0022] Figure 4 is a structural diagram of a pixel driving circuit according to some embodiments;

[0023] Figure 5 is a structural diagram of a display panel according to some embodiments;

[0024] Figure 6A is a structural diagram of a display panel according to some embodiments;

[0025] Figure 6B is a structural diagram of a display device according to some embodiments;

[0026] Figure 7 is a structural diagram of a display panel according to some embodiments;

[0027] Figure 8 is a structural diagram of a display panel according to some embodiments;

[0028] Figure 9 is a structural diagram of a display panel according to some embodiments;

[0029] Figure 10 is a structural diagram of a source / drain metal layer according to some embodiments;

[0030] Figure 11 is a structural diagram of a display panel according to some embodiments;

[0031] Figure 12 is a schematic diagram showing a concave surface formed after the first sub-metal layer in the second source / drain metal layer is corroded;

[0032] Figure 13 A schematic diagram showing that the first electrode pattern layer and the second electrode pattern layer are punctured due to the presence of Ag particles in the display panel;

[0033] Figure 14 A schematic diagram showing the presence of water and oxygen channels in the display panel;

[0034] Figure 15 is a structural diagram of a display panel according to some embodiments;

[0035] Figure 16 is a cross-sectional view of a display panel according to some embodiments;

[0036] Figure 17A is a structural diagram of a display panel according to some embodiments;

[0037] Figure 17B for Figure 17A Cross-sectional view along line C-C';

[0038] Figure 18A for Figure 17A Cross-sectional view at D-D';

[0039] Figure 18B is a structural diagram of a display panel according to some embodiments;

[0040] Figure 19 is a structural diagram of a display panel according to some embodiments;

[0041] Figure 20 is a diagram showing steps of a method for manufacturing a display panel according to some embodiments;

[0042] Figure 21 is a diagram showing steps of a method for manufacturing a display panel according to some embodiments;

[0043] Figure 22 is a diagram showing steps of a method for manufacturing a display panel according to some embodiments;

[0044] Figure 23 is a diagram showing steps of a method for manufacturing a display panel according to some embodiments;

[0045] Figure 24 is a diagram showing steps of a method for manufacturing a display panel according to some embodiments;

[0046] Figure 25 1 is a diagram showing steps of a method for preparing a display panel according to some embodiments. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, "perpendicular" includes the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable range of deviation, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes both absolute perpendicularity and approximately perpendicularity, where the acceptable range of deviation for approximately perpendicularity can be, for example, within 5°.

[0052] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0053] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0054] Figure 1 is a structural diagram of a display device 1000 according to some embodiments.

[0055] See also Figure 1 Some embodiments of the present disclosure provide a display device 1000. The display device 1000 includes a display panel 100.

[0056] The display device 1000 is a product capable of displaying images (including static images or dynamic images, where dynamic images can be videos). For example, the display device 1000 can be any of the following: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigation system, a vehicle, a large-area wall, a home appliance, an information query device (such as a business query device for e-government, banks, hospitals, power departments, etc.), a monitor, etc.

[0057] Figure 2 is a structural diagram of a display panel 100 according to some embodiments.

[0058] See also Figure 2 Some embodiments of the present disclosure provide a display panel 100 having a display area AA and a peripheral area BB, wherein the peripheral area BB may be arranged around the display area AA.

[0059] Numerous sub-pixels 110 are provided within the display area AA. Sub-pixels 110 are the smallest unit used by the display panel 100 for displaying images. Each sub-pixel 110 can display a single color, such as red (R), green (G), or blue (B). The display panel 100 includes numerous red, green, and blue sub-pixels. By adjusting the brightness (grayscale) of the sub-pixels, multiple colors can be displayed through color combination and overlay, thereby achieving full-color display on the display panel 100.

[0060] Figure 3 is a structural diagram of a display panel 100 according to some embodiments, wherein: Figure 3 The structure of one sub-pixel 110 is shown in FIG.

[0061] See also Figure 3 A sub-pixel 110 includes a pixel driving circuit 111 and a light emitting device 112. The light emitting device 112 is located on one side of the pixel driving circuit 111 and is electrically connected to the pixel driving circuit 111. The pixel driving circuit 111 is used to drive the light emitting device 112 to emit light.

[0062] The display panel 100 further includes a substrate 120 , a plurality of sub-pixels 110 are located on one side of the substrate 120 , and the light-emitting device 112 is located on a side of the pixel driving circuit 111 away from the substrate 120 .

[0063] The substrate 120 may be a single-layer structure or a stacked structure, and may be rigid or flexible. For example, the flexible substrate may include a first flexible film, a first barrier layer, a second flexible film, and a second barrier layer stacked in sequence. A buffer layer may be provided on the side of the second barrier layer away from the second flexible film. The buffer layer may block water and gas, while preventing impurity ions in the first and second flexible films from contaminating the sub-pixels 110. The first and second flexible films may be polyimide. The pixel driving circuit 111 may be provided on the side of the second barrier layer away from the first flexible film.

[0064] The light emitting device 112 includes an anode AND1 , a light emitting pattern layer EL, and a cathode CTD1 .

[0065] In some examples, the anode AND1 is located on a side of the pixel driving circuit 111 away from the substrate 120 and is electrically connected to the pixel driving circuit 111. The light-emitting pattern layer EL is located on a side of the anode AND1 away from the substrate 120, and the cathode CTD1 is located on a side of the light-emitting pattern layer EL away from the substrate 120. In some examples, the light-emitting device 112 further includes one or more layers of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0066] Among them, each pixel driving circuit 111 includes a plurality of transistors. In some embodiments, the structure of the pixel driving circuit in the present disclosure includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C" or "7T2C" and the like. Here, "T" represents a thin film transistor, and the number before "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number before "C" represents the number of storage capacitors C. The structure of the pixel driving circuit 111 is introduced below using "7T1C" as an example.

[0067] Figure 4 is a structural diagram of a pixel driving circuit 111 according to some embodiments.

[0068] See also Figure 4 , Figure 4 FIG. 1 shows the structure of the pixel driving circuit 111 when the pixel driving circuit 111 has a 7T1C structure.

[0069] Exemplarily, the pixel driving circuit 111 may specifically include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a capacitor C, and the signal lines electrically connected to the pixel driving circuit 111 include a gate scan signal line G, a first reset signal line Rst1, a second reset signal line Rst2 and a light emitting control signal line Em.

[0070] Among them, the gate of the first transistor T1 is electrically connected to the first reset signal line Rst1, the first electrode of the first transistor T1 is electrically connected to the initialization signal line Vt, and the second electrode of the first transistor T1 is electrically connected to the driving node A; the gate of the second transistor T2 is electrically connected to the gate scanning signal line G, the first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the driving node A; the gate of the third transistor T3 is electrically connected to the driving node A; the gate of the fourth transistor T4 is electrically connected to the gate scanning signal line G, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Dt, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3; the fifth transistor The gate of T5 and the gate of the sixth transistor T6 are both electrically connected to the light-emitting control signal line Em, the first electrode of the fifth transistor T5 is electrically connected to the first voltage signal line Vdd1, the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device 112; the gate of the seventh transistor T7 is electrically connected to the second reset signal line Rst2, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal line Vt, the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device 112, and the cathode of the light-emitting device 112 is electrically connected to the second voltage signal line Vss1.

[0071] In some embodiments, each transistor in the pixel driving circuit 111 may be a P-type transistor, which is turned on when the gate receives a low voltage signal. In other embodiments, each transistor in the pixel driving circuit 111 may be an N-type transistor, which is turned on when the gate receives a high voltage signal. In addition, in other embodiments, some transistors in the pixel driving circuit 111 are N-type transistors, and the rest are P-type transistors, for example, T1 and T2 are N-type transistors, and the rest are P-type transistors. It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turn-on condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, then the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turn-on condition of a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, then the gate voltage signal that turns on the P-type transistor is called a low voltage signal. The high and low in "high voltage signal" and "low voltage signal" are relative to a reference voltage (for example, 0V).

[0072] Figure 5is a structural diagram of a display panel 100 according to some embodiments.

[0073] See also Figure 5 In the display area AA, a plurality of pixel driving circuits 111 may be arranged in an array.

[0074] The display panel 100 further includes a plurality of first voltage signal lines Vdd1 , which are disposed in the display area AA. The plurality of first voltage signal lines Vdd1 are sequentially disposed along the second direction X, and each first voltage signal line Vdd1 extends along the first direction Y.

[0075] The second direction X intersects the first direction Y. For example, the second direction X is perpendicular to the first direction Y.

[0076] In some examples, one first voltage signal line VDD1 is electrically connected to one column of pixel driving circuits 111 .

[0077] The display panel 100 further includes a plurality of data lines Dt, which are disposed in the display area AA. The plurality of data lines Dt are sequentially arranged along the second direction X, and each data line Dt extends along the first direction Y.

[0078] See also Figure 5 In some examples, the gate scan signal line G, the first reset signal line Rst1 , the second reset signal line Rst2 , the light emission control signal line Em, and the initialization signal line Vt may extend along the second direction X.

[0079] Figure 6A FIG is a structural diagram of a display panel 100 according to some embodiments. Figure 6A FIG shows a display area AA, a lead-out area B10, a frame area B20 and a binding area B30 in the display panel 100. Figure 6A The display area AA, the lead-out area B10, the border area B20 and the binding area B30 are illustrated by multiple dotted boxes, wherein the dotted boxes do not represent the actual boundaries of the display area AA, the lead-out area B10, the border area B20 and the binding area B30.

[0080] See also Figure 6A The peripheral area BB further includes a lead-out area B10. The lead-out area B10 is disposed on one side of the display area AA, wherein a direction from the display area AA to the lead-out area B10 is a first direction Y.

[0081] The display panel 100 further includes a first voltage lead line Vdd2, which is disposed in the lead-out area B10. A plurality of first voltage signal lines Vdd1 extend to the lead-out area B10 and are electrically connected to the first voltage lead line Vdd2. The first voltage signal line Vdd1 and the first voltage lead line Vdd2 are both used to transmit VDD signals. Figure 6A Only two first voltage signal lines Vdd1 are illustrated, and a plurality of first voltage signal lines Vdd1 between the two first voltage signal lines Vdd1 are omitted.

[0082] See also Figure 6A The peripheral area BB further includes a frame area B20 , which is disposed on at least one side of the display area AA. The frame area B20 and the lead-out area B10 are disposed on different sides of the display area AA.

[0083] The display panel 100 further includes a second voltage signal line Vss1 and a second voltage lead line Vss2. The second voltage signal line Vss1 is disposed in the border area B20, and the second voltage lead line Vss2 is disposed in the lead area B10. The second voltage signal line Vss1 can extend to the lead area B10 and be electrically connected to the second voltage lead line Vss2. Both the second voltage signal line Vss1 and the second voltage lead line Vss2 are used to transmit a VSS signal.

[0084] In some examples, the second voltage signal line Vss1 may extend along the border area B20, wherein both ends of the second voltage signal line Vss1 may be respectively located on both sides of the display area AA in the second direction X. Correspondingly, two second voltage lead-out lines Vss2 may be provided in the lead-out area B10, such that both ends of the second voltage signal line Vss1 are respectively electrically connected to the second voltage lead-out lines Vss2.

[0085] See also Figure 6A The peripheral area BB also includes a bonding area B30, which is provided with multiple pins. A first voltage lead line Vdd2 and a second voltage lead line Vss2 can both extend from the lead area B10 to the bonding area B30 and be electrically connected to some of the pins on the bonding area B30. The first voltage lead line Vdd2 and the second voltage lead line Vss2 are electrically connected to different pins.

[0086] Figure 6B is a structural diagram of a display device 1000 according to some embodiments.

[0087] See also Figure 6BThe display device 1000 provided in some embodiments of the present disclosure further includes a flexible circuit board 200 and a main control circuit board 300. One end of the flexible circuit board 200 is bonded to the bonding area B30, and the main control circuit board 300 is electrically connected to the other end of the flexible circuit board 200. For example, one end of the flexible circuit board 200 can be bonded to multiple pins on the bonding area B30, and the main control circuit board 300 can transmit a VDD signal to the first voltage lead line Vdd2 and a VSS signal to the second voltage lead line Vss2 through the flexible circuit board 200.

[0088] Figure 7 is a structural diagram of a display panel 100 according to some embodiments.

[0089] See also Figure 7 In some examples, the lead-out area B10 includes: a first fan-out area B11, a bending area B12, a second fan-out area B13, a test circuit area B14, and a chip area B15, which are sequentially arranged along the first direction Y. The first fan-out area B11 is adjacent to the display area AA, and the chip area B15 is adjacent to the bonding area B30.

[0090] The first fan-out area B11 is provided with a data line Dt (eg Figure 5 The data line Dt is gathered in the first fan-out area B11. The bending area B12 is made of a flexible material and can be bent. After the bending area B12 is bent, the second fan-out area B13, the test circuit area B14 and the chip area B15 are all located on the back of the display panel 100. The first voltage lead line Vdd2 (as shown in FIG. 1 ) is provided in the second fan-out area B13. Figure 6A as shown) and the second voltage lead line Vss2 (as shown) Figure 6A The test circuit area B14 houses the display test circuit. The chip area B15 is provided with multiple pins. The lead-out portion of the data line Dt can sequentially extend through the bend area B12, the second fan-out area B13, and the test circuit area B14 to the chip area B15. The chip area B15 is provided with multiple pins, and the display panel 100 can be electrically connected to the driver IC through the multiple pins on the chip area B15.

[0091] Figure 8 is a structural diagram of a display panel 100 according to some embodiments.

[0092] See also Figure 8 In some other examples, the lead-out area B10 includes: a first fan-out area B11, a second fan-out area B13, and a test circuit area B14 sequentially arranged along the first direction Y. In this case, the test circuit area B14 is adjacent to the bonding area B30.

[0093] At this time, the data line Dt (such as Figure 5The lead portion (shown in FIG. 1 ) can extend from the first fan-out area B11 through the second fan-out area B13 and the test circuit area B14 to the binding area B30, and is electrically connected to multiple pins on the binding area B30. The driver IC is bound to one end of the flexible circuit board, and the other end of the flexible circuit board is bound to multiple pins on the binding area B30. That is, the driver IC is electrically connected to the multiple pins on the binding area B30 through the flexible circuit board. In this example, the flexible circuit board can be bent to the back of the display panel 100.

[0094] Figure 9 is a structural diagram of a display panel 100 according to some embodiments.

[0095] See also Figure 9 The display panel 100 includes multiple film layers. Exemplarily, the display panel 100 includes a substrate 120, an active layer 130, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a first electrode pattern layer 140, a light emitting pattern layer EL, a second electrode pattern layer 150, and an encapsulation layer 160, which are stacked in sequence.

[0096] In addition, the display panel 100 further includes a pixel definition layer (PDL), wherein the pixel definition layer (PDL) includes a plurality of pixel openings, and the light-emitting pattern layer (EL) may be located in the pixel openings. The light-emitting pattern layer (EL) is located on the side of the first electrode pattern layer 140 away from the substrate 120, while the second electrode pattern layer 150 is located on the side of the light-emitting pattern layer (EL) away from the substrate 120. The encapsulation layer 160 is located on the side of the second electrode pattern layer 150 away from the substrate 120.

[0097] In some examples, the encapsulation layer 160 includes a first inorganic encapsulation layer 161, an organic encapsulation layer 162, and a second inorganic encapsulation layer 163 stacked in sequence, wherein the first inorganic encapsulation layer 161 and the second inorganic encapsulation layer 163 may be made of an inorganic material, and the organic encapsulation layer 162 may be made of an organic material.

[0098] In some examples, the first electrode pattern layer 140 includes a plurality of first electrodes, which may be located in the display area AA. Exemplarily, the first electrode is the anode AND1 , and correspondingly, the second electrode pattern layer 150 may be the cathode CTD1 .

[0099] Exemplarily, the first electrode pattern layer 140 (i.e., the anode AND1) includes a transparent conductive oxide layer, a metal layer, and a transparent conductive oxide layer stacked in sequence. The transparent conductive oxide layer may be made of, for example, ITO (Indium Tin Oxides) and IZO (Indium Zinc Oxide), and the metal layer may be made of, for example, gold (Au), silver (Ag), nickel (Ni), and platinum (Pt). Exemplarily, the anode AND1 includes an ITO layer, an Ag layer, and an ITO layer stacked in sequence.

[0100] For example, the material of the second electrode pattern layer 150 may be aluminum (Al), Ag, and magnesium (Mg). In addition, the second electrode pattern layer 150 may also be a Mg:Ag alloy or an Al:Li (lithium) alloy.

[0101] The second electrode pattern layer 150 is electrically connected to the second voltage lead line Vss2 for transmitting the VSS signal. Exemplarily, the first electrode pattern layer 140 may include a bridge pattern, wherein the bridge pattern is insulated from the first electrode. The second voltage signal line Vss1 may be electrically connected to the second electrode pattern layer 150 via the bridge pattern, and the second voltage signal line Vss1 may be electrically connected to the second voltage lead line Vss2, thereby electrically connecting the second voltage lead line Vss2 to the second electrode pattern layer 150.

[0102] In some examples, the active layer 130 and the first gate metal layer Gate1 are used to form a transistor. In other examples, the active layer 130 and the second gate metal layer Gate2 can also be used to form a transistor.

[0103] In some examples, the first voltage signal line Vdd1 and the first voltage lead line Vdd2 may be disposed in the second source-drain metal layer SD2 , and the second voltage signal line Vss1 and the second voltage lead line Vss2 may also be disposed in the second source-drain metal layer SD2 .

[0104] In some other examples, the first voltage signal line Vdd1 and the first voltage lead line Vdd2 can be respectively provided in the first source-drain metal layer SD1 and the second source-drain metal layer SD2. For example, the first voltage signal line Vdd1 can be provided in the second source-drain metal layer SD2, and the first voltage lead line Vdd2 can be provided in the first source-drain metal layer SD1.

[0105] In some other examples, the second voltage signal line Vss1 and the second voltage lead line Vss2 can be respectively provided in the first source-drain metal layer SD1 and the second source-drain metal layer SD2. For example, the second voltage signal line Vss1 can be provided in the second source-drain metal layer SD2, and the second voltage lead line Vss2 can be provided in the first source-drain metal layer SD1.

[0106] For the convenience of description, the first source-drain metal layer SD1 and the second source-drain metal layer SD2 may both be referred to as source-drain metal layers.

[0107] Figure 10 FIG. 4 is a structural diagram of a source / drain metal layer according to some embodiments.

[0108] In some embodiments, the second source / drain metal layer SD2 (eg Figure 9 The first sub-metal layer 171 is located on the substrate 120 (as shown in FIG. Figure 9 As shown in the figure, the first sub-metal layer 171 is located between the first sub-metal layer 171 and the second sub-metal layer 172 , and the activity of the first sub-metal layer 171 is higher than that of the second sub-metal layer 172 .

[0109] In other embodiments, the second source / drain metal layer SD2 may further include a third sub-metal layer 173 ; the third sub-metal layer 173 is located between the first sub-metal layer 171 and the substrate 120 ; and the activity of the first sub-metal layer 171 is higher than that of the third sub-metal layer 173 .

[0110] In some examples, the materials of the second sub-metal layer 172 and the third sub-metal layer 173 may be the same.

[0111] For example, the second sub-metal layer 172 and the third sub-metal layer 173 are both made of titanium (Ti), while the first sub-metal layer 171 can be made of aluminum (Al). In this case, the structure of the second source / drain metal layer SD2 can be called a Ti-Al-Ti structure.

[0112] When the second source-drain metal layer SD2 includes the first voltage lead line Vdd2 (such as Figure 6A As shown), the first voltage lead line Vdd2 also includes a first sub-metal layer 171 and a second sub-metal layer 172. In some examples, the first voltage lead line Vdd2 may also include a first sub-metal layer 171, a second sub-metal layer 172 and a third sub-metal layer 173.

[0113] When the second source-drain metal layer SD2 includes the second voltage lead line Vss2 (such as Figure 6A As shown), the second voltage lead line Vss2 also includes a first sub-metal layer 171 and a second sub-metal layer 172. In some examples, the second voltage lead line Vss2 may also include a first sub-metal layer 171, a second sub-metal layer 172 and a third sub-metal layer 173.

[0114] In some examples, the structure of the first source / drain metal layer SD1 is the same as that of the second source / drain metal layer SD2. In other examples, the first source / drain metal layer SD1 also includes a first sub-metal layer 171 and a second sub-metal layer 172. In other examples, the first source / drain metal layer SD1 includes a first sub-metal layer 171, a second sub-metal layer 172, and a third sub-metal layer 173.

[0115] Some embodiments of the present disclosure are described below by taking an example in which the first voltage lead line Vdd2 and the second voltage lead line Vss2 are both provided in the second source-drain metal layer SD2 .

[0116] Figure 11 is a structural diagram of a display panel 100 according to some embodiments.

[0117] See also Figure 11 After forming the first voltage lead line Vdd2 and the second voltage lead line Vss2, a second planarization layer PLN2 (such as Figure 9 shown).

[0118] The second planarization layer PLN2 includes a hollow portion 181 , wherein the hollow portion 181 is located at least in the lead-out area B10 . There may be multiple hollow portions 181 , so that a barrier portion 182 can be formed between two adjacent hollow portions 181 .

[0119] In one implementation, after the hollow portion 181 is formed, part of the side surface of the first voltage lead line Vdd2 and part of the side surface of the second voltage lead line Vss2 are exposed, thereby exposing the first sub-metal layer 171 in the second source / drain metal layer SD2. Figure 11 The positions of the hollow portion 181 and the blocking portion 182 are schematically illustrated by multiple dotted boxes, which do not represent the actual boundaries of the hollow portion 181 and the blocking portion 182. In addition, it should be noted that one end of the side surface of the first voltage lead line Vdd2 is connected to the surface of the first voltage lead line Vdd2 away from the substrate 120, and the other end is connected to the surface of the first voltage lead line Vdd2 facing the substrate 120. One end of the side surface of the second voltage lead line Vss2 is connected to the surface of the second voltage lead line Vss2 away from the substrate 120, and the other end is connected to the surface of the second voltage lead line Vss2 facing the substrate 120.

[0120] After forming the second planarization layer PLN2, a first electrode pattern layer 140 is formed. The first electrode pattern layer 140 includes a plurality of anodes AND1. Therefore, after forming the first electrode film layer, the first electrode film layer needs to be etched. After etching the first electrode film layer, the first electrode pattern layer 140 is formed.

[0121] During the etching process of the first electrode film layer, an etchant is required. When the etchant etches the first electrode pattern layer 140, the HNO3 in the etchant reacts with the Ag in the first electrode pattern layer 140 to produce the intermediate product AgNO3. The reaction equation of HNO3 and Ag is: 3Ag + 4HNO3 (dilute) = 3AgNO3 + NO↑ + 2H2O.

[0122] Figure 12 FIG. 4 is a schematic diagram showing a concave surface formed after the first sub-metal layer in the second source / drain metal layer SD2 is corroded.

[0123] See also Figure 12 , due to the hollow portion 181 (such as Figure 11 As shown, the side surfaces of the Al layer (i.e., the first sub-metal layer) in the first voltage lead line Vdd2 and the second voltage lead line Vss2 are exposed. The HNO3 in the etchant reacts with the Al in the following manner: Al + 4HNO3 = Al(NO3)3 + NO↑ + 2H2O. This corrodes the side surfaces of the Al layer in the second source / drain metal layer SD2, forming concave surfaces.

[0124] In addition, the intermediate product AgNO3 will also undergo a replacement reaction with Al to form Ag particles. At this time, the chemical equation of the replacement reaction is: Al+3AgNO3==3Ag+Al(NO3)3.

[0125] Figure 13 FIG. 1 is a schematic diagram showing that the first electrode pattern layer 140 and the second electrode pattern layer 150 are punctured due to the presence of Ag particles in the display panel 100 .

[0126] See also Figure 13 , the Ag particles formed by the corrosion of Al in the second source and drain metal layer SD2 will be washed away by the subsequent wet process and fall on the surface of the anode AND in the display area AA. Then, after the light-emitting pattern layer EL and the second electrode pattern layer 150 are formed, the Ag particles will pierce the light-emitting pattern layer EL and contact the second electrode pattern layer 150, thereby causing the anode AND and the cathode CTD to be short-circuited, thereby causing the light-emitting device 112 to be unable to emit light.

[0127] Figure 14 FIG. 1 is a schematic diagram showing the presence of water-oxygen channels in the display panel 100 .

[0128] See also Figure 14 After forming the first electrode pattern layer 140, the light-emitting pattern layer EL, and the second electrode pattern layer 150, it is necessary to form an encapsulation layer 160. The encapsulation layer 160 will contact the side surface of the second source / drain metal layer SD2. Since the side surface of the Al layer is corroded into a concave surface at this time, the film forming stress of the encapsulation layer 160 around the concave surface is relatively large, which easily causes cracks and fails to achieve the effect of blocking water and oxygen. During the subsequent reliability process, water and oxygen invade the display area AA through the cracks, causing the cathode layer CTD and the light-emitting pattern layer EL of the light-emitting device 112 in the display area AA to fail due to water and oxygen, resulting in the light-emitting device 112 not emitting light, forming a dark spot.

[0129] In another implementation, the first voltage lead line Vdd2 and the second voltage lead line Vss2 can be disposed in the first source / drain metal layer SD1, and then a passivation layer can be formed on a layer of the first source / drain metal layer SD1 away from the substrate 120, followed by a first planarization layer PLN1. The passivation layer can cover the surfaces of the first voltage lead line Vdd2 and the second voltage lead line Vss2, thereby protecting the first voltage lead line Vdd2 and the second voltage lead line Vss2 and preventing the side surfaces of the first voltage lead line Vdd2 and the second voltage lead line Vss2 from contacting the etching solution. In this implementation, the addition of a passivation layer formation process increases the manufacturing cost of the display panel 100.

[0130] Figure 15 is a structural diagram of a display panel 100 according to some embodiments, Figure 16 is a cross-sectional view of a display panel 100 according to some embodiments. Figure 16 In the embodiment, multiple film layers between the substrate 120 and the first metal pattern layer 170 are omitted.

[0131] See also Figure 15 and Figure 16 In some embodiments of the present disclosure, a protective portion 141 can be provided on the side surface of the hollow portion 181 where the first voltage lead-out line Vdd2 and the second voltage lead-out line Vss2 are exposed, so as to avoid exposure of the side surface of the first voltage lead-out line Vdd2 and the second voltage lead-out line Vss2, thereby avoiding exposure of the first sub-metal layer 171 in the first voltage lead-out line Vdd2 and the second voltage lead-out line Vss2, thereby reducing the phenomenon of the first sub-metal layer 171 being corroded by the etching solution to form a concave surface, and also reducing the formation of Ag particles.

[0132] See also Figure 15 and Figure 16 In some embodiments of the present disclosure, the display panel 100 includes: a substrate 120 , a first metal pattern layer 170 , an organic insulation pattern layer 180 and a first electrode pattern layer 140 .

[0133] The substrate 120 has been introduced above and will not be described in detail here.

[0134] The first metal pattern layer 170 is located on one side of the substrate 120. The first metal pattern layer 170 includes a voltage lead 174, which is located in the lead area B10; the voltage lead 174 includes a stacked first sub-metal layer 171 (such as Figure 10 as shown) and the second sub-metal layer 172 (as shown Figure 10 The first sub-metal layer 171 is located between the substrate 120 and the second sub-metal layer 172, and the activity of the first sub-metal layer 171 is higher than that of the second sub-metal layer 172.

[0135] In some examples, the first metal pattern layer 170 may be a first source / drain metal layer SD1 (eg, Figure 9 In other examples, the first metal pattern layer 170 may be a second source / drain metal layer SD2 (eg, Figure 9 The first sub-metal layer 171 and the second sub-metal layer 172 have been introduced in some of the above embodiments and will not be described in detail here.

[0136] In some examples, the voltage lead-out line 174 may extend from the lead-out region B10 to the bonding region B30 .

[0137] In some examples, the voltage lead 174 may include a first voltage lead Vdd2. In other examples, the voltage lead 174 may include a second voltage lead Vss2. In still other examples, the voltage lead 174 may include a first voltage lead Vdd2 and a second voltage lead Vss2. The first voltage lead Vdd2 and the second voltage lead Vss2 have been described above and are not further described here.

[0138] The organic insulation pattern layer 180 is located on a side of the first metal pattern layer 170 away from the substrate 120 . The organic insulation pattern layer 180 has a hollow portion 181 at least in the lead-out area B10 , and the hollow portion 181 exposes at least part of the side surface of the first sub-metal layer 171 .

[0139] The organic insulating pattern layer 180 may be formed of an organic material. In some examples, the organic insulating pattern layer 180 may be a first planarization layer PLN1. In other examples, the organic insulating pattern layer 180 may be a second planarization layer PLN2.

[0140] The first electrode pattern layer 140 is located on a side of the organic insulation pattern layer 180 away from the substrate 120 . The first electrode pattern layer 140 includes a protection portion 141 , which at least covers the side surface of the first sub-metal layer 171 exposed by the hollow portion 181 .

[0141] The first electrode pattern layer 140 may further include a plurality of first electrodes. Therefore, the first electrodes and the protective portion 141 are provided in the same layer. Therefore, the first electrodes and the protective portion 141 may be formed in the same process, thereby reducing the manufacturing steps of the display panel 100 and saving costs.

[0142] In the process of forming the display panel 100 , the first metal pattern layer 170 may be formed first, and then the organic insulation pattern layer 180 may be formed, and then the first electrode pattern layer 140 may be formed.

[0143] During the process of forming the first electrode pattern layer 140, a first electrode pattern film may need to be formed first. It should be noted that the first electrode pattern film may completely cover the organic insulating pattern layer 180, and a portion of the first electrode pattern film may cover the portion of the voltage lead 174 exposed by the hollow portion 181. The first electrode pattern film is then etched to form the first electrode pattern layer 140. Since the first electrode pattern layer 140 includes the protective portion 141, when the first electrode pattern film is etched, the protective portion 141 can remain on the side surface of the first sub-metal layer 171 to protect the side surface of the first sub-metal layer 171, and the etching solution cannot contact the side surface of the first sub-metal layer 171, thereby reducing the phenomenon of the first sub-metal layer 171 being corroded to form a concave surface. Therefore, when forming the encapsulation layer 160, the film forming stress of the encapsulation layer 160 near the side surface of the first sub-metal layer 171 can be avoided to be too large, thereby improving the problem of cracks in the encapsulation layer 160, thereby improving the effect of the encapsulation layer 160 in blocking water and oxygen, improving the problem of water and oxygen invading the display area AA, resulting in water and oxygen failure of the light-emitting pattern layer EL in the display area AA, thereby improving the problem of failure of the light-emitting device 112, and thereby reducing the formation of dark spots.

[0144] In addition, since the first sub-metal layer 171 will not come into contact with the etching solution, Ag particles will not be formed due to the replacement reaction, thereby improving the problem of Ag particles falling onto the first electrode pattern layer 140, and further improving the problem of Ag particles piercing the light-emitting pattern layer EL, resulting in a short circuit between the first electrode pattern layer 140 and the second electrode pattern layer 150, improving the problem of failure of the light-emitting device 112, and thus reducing the generation of dark spots.

[0145] See also Figure 16In some examples, the protection portion 141 is not only arranged in the hollow portion 181, but can also extend outside the hollow portion 181 and cover the side of the organic insulation pattern layer 180 away from the substrate 120, thereby increasing the area of ​​the protection portion 141 and further improving the protection effect of the protection portion 141 on the first sub-metal layer 171.

[0146] See also Figure 16 In some embodiments, the protection portion 141 covers the side surface of the voltage lead 174 exposed by the hollow portion 181. The side surface of the voltage lead 174 exposed by the hollow portion 181 includes the first sub-metal layer 171 (such as Figure 10 as shown) and the second sub-metal layer 172 (as shown Figure 10 Partial side surfaces of the two.

[0147] In some embodiments, the voltage lead 174 further includes a third sub-metal layer 173 (eg, Figure 10 (as shown); the third sub-metal layer 173 is located between the first sub-metal layer 171 and the substrate 120; the first sub-metal layer 171 has a higher activity than the third sub-metal layer 173. At this time, the side surface of the voltage lead 174 exposed by the hollow portion 181 includes the side surfaces of the first sub-metal layer 171, the second sub-metal layer 172, and the third sub-metal layer 173 exposed by the hollow portion 181.

[0148] In addition, the hollow portion 181 may also expose a portion of the surface of the voltage lead-out line 174 facing away from the substrate 120 .

[0149] See also Figure 16 In some embodiments, the protection portion 141 extends to a surface of the voltage lead 174 away from the substrate 120 , thereby increasing the protection effect of the protection portion 141 on the side surface of the voltage lead 174 .

[0150] In some examples, the protection portion 141 covers the portion of the voltage lead line 174 away from the surface of the substrate 120, and the dimension in the width direction of the voltage lead line 174 is greater than or equal to 2 μm, thereby ensuring the protection effect of the protection portion 141 on the side surface of the voltage lead line 174.

[0151] See also Figure 16 In some embodiments, the protection portion 141 extends beyond the positive projection of the voltage lead 174 on the substrate 120 , thereby increasing the protection effect of the protection portion 141 on the side surface of the voltage lead 174 .

[0152] For example, when the first electrode pattern layer 140 is the second source / drain metal layer SD2 (eg Figure 9As shown), the first electrode pattern layer 140 is disposed on the first planarization layer PLN1 (as shown Figure 9 As shown), the protection portion 141 may extend to the surface of the first planarization layer PLN1 away from the substrate 120.

[0153] In some examples, the protection portion 141 extends to a portion outside the positive projection of the voltage lead line 174 on the substrate 120, and the dimension in the width direction of the voltage lead line 174 is greater than or equal to 2 μm, thereby ensuring the protection effect of the protection portion 141 on the side surface of the voltage lead line 174.

[0154] See also Figure 16 In some embodiments, encapsulation layer 160 contacts the side of protection portion 141 away from substrate 120. Because protection portion 141 protects first sub-metal layer 171, a concave surface is avoided on the surface of first sub-metal layer 171. Therefore, encapsulation layer 160 does not contact the concave surface, thereby improving the problem of cracks in encapsulation layer 160.

[0155] In some examples, the first inorganic encapsulation layer 161 in the encapsulation layer 160 is in contact with a side of the protection part 141 away from the substrate 120 .

[0156] See also Figure 15 In some embodiments, there are multiple voltage lead lines 174 .

[0157] In some examples, multiple voltage lead lines 174 are used to transmit the same signal. In this case, the multiple voltage lead lines 174 can all be first voltage lead lines Vdd2, or the multiple voltage lead lines 174 can all be second voltage lead lines Vss2.

[0158] In other examples, the plurality of voltage lead lines 174 are used to transmit different signals, and in this case, the plurality of voltage lead lines 174 include a first voltage lead line Vdd2 and a second voltage lead line Vss2.

[0159] See also Figure 15 In some embodiments, at least one of the plurality of voltage lead lines 174 is used to transmit a VDD signal, that is, at least one voltage lead line 174 is a first voltage lead line Vdd2. The remaining voltage lead lines 174 are used to transmit a VSS signal, that is, the remaining voltage lead lines 174 are second voltage lead lines Vss2.

[0160] In some examples, the voltage lead lines 174 include two second voltage lead lines Vss2 and one first voltage lead line Vdd2 , wherein the two second voltage lead lines Vss2 are respectively located on both sides of the first voltage lead line Vdd2 in the second direction X.

[0161] See also Figure 15 In some embodiments, there are multiple protection portions 141 . For any voltage lead 174 , the side surface of the first sub-metal layer 171 exposed by the hollow portion 181 is covered by at least one protection portion 141 .

[0162] In some examples, a protection portion 141 may be provided on a voltage lead-out line 174 , and the protection portion 141 may completely cover the side surface of the voltage lead-out line 174 exposed by the hollow portion 181 .

[0163] In other examples, a plurality of protection portions 141 may be provided on a voltage lead-out line 174 , and the plurality of protection portions 141 completely cover the side surface of the voltage lead-out line 174 that is surrounded by the hollow portion 181 .

[0164] When there are multiple voltage lead-out lines 174 , the protection portions 141 on different voltage lead-out lines 174 are insulated from each other.

[0165] See also Figure 15 In some embodiments, the voltage lead line 174 includes a first routing segment 1741 extending along the first direction Y; the hollow portion 181 extends along the edge of the display area AA, and the hollow portion 181 exposes a portion of the side surface of the first routing segment 1741. The hollow portion 181 may extend along the second direction X.

[0166] The first routing segment 1741 can extend to the binding area B30 and connect to the binding area B30 (eg Figure 7 Some of the pins on the PCB are electrically connected.

[0167] The hollow portion 181 extends along the edge of the display area AA, so that a gap is formed between the hollow portion 181 and the edge of the display area AA.

[0168] In some examples, the voltage lead line 174 further includes a second routing segment 1742 extending along the second direction X. The second routing segment 1742 is located between the first routing segment 1741 and the display area AA, and the second routing segment 1742 is electrically connected to the first routing segment 1741 .

[0169] The first routing segment 1741 and the second routing segment 1742 in the first voltage lead wire Vdd2 and the second voltage lead wire Vss2 are introduced below respectively.

[0170] In some examples, the first voltage lead line Vdd2 includes one second trace segment 1742 and two first trace segments 1741. In the first voltage lead line Vdd2, the two first trace segments 1741 are located on the same side of the second trace segment 1742 and are both electrically connected to the second trace segment 1742.

[0171] In some examples, a second voltage lead line Vss2 includes a second routing segment 1742 and a first routing segment 1741 .

[0172] In some embodiments, the protection portion 141 covers the side surface of the first trace segment 1741 exposed by the hollow portion 181 .

[0173] Figure 17A is a structural diagram of a display panel 100 according to some embodiments, Figure 17B for Figure 17A Cross-sectional view along line C-C'.

[0174] See also Figure 17A and Figure 17B The protection portion 141 extends beyond the hollow portion 181 along the first direction Y and covers the organic insulation pattern layer 180 .

[0175] The protection portion 141 is not only in the hollow portion 181 , but also extends to the outside of the hollow portion 181 and covers the organic insulation pattern layer 180 . At this time, part of the protection portion 141 is located on a surface of the organic insulation pattern layer 180 away from the substrate 120 .

[0176] By extending the protection portion 141 to a surface of the organic insulation pattern layer 180 facing away from the substrate 120 , the area of ​​the protection portion 141 can be increased, thereby improving the protection effect of the protection portion 141 on the first sub-metal layer 171 .

[0177] See also Figure 17A In some embodiments, the number of the hollow portions 181 is at least two, and at least two of the hollow portions 181 are sequentially away from the display area AA (eg Figure 15 As shown in FIG, to form a blocking portion 182. At this time, at least two hollow portions 181 are sequentially arranged along the first direction Y.

[0178] In some examples, the number of the hollow portions 181 may be two, and in this case, one blocking portion 182 may be provided in the display panel 100 .

[0179] In some other examples, the number of the hollow portions 181 may be three, and in this case, two blocking portions 182 may be provided in the display panel 100. One blocking portion 182 may be formed between two adjacent hollow portions 181.

[0180] Among them, at least two hollow portions 181 can pass through the voltage lead line 174. On one voltage lead line 174, multiple side surfaces are exposed by the hollow portions 181, and the multiple exposed side surfaces can be arranged in sequence along the first direction Y. Figure 17A As shown, the exposed side surfaces of the voltage lead-out line 174 are located within the dotted-line frame.

[0181] In some embodiments, the protection portion 141 may extend along the first direction Y. In this case, the protection portion 141 may be in a bar shape.

[0182] In some examples, two protection portions 141 are disposed on a first routing segment 1741 , and the two protection portions 141 are respectively disposed on two sides of the first routing segment 1741 in the second direction X.

[0183] Figure 18A for Figure 17A The cross-sectional view at D-D', where Figure 18A In the embodiment, multiple film layers between the substrate 120 and the first metal pattern layer 170 are omitted.

[0184] See also Figure 18A The protection portion 141 covers at least two hollow portions 181 and covers the blocking portion 182 it passes through.

[0185] The protection portion 141 covering the hollow portion 181 means that the orthographic projection of the protection portion 141 on the substrate 120 overlaps with the orthographic projection of the hollow portion 181 on the substrate 120 .

[0186] The protection portion 141 can not only cover the side surface of the voltage lead-out line 174 exposed by at least two hollow portions 181, but also cover the blocking portion 182 between the hollow portions 181. At this time, there is no interruption between the protection portions 141 in two adjacent hollow portions 181, which is convenient for manufacturing.

[0187] In some examples, when the number of the hollow portions 181 is three, the number of the blocking portions 182 is two, wherein the two blocking portions 182 are respectively a first blocking portion 1821 and a second blocking portion 1822. The second blocking portion 1822 is located at the first blocking portion 1821 away from the display area AA (e.g., Figure 15 side as shown).

[0188] Figure 18B is a structural diagram of a display panel 100 according to some embodiments.

[0189] See also Figure 18B The barrier portion 182 can be used to form a barrier wall DAM. In some examples, the barrier portion 182 can serve as a portion of the barrier wall DAM. When forming the organic encapsulation layer 162, the barrier wall DAM can block the organic encapsulation layer 162 in the encapsulation layer, preventing the organic encapsulation material from flowing to the side of the barrier wall DAM away from the display area AA.

[0190] In some examples, there may be multiple DAMs. When the organic encapsulation material passes over the first DAM closest to the display area AA, DAMs further from the display area AA can intercept the organic encapsulation material again, thereby preventing the organic encapsulation material from flowing to the side of all DAMs away from the display area AA. Therefore, by providing multiple DAMs, the blocking effect of the DAMs on the organic encapsulation material can be enhanced. Figure 16 That is, it is a cross-sectional view of the display panel 100 along the second direction X at a hollow portion 181 closest to the display area AA.

[0191] For example, there are two retaining walls DAM, namely a first retaining wall DAM1 and a second retaining wall DAM2, wherein the second retaining wall DAM2 is located on a side of the first retaining wall DAM1 away from the display area AA.

[0192] The height of the second retaining wall DAM2 is greater than that of the first retaining wall DAM1 , thereby preventing the organic packaging material from flowing through the second retaining wall DAM2 .

[0193] In some examples, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, and the spacer layer can all be used to form the retaining wall DAM, wherein the structure of the first retaining wall DAM1 and the second retaining wall DAM2 can be adjusted according to requirements. Figure 9 ) away from the substrate 120 (as shown) Figure 9 As shown in FIG, the spacer layer can support the mask plate, and the mask plate can be used to form the light emitting pattern layer EL.

[0194] The structures of the first retaining wall DAM1 and the second retaining wall DAM2 in the present disclosure are introduced below by taking the organic insulating pattern layer 180 as the second planarization layer PLN2 as an example.

[0195] In some examples, a portion of the first retaining wall DAM1 is located in the second planarization layer PLN2 , and the remaining portion may be located in the spacer layer PS, wherein the portion of the first retaining wall DAM1 located in the second planarization layer PLN2 is the first blocking portion 1821 .

[0196] In some examples, part of the second barrier wall DAM2 is located in the second planarization layer PLN2 , while the remaining part may be located in the first planarization layer PLN1 . In other examples, the remaining part of the second barrier wall DAM2 may also be located in the pixel definition layer PDL.

[0197] Please refer again Figure 15 In the lead-out area B10, the hollow portion 181 and the blocking portion 182 are both located between the bending area B12 and the display area AA.

[0198] Please refer again Figure 17A The first metal pattern layer 170 further includes an extension portion 175. The orthographic projection of the extension portion 175 on the substrate 120 is located on a side of the orthographic projection of the protection portion 141 on the substrate 120 that is away from the display area AA. The extension portion 175 is connected to the voltage lead 174. If cracks develop in the encapsulation layer 160, the provision of the extension portion 175 can increase the length of the water-oxygen channel, thereby improving the problem of water-oxygen metal display panels causing failure of the luminescent material in the display area AA.

[0199] In some examples, there may be multiple extending portions 175 , which are arranged sequentially along the first direction Y.

[0200] Figure 19 is a structural diagram of a display panel 100 according to some embodiments.

[0201] See also Figure 19 In some embodiments, the hollow portion 181 (eg Figure 17A In the case where there are multiple hollow portions 181, the plurality of hollow portions 181 are sequentially spaced away from the display area AA to form at least one circle of blocking portions 182 between all the hollow portions 181. In this case, the blocking portions 182 can be arranged around the display area AA.

[0202] For example, when there are two hollow portions 181 and one blocking portion 182 , only one blocking wall DAM may be provided in the display panel 100 , wherein the orthographic projection of the blocking wall DAM on the substrate 120 overlaps with the orthographic projection of the blocking portion 182 on the substrate 120 .

[0203] For example, when there are three hollow portions 181, there are two blocking portions 182. In this case, the display panel 100 may include two blocking walls DAM. For example, the two blocking portions 182 are respectively a first blocking portion 1821 and a second blocking portion 1822, and the two blocking walls DAM are respectively a first blocking wall DAM1 and a second blocking wall DAM2.

[0204] The display device 1000 provided in some embodiments of the present disclosure includes the display panel 100 provided in some of the above embodiments. Therefore, the display device 1000 provided in some embodiments of the present disclosure includes all the beneficial effects of the display panel 100 provided in some of the above embodiments, which will not be repeated here.

[0205] In some of the above embodiments, the structure of the display panel 100 is introduced. Next, a method for manufacturing the display panel 100 is introduced.

[0206] Figure 20 1 is a diagram showing steps of a method for manufacturing a display panel 100 according to some embodiments.

[0207] See also Figure 20 , a first metal pattern film 170 ′ is formed on the substrate 190 , wherein the first metal pattern film 170 ′ is etched to form the first metal pattern layer 170 .

[0208] In some examples, when the first metal pattern layer 170 is the second source / drain metal layer SD2 , the substrate 190 includes all film layers between the substrate 120 and the first metal pattern layer 170 , but does not include the first metal pattern layer 170 .

[0209] The first metal pattern film 170 ′ may be formed by a deposition process.

[0210] Figure 21 1 is a diagram showing steps of a method for manufacturing a display panel 100 according to some embodiments.

[0211] See also Figure 21 After etching the first metal pattern film 170 ′, a first metal pattern layer 170 is formed.

[0212] The first metal pattern layer 170 includes a voltage lead 174 .

[0213] Then, an organic insulating pattern film is formed, and the organic insulating pattern film is etched to form an organic insulating pattern layer 180 ( Figure 21 ), wherein the organic insulation pattern layer 180 includes a hollow portion 181.

[0214] Figure 22 1 is a diagram showing steps of a method for manufacturing a display panel 100 according to some embodiments.

[0215] See also Figure 22 Next, a first electrode pattern film 140' is formed on a side of the first metal pattern layer 170 away from the substrate 190. The first electrode pattern film 140' can be formed by a deposition process.

[0216] At this time, a portion of the first electrode pattern film 140 ′ may cover the side surface of the voltage lead-out line 174 exposed by the hollow portion 181 .

[0217] Figure 23 1 is a diagram showing steps of a method for manufacturing a display panel 100 according to some embodiments.

[0218] See also Figure 23 , at the first electrode Figure 1A photoresist is formed on the side of the case film 140' away from the substrate 190, and the photoresist is exposed and developed to form a photoresist pattern. In the lead-out area B10, at least a portion of the photoresist pattern can be projected in a direction perpendicular to the substrate 190 to cover the side surface of the voltage lead-out line 174 exposed by the hollow portion 181.

[0219] Figure 24 1 is a diagram showing steps of a method for manufacturing a display panel 100 according to some embodiments.

[0220] See also Figure 24 The first electrode pattern film 140 ′ is etched according to the photoresist pattern to form a first electrode pattern layer 140 , wherein the first electrode pattern layer 140 includes a protective portion 141 .

[0221] Figure 25 1 is a diagram showing steps of a method for manufacturing a display panel 100 according to some embodiments.

[0222] See also Figure 25 After forming the protection portion 141 , the photoresist pattern is removed.

[0223] After removing the photoresist pattern, a packaging layer 160 (eg Figure 16 As shown), the display panel 100 is packaged to form a Figure 16 The display panel 100.

[0224] It is understandable that, before forming the encapsulation layer 160 , the steps of forming the light emitting pattern layer EL and the second electrode pattern layer 150 are also included.

[0225] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: The display panel has a display area and a lead-out area, wherein the lead-out area is located on one side of the display area; the display panel includes: substrate; a first metal pattern layer located on one side of the substrate; the first metal pattern layer includes a voltage lead, the voltage lead located in the lead-out region; the voltage lead includes a stacked first sub-metal layer and a second sub-metal layer; the first sub-metal layer is located between the substrate and the second sub-metal layer, and the activity of the first sub-metal layer is higher than that of the second sub-metal layer; an organic insulating pattern layer located on a side of the first metal pattern layer away from the substrate; the organic insulating pattern layer having a hollow portion at least in the lead-out region, the hollow portion exposing at least a portion of a side surface of the first sub-metal layer; a first electrode pattern layer, located on a side of the organic insulating pattern layer away from the substrate; the first electrode pattern layer comprises a protective portion, the protective portion at least covering a side surface of the first sub-metal layer exposed by the hollow portion; The direction from the display area to the lead-out area is a first direction; There are at least two hollow portions, and at least two of the hollow portions are sequentially spaced away from the display area, so as to form at least one circle of blocking portions between all the hollow portions; The protection portion extends along the first direction; the protection portion covers the at least two hollow portions and the blocking portion it passes through.

2. The display panel according to claim 1, wherein: The voltage lead further includes a third sub-metal layer; the third sub-metal layer is located between the first sub-metal layer and the substrate; the activity of the first sub-metal layer is higher than that of the third sub-metal layer; The protective portion covers the side surface of the voltage lead exposed by the hollow portion; the side surface of the voltage lead exposed by the hollow portion includes the side surfaces of the first sub-metal layer, the second sub-metal layer and the third sub-metal layer exposed by the hollow portion.

3. The display panel according to claim 2, wherein: The protection portion extends to a surface of the voltage lead wire that is away from the substrate; and / or the protection portion extends beyond an orthographic projection of the voltage lead wire on the substrate.

4. The display panel according to any one of claims 1 to 3, wherein: The voltage lead line includes a first wiring segment extending along the first direction; the hollow portion extends along the edge of the display area, and the hollow portion exposes a portion of the side surface of the first wiring segment; The protection portion covers the side surface of the first wiring segment exposed by the hollow portion, and the protection portion extends beyond the hollow portion along the first direction and covers the organic insulation pattern layer.

5. The display panel according to any one of claims 1 to 3, wherein: There are multiple voltage lead wires and multiple protection parts; wherein, for any voltage lead wire: the side surface of the first sub-metal layer exposed by the hollow part is covered by at least one protection part; At least one of the voltage lead lines is used to transmit a VDD signal, and the remaining voltage lead lines are used to transmit a VSS signal.

6. The display panel according to any one of claims 1 to 3, wherein: The first electrode pattern layer further includes a plurality of first electrodes, and the plurality of first electrodes are located in the display area.

7. The display panel according to any one of claims 1 to 3, wherein: Also includes: a light-emitting pattern layer, the light-emitting pattern layer being located on a side of the first electrode pattern layer away from the substrate; a second electrode pattern layer, the second electrode pattern layer being located on a side of the light-emitting pattern layer away from the substrate; the second electrode pattern layer being electrically connected to the voltage lead wire for transmitting a VSS signal; The encapsulation layer is located on a side of the second electrode pattern layer away from the substrate, and the encapsulation layer is in contact with a side of the protection portion away from the substrate.

8. The display panel according to claim 7, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence. The first inorganic encapsulation layer is in contact with a side of the protection portion away from the substrate.

9. A display device, characterized in that: include: The display panel according to any one of claims 1 to 8, comprising a display area, a lead-out area, and a binding area, wherein the binding area is located on a side of the lead-out area away from the display area, and the voltage lead line extends from the lead-out area to the binding area; a flexible circuit board, one end of which is bound and connected to the binding area; as well as The main control circuit board is electrically connected to the other end of the flexible circuit board.

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