An LDMOS device with a metal field plate and a manufacturing method thereof

Abstract

The present application belongs to the field of semiconductor technology and provides an LDMOS device with a metal field plate and a preparation method thereof. The LDMOS device includes: a semiconductor substrate, a buried oxide region, a drift region, a drain region, a P-type well region, a source region, a P-type base region, a passivation layer, a gate region, a gate extension region, multiple metal field plates, a source electrode, a drain electrode, and a gate electrode. By disposing multiple metal field plates at the interface between the buried oxide region and the drift region, each metal field plate generates an electric field spike, thereby forming multiple high electric fields at the bottom of the drift region. This not only improves the longitudinal withstand voltage of the device, but also uses the multiple electric field spikes to increase the surface electric field of the LDMOS device, making the lateral electric field distribution more uniform and improving the lateral withstand voltage. The gate extension region can form a low-resistance electron channel above the drift region, thereby reducing the on-resistance of the LDMOS device, thereby achieving the purpose of reducing the on-resistance of the device on the basis of improving the breakdown voltage of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an LDMOS device with a metal field plate and a method for manufacturing the same. Background Art

[0002] With the increasing integration density of integrated circuits, laterally diffused metal oxide semiconductors (LDMOS) are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially commonly used in high-voltage power amplifier applications such as LED drivers, switching converters, audio amplifiers, and power management products.

[0003] In practical applications, since MOSFETs are unipolar devices, increasing their withstand voltage is accompanied by an increase in the length of the drift region and a decrease in the drift region concentration. Furthermore, for traditional high-voltage power MOSFETs, their on-resistance is primarily determined by the drift region resistance. For conventional SOI LDMOS, the thickness and size of the drift region must satisfy the RESURF principle to ensure complete depletion in the blocking state, thereby achieving the device's maximum withstand voltage. A thicker drift region results in a lower doping concentration, resulting in a higher specific on-resistance. Furthermore, the RESURF effect is weak, and the electric field regulation effect on the drift region is insignificant, thus negating the significant improvement in the device's withstand voltage.

[0004] This shows that it is difficult for traditional LDMOS devices to strike a balance between increasing breakdown voltage and reducing on-resistance. Summary of the Invention

[0005] In order to solve the above technical problems, the embodiments of the present application provide an LDMOS device with a metal field plate and a preparation method thereof, which can solve the problem that existing LDMOS devices cannot achieve a balance between improving the breakdown voltage and reducing the on-resistance.

[0006] An embodiment of the present application provides an LDMOS device with a metal field plate, the LDMOS device with a metal field plate comprising:

[0007] semiconductor substrates;

[0008] a buried oxide region, provided on the semiconductor substrate;

[0009] A drift region is provided on the buried oxide region; wherein the drift region has an "L"-shaped structure;

[0010] a drain region disposed on a horizontal portion of the drift region;

[0011] A P-type well region is provided on the buried oxide region and contacts the drift region; wherein the P-type well region has an "L"-shaped structure;

[0012] a source region disposed on a horizontal portion of the P-type well region;

[0013] A P-type base region is provided on the buried oxide region and is in contact with the P-type well region and the source region respectively;

[0014] a passivation layer, disposed on the source region, the P-type well region, and the drift region; wherein the passivation layer has an "L"-shaped structure;

[0015] a gate region disposed on the horizontal portion of the passivation layer and in contact with the vertical portion of the passivation layer;

[0016] a gate extension region, disposed on a horizontal portion of the passivation layer and in contact with the gate region;

[0017] a plurality of metal field plates, each of which is disposed at the bottom of the drift region and is in contact with the buried oxide region;

[0018] a source electrode, contacting the source region;

[0019] a drain electrode in contact with the drain region;

[0020] A gate electrode contacts the gate region.

[0021] In one embodiment, the gate extension region includes:

[0022] a first P-type doped region, disposed on a horizontal portion of the passivation layer and in contact with the gate region;

[0023] a second P-type doping region, disposed on a horizontal portion of the passivation layer and in contact with the first P-type doping region;

[0024] a first N-type doping region, disposed on a horizontal portion of the passivation layer and in contact with the second P-type doping region;

[0025] The third P-type doping region is disposed on the horizontal portion of the passivation layer and is in contact with the first N-type doping region.

[0026] In one embodiment, a plurality of the metal field plates are arranged at intervals.

[0027] In one embodiment, the distance between adjacent metal field plates decreases sequentially in the direction from the source region to the drain region.

[0028] In one embodiment, the spacing between adjacent metal field plates is inversely proportional to the distance between the source regions.

[0029] In one embodiment, the thickness of the drift region is greater than the sum of the thickness of the metal field plate and the thickness of the drain region.

[0030] In one embodiment, the thickness of the P-type base region is the sum of the thicknesses of the source region and the horizontal portion of the P-type well region.

[0031] In one embodiment, the thickness of the metal field plate is proportional to the distance between the metal field plate and the source region.

[0032] In one embodiment, the sum of the widths of the first P-type doping region, the second P-type doping region, the first N-type doping region, and the third P-type doping region is equal to the width of the vertical portion of the drift region.

[0033] A second aspect of an embodiment of the present application provides a method for preparing an LDMOS device having a metal field plate, comprising:

[0034] forming a buried oxide region on a semiconductor substrate;

[0035] forming a plurality of metal field plates on the buried oxide region;

[0036] forming a drift region, a P-type well region, and a P-type base region on the buried oxide region; wherein the drift region has an "L"-shaped structure, the P-type well region has an "L"-shaped structure, and is located between the P-type base region and the drift region;

[0037] forming a source region on a horizontal portion of the P-type well region, wherein the source region is also in contact with the P-type base region;

[0038] forming a drain region on a horizontal portion of the drift region;

[0039] forming a passivation layer on the source region, the P-type well region, and the drift region; wherein the passivation layer has an "L"-shaped structure;

[0040] forming a gate region and a gate extension region in sequence on the horizontal portion of the passivation layer; wherein the gate region contacts the vertical portion of the passivation layer, and the gate extension region contacts the gate region;

[0041] A source electrode is formed on the source region, a drain electrode is formed on the drain region, and a gate electrode is formed on the gate region.

[0042] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: by setting multiple metal field plates at the interface position between the buried oxide region and the drift region, the electric field modulation effect is utilized so that each metal field plate generates an electric field spike, thereby forming multiple high electric fields at the bottom of the drift region, which can not only improve the longitudinal withstand voltage of the device, but also utilize the multiple electric field spikes at the bottom of the drift region to increase the surface electric field of the LDMOS device, so that the lateral electric field distribution is more uniform, thereby improving the lateral withstand voltage. By setting the gate extension region, a low-resistance electron channel can be formed above the drift region, thereby reducing the on-resistance of the LDMOS device, thereby achieving the purpose of reducing the on-resistance of the device on the basis of improving the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a schematic diagram of the structure of the LDMOS device with a metal field plate provided in the embodiment of the present application. Figure 1 ;

[0044] Figure 2 This is a schematic diagram of the structure of the LDMOS device with a metal field plate provided in the embodiment of the present application. Figure 2 ;

[0045] Figure 3 This is a schematic diagram of the structure of the LDMOS device with a metal field plate provided in the embodiment of the present application. Figure 3 ;

[0046] Figure 4 This is a schematic diagram of the structure of the LDMOS device with a metal field plate provided in the embodiment of the present application. Figure 4 ;

[0047] Figure 5 This is a schematic diagram of the structure of the LDMOS device with a metal field plate provided in the embodiment of the present application. Figure 5 ;

[0048] Figure 6 This is a schematic diagram of the steps of a method for preparing an LDMOS device with a metal field plate provided by one embodiment of the present application;

[0049] Figure 7 This is a schematic diagram after forming a buried oxygen region according to an embodiment of the present application;

[0050] Figure 8 This is a schematic diagram after forming multiple metal field plates according to an embodiment of the present application;

[0051] Figure 9 This is a schematic diagram after forming a drift region, a P-type well region, and a P-type base region according to an embodiment of the present application;

[0052] Figure 10 This is a schematic diagram of forming a source region and a drain region provided by one embodiment of the present application;

[0053] Figure 11 This is a schematic diagram after forming a passivation layer according to an embodiment of the present application;

[0054] Figure 12 This is a schematic diagram of the structure after the gate region and the gate extension region are formed, provided by one embodiment of the present application;

[0055] Figure 13 This is a schematic diagram of the structure after the source electrode, drain electrode and gate electrode are formed, provided by an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0057] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0058] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0060] With the increasing integration density of integrated circuits, laterally diffused metal oxide semiconductors (LDMOS) are frequently used in the design of high-voltage power integrated circuits due to their outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. They are especially commonly used in high-voltage power amplifier applications such as LED drivers, switching converters, audio amplifiers, and power management products.

[0061] In practical applications, since MOSFETs are unipolar devices, increasing their withstand voltage is accompanied by an increase in the length of the drift region and a decrease in the drift region concentration. Furthermore, for traditional high-voltage power MOSFETs, their on-resistance is primarily determined by the drift region resistance. For conventional SOILDMOS, the thickness and size of the drift region must satisfy the RESURF principle to ensure complete depletion in the blocking state, thereby achieving the device's maximum withstand voltage. A thicker drift region results in a lower doping concentration, resulting in a higher specific on-resistance and a weaker RESURF effect. This ineffectively regulates the electric field in the drift region, thus minimizing the device's withstand voltage.

[0062] This shows that it is difficult for traditional LDMOS devices to strike a balance between increasing breakdown voltage and reducing on-resistance.

[0063] In order to solve the above technical problems, the present invention provides an LDMOS device with a metal field plate. Figure 1 As shown, the LDMOS device with a metal field plate includes: a semiconductor substrate 10, a buried oxide region 20, a drift region 30, a drain region 40, a P-type well region 50, a source region 60, a P-type base region 70, a passivation layer 80, a gate region 100, a gate extension region 90, a plurality of metal field plates 110, a source electrode S, a drain electrode D and a gate electrode G.

[0064] Specifically, the buried oxide region 20 is provided on the semiconductor substrate 10; the drift region 30 is provided on the buried oxide region 20; wherein the drift region 30 is in an "L"-shaped structure; the drain region 40 is provided on the horizontal portion of the drift region 30; the P-type well region 50 is provided on the buried oxide region 20, and the P-type well region 50 is in contact with the drift region 30; wherein the P-type well region 50 is in an "L"-shaped structure; the source region 60 is provided on the horizontal portion of the P-type well region 50; the P-type base region 70 is provided on the buried oxide region 20, and the P-type base region 70 is in contact with the P-type well region 50 and the source region 60 respectively; the passivation layer 80 is provided on the source region 60, the P-type well region 50 and the drift region 30; wherein the passivation layer 80 is in an "L"-shaped structure; the gate region 100 is arranged on the horizontal portion of the passivation layer 80, and the gate region 100 is in contact with the vertical portion of the passivation layer 80; the gate extension region 90 is arranged on the horizontal portion of the passivation layer 80, and the gate extension region 90 is in contact with the gate region 100; a plurality of metal field plates 110 are respectively arranged at the bottom of the drift region 30, and the plurality of metal field plates 110 are respectively in contact with the buried oxide region 20; the source electrode S is in contact with the source region 60; the drain electrode D is in contact with the drain region 40; the gate electrode G is in contact with the gate region 100, and the gate electrode G is also in contact with the gate extension region 90.

[0065] In this embodiment, multiple metal field plates 110 are set at the interface position between the buried oxide region 20 and the drift region 30, and the electric field modulation effect is utilized to generate an electric field spike at the position corresponding to each metal field plate 110, thereby forming multiple high electric fields at the bottom of the drift region 30. This not only improves the longitudinal withstand voltage of the device, but also utilizes the multiple electric field spikes at the bottom of the drift region 30 to increase the surface electric field of the LDMOS device, making the lateral electric field distribution more uniform and improving the lateral withstand voltage.

[0066] In this embodiment, the drift region 30 has an "L"-shaped structure, which consists of a horizontal portion and a vertical portion, and the drain region 40 is arranged on the horizontal portion of the drift region 30; in a specific application embodiment, the upper surface of the drain region 40 is flush with the upper surface of the vertical portion of the drift region 30, and the width of the drain region 40 is equal to the width of the horizontal portion of the drift region 30. At this time, the drain region 40 and the drift region 30 can form a rectangular parallelepiped.

[0067] In this embodiment, the P-type well region 50 has an "L"-shaped structure, which consists of a horizontal portion and a vertical portion. The source region 60 is provided on the horizontal portion of the P-type well region 50. In a specific application embodiment, the upper surface of the source region 60 is flush with the upper surface of the P-type well region 50, and the width of the source region 60 is equal to the width of the P-type well region 50. In this case, the source region 60 and the P-type well region 50 form a rectangular parallelepiped.

[0068] In this embodiment, the drain region 40 , the drift region 30 , the P-type well region 50 , the source region 60 and the P-type base region 70 are at the same level, and the passivation layer 80 is disposed on the source region 60 , the P-type well region 50 and the drift region 30 .

[0069] In this embodiment, the passivation layer 80 has an "L"-shaped structure, which consists of a horizontal portion and a vertical portion. The gate region 100 and the gate extension region 90 are both arranged on the horizontal portion of the passivation layer 80, and the gate region 100 is in contact with the vertical portion of the passivation layer 80, and the gate extension region 90 is in contact with the gate region 100; in a specific application embodiment, the upper surfaces of the gate region 100 and the gate extension region 90 are flush with the upper surface of the passivation layer 80, and the sum of the widths of the gate region 100 and the gate extension region 90 is equal to the sum of the widths of the horizontal portion of the passivation layer 80. At this time, the gate region 100, the gate extension region 90 and the passivation layer 80 together form a rectangular parallelepiped.

[0070] In this embodiment, the gate electrode G is disposed on the gate region 100 and the gate extension region 90 , and the gate electrode G is in contact with the gate region 100 and the gate extension region 90 , respectively.

[0071] In this embodiment, a plurality of metal field plates 110 are arranged at the bottom of the drift region 30 and are respectively in contact with the buried oxide region 20. At this time, a Schottky contact is formed between the metal field plate 110 and the drift region 30. When the device is working, a Schottky semiconductor junction is formed between the metal field plate 110 and the drift region 30, which can enhance the electric field strength of the buried oxide region 20, so that the LDMOS device is subjected to more voltage from the buried oxide region 20 during operation, thereby achieving the purpose of enhancing the longitudinal withstand voltage of the device. By arranging a plurality of metal field plates 110 at the bottom of the drift region 30, each metal field plate 110 corresponds to an electric field peak. Since there are multiple high electric fields below the drift region 30, due to the electric field modulation effect, the multiple electric field peaks at the bottom will increase the surface electric field of the LDMOS device, making the lateral electric field distribution more uniform, thereby improving the lateral withstand voltage.

[0072] In this embodiment, the gate extension region 90 is provided on the horizontal portion of the passivation layer 80 and contacts the gate region 100. By providing the gate extension region 90 on the horizontal portion of the passivation layer 80, the electric field above the passivation layer 80 can be enhanced, thereby forming a low-resistance electron channel above the drift region 30, thereby reducing the on-resistance of the LDMOS device. In this embodiment, the on-resistance of the LDMOS device is reduced by providing the gate extension region 90, and the breakdown voltage of the LDMOS device is increased by providing multiple metal field plates 110, so that a balance is achieved between the breakdown voltage and the on-resistance, thereby achieving the purpose of reducing the on-resistance of the device while increasing the breakdown voltage of the device.

[0073] In one embodiment, for the material in the buried oxide region 20 , the commonly used material with mature technology is SiO 2 . A low-K dielectric with a dielectric constant lower than that of SiO 2 can also be used to improve the longitudinal withstand voltage of the device and reduce the thickness of the buried oxide region 20 .

[0074] In one embodiment, the metal field plate 110 may be aluminum.

[0075] In one embodiment, reference Figure 2 As shown, the gate extension region 90 includes a first P-type doping region 91 , a second P-type doping region 92 , a first N-type doping region 93 and a third P-type doping region 94 .

[0076] Specifically, the first P-type doping region 91 is arranged on the horizontal portion of the passivation layer 80, and the first P-type doping region 91 is in contact with the gate region 100; the second P-type doping region 92 is arranged on the horizontal portion of the passivation layer 80, and the second P-type doping region 92 is in contact with the first P-type doping region 91; the first N-type doping region 93 is arranged on the horizontal portion of the passivation layer 80, and the first N-type doping region 93 is in contact with the second P-type doping region 92; the third P-type doping region 94 is arranged on the horizontal portion of the passivation layer 80, and the third P-type doping region 94 is in contact with the first N-type doping region 93.

[0077] In this embodiment, the first P-type doping region 91 and the second P-type doping region 92 are doped with P-type doping ions, wherein the doping concentration of the first P-type doping region 91 is greater than the doping concentration of the second P-type doping region 92, the first N-type doping region 93 can be doped with N-type doping ions, for example, the N-type doping ions can be nitrogen ions or phosphorus ions, and the third P-type doping region 94 can be doped with P-type doping ions, for example, the P-type doping ions can be aluminum ions. By doping different elements, the first N-type doping region 93 and the third P-type doping region 94 form a PN junction, which can enhance the electric field above the passivation layer 80, thereby forming a low-resistance electron channel above the drift region 30 and reducing the on-resistance.

[0078] In one embodiment, the second P-type doping region 92 has the same doping ions as the first P-type doping region 91, but at a different doping concentration. This is different from the doping ions in the first N-type doping region 93. This can prevent the depletion of the second P-type doping region 92 from adversely affecting the longitudinal electric field strength in the drift region 30 when the device is in the off state. Therefore, the device's withstand voltage capability can be improved. However, due to the different doping type of the first N-type doping region 93, the process requirements are more complex.

[0079] In one embodiment, the doping concentration of the drift region 30 increases in stages from near the P-type well region 50 to near the drain region 40. The staged doping of the drift region 30 weakens the impact of the RESURF effect (high surface electric field, low surface electric field) on the electric field distribution in the drift region 30 in the LDMOS device. As a result, the device's relative withstand voltage is significantly improved. However, the staged doping of the drift region 30 places high demands on the process.

[0080] In one embodiment, the plurality of metal field plates 110 are spaced apart.

[0081] Specifically, when the LDMOS device is in a working state, an electric field is generated from the drain region 40 to the source region 60. By arranging multiple metal field plates 110 at intervals at the bottom of the drift region 30, a Schottky semiconductor junction can be formed between the metal field plates 110 and the drift region 30, thereby increasing the electric field strength of the buried oxide region 20, and improving the withstand voltage value of the device in the blocking state, so that the LDMOS device with the metal field plate bears more voltage when working, thereby improving the longitudinal withstand voltage of the LDMOS device with the metal field plate; by arranging multiple metal field plates 110 at intervals at the bottom of the drift region 30, because each metal field plate 110 corresponds to an electric field spike, since there are multiple high electric fields below the drift region 30, due to the electric field modulation effect, the multiple electric field spikes at the bottom will increase the surface electric field of the LDMOS device, making the lateral electric field distribution more uniform, improving the lateral withstand voltage, and thus improving the overall withstand voltage of the LDMOS device.

[0082] In one embodiment, reference Figure 3 As shown, the distance between adjacent metal field plates 110 decreases in sequence from the source region 60 to the drain region 40 .

[0083] In this embodiment, multiple metal field plates 110 are arranged at intervals because when the LDMOS device is operating, an electric field is generated from the drain region 40 to the source region 60, and the electric field strength near the drain region 40 is greater than the electric field strength near the source region 60. By arranging the metal field plates 110 to generate electric field spikes, based on the electric field modulation effect, multiple electric field spikes can increase the surface electric field of the device, making the lateral electric field distribution more uniform and improving the lateral withstand voltage. Therefore, the spacing between two adjacent metal field plates 110 near the drain region 40 is smaller than the spacing between two adjacent metal field plates 110 near the source region 60. The closer to the drain region 40, the denser the distribution of the metal field plates 110, thereby solving the larger electric field strength near the drain region 40 and improving the lateral withstand voltage.

[0084] In one embodiment, reference Figure 3 As shown, the spacing between adjacent metal field plates 110 is inversely proportional to the distance between the source regions 60. Specifically, the closer the adjacent metal field plates 110 are to the source region 60, the larger the spacing, and the farther the adjacent metal field plates 110 are from the source region 60, the smaller the spacing. That is, the closer the metal field plates 110 are to the drain region 40, the denser the distribution. This is because when the LDMOS device is operating, an electric field is generated from the drain region 40 to the source region 60, and the electric field strength near the drain region 40 is greater than the electric field strength near the source region 60. This operation can improve the voltage withstand capability of the LDMOS device, and by providing the gate extension region 90, the on-resistance of the LDMOS device is reduced.

[0085] In one embodiment, reference Figure 2 As shown, the thickness d1 of the drift region 30 is greater than the sum of the thickness d2 of the metal field plate 110 and the thickness d3 of the drain region 40 .

[0086] In this embodiment, the metal field plate 110 is arranged at the bottom of the drift region 30, and the drain region 40 is arranged on the horizontal portion of the drift region 30. The thickness d2 of the metal field plate 110 is less than the thickness of the horizontal portion of the drift region 30. In this way, the multiple electric field spikes generated by the multiple metal field plates 110 can modulate the surface electric field of the LDMOS device, thereby improving the lateral withstand voltage.

[0087] In one embodiment, reference Figure 2As shown, the thickness of the P-type base region 70 is the sum of the thicknesses of the horizontal portions of the source region 60 and the P-type well region 50. Since the P-type base region 70 is the voltage access point of the LDMOS device, by setting the thickness of the P-type base region 70 to be the sum of the thicknesses of the horizontal portions of the source region 60 and the P-type well region 50, better voltage access can be achieved, thereby maintaining the stability of the LDMOS device and improving the performance of the LDMOS device.

[0088] In one embodiment, reference Figure 4 As shown, the thickness of the metal field plate 110 is proportional to the distance between the metal field plate 110 and the source region 60 .

[0089] Specifically, refer to Figure 4 As shown, the farther the metal field plate 110 is from the source region 60, the thicker the metal field plate 110 is, and the closer the metal field plate 110 is to the source region 60, the thinner the thickness of the metal field plate 110 is. That is, the closer the metal field plate 110 is to the drain region 40, the thicker the metal field plate 110 is, and the farther the metal field plate 110 is from the drain region 40, the thinner the metal field plate 110 is. This is because, when the LDMOS device is working, the electric field intensity between the drain regions 40 is relatively large. By setting the metal field plate 110 closer to the drain region 40, the thicker the metal field plate 110 is, the thicker the metal field plate 110 is, the larger the electric field peak generated by the metal field plate 110 is, and the stronger its ability to modulate the electric field near the drain region 40 is, which can better modulate the surface electric field of the LDMOS device and improve the lateral withstand voltage.

[0090] In one embodiment, reference Figure 5 As shown, the LDMOS device with a metal field plate further includes: multiple shallow trench isolation regions 120 (STI), wherein the multiple STIs 120 are all arranged in the second P-type doped region 92, wherein the depth of the multiple STIs 120 gradually increases from the source region 60 to the drain region 40, specifically, the depth of the STIs 120 near the source region 60 is less than the depth of the STIs near the drain region 40, wherein the multiple STIs 120 are formed by depositing, patterning, and etching silicon using a silicon nitride mask to form trenches, and then filling the trenches with deposited oxide. By arranging the multiple STIs 120 in the second P-type doped region 92, a high electric field can be formed at the multiple STIs 120, which cooperates with the multiple metal field plates 110 to modulate the electric field distribution of the LDMOS device and improve the breakdown voltage of the LDMOS device.

[0091] In one embodiment, the material used for the passivation layer 80 is a high-K dielectric. By using a high-K dielectric, the electron channel formed above the drift region 30 can have a higher concentration and a lower resistance, thereby better reducing the on-resistance of the LDMOS device.

[0092] In one embodiment, reference Figure 2As shown, the sum of the widths of the first P-type doping region 91, the second P-type doping region 92, the first N-type doping region 93 and the third P-type doping region 94 (W1+W2+W3+W4) is equal to the width W5 of the vertical portion of the drift region 30, wherein W1 is the width of the first P-type doping region 91, W2 is the width of the second P-type doping region 92, W3 is the width of the first N-type doping region 93, W4 is the width of the third P-type doping region 94, and W5 is the width of the vertical portion of the drift region 30.

[0093] Specifically, the width of the second P-type doping region 92 is greater than the width of any of the first P-type doping region 91, the first N-type doping region 93, and the third P-type doping region 94. By setting the second P-type doping region 92 to be larger in width, the depletion of the second P-type doping region 92 in the device's off state can be avoided from adversely affecting the longitudinal electric field strength of the drift region 30. Therefore, the device's withstand voltage capability can be improved.

[0094] In one embodiment, the passivation layer 80 is in an "L"-shaped stepped shape. For example, the passivation layer 80 can be in an "L"-shaped three-step shape, wherein the gate region 100 and the first P-type doping region 91 are located on the first step, the second P-type doping region 92 is located on the second step, and the first N-type doping region 93 and the third P-type doping region 94 are located on the third step. By setting the gate extension region 90, a low-resistance electron channel can be formed above the drift region 30. By setting the gate extension region 90 on different steps, the concentration of the low-resistance electron channel formed above the drift region 30 can be made different, so that the size of the reduced on-resistance is different. Because the electric field strength near the drain region 40 is large, by forming a low-resistance electron channel with a large concentration, its on-resistance can be greatly reduced, thereby reducing the on-resistance of the LDMOS device and improving its performance.

[0095] The present application also provides a method for preparing an LDMOS device having a metal field plate, referring to Figure 6 As shown, the method for manufacturing the LDMOS device in this embodiment includes steps S10 to S70.

[0096] In step S10 , a buried oxide region 20 is formed on the semiconductor substrate 10 .

[0097] In this embodiment, the semiconductor substrate 10 may be an N-type silicon substrate. Figure 7 As shown, in a specific application, a buried oxide region 20 can be formed on the semiconductor substrate 10 by depositing silicon dioxide material or oxidizing an N-type silicon substrate. The thickness of the buried oxide region 20 can be set according to the application requirements of the device.

[0098] In a specific application embodiment, the material used in the buried oxide region 20 can also be a low-K dielectric material with a dielectric constant lower than that of SiO2. By using the low-K dielectric material, the longitudinal withstand voltage of the device is improved and the thickness of the buried oxide region 20 is reduced.

[0099] In step S20: refer to Figure 8 As shown, a plurality of metal field plates 110 are formed on the buried oxide region 20;

[0100] In a specific application, the plurality of metal field plates 110 can be formed by depositing semiconductor material or metal material in a predetermined area on the buried oxide region 20 through a mask.

[0101] In one embodiment, the plurality of metal field plates 110 may be formed by sputtering in a predetermined area on the buried oxide region 20 through a mask. Specifically, metal atoms are sputtered to a designated position at a certain angle.

[0102] In step S30: refer to Figure 9 As shown, a drift region 30 , a P-type well region 50 , and a P-type base region 70 are formed on the buried oxide region 20 .

[0103] Specifically, the drift region 30 has an "L"-shaped structure, and the P-type well region 50 contacts the drift region 30; the P-type well region 50 has an "L"-shaped structure; the P-type base region 70 contacts the P-type well region 50 and the source region 60 respectively, and the P-type well region 50 is located between the P-type base region 70 and the drift region 30.

[0104] In a specific application embodiment, the drift region 30 , the P-type well region 50 and the P-type base region 70 may be formed in a predetermined area on the buried oxide region 20 by depositing semiconductor materials or metal materials.

[0105] In this embodiment, multiple metal field plates are set at the interface position between the buried oxide region 20 and the drift region, and the electric field modulation effect is utilized to generate an electric field spike at the position corresponding to each metal field plate, thereby forming multiple high electric fields at the bottom of the drift region. This can not only improve the longitudinal withstand voltage of the device, but also utilize the multiple electric field spikes at the bottom of the drift region to increase the surface electric field of the LDMOS device, making the lateral electric field distribution more uniform and improving the lateral withstand voltage.

[0106] In this embodiment, multiple metal field plates 110 are arranged at intervals because when the LDMOS device is operating, an electric field is generated from the drain region 40 to the source region 60, and the electric field strength near the drain region 40 is greater than the electric field strength near the source region 60. By arranging the metal field plates 110 to generate electric field spikes, based on the electric field modulation effect, multiple electric field spikes can increase the surface electric field of the device, making the lateral electric field distribution more uniform and improving the lateral withstand voltage. Therefore, the spacing between two adjacent metal field plates 110 near the drain region 40 is smaller than the spacing between two adjacent metal field plates 110 near the source region 60. The closer to the drain region 40, the denser the distribution of the metal field plates 110, thereby solving the larger electric field strength near the drain region 40 and improving the lateral withstand voltage.

[0107] Step S40: Reference Figure 10 As shown, a source region 60 is formed on a horizontal portion of the P-type well region 50 ; a drain region 40 is formed on a horizontal portion of the drift region 30 ;

[0108] In this embodiment, a mask is used to determine the shapes of the source region 60 and the drain region 40 , and the source region 60 and the drain region 40 are formed by deposition on the mask.

[0109] In one embodiment, the thickness d1 of the drift region 30 is greater than the sum of the thickness d2 of the metal field plate 110 and the thickness d3 of the drain region 40 .

[0110] In this embodiment, the metal field plate 110 is arranged at the bottom of the drift region 30, and the drain region 40 is arranged on the horizontal portion of the drift region 30. The thickness d2 of the metal field plate 110 is less than the thickness of the horizontal portion of the drift region 30. In this way, the multiple electric field spikes generated by the multiple metal field plates 110 can modulate the surface electric field of the LDMOS device, thereby improving the lateral withstand voltage.

[0111] Step S50: Reference Figure 11 As shown, a passivation layer 80 is formed on the source region 60 , the P-type well region 50 and the drift region 30 .

[0112] In this embodiment, the passivation layer 80 has an "L"-shaped structure, the gate region 100 and the gate extension region 90 are both arranged on the horizontal portion of the passivation layer 80, and the gate region 100 is in contact with the vertical portion of the passivation layer 80, and the gate extension region 90 is in contact with the gate region 100; the upper surfaces of the gate region 100 and the gate extension region 90 are flush with the upper surface of the vertical portion of the passivation layer 80, and the widths of the gate region 100 and the gate extension region 90 are equal to the width of the horizontal portion of the passivation layer 80. At this time, the gate region 100, the gate extension region 90 and the passivation layer 80 together form a rectangular parallelepiped.

[0113] Step S60: Reference Figure 12As shown, a gate region 100 and a gate extension region 90 are sequentially formed on a horizontal portion of the passivation layer 80 .

[0114] In this embodiment, the gate region 100 contacts the vertical portion of the passivation layer 80, and the gate extension region 90 contacts the gate region 100. The gate extension region 90 is provided on the horizontal portion of the passivation layer 80. The provision of the gate extension region 90 can enhance the electric field above the passivation layer 80, thereby forming a low-resistance electron channel above the drift region 30, thereby reducing the on-resistance of the LDMOS device. In this embodiment, the provision of the gate extension region 90 reduces the on-resistance of the LDMOS device, and the provision of multiple metal field plates 110 increases the breakdown voltage of the LDMOS device, thereby achieving a balance between the breakdown voltage and the on-resistance, thereby providing an LDMOS device with reduced on-resistance and increased breakdown voltage.

[0115] Step S70: Reference Figure 13 As shown, a source electrode S is formed on the source region 60 , a drain electrode D is formed on the drain region 40 , and a gate electrode G is formed on the gate region 100 .

[0116] In a specific application, a mask is used to determine the shapes of the source electrode S, the gate electrode G, and the drain electrode D, and metal is deposited on the mask to form the source electrode S, the gate electrode G, and the drain electrode D.

[0117] In this embodiment, a mask is used to define the shapes of the source electrode S, the gate electrode G, and the drain electrode D, and then a metal material is deposited on the mask to form the source electrode S, the gate electrode G, and the drain electrode D, and then the mask is removed.

[0118] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0119] The units described as separate components may or may not be physically separate, and the components used to display data may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0120] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. An LDMOS device with a metal field plate, characterized in that: The LDMOS device includes: semiconductor substrates; a buried oxide region, provided on the semiconductor substrate; A drift region is provided on the buried oxide region; wherein the drift region has an "L"-shaped structure; a drain region disposed on a horizontal portion of the drift region; A P-type well region is provided on the buried oxide region and contacts the drift region; wherein the P-type well region has an "L"-shaped structure; a source region disposed on a horizontal portion of the P-type well region; A P-type base region is provided on the buried oxide region and is in contact with the P-type well region and the source region respectively; a passivation layer, disposed on the source region, the P-type well region, and the drift region; wherein the passivation layer has an "L"-shaped structure; a gate region disposed on the horizontal portion of the passivation layer and in contact with the vertical portion of the passivation layer; a gate extension region, disposed on a horizontal portion of the passivation layer and in contact with the gate region; a plurality of metal field plates, each of which is disposed at the bottom of the drift region and is in contact with the buried oxide region; a source electrode, contacting the source region; a drain electrode in contact with the drain region; A gate electrode contacts the gate region.

2. The LDMOS device with a metal field plate according to claim 1, wherein: The gate extension region includes: a first P-type doped region, disposed on a horizontal portion of the passivation layer and in contact with the gate region; a second P-type doping region, disposed on a horizontal portion of the passivation layer and in contact with the first P-type doping region; a first N-type doping region, disposed on a horizontal portion of the passivation layer and in contact with the second P-type doping region; The third P-type doping region is disposed on the horizontal portion of the passivation layer and is in contact with the first N-type doping region.

3. The LDMOS device with a metal field plate according to claim 1, wherein: The plurality of metal field plates are arranged at intervals.

4. The LDMOS device with a metal field plate according to claim 3, wherein: The distance between adjacent metal field plates decreases sequentially from the source region to the drain region.

5. The LDMOS device with a metal field plate according to claim 3, wherein: The distance between adjacent metal field plates is inversely proportional to the distance between the source regions.

6. The LDMOS device with a metal field plate according to claim 1, wherein: The thickness of the drift region is greater than the sum of the thickness of the metal field plate and the thickness of the drain region.

7. The LDMOS device with a metal field plate according to claim 1, wherein: The thickness of the P-type base region is the sum of the thicknesses of the source region and the horizontal portion of the P-type well region.

8. The LDMOS device with a metal field plate according to claim 6, wherein: The thickness of the metal field plate is proportional to the distance between the metal field plate and the source region.

9. The LDMOS device with a metal field plate according to claim 2, wherein: The sum of the widths of the first P-type doping region, the second P-type doping region, the first N-type doping region, and the third P-type doping region is equal to the width of the vertical portion of the drift region.

10. A method for preparing an LDMOS device having a metal field plate, characterized in that: include: forming a buried oxide region on a semiconductor substrate; forming a plurality of metal field plates on the buried oxide region; A drift region, a P-type well region, and a P-type base region are formed on the buried oxide region; wherein the drift region has an "L"-shaped structure, the P-type well region has an "L"-shaped structure, and is located between the P-type base region and the drift region; forming a source region on a horizontal portion of the P-type well region, wherein the source region is also in contact with the P-type base region; forming a drain region on a horizontal portion of the drift region; forming a passivation layer on the source region, the P-type well region, and the drift region; wherein the passivation layer has an "L"-shaped structure; forming a gate region and a gate extension region in sequence on the horizontal portion of the passivation layer; wherein the gate region contacts the vertical portion of the passivation layer, and the gate extension region contacts the gate region; A source electrode is formed on the source region, a drain electrode is formed on the drain region, and a gate electrode is formed on the gate region.

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