Silicon carbide device with vertical channel and preparation method thereof

Abstract

The present invention relates to the technical field of silicon carbide power devices, and specifically to a silicon carbide device with a vertical channel and a preparation method, comprising: a substrate; an epitaxial layer formed above the substrate; a pair of well regions buried in the epitaxial layer; a pair of first trenches formed in the epitaxial layer, the bottom of which reaches the well region; a gate oxide layer formed on the epitaxial layer and extending to the well region along the sidewalls of the first trench; a polysilicon layer formed on the gate oxide layer and extending to the bottom along the sidewalls of the first trench; and an interlayer dielectric layer formed above the epitaxial layer and the polysilicon layer. The beneficial effect is that by providing a first channel and allowing the gate oxide layer and the polysilicon layer to extend to the well region along the sidewalls of the first channel, a vertical conductive channel with an <11-20> crystal orientation or a <1-100> crystal orientation is formed in the first channel, thereby improving electron mobility and reducing on-resistance compared to the planar conductive channel of the prior art. At the same time, the well region is provided at the bottom of the first trench, which achieves shielding of the electric field during reverse blocking.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon carbide power devices, and in particular to a silicon carbide device with a vertical channel and a preparation method thereof. Background Art

[0002] Silicon carbide devices refer to semiconductor devices made of silicon carbide. Due to the physical properties of silicon carbide such as wide bandgap, high breakdown electric field, high thermal conductivity and high electron saturation rate, it has the advantages of high temperature resistance, high voltage resistance, high frequency, high power and radiation resistance, which can reduce the energy consumption of downstream products. Therefore, it has a wide range of applications in new energy vehicles, rail transit, photovoltaic energy storage and smart grids.

[0003] In the prior art, there are already many semiconductor devices made of silicon carbide. For example, Chinese patent CN202210299125.3 discloses a high-reliability silicon carbide MOSFET device with an integrated P-type channel. This device achieves good device performance by sequentially preparing an N-type substrate, an N-type epitaxial layer, a P-contact region in the body, a trenched gate dielectric, a P+ shield region, a source electrode, a trenched gate, a planar gate, a P+ contact region, an N+ contact region, a P-body region, and a drain.

[0004] However, during actual implementation, the inventors discovered that the aforementioned silicon carbide device, due to the use of a planar channel, has a low electron mobility in the channel after being turned on, thereby increasing the resistance of the channel portion. Summary of the Invention

[0005] In view of the above problems existing in the prior art, a silicon carbide device with a vertical channel is provided; on the other hand, a preparation method suitable for the silicon carbide device is also provided.

[0006] The specific technical solutions are as follows:

[0007] A silicon carbide device having a vertical channel, comprising:

[0008] a substrate having a first doping type;

[0009] an epitaxial layer, the epitaxial layer being formed above the substrate, the epitaxial layer having the first doping type;

[0010] a pair of well regions, the well regions being buried in the epitaxial layer, the well regions having a second doping type;

[0011] a pair of first trenches, wherein the first trenches are formed in the epitaxial layer, and the bottoms of the first trenches reach the well region;

[0012] a gate oxide layer formed above the epitaxial layer and extending along the sidewalls of the first trench to above the well region;

[0013] a polysilicon layer, wherein the polysilicon layer is formed above the gate oxide layer and extends along the sidewalls of the first trench to the bottom of the first trench;

[0014] an interlayer dielectric layer, the interlayer dielectric layer being formed above the epitaxial layer and the polysilicon layer;

[0015] a pair of first contact holes, wherein the first contact holes are formed above the first trench and pass through the interlayer dielectric layer to reach the well region;

[0016] A second contact hole is formed in the interlayer dielectric layer and reaches the polysilicon layer, and the second contact hole is located in a region between the first trenches.

[0017] Preferably, the silicon carbide device further includes:

[0018] a junction region formed in the epitaxial layer and distributed on both sides of the well region;

[0019] A transport layer is formed in the epitaxial layer and covers the junction region.

[0020] Preferably, the silicon carbide device further includes:

[0021] a well region contact region, wherein the well region contact region is formed in the well region and is located below the first contact hole;

[0022] A source region is formed at the bottom of the first trench.

[0023] Preferably, the first contact hole and the second contact hole are filled with a metal dielectric;

[0024] The silicon carbide device further includes:

[0025] a pair of first metal layers, wherein the first metal layers are formed above the first contact holes;

[0026] a second metal layer formed above the second contact hole;

[0027] A third metal layer is formed below the substrate.

[0028] A method for preparing a silicon carbide device, used to implement the above-mentioned silicon carbide device, comprising:

[0029] Step S1: forming an epitaxial layer on a substrate;

[0030] Step S2: forming a well region in the epitaxial layer and etching a first trench;

[0031] Step S3: sequentially preparing a gate oxide layer and a polysilicon layer on the epitaxial layer;

[0032] Step S4: forming an interlayer dielectric layer and etching a first contact hole and a second contact hole;

[0033] Step S5: preparing and forming a first metal layer, a second metal layer and a third metal layer.

[0034] Preferably, the step S1 includes:

[0035] Step S11: performing epitaxial growth on the substrate to form the epitaxial layer;

[0036] Step S12: performing ion implantation on the epitaxial layer to form a junction region;

[0037] Step S13: performing ion implantation on the upper portion of the junction region to form a transport layer.

[0038] Preferably, step S2 includes:

[0039] Step S21: performing ion implantation in the epitaxial layer to form the well region;

[0040] Step S22: etching both sides of the epitaxial layer to form a pair of the first trenches;

[0041] Step S23: performing ion implantation at the bottom of the first trench to form a source region;

[0042] Step S24: performing ion implantation below the source region to form a well region contact region.

[0043] Preferably, step S3 includes:

[0044] Step S31: growing a gate oxide layer on the epitaxial layer;

[0045] Step S32: depositing polysilicon on the gate oxide layer to form a polysilicon intermediate layer;

[0046] Step S33: etching the area of ​​the polysilicon intermediate layer where the first contact hole is to be formed to form the polysilicon layer.

[0047] Preferably, step S4 includes:

[0048] Step S41: depositing the interlayer dielectric layer on the polysilicon layer;

[0049] Step S42: etching the interlayer dielectric layer at the center of the first trench and filling the layer with metal to form the first contact hole, and etching the interlayer dielectric layer at the center of the first trench and filling the layer with metal to form the second contact hole.

[0050] Preferably, step S5 includes:

[0051] Step S51: depositing metal on the interlayer dielectric layer, and then etching to retain the areas above the first contact hole and the second contact hole to form the first metal layer and the second metal layer;

[0052] Step S52: forming the third metal layer on the back side of the substrate.

[0053] The above technical solution has the following advantages or beneficial effects: by providing a first trench and extending the gate oxide layer and polysilicon layer along the sidewalls of the first trench into the well region, a vertical conductive channel with an <11-20> or <1-100> crystal orientation is formed within the first trench. This improves electron mobility and reduces on-resistance compared to conventional planar conductive channels. Furthermore, the well region at the bottom of the first trench shields the electric field during reverse blocking. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0055] Figure 1 is an overall schematic diagram of an embodiment of the present invention;

[0056] Figure 2 is a schematic diagram of another embodiment of the present invention;

[0057] Figure 3 Schematic diagram of the preparation method of an embodiment of the present invention;

[0058] Figure 4 This is a schematic diagram of the sub-steps of step S1 in an embodiment of the present invention;

[0059] Figure 5 Schematic diagram of the device in step S11 in an embodiment of the present invention;

[0060] Figure 6 Schematic diagram of the device in step S12 in an embodiment of the present invention;

[0061] Figure 7 Schematic diagram of the device in step S13 in an embodiment of the present invention;

[0062] Figure 8 This is a schematic diagram of the sub-steps of step S2 in an embodiment of the present invention;

[0063] Figure 9 Schematic diagram of the device in step S21 in an embodiment of the present invention;

[0064] Figure 10 Schematic diagram of the device in step S22 in an embodiment of the present invention;

[0065] Figure 11 Schematic diagram of the device in step S23 in an embodiment of the present invention;

[0066] Figure 12 Schematic diagram of the device in step S24 in an embodiment of the present invention;

[0067] Figure 13 This is a schematic diagram of sub-steps of step S3 in an embodiment of the present invention;

[0068] Figure 14 Schematic diagram of the device in step S31 in an embodiment of the present invention;

[0069] Figure 15 Schematic diagram of the device in step S32 in an embodiment of the present invention;

[0070] Figure 16 Schematic diagram of the device in step S33 in an embodiment of the present invention;

[0071] Figure 17 This is a schematic diagram of sub-steps of step S4 in an embodiment of the present invention;

[0072] Figure 18 Schematic diagram of the device in step S41 in an embodiment of the present invention;

[0073] Figure 19 Schematic diagram of the device in step S42 in an embodiment of the present invention;

[0074] Figure 20 This is a schematic diagram of sub-steps of step S5 in an embodiment of the present invention;

[0075] Figure 21 Schematic diagram of the device in step S51 in an embodiment of the present invention;

[0076] Figure 22 Schematic diagram of the device in step S52 in an embodiment of the present invention. DETAILED DESCRIPTION

[0077] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0078] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0079] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0080] The present invention comprises:

[0081] A silicon carbide device having a vertical channel, such as Figure 1 Shown, including:

[0082] a substrate A1, the substrate A1 having a first doping type;

[0083] Epitaxial layer A2, where the epitaxial layer A2 is formed on the substrate A1 and has a first doping type;

[0084] a pair of well regions A3, the well regions A3 being buried in the epitaxial layer and having a second doping type;

[0085] a pair of first trenches A4, wherein the first trenches A4 are formed in the epitaxial layer, and the bottoms of the first trenches A4 reach the well region A3;

[0086] A gate oxide layer A5 is formed on the epitaxial layer A2 and extends along the sidewall of the first trench A4 to above the well region A3;

[0087] A polysilicon layer A6 is formed on the gate oxide layer A5 and extends along the sidewalls of the first trench A4 to the bottom of the first trench A4;

[0088] An interlayer dielectric layer A7 is formed above the epitaxial layer A2 and the polysilicon layer A6;

[0089] A pair of first contact holes A81, the first contact holes A81 are formed above the first trench A4, and the first contact holes A81 pass through the interlayer dielectric layer A7 to reach the well region A3;

[0090] The second contact hole A82 is formed in the interlayer dielectric layer A7 and reaches the polysilicon layer A6. The second contact hole A82 is located in the area between the first trenches A4.

[0091] In a preferred embodiment, the first contact hole A81 and the second contact hole A82 are filled with a metal dielectric;

[0092] Silicon carbide devices also include:

[0093] a pair of first metal layers A91, wherein the first metal layer A91 is formed above the first contact hole A81;

[0094] A second metal layer A92, where the second metal layer A92 is formed above the second contact hole A82;

[0095] The third metal layer A93 is formed below the substrate A1.

[0096] Specifically, for the planar silicon carbide device in the prior art, during the conduction process <0001> The electron mobility of the channel with a relatively low crystal orientation is relatively low, which leads to a problem of high on-resistance of the device. In this embodiment, by burying the well region A3 in the epitaxial layer A2 and sequentially forming a gate oxide layer A5 and a polysilicon layer A6 on the sidewall of the first channel A4, the device is formed as follows when it is turned on. Figure 1 The arrow in the middle indicates the current. This current flows from the bottom of the device, passes through the third metal layer A93, substrate A1, epitaxial layer A2, and reaches the gate oxide layer A5 in the center of the device. It then flows laterally along the gate oxide layer A to the sidewall of the first trench A4, and then flows downward into the well region A3 before reaching the first contact hole A81. During this process, the current flows through the channel with the <11-20> crystal orientation. The electron surface mobility in this crystal orientation is much higher than that of ordinary planar silicon carbide devices. <0001> The surface mobility of the crystal direction is improved, so that the device has a smaller on-resistance than the prior art.

[0097] Furthermore, by burying the well region A3 into the epitaxial layer A2 during the device preparation process, when the device is reverse blocked, the bottom of the first contact hole A81 is surrounded by the well region A3, and the well region A3 achieves a shielding effect on the electric field, thereby reducing the electric field strength of the gate oxide layer A5 at the bottom of the first trench A4 in the blocking state.

[0098] During implementation, the above device can be implemented as several typical silicon carbide power devices, such as silicon carbide MOSFET, silicon carbide IGBT device, silicon carbide super junction device, etc. For example, when the device is an N-type silicon carbide MOSFET, the first doping type is N-type, the second doping type is P-type, the first metal layer A91 is used as the source, the second metal layer A92 is the gate, and the third metal layer A93 is the drain. When the device is turned on, the current direction is from the bottom of the device along the Figure 1The first metal layer A91 above the device is connected in the direction shown in FIG. When the device is a P-type silicon carbide MOSFET, the first doping type is P-type and the second doping type is N-type. When the device is an IGBT, the first metal layer A91 is the emitter and the third metal layer A93 is the collector, or vice versa. Any configuration can be used based on actual needs.

[0099] In a preferred embodiment, Figure 2 As shown, the silicon carbide device also includes:

[0100] A junction region B21 is formed in the epitaxial layer B2 and is distributed on both sides of the well region B3. The junction region B21 has a first doping type.

[0101] The transport layer B22 is formed in the epitaxial layer B2 and covers the junction region B21 . The transport layer B22 has a first doping type.

[0102] Specifically, for the planar silicon carbide device in the prior art, during the conduction process <0001> The electron mobility of the <11-20> crystal orientation channel is relatively low, which leads to the problem of high on-resistance of the device. In this embodiment, by forming a junction region B21 and a transport layer B22 on both sides of the well region B3, a relatively stable current is formed in the area between the first channel B4 on both sides through the junction region B21. Then, when approaching the gate oxide layer B5, the current moves laterally to the first trench B4 through the transport layer B22, realizing the conversion of the trench direction, so that the current can flow through the <11-20> crystal orientation channel and achieve higher electron mobility. Among them, the junction region B21 refers to the JFET region formed by ion implantation, and the transport layer refers to the CSL region formed by ion implantation.

[0103] In a preferred embodiment, the silicon carbide device further includes:

[0104] A well region contact region B32, where the well region contact region B32 is formed in the well region B3 and is located below the first contact hole;

[0105] The source region B31 is formed at the bottom of the first trench.

[0106] Specifically, for silicon carbide devices in the prior art, the electric field strength at the gate oxide is large in the reverse blocking state, resulting in a thinning of the depletion layer thickness and thus an inability to effectively block the device. In this embodiment, a well region B3 is provided at the bottom of the first trench B4, thereby achieving a better shielding effect on the electric field when the device is reverse blocked, thereby reducing the electric field strength of the gate oxide layer B5.

[0107] A method for preparing a silicon carbide device, for implementing the above-mentioned silicon carbide device, such as Figure 3 Shown, including:

[0108] Step S1: forming an epitaxial layer on a substrate;

[0109] Step S2: forming a well region in the epitaxial layer and etching a first trench;

[0110] Step S3: sequentially preparing a gate oxide layer and a polysilicon layer on the epitaxial layer;

[0111] Step S4: forming an interlayer dielectric layer and etching a first contact hole and a second contact hole;

[0112] Step S5: preparing and forming a first metal layer, a second metal layer and a third metal layer.

[0113] Specifically, for the planar silicon carbide device in the prior art, during the conduction process <0001> The electron mobility of the channel in the <11-20> crystal orientation is relatively low, which leads to the problem of high on-resistance of the device. In this embodiment, the well region is buried in the epitaxial layer and a first trench with the bottom reaching the well region is opened. Subsequently, when preparing the gate oxide layer and polysilicon layer, the gate oxide layer and the polysilicon layer are allowed to grow along the sidewalls of the first trench, thereby forming a channel in the <11-20> crystal orientation. The electron surface mobility of this crystal orientation is much higher than that of ordinary planar silicon carbide devices. <0001> The surface mobility of the crystal direction is improved, so that the device has a smaller on-resistance than the prior art.

[0114] Furthermore, by burying the well region into the epitaxial layer during the device preparation process, when the device is reverse blocked, the bottom of the first channel is surrounded by the well region, and the well region achieves a shielding effect on the electric field, thereby reducing the electric field strength of the gate oxide layer at the bottom of the first trench in the blocking state, achieving a better blocking effect.

[0115] In a preferred embodiment, Figure 4 As shown, step S1 includes:

[0116] Step S11: Figure 5 As shown, epitaxial growth is performed on the substrate C1 to form an epitaxial layer C2;

[0117] Step S12: Figure 6 As shown, ion implantation is performed on the epitaxial layer C2 to form a junction region C21;

[0118] Step S13: Figure 7 As shown, ion implantation is performed on the upper half of the junction region C21 to form a transport layer C22.

[0119] Specifically, for the planar silicon carbide device in the prior art, during the conduction process <0001> The electron mobility of the crystal-oriented channel is relatively low, which leads to the problem of high on-resistance of the device. In this embodiment, before preparing the well region C3, ion implantation is performed on the epitaxial layer C2 to form a junction region C21, thereby forming a relatively constant current when the device is turned on, and ion implantation is performed on the upper half of the junction region C21 to form a lateral transport layer C22, so that the current can more easily move to the vicinity of the lateral first channel C4 when approaching the gate oxide layer C5, thereby improving the overall electron mobility of the device.

[0120] In a preferred embodiment, Figure 8 As shown, step S2 includes:

[0121] Step S21: Figure 9 As shown, ion implantation is performed in the epitaxial layer C2 to form a well region C3;

[0122] Step S22: Figure 10 As shown, both sides of the epitaxial layer C2 are etched to form a pair of first trenches C4;

[0123] Step S23: Figure 11 As shown, ion implantation is performed at the bottom of the first trench C4 to form a source region C31;

[0124] Step S24: Figure 12 As shown, ion implantation is performed below the source region C31 to form a well region contact region C32.

[0125] Specifically, with respect to silicon carbide devices in the prior art, the electric field strength at the gate oxide is relatively large in the reverse blocking state, resulting in a thinning of the depletion layer thickness and thus an inability to effectively block the device. In this embodiment, a well region is provided at the bottom of the first trench C4, so that a better electric field shielding effect is achieved at the bottom of the first trench C4.

[0126] In practice, the above process can be performed by depositing a hard mask on the device, defining the pattern using a photoresist, and forming the well region C3 through ion implantation. Subsequently, the hard mask is removed, and the location of the first trench C4 is re-deposited and defined. A first trench C4 is formed to a depth reaching the well region C3 through trench etching. Subsequently, ion implantation (NPS) is performed in the first trench C4 to form the source region C31. After the source region C31 is formed, a hard mask is deposited, the pattern is defined using a photoresist, and ion implantation (PPS) is performed to form the well region contact region C32.

[0127] In a preferred embodiment, Figure 13 As shown, step S3 includes:

[0128] Step S31: Figure 14 As shown, a gate oxide layer C5 is grown above the epitaxial layer C2 and on the sidewalls of the first trench C4;

[0129] Step S32: Figure 15 As shown, polysilicon is deposited on the gate oxide layer C5 to form a polysilicon intermediate layer C61;

[0130] Step S33: Figure 16 As shown, the area on the polysilicon intermediate layer C61 where the first contact hole C81 is to be formed is etched to form a polysilicon layer C6.

[0131] Specifically, to achieve better device fabrication results, in this embodiment, a gate oxide layer C5 is generated by thermally oxidizing the epitaxial layer C2 and the sidewalls of the first trench C4, and then polysilicon is deposited and etched to form a polysilicon layer C6.

[0132] In a preferred embodiment, Figure 17 As shown, step S4 includes:

[0133] Step S41: Figure 18 As shown, an interlayer dielectric layer C7 is deposited on the polysilicon layer C6;

[0134] Step S42: Figure 19 As shown, the interlayer dielectric layer C7 is etched and filled with metal at the center of the first trench C4 to form a first contact hole C81, and the interlayer dielectric layer C7 is etched and filled with metal at the center to form a second contact hole C82.

[0135] In a preferred embodiment, Figure 20 As shown, step S5 includes:

[0136] Step S51: Figure 21 As shown, metal is deposited on the interlayer dielectric layer C7, and then etched to retain the area above the first contact hole C81 and the second contact hole C82 to form a first metal layer C91 and a second metal layer C92;

[0137] Step S52: Figure 22 As shown, a third metal layer C93 is formed on the back side of the substrate C1.

[0138] Specifically, in order to achieve better preparation effects, in this embodiment, metal is deposited on the interlayer dielectric layer C7 to form a continuous metal layer, and then the excess metal area is removed by etching, and the first metal layer C91 and the second metal layer C92 are disconnected, thereby completing the preparation of the lead-out electrode on the front side of the device. Subsequently, the device is flipped over, the substrate C1 on the back side is thinned and flattened, and metal is evaporated or deposited, thereby forming a third metal layer C93.

[0139] The present invention has the beneficial effect of providing a first trench and extending the gate oxide layer and polysilicon layer along the sidewalls of the first trench to the well region, thereby forming a vertical conductive channel with an <11-20> or <1-100> crystal orientation within the first trench. This improves electron mobility and reduces on-resistance compared to conventional planar conductive channels. Furthermore, the well region at the bottom of the first trench shields the electric field during reverse blocking.

[0140] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A silicon carbide device having a vertical channel, characterized in that: include: a substrate having a first doping type; an epitaxial layer, the epitaxial layer being formed above the substrate, the epitaxial layer having the first doping type; a pair of well regions, the well regions being buried in the epitaxial layer, the well regions having a second doping type; a pair of first trenches, wherein the first trenches are formed in the epitaxial layer, and the bottoms of the first trenches reach the well region; a gate oxide layer formed above the epitaxial layer and extending along the sidewalls of the first trench to above the well region; a polysilicon layer, wherein the polysilicon layer is formed above the gate oxide layer and extends along the sidewalls of the first trench to the bottom of the first trench; an interlayer dielectric layer, the interlayer dielectric layer being formed above the epitaxial layer and the polysilicon layer; a pair of first contact holes, wherein the first contact holes are formed above the first trench and pass through the interlayer dielectric layer to reach the well region; a second contact hole formed in the interlayer dielectric layer and reaching the polysilicon layer, the second contact hole being located in a region between the first trenches; The first contact hole and the second contact hole are filled with a metal dielectric; The silicon carbide device further includes: a pair of first metal layers, wherein the first metal layers are formed above the first contact holes; a second metal layer formed above the second contact hole; a third metal layer formed below the substrate; A source region is formed at the bottom of the first trench.

2. The silicon carbide device according to claim 1, characterized in that The silicon carbide device further includes: a junction region formed in the epitaxial layer and distributed on both sides of the well region, the junction region having a first doping type; The transport layer is formed in the epitaxial layer and covers the junction region, and has a first doping type.

3. The silicon carbide device according to claim 1, wherein The silicon carbide device further includes: a well region contact region, wherein the well region contact region is formed in the well region and is located below the first contact hole; A source region is formed at the bottom of the first trench.

4. A method for preparing a silicon carbide device, characterized in that: A silicon carbide device for implementing any one of claims 1 to 3, comprising: Step S1: forming an epitaxial layer on a substrate; Step S2: forming a well region in the epitaxial layer and etching a first trench; Step S3: sequentially preparing a gate oxide layer and a polysilicon layer on the epitaxial layer; Step S4: forming an interlayer dielectric layer and etching a first contact hole and a second contact hole; Step S5: preparing and forming a first metal layer, a second metal layer and a third metal layer.

5. The preparation method according to claim 4, characterized in that The step S1 comprises: Step S11: performing epitaxial growth on the substrate to form the epitaxial layer; Step S12: performing ion implantation on the epitaxial layer to form a junction region; Step S13: performing ion implantation on the upper portion of the junction region to form a transport layer.

6. The preparation method according to claim 4, characterized in that The step S2 comprises: Step S21: performing ion implantation in the epitaxial layer to form the well region; Step S22: etching both sides of the epitaxial layer to form a pair of the first trenches; Step S23: performing ion implantation at the bottom of the first trench to form a source region; Step S24: performing ion implantation below the source region to form a well region contact region.

7. The preparation method according to claim 4, characterized in that The step S3 comprises: Step S31: growing a gate oxide layer on the epitaxial layer; Step S32: depositing polysilicon on the gate oxide layer to form a polysilicon intermediate layer; Step S33: etching the area of ​​the polysilicon intermediate layer where the first contact hole is to be formed to form the polysilicon layer.

8. The preparation method according to claim 4, characterized in that The step S4 comprises: Step S41: depositing the interlayer dielectric layer on the polysilicon layer; Step S42: etching the interlayer dielectric layer at the center of the first trench and filling the layer with metal to form the first contact hole, and etching the interlayer dielectric layer at the center of the first trench and filling the layer with metal to form the second contact hole.

9. The preparation method according to claim 4, characterized in that The step S5 comprises: Step S51: depositing metal on the interlayer dielectric layer, and then etching to retain the areas above the first contact hole and the second contact hole to form the first metal layer and the second metal layer; Step S52: forming the third metal layer on the back side of the substrate.

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