Systems and methods for packaging acoustic devices included in integrated circuits (ICs).

Abstract

A system and method for encapsulating an acoustic device (408A) in an integrated circuit (400) includes: a wall formed on a wiring substrate (504). The height of the wall (405) is just shorter than the expected height of the solder bumps (504) on the acoustic device after solder reflow. The wall is positioned on either side of the acoustic device and a small portion is located below the outer edge of the acoustic device, such that a relatively small gap (516) is formed between the upper surface of the wall and the lower surface of the acoustic device. By providing a small gap between the wall and the acoustic device, the intrusion of the encapsulation material (518) into the forbidden area (520) of the acoustic device is minimized.

Description

[0001] Priority requirements

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 005,760, filed April 6, 2020, entitled “SYSTEMS AND METHODS FOR PACKAGINGAN ACOUSTIC DEVICE IN AN INTEGRATED CIRCUIT (IC),” the entire contents of which are incorporated herein by reference.

[0003] This application also claims priority to U.S. Patent Application Serial No. 17 / 007,454, filed August 31, 2020, entitled “SYSTEMS AND METHODS FORPACKAGING AN ACOUSTIC DEVICE IN AN INTEGRATED CIRCUIT (IC),” the entire contents of which are incorporated herein by reference. Technical Field

[0004] The technology disclosed herein generally relates to encapsulated integrated circuits (ICs), and more specifically, to ICs encapsulated therein having acoustic devices. Background Technology

[0005] Most mobile communication devices comprise a radio frequency (RF) front-end consisting of multiple integrated circuits (ICs). These ICs can have different functions, such as amplifiers, filters, duplexers, antenna combiners, etc. Duplexers and antenna combiners are particularly used to operate in different frequency bands or to separate transmitted and received signals. One of the most effective devices for separating signals at the frequency of interest is acoustic wave devices, such as surface acoustic wave (SAW) devices. Acoustic devices are often fragile, thus requiring constant improvement in their packaging choices. Summary of the Invention

[0006] The aspects disclosed in the detailed description include systems and methods for packaging acoustic devices within an integrated circuit (IC). In an exemplary aspect, an IC including an IC chip is provided, the IC chip including an acoustic device. The IC is coupled to a wiring substrate to provide connectivity with the IC chip and its acoustic device. For example, the acoustic device can be used as a filter. The IC chip is packaged. In an exemplary aspect, the IC chip includes a wall formed on the wiring substrate. The height of the wall is shorter than the expected height of solder bumps on the acoustic device after solder reflow. The wall is positioned on either side of the acoustic device and a small portion is located below the outer edge of the acoustic device, such that a relatively small gap is formed between the upper surface of the wall and the lower surface of the acoustic device. By providing a small gap between the wall and the acoustic device, the intrusion of the packaging material into the forbidden area of ​​the acoustic device is minimized. This reduction in intrusion allows more area within the acoustic device to be used for the acoustic element, which reduces the overall size of the acoustic device.

[0007] In this regard, on one hand, an IC is disclosed. The IC includes an IC chip. The IC also includes a wall positioned on a substrate, the wall being at least partially below the IC chip. The IC also includes a gap formed between the wall and the IC chip.

[0008] In another aspect, a method for forming an IC is disclosed. The method includes forming a wall on a wiring substrate. The method also includes bonding an IC chip containing acoustic wave devices to the wiring substrate such that a gap is maintained between the lower surface of the IC chip and the upper surface of the wall.

[0009] In another aspect, an IC is disclosed. The IC includes a metallized structure having a first surface and an outer edge. The IC also includes a chip containing acoustic devices, the chip having a second surface. The IC further includes at least one solder bump extending from the first surface of the metallized structure to the second surface of the chip, the at least one solder bump having a first height. The IC also includes at least one wall extending upward from the first surface of the metallized structure, the at least one wall having a second height shorter than the first height and closer to the outer edge than the solder bump. The wall is at least partially located between the second surface and the first surface and maintains a gap between the at least one wall and the second surface. The IC also includes an encapsulation material surrounding the chip and tangentially coupled to at least a portion of the first surface of the metallized structure. Attached Figure Description

[0010] Figure 1 It is a top view of a stylized diagram of a conventional integrated circuit (IC) having acoustic devices positioned on a metallized structure (such as a wiring substrate).

[0011] Figure 2 It is along Figure 1 The line 2-2 cut Figure 1 A cross-sectional side view of the IC;

[0012] Figure 3 It is along Figure 1 The line 3-3 was cut off Figure 1 Another cross-sectional side view of the IC;

[0013] Figure 4 This is a top view of a stylized diagram of an IC having acoustic devices positioned on a wiring substrate with a wall in use, according to an exemplary aspect of this disclosure.

[0014] Figure 5 It is along Figure 4 The line cut from 5-5 Figure 4 A cross-sectional side view of the IC;

[0015] Figure 6 This is an explanation of what is used to form Figure 4 A flowchart illustrating an exemplary process of an IC;

[0016] Figures 7A-7E It shows in Figure 6 Different stages of the process according to Figure 6 ICs formed using advanced technology;

[0017] Figure 8 It is similar to Figure 4 A cross-sectional side view of an alternative exemplary aspect of an IC, but with an intermediate support wall;

[0018] Figure 9 It is similar to Figure 4 A cross-sectional side view of an alternative exemplary aspect of an IC, but with two layers of encapsulation material;

[0019] Figure 10 It is similar to Figure 4 A cross-sectional side view of an alternative exemplary aspect of an IC that has a smaller lateral dimension compared to the wall to facilitate cutting the IC during manufacturing;

[0020] Figure 11 It is similar to Figure 7E But has Figure 10 The IC is shown in the cross-sectional side view to illustrate how the cutting is facilitated;

[0021] Figure 12 It is similar to Figure 4 A cross-sectional side view of an alternative exemplary aspect of an IC, but with an L-shaped wall;

[0022] Figure 13 This is a block diagram of an exemplary processor-based system, which may include systems having, for example, processor-based systems. Figure 4 and Figure 8-12 ICs for acoustic devices;

[0023] Figure 14This is a block diagram of a wireless transceiver, which may include features such as Figure 4 and Figure 8-12 ICs for acoustic devices;

[0024] Figure 15 This is a block diagram of an exemplary mobile terminal having a radio frequency (RF) front-end, which may include having, for example, Figure 4 and Figure 8-12 ICs for acoustic devices. Detailed Implementation

[0025] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “as an example, instance, or illustration.” Any aspect described herein as “exemplary” should not be construed as being preferred or superior to the other aspects.

[0026] The aspects disclosed in the detailed description include systems and methods for packaging acoustic devices in an integrated circuit (IC). In an exemplary aspect, an IC including an IC chip is provided, the IC chip including an acoustic device. The IC is coupled to a wiring substrate to provide connectivity with the IC chip and its acoustic device. For example, the acoustic device can be used as a filter. The IC chip is encapsulated. In an exemplary aspect, the IC chip includes a wall formed on the wiring substrate. The height of the wall is shorter than the expected height of the solder bumps on the acoustic device after solder reflow. The wall is positioned on either side of the acoustic device and a small portion is located below the outer edge of the acoustic device, such that a relatively small gap is formed between the upper surface of the wall and the lower surface of the acoustic device. By providing a small gap between the wall and the acoustic device, the intrusion of the encapsulation material into the prohibited areas of the acoustic device is minimized. The reduction in intrusion allows more area within the acoustic device to be used for the acoustic element, which reduces the overall size of the acoustic device.

[0027] Before describing exemplary aspects of this disclosure, refer to Figures 1-3 An overview of conventional ICs with acoustic devices is provided to allow for a comparison of the advantages of such conventional devices with those of this disclosure. References are made below. Figure 4 Let's begin by discussing exemplary aspects of acoustic devices in ICs.

[0028] In this respect, Figure 1This is a top view of a conventional IC 100, which has an IC chip 102 positioned on a wiring substrate 104 as a metallized structure. The wiring substrate 104 may include conductors in the form of metal traces extending in a plurality of planes defined by the X and Y axes shown. The IC chip 102 includes an acoustic device 106 having acoustic wave elements 108A-108D, as is well known. The acoustic device 106 may be a surface acoustic wave (SAW) device, a temperature compensated surface acoustic wave (TC-SAW) device, a thin-film bulk acoustic resonator (FBAR), a bulk acoustic wave (BAW) device, and a thin-film surface acoustic wave (TF-SAW) device. In this context, the device type may be a filter, a duplexer, a multiplexer, an extractor, or other radio frequency front-end (RFFE) product that includes at least one acoustic element.

[0029] IC chip 102 may be a flip-chip device connected to wiring substrate 104 via interconnects 110A-110D. IC chip 102 may also have a forbidden region 112 (the space between the solid and dashed lines of IC chip 102) within IC chip 102, but without acoustic elements 108. As the name suggests, a forbidden region is an area within or near a processor or device (in this case, an acoustic device) that cannot be used in the board layout design due to thermal management components, cooling, mounting constraints, and / or operational constraints. For acoustic devices, the forbidden region is an area that needs to be avoided to prevent altering the performance characteristics of the acoustic element (e.g., this might change the center frequency of an acoustic filter).

[0030] IC chip 102 can be manufactured in wafer form and then monolithically processed into a chip, and may include a piezoelectric substrate, such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). Alternatively, IC chip 102 can be made of silicon or a silicon-based substrate with a piezoelectric material such as aluminum nitride (AlN) deposited on top. Another alternative would be a composite wafer, such as bonded LiTaO3-Si or bonded LiTaO3-sapphire.

[0031] The wiring substrate 104 can be configured as a printed circuit board (PCB, not shown) for connecting the acoustic device 106 to a computing device, and can include multiple metal layers, inductors, and / or capacitors (not shown). The wiring substrate 104 can be made of ceramic materials such as high-temperature co-fired ceramic (HTCC) or low-temperature co-fired ceramic (LTCC), organic materials such as FR4, Roger, or liquid crystal polymer (LCP), or molded substrates such as molded lead frames. Figure 2 and Figure 3 As can be seen more clearly, the wiring substrate 104 can have a thickness of about 80 to 500 micrometers (μm) 104T.

[0032] As a noun-related note, "about" as used in this paper is defined as meaning within three percent (3%) of the basic range or number. Therefore, about 80 to 500 μm covers 77.6–515 μm.

[0033] Acoustic wave elements 108A-108D are functional components of acoustic device 106 and may be, for example, interdigital transducers in a SAW device or piezoelectric material sandwiched between the top and bottom electrodes in a BAW device. Acoustic wave elements 108A-108D may sometimes be referred to as active elements and are typically arranged on the side of IC chip 102 that is parallel to and faces the wiring substrate 104. That is, the side of IC chip 102 closest to the wiring substrate 104 on the Z-axis.

[0034] Interconnects 110A-110D can be made of solder materials (such as lead-free solder bumps) produced by solder paste printing, solder ball mounting, or electroplating. Alternatively, interconnects 110A-110D can be made of gold (Au) column bumps or copper (Cu) column bumps.

[0035] The forbidden region 112 in a typical IC 100 can be approximately 35 to 60 μm. If something impacts this forbidden region 112, the performance of the acoustic device 106 may be negatively affected. The consequences will be discussed in more detail below.

[0036] Figure 2 It is along Figure 1 The line 2-2 cut Figure 1 A cross-sectional side view of IC 100. As described above, the IC chip 102 is interconnected with the wiring substrate 104 at a height 114 (as defined on the Z-axis). To protect the acoustic wave components 108A-108D from environmental factors such as particles, humidity, and impact, an encapsulation material 116 is provided to surround (encapsulate) the IC chip 102 and rigidly connect the IC chip 102 to the wiring substrate 104. In particular, a cavity 118 is formed between the IC chip 102 and the wiring substrate 104, and any external environmental factors are sealed by the encapsulation material 116.

[0037] The encapsulation material 116 may be made of an epoxy resin-based material, which may contain fillers such as silica. When the encapsulation material 116 is applied to cover the IC chip 102, certain portions of the encapsulation material 116 may creep beneath the IC chip 102, such as... Figure 3 A better view.

[0038] Figure 3 It is along Figure 1 The line 3-3 was cut off Figure 1A cross-sectional side view of IC 100. As described above, when encapsulation material 116 is applied to cover IC chip 102, some portions of encapsulation material 116 may creep distances 120A and 120B (along the Y-axis) below IC chip 102 (on the Z-axis). That is, during the application of encapsulation material 116 to IC chip 102, encapsulation material 116 slowly flows into (“creeps”) the space below IC chip 102. The resulting material located below IC chip 102 may be referred to as intrusion or “creep”. Distances 120A and 120B may exceed the width (W) of the forbidden zone 112 and respectively contact acoustic element 108 such as element 108C for some portions 122A or 122B. This physical contact of encapsulation material 116 on acoustic element 108C alters the physical properties of the wave propagating on acoustic element 108C and thus alters (and may degrade) the performance of acoustic device 106.

[0039] Typically, creep or intrusion of the encapsulation material 116 beneath IC chip 102 has been addressed by enlarging the forbidden zone 112, which increases the overall size of IC chip 102 and, consequently, the size of IC 100. Generally, this size increase is commercially impractical due to industry pressure to reduce the size of any given IC, and especially the RFFE IC in which IC chip 102 is located. Alternatively, the height 114 of the gap between IC chip 102 and wiring substrate 104 can be reduced by using gold bumps for interconnects 110A-110D. A smaller gap means less encapsulation material 116 can flow into the gap before curing, resulting in less intrusion or creep. While gold bumps can provide the same electrical connectivity characteristics while being shorter than solder bumps or copper pillars, gold is expensive and more difficult to manufacture. Therefore, gold is not the optimal solution to the intrusion problem. Another solution is to use a shrink-pack polymer film that seals cavity 118 with the encapsulation material. However, the polymer film may stretch when the encapsulation material 116 is applied, leading to some intrusion. Furthermore, the difficulty in controlling the amount of stretching leads to uneven creep. When planning the forbidden zone 112, this uneven creep requires worst-case assumptions, which again leads to an increase in the size of the IC chip 102.

[0040] As follows Figure 4To begin discussing in more detail, an exemplary aspect of this disclosure reduces or eliminates the intrusion of encapsulation material beneath the IC chip by introducing a wall on top of the IC's wiring substrate. This wall is shorter than the height of the interconnects such that even if the wall extends from an area just inside the outer edge of the chip to a position extending outwards from below the chip, the wall does not contact the lower surface of the chip. The remaining gap between the lower surface of the chip and the top surface of the wall is sufficient to prevent the wall from affecting the physical properties of the wave components, but also close enough to prevent significant creep or intrusion of the encapsulation material beneath the chip.

[0041] in this regard, Figure 4 This is a top view of a stylized diagram of an IC 400 containing an IC chip, referred to herein as chip 402. Chip 402 (on the Z-axis) is positioned on a metallized structure (such as a wiring substrate 404) used in… Figure 4 Wall 405 is shown as a crosshair and is referenced below. Figure 5 A more detailed explanation is needed. Specifically, IC 400 is similar to... Figures 1-3 IC 100, wherein chip 402 includes an acoustic device 406 having acoustic wave elements 408A-408D. Although four acoustic wave elements 408A-408D are shown, it should be understood that more or fewer acoustic wave elements may be present, and the precise number is not the focus of this disclosure. Chip 402 may be a flip-chip device connected to wiring substrate 404 via interconnects 410A-410D. Although four interconnects 410A-410D are shown, it should be understood that more or fewer interconnects may be present, and the precise number is not the focus of this disclosure. Chip 402 may also have a forbidden region 412 (the space between the solid and dashed lines of chip 402) (in the plane formed by the X and Y axes), i.e., within chip 402, but without acoustic wave elements 408.

[0042] It should be understood that acoustic elements 408A-408D are structurally and functionally similar to acoustic device 106 and can be SAW devices, TC-SAW devices, FBARs, BAW devices, and TF-SAW devices. It should also be understood that such acoustic devices are formed by mechanical elements that operate or vibrate within a cavity. In this context, the type of device can be a filter, duplexer, multiplexer, extractor, or other RFFE product including at least one acoustic element.

[0043] Chip 402 can be manufactured in wafer form and then diced into individual chips and may include a piezoelectric substrate (such as LiTaO3 or LiNbO3). Alternatively, the chip can be made from a silicon or silicon-based substrate on which a piezoelectric material such as AlN is deposited on top. Another alternative is a composite wafer, such as bonded LiTaO3-Si or bonded LiTaO3-sapphire.

[0044] Wiring substrate 404 can be configured as a printed circuit board (PCB, not shown) for connecting acoustic device 406 to computing device, and can include multiple metal layers, inductors, and / or capacitors (not shown). Wiring substrate 404 can be made of ceramic materials (such as HTCC or LTCC), organic materials (such as FR4, Roger, or liquid crystal polymer (LCP)), or molded substrates (such as molded leadframes). Figure 5 As can be seen more clearly, the wiring substrate 404 can have a thickness of about 80 to 500 μm.

[0045] Acoustic device 406 can be a SAW device, TC-SAW device, FBAR, BAW device, and TF-SAW device. In this context, the type of device can be a filter, duplexer, multiplexer, extractor, or other RFFE product that includes at least one acoustic element.

[0046] Acoustic wave elements 408A-408D are functional components of acoustic device 406 and may be, for example, interdigital transducers in a SAW device or piezoelectric material sandwiched between the top and bottom electrodes in a BAW device. Acoustic wave elements 408A-408D may sometimes be referred to as active elements and are typically arranged on the side of chip 402 facing the wiring substrate 404.

[0047] Figure 5 It is along Figure 5 The line cut from 5-5 Figure 4A cross-sectional side view of IC 400 is shown, and the wall 405 according to this disclosure is better illustrated. By design, wall 405 has a uniform cross-section and surrounds chip 402 laterally outward from a point just inside the outer edge 502 of chip 402 to the outer edge 504 of wiring substrate 404, wherein the lateral direction is indicated by arrow 506. The amount of lateral overlap between wall 405 and chip 402 is indicated by arrow 508. It should be understood that this overlap is less than ten percent of the forbidden area 412. Wall 405 may have a height 510 (on the Z-axis) extending upward from the upper surface 512 of wiring substrate 404. Similarly, interconnect 410 may have a height 514 (on the Z-axis) extending upward from the upper surface 512 of wiring substrate 404. A gap 516 is maintained between wall 405 and chip 402 by keeping the height 510 of wall 405 shorter than the height 514 of interconnect 410. In an exemplary aspect, height 510 is between approximately twenty (20) μm and thirty (30) μm, and height 514 is between approximately thirty (30) μm and fifty (50) μm. In an exemplary aspect, gap 516 has a height between one (1) μm and twenty-one (21) μm, which is small enough to reduce and / or eliminate creep from encapsulation material 518 beneath chip 402. In the presence of encapsulation material 518, cavity 520 beneath chip 402 is sealed. In a particularly considered aspect, gap 516 has a height of eleven (11) μm. By reducing creep or intrusion of encapsulation material 518, acoustic element 408 can be placed closer to the outer edge 502 of chip 402. The use of expensive gold column bumps is also avoided.

[0048] In an exemplary aspect, wall 405 may be made of a polymer or epoxy-based material (such as solder resist or permanent photoresist). Alternatively, wall 405 may be made of a ceramic material (such as HTCC or LTCC) to match the corresponding material of wiring substrate 404 (e.g., if wiring substrate 404 is HTCC material, then wall 405 may also be made of HTCC material).

[0049] Figure 6 It shows the method used to form Figure 4 A flowchart of an exemplary process 600 for IC 400, see reference. Figures 7A-7E This illustrates the work being carried out in the intermediate manufacturing steps of process 600. In this respect, process 600 begins in a branching manner with the fabrication of wiring substrate 404 (block 604) and the relatively simultaneous fabrication of chip 402 (block 602). As is conventional, the fabrication of chip 402 can be broken down into the fabrication of acoustic wave element 408 on the wafer by photolithography and passivation (block 602A). Next, as is conventional, bumps or interconnects 410 are formed on the wafer (block 602B). The wafer is then diced into individual chips 402 (block 602C), such as by dicing.

[0050] Continue to refer to Figure 6 Essentially simultaneously, the fabrication of wiring substrate 402 begins with wiring substrate 700, which has layer 702 and a metal layer 704 (block 604A, see also) sandwiched therebetween. Figure 7A As described, this can be a laminate of ceramic or other materials. Wall 405 is then manufactured (block 604B, see also...). Figure 7B This process forms the intermediate structure 710, which can be accomplished by laminating a dry film solder resist followed by a patterning step. Wall 405 can have a uniform cross-section and surrounds chip 402. Height 510 is carefully controlled to the desired height, taking into account the height 514 of the solder bumps.

[0051] As used herein, "simultaneously" essentially means that both block 602 and block 604 are completed (possibly asynchronously) before block 606 can begin. There are no strict requirements that chip 402 and wiring substrate 404 be manufactured in the same location, at the same time, or on the same day. The only requirement is that both steps be completed before block 606 can begin.

[0052] Continue to refer to Figure 6 Then the chip 402 is bonded to the wiring substrate 404 with walls 405 (i.e., intermediate structure 710) (block 606, see also) Figure 7C This forms the intermediate structure 720. Chip 402 can be used as a flip chip via a pick-and-place machine. Bonding can be accomplished via flip chip bonding and reflow soldering.

[0053] Then, the intermediate structure 720 (block 608, see also encapsulation material 518) is encapsulated with encapsulation material 518 (sometimes called encapsulation material). Figure 7D This encapsulation forms an intermediate structure 730. A cavity 520 is formed. A gap 516 is maintained between the wall 405 and the chip 402.

[0054] Then, the encapsulated substrate is cut into individual IC 400s (block 610, see also) Figure 7E IC 400 can be formed, for example, by cutting with a cutting blade 740. IC 400 can then be further tested and packaged (block 612). While many of the steps are known, the use of wall 405 provides a difference in the intrusion of the encapsulation material 518 and prevents or reduces performance degradation of the acoustic device.

[0055] Although IC 400 is sufficient in most respects, there are references Figures 8-12 Alternative exemplary aspects of this disclosure are described.

[0056] Figure 8 It is similar to Figure 4A cross-sectional side view of an alternative exemplary aspect of IC 800, but with an intermediate support wall 802 formed in cavity 520. In most other respects, IC 800 is identical to IC 400, and the reference numerals of comparable components are the same. The intermediate support wall 802 may be disposed directly below the acoustic wave element 408, but maintaining gap 516. The intermediate support wall 802 can serve as a secondary heat sink for the heat generated by the acoustic wave element 408. Furthermore, the intermediate support wall 802 can aid in the manufacturing process by preventing excessive bending of the chip 402 during pick-and-place activities. Note that the use of the intermediate wall structure 802 is optional.

[0057] Figure 9 It is similar to Figure 4 A cross-sectional side view of an alternative exemplary aspect of an IC 900 having two encapsulation layers is provided. Specifically, a top layer 902 may be disposed above a bottom layer 904 (relative to the Z-axis). Both layers 902 and 904 may be epoxy-based materials and may be filled with fillers (such as silica). Compared to the bottom layer 904, the top layer 902 may have a relatively lower storage modulus at low temperatures, allowing for a more uniform distribution of the top layer 902 across the entire wiring substrate 404 during the encapsulation process (e.g., block 608), resulting in a more uniform height of the IC 900. The bottom layer 904 may have good elongation properties to reduce creep in the cavity 520. In other respects, the IC 900 is identical to the IC 400.

[0058] Figure 10 This is a cross-sectional side view of an alternative exemplary aspect of IC 1000, which is similar to... Figure 4 The IC 400, however, has a smaller lateral (as shown on the Y-axis) dimension for wall 1002 in order to facilitate... Figure 11 The IC 1000 is shown being cut during manufacturing. Specifically, the wall 1002 is internally spaced from the outer edge 1004 of the wiring substrate 404 to form a break 1100 in the intermediate structure 1102 (see [reference]). Figure 11 This allows the cutting blade 1104 to cut through the fracture 1100, reducing the need to cut through the relatively hard material of the wall 1002 and thus reducing the wear rate of the cutting blade 1104. The encapsulating material 1006 is shown as... Figure 9 Similar to the two-layer IC 900, it should be understood that the smaller wall 1002 can also be used with a single-layer encapsulation material.

[0059] Figure 12 It is similar to Figure 4A cross-sectional side view of IC 1200, but with an alternative exemplary aspect of IC 400, including L-shaped wall 1202. In IC 1200, the relevant portion of wall 1202 remains relatively short and is below chip 402, and has the previously described gap 516, but gap 516 has been established, and some portions of wall 1202 are higher than the lower surface of chip 402. This structure offers no known advantage over wall 405, but it is included for completeness.

[0060] Systems and methods for packaging acoustic devices in an IC according to the aspects disclosed herein can be disposed in or integrated into any processor-based device. Examples, but not limited to, include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0061] in this regard, Figure 13 An example of a processor-based system 1300 is shown, which can employ a processor-based system 1300. Figure 4 and Figures 8-12 The IC of the acoustic device is shown in the figure. In this example, the processor-based system 1300 includes one or more central processing units (CPUs) 1302, each CPU including one or more processors 1304. The CPUs 1302 may have cache memory 1306 coupled to the processors(s)1304 for fast access to temporarily stored data. The CPUs(s)1302 are coupled to a system bus 1308 and can couple master and slave devices included in the processor-based system 1300 to each other. As is known, the CPUs(s)1302 communicate with these other devices on the system bus 1308 by exchanging address, control, and data information. For example, the CPUs(s)1302 may transmit bus transaction requests to a memory controller 1310, which is an example of a slave device.

[0062] Other master and slave devices can be connected to system 1308. For example... Figure 13As shown, by way of example, these devices may include a memory system 1312, one or more input devices 1314, one or more output devices 1316, one or more network interfaces 1318, and one or more display controllers 1320. The input devices 1314 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 1316 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface devices 1318 may be any device configured to allow the exchange of data to and from network 1322. In an exemplary aspect, some of the network interface devices 1318 may include... Figure 4 and / or Figures 8-12 The IC. Network 1322 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetooth networks. TM Networks and the Internet. Multiple network interface devices 1318 can be configured to support any type of communication protocol required. The memory system 1312 may include one or more memory cells 1324 (0-N).

[0063] The CPUs 1302 can also be configured to access the display controllers 1320 via the system bus 1308 to control information sent to one or more displays 1326. The display controllers 1320 send information to the displays 1326 for display via one or more video processors 1328, which process the information to be displayed into a format suitable for the displays 1326. The displays 1326 can include any type of display, including but not limited to liquid crystal displays (LCDs), plasma displays, light-emitting diode (LED) displays, etc.

[0064] Figure 14 An exemplary wireless communication device 1400 is shown, which includes a radio frequency (RF) component formed by IC 1402, wherein any component therein may include Figure 4 and / or Figures 8-12 The IC, and according to any aspect disclosed herein. As an example, wireless communication device 1400 may include or be incorporated in any of the aforementioned devices. Figure 14As shown, the wireless communication device 1400 includes a transceiver 1404 and a data processor 1406. The data processor 1406 may include memory for storing data and program code. The transceiver 1404 includes a transmitter 1408 and a receiver 1410 supporting bidirectional communication. Typically, the wireless communication device 1400 may include any number of transmitters 1408 and / or receivers 1410 for any number of communication systems and frequency bands. All or part of the transceiver 1404 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0065] Transmitter 1408 or receiver 1410 can be implemented in either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage of receiver 1410. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 14 In the wireless communication device 1400, the transmitter 1408 and the receiver 1410 are implemented using a direct conversion architecture.

[0066] In the transmission path, data processor 1406 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1408. In the exemplary wireless communication device 1400, data processor 1406 includes digital-to-analog converters (DACs) 1412(1) and 1412(2) for converting digital signals generated by data processor 1406 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0067] Within transmitter 1408, low-pass filters 1414(1) and 1414(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1416(1) and 1416(2) amplify the signals from low-pass filters 1414(1) and 1414(2), respectively, and provide I and Q baseband signals. Upconverter 1418 upconverts the I and Q baseband signals using the I and Q transmit (TX) local oscillator (LO) signals from mixers 1420(1) and 1420(2) from TX LO signal generator 1422 to provide upconverted signal 1424. Filter 1426 filters upconverted signal 1424 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1428 amplifies the up-converted signal 1424 from filter 1426 to obtain the desired output power level and provides the transmitted RF signal. The transmitted RF signal is routed through duplexer or switch 1430 and transmitted via antenna 1432.

[0068] In the receiving path, antenna 1432 receives signals transmitted via the base station and provides the received RF signal, which is routed through duplexer or switch 1430 and provided to low-noise amplifier (LNA) 1434. Duplexer or switch 1430 is designed to operate at a specific receive (RX) to TX duplexer frequency, thus isolating the RX signal from the TX signal. The received RF signal is amplified by LNA 1434 and filtered by filter 1436 to obtain the desired RF input signal. Downconversion mixers 1438(1) and 1438(2) mix the output of filter 1436 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RXLO signal generator 1440 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1442(1) and 1442(2) and further filtered by low-pass filters 1444(1) and 1444(2) to obtain I and Q analog input signals, which are then provided to data processor 1406. In this example, data processor 1406 includes ADCs 1446(1) and 1446(2) for converting the analog input signals into digital signals to be further processed by data processor 1406.

[0069] exist Figure 14In the wireless communication device 1400, a TX LO signal generator 1422 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1440 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1448 receives timing information from a data processor 1406 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1422. Similarly, an RX PLL circuit 1450 receives timing information from the data processor 1406 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1440.

[0070] Figure 15 This is a system-level block diagram of an exemplary mobile terminal 1500, such as a smartphone, mobile computing device, tablet computer, etc., and which may include a radio frequency (RF) front-end, which may include one or more acoustic devices in an IC according to this disclosure. In this respect, the mobile terminal 1500 includes an application processor 1504 (sometimes referred to as a host) communicating with a mass storage element 1506 via a Universal Flash Memory (UFS) bus 1508. The application processor 1504 may also be connected to a display 1510 via a Display Serial Interface (DSI) bus 1512 and to a camera 1514 via a Camera Serial Interface (CSI) bus 1516. Various audio elements, such as a microphone 1518, a speaker 1520, and an audio codec 1522, may be coupled to the application processor 1504 via a Serial Low Power Inter-Chip Multimedia Bus (SLIMbus) 1524. Additionally, the audio elements may communicate with each other via a Soundwire bus 1526. A modem 1528 may also be coupled to the SLIM bus 1524 and / or the Soundwire bus 1526. The modem 1528 can also be connected to the application processor 1504 via the Peripheral Component Interconnect (PCI) or High-Speed ​​PCI (PCIe) bus 1530 and / or System Power Management Interface (SPMI) bus 1532.

[0071] Continue to refer to Figure 15The SPMI bus 1532 can also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 1534, a power management integrated circuit (PMIC) 1536, a companion IC (sometimes called a bridge chip) 1538, and a radio frequency IC (RFIC) 1540. It should be understood that separate PCI buses 1542 and 1544 can also couple the application processor 1504 to the companion IC 1538 and the WLAN IC 1534. The application processor 1504 can also be connected to the sensor 1546 via the sensor bus 1548. The modem 1528 and the RFIC 1540 can communicate using bus 1550.

[0072] Continue to refer to Figure 15 RFIC 1540 can be coupled to one or more RFFE components, such as antenna tuner 1552, switch 1554, and power amplifier 1556, via RFFE bus 1558. Furthermore, RFIC 1540 can be coupled to envelope tracking power supply (ETPS) 1560 via bus 1562, and ETPS 1560 can communicate with power amplifier 1556. In general, RFFE components including RFIC 1540 can be considered as RFFE system 1564. It should be understood that RFFE bus 1558 can be formed by clock lines and data lines (not shown). Components of RFFE system 1564, and particularly antenna tuner 1552, can include ICs having acoustic elements according to exemplary aspects of this disclosure.

[0073] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium, and executed by a processor or other processing device or a combination of both. As an example, the devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0074] The various illustrative logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0075] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0076] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations can be performed in many different orders besides the order shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and processes. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0077] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to limit the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit IC, comprising: IC chips; A wall is positioned on the substrate, and the wall is at least partially below the IC chip; Solder bumps couple the IC chip to the substrate, and the wall height of the wall is less than the solder bump height of the solder bump; and A gap is formed between the wall and the IC chip.

2. The IC according to claim 1, wherein, The IC chip includes an acoustic device, and the acoustic device includes a cavity.

3. The IC according to claim 2, wherein, The IC chip includes a forbidden area, and the wall is positioned below the IC chip outside the forbidden area.

4. The IC according to claim 1, wherein, The substrate includes a metallized structure.

5. The IC according to claim 1, wherein, The gap is configured to prevent encapsulation material surrounding the IC chip from intruding into the gap.

6. The IC according to claim 1, wherein, The gap is between 1 and 21 μm.

7. The IC according to claim 1, wherein, The gap is 11 μm.

8. The IC according to claim 1, wherein, The IC chip is positioned at a first height above the substrate.

9. The IC according to claim 8, wherein, The first height is between 30 and 40 μm.

10. The IC according to claim 9, wherein, The wall includes a second height, wherein the second height is between 20 and 30 μm.

11. The IC according to claim 2, wherein, The acoustic device includes devices selected from the group consisting of: surface acoustic wave (SAW) devices, temperature compensated surface acoustic wave (TC-SAW) devices, thin-film bulk acoustic resonators (FBAR), bulk acoustic wave (BAW) devices, and thin-film surface acoustic wave (TF-SAW) devices.

12. The IC of claim 1, wherein the IC is integrated into a device selected from the group consisting of: an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a monitor; a vehicle component; and a drone.

13. The IC of claim 1, wherein the IC is integrated into a device selected from the group consisting of: a computer; an automobile; and an avionics system.

14. A method for forming an integrated circuit (IC), the method comprising: A wall is formed on a wiring substrate, wherein the wall has a wall height; and An IC chip containing acoustic wave devices is bonded to the wiring substrate using solder bumps, wherein the height of the solder bumps is greater than the height of the wall, thereby maintaining a gap between the lower surface of the IC chip and the upper surface of the wall.

15. The method of claim 14, further comprising forming the wiring substrate.

16. The method according to claim 15, wherein, The step of forming the wall includes forming a wall having a uniform cross-section surrounding the IC chip.

17. The method of claim 14, further comprising forming the IC chip.

18. The method of claim 17, wherein the step of forming the IC chip includes fabricating at least one acoustic element on the wafer.

19. The method of claim 17, wherein, The steps for forming the IC chip include forming bumps on the wafer.

20. The method of claim 17, further comprising cutting the IC chip from other IC chips on the wafer.

21. The method of claim 14, further comprising encapsulating the IC chip with an encapsulating material.

22. The method according to claim 21, wherein, The step of bonding the IC chip to the wiring substrate includes maintaining the gap.

23. The method according to claim 14, wherein, The gap is less than 21 μm.

24. The method according to claim 14, wherein, The gap is 11 μm.

25. An integrated circuit IC, comprising: A metallized structure having a first surface and an outer edge; A chip, including acoustic devices, said chip having a second surface; At least one solder bump extends from the first surface of the metallized structure to the second surface of the chip, the at least one solder bump having a first height; At least one wall extends upward from the first surface of the metallized structure, the at least one wall having a second height shorter than the first height, and the at least one wall being positioned closer to the outer edge than the solder bump, the at least one wall being at least partially between the second surface and the first surface and maintaining a gap between the at least one wall and the second surface; and Encapsulating material surrounds the chip and is coupled to at least a portion of the first surface of the metallized structure.

26. The IC according to claim 25, wherein, The metallized structure includes a laminate.

27. The IC according to claim 25, wherein, The metallized structure includes ceramic materials.

28. The IC according to claim 27, wherein, The at least one wall comprises a second ceramic material.

29. The IC according to claim 25, wherein, The at least one wall extends from the outer edge to the bottom of the chip.

30. The IC according to claim 25, wherein, The at least one wall is spaced apart inside the outer edge.

31. The IC according to claim 25, wherein, The encapsulation material includes a first encapsulation material and a second encapsulation material.

32. The IC according to claim 25, wherein, The gap is between 1 and 21 μm.

33. The IC according to claim 25, wherein, The gap is 11 μm.

34. The IC according to claim 25, wherein, The first height is between 30 and 40 μm.

35. The IC according to claim 34, wherein, The second height is between 20 and 30 μm.

36. The IC according to claim 25, wherein, The acoustic device includes devices selected from the group consisting of: surface acoustic wave (SAW) devices, temperature compensated surface acoustic wave (TC-SAW) devices, thin-film bulk acoustic resonators (FBAR), bulk acoustic wave (BAW) devices, and thin-film surface acoustic wave (TF-SAW) devices.

37. The IC of claim 25, wherein the IC is integrated into a device selected from the group consisting of: an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a monitor; a vehicle component; and a drone.

38. The IC of claim 25, wherein the IC is integrated into a device selected from the group consisting of: a computer; an automobile; and an avionics system.

39. The IC according to claim 25, wherein, The encapsulating material fills only a portion of the gap.

Images