Chip structure analysis method

Abstract

The present invention provides a chip structure analysis method, comprising the steps of: grinding solder balls, and during the grinding process, controlling the grinding power so that the vibration generated by the grinding is transmitted to the intermediate layer, forming cracks in the intermediate layer; removing the passivation layer, removing the intermediate layer where the cracks are formed, and analyzing the metal circuit layer. Vibration is generated by grinding the solder balls, and by controlling the grinding process parameters, the vibration energy generated during the grinding process is accurately transmitted to the intermediate layer, causing cracks to be generated in the intermediate layer including the mask layer and the via layer. The structural strength of the cracked intermediate layer is reduced, and the interlayer bonding force is reduced, making it easier to remove without the use of special chemical solvents or specialized grinding machines. The method is highly operational and efficient. Furthermore, by using the solder balls as an intermediate medium for transmitting vibration energy, the transmission process of the vibration energy is more gentle and controllable, and the solder balls can also provide a certain protective function, preventing damage to the metal circuit layer.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip structure analysis method. Background Art

[0002] During chip structure analysis, it's necessary to confirm the chip's multi-layer structure. Existing techniques include: first, chemical etching; second, mechanical grinding and sectioning; third, direct chip grinding and delamination, or a combination of these methods. However, these methods are only suitable for simple one- or two-layer chip structures. They are incapable of performing analysis on chips with corrosion-resistant interlayers. Alternatively, they require specialized equipment, various targeted chemical solutions, and associated labor costs, resulting in lengthy and cumbersome operations. Summary of the Invention

[0003] The purpose of the present invention is to provide a chip structure analysis method.

[0004] The present invention provides a chip structure analysis method, wherein the chip includes: a substrate, metal circuit layers formed on the substrate, at least one intermediate layer formed on the metal circuit layer, a passivation layer formed on the intermediate layer, and a solder pad located in the passivation layer, wherein the intermediate layer includes a mask layer and / or a through-hole layer. The analysis method comprises the following steps:

[0005] forming solder balls on the surface of the solder pad, grinding the solder balls, and during the grinding of the solder balls, controlling the grinding power so that vibrations generated by the grinding are transmitted to the middle layer through the solder balls, thereby forming cracks on the middle layer;

[0006] The passivation layer is removed, the intermediate layer where cracks are formed is removed, and the metal circuit layer is analyzed.

[0007] As a further improvement of the present invention, grinding the solder balls specifically includes:

[0008] The solder balls are ground with a wedge through wire bonding, and cracks are formed in the intermediate layer by controlling the grinding power of the wedge.

[0009] As a further improvement of the present invention, it also includes:

[0010] The wrecking knife is selected according to the size of the solder pad opening in the passivation layer so that the inner chamfered surface of the wrecking knife fits the solder ball.

[0011] As a further improvement of the present invention, grinding the solder balls with a whet through wire bonding specifically includes:

[0012] The cleaver is controlled to grind the solder ball in a transverse direction, a longitudinal direction, or a circular direction.

[0013] As a further improvement of the present invention, the method of grinding the solder balls with a whet through wire bonding further includes:

[0014] The grinding time of the wrecking knife is controlled, and the grinding is continued until the crack extends to the complete area of ​​the middle layer corresponding to the bonding pad, and cracks are avoided in the metal circuit layer.

[0015] As a further improvement of the present invention, controlling the grinding time of the cleaver specifically includes:

[0016] The wedge grinding is controlled to be 100 to 200 ms, but not limited thereto.

[0017] As a further improvement of the present invention, the controlling of the grinding power so that the vibration generated by the grinding is transmitted to the intermediate layer through the solder balls, thereby forming cracks on the intermediate layer, specifically includes:

[0018] The grinding power is controlled so that vibration generated by grinding is transmitted to the mask layer, thereby forming cracks on the mask layer.

[0019] As a further improvement of the present invention, the removing of the intermediate layer where cracks are formed specifically includes:

[0020] The mask layer forming the cracks is chemically etched.

[0021] As a further improvement of the present invention, the controlling of the grinding power so that the vibration generated by the grinding is transmitted to the intermediate layer through the solder balls, thereby forming cracks on the intermediate layer, specifically includes:

[0022] The grinding power is controlled so that the vibration generated by the grinding is transmitted to the through-hole layer, thereby forming cracks in the through-hole layer.

[0023] As a further improvement of the present invention, the removing of the intermediate layer where cracks are formed specifically includes:

[0024] The cracked through-hole layer is vibrated and peeled off.

[0025] The beneficial effects of the present invention are as follows: the present invention generates vibrations by grinding solder balls, and by controlling the grinding process parameters, the vibration energy generated during the grinding process is accurately transferred to the intermediate layer, causing cracks to be generated in the intermediate layer including the mask layer and the through-hole layer. The structural strength of the cracked intermediate layer is reduced, and the bonding force between the layers is reduced, making it easier to remove. There is no need to use special chemical solvents or professional grinders, and the method is highly operational and efficient. Moreover, by using solder balls as an intermediate medium for transmitting vibration energy, the transmission process of vibration energy is more gentle and controllable, and the solder balls can also play a certain protective function to prevent damage to the metal circuit layer. In addition, the present invention can accurately obtain structural information of each layer including the metal layer and the intermediate layer by combining grinding solder balls with chemical solution corrosion, and has lower costs and wider adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the steps of a chip structure analysis method in one embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram of the chip structure in one embodiment of the present invention.

[0028] Figure 3 Schematic diagram of the grinding direction of the wedge in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0030] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention.

[0031] For ease of explanation, this document uses terms that indicate spatial relative positions, such as "upper," "lower," "rear," "front," etc., to describe the relationship of one unit or feature shown in the drawings relative to another unit or feature. Terms that indicate spatial relative positions may include different orientations of the device during use or operation other than the orientation shown in the drawings. For example, if the device in the drawings is turned over, units described as being "below" or "above" other units or features will be located "below" or "above" the other units or features. Therefore, the exemplary term "below" can encompass both below and above spatial orientations.

[0032] This embodiment provides a chip structure analysis method that can conveniently remove the various intermediate layers of a chip, thereby inspecting and analyzing the chip's metal circuit layers, providing scientific guidance for wire bonding processes and chip research. The analysis method provided by this embodiment is highly accurate, efficient, and stable, effectively removing the intermediate layers of a chip. The required materials and equipment are low-cost, and there is no need for special chemical solvents for corrosion-resistant materials or specialized grinders.

[0033] The chip 1 to be analyzed includes: a substrate 11, a metal circuit layer 12 formed on the substrate 11, at least one intermediate layer 13 formed on the metal circuit layer 12, a passivation layer 14 formed on the intermediate layer 13, and a bonding pad 15 located within the passivation layer 14. The intermediate layer 13 includes a mask layer 131 and / or a via layer 132. The mask layer 131 is a hard mask layer 131 made of a material such as titanium nitride. The via layer 132 is a dielectric layer having a via structure filled with a conductive material such as metal or polysilicon tungsten to achieve electrical interconnection between the chip 1 and the surface bonding pad 15. The chip 1 structural analysis method provided in this embodiment is capable of efficiently stripping the mask layer 131 and / or the via layer 132.

[0034] like Figure 1 As shown, the chip 1 structure analysis method includes the following steps:

[0035] S1: forming a solder ball 16 on the surface of the solder pad 15, grinding the solder ball 16, and during the grinding process of the solder ball 16, controlling the grinding power so that the vibration generated by the grinding is transmitted to the intermediate layer 13, forming a crack in the intermediate layer 13;

[0036] S2: Remove the passivation layer 14, remove the intermediate layer 13 where cracks are formed, and analyze the metal circuit layer 12.

[0037] In this method, vibration is generated by grinding the solder balls 16, and by controlling the grinding process parameters, the vibration energy generated during the grinding process is accurately transferred to the intermediate layer 13, causing cracks in the intermediate layer 13 including the mask layer 131 and / or the through-hole layer 132. The structural strength of the cracked intermediate layer 13 is reduced, and the interlayer bonding force is reduced, making it easier to remove. The removal of each layer of the chip 1 can be completed without using special chemical solvents or professional grinding machines. In addition, by using the solder balls 16 as an intermediate medium for transmitting vibration energy, the transmission process of the vibration energy is more gentle and controllable, and the solder balls 16 can also play a certain protective function to prevent damage to the metal circuit layer 12. If each layer is directly ground, the grinding process parameters are difficult to control, and it is easy to directly damage the metal circuit layer 12, making the structure of the metal circuit layer 12 incomplete.

[0038] For example, Figure 2As shown, this embodiment illustrates the method based on a chip 1 with a specific structure. The chip 1 includes a substrate 11, on which a metal circuit layer 12 is formed. A second mask layer 1312, a through-hole layer 132, and a first mask layer 1311 are sequentially formed upward from the metal circuit layer 12. A passivation layer 14 is formed on the first mask layer 1311, and a solder pad 15 is provided within the passivation layer 14. When performing failure analysis or reverse analysis on the chip 1, the chip 1 is usually analyzed after the solder balls 16 and solder wires 17 are already set. Therefore, in step S1, the process of forming the solder balls 16 may have been completed in other production steps. For the chip 1 without solder balls 16, the solder balls 16 are first set, and then the solder balls 16 are ground.

[0039] In step S1, it specifically includes:

[0040] The solder balls 16 are ground with a wedge 2 for wire bonding, and cracks are formed in the metal layer and the via layer 132 by controlling the grinding power of the wedge 2. Specifically, the wedge 2 is selected according to the size of the pad opening in the passivation layer 14 so that the chamfered surface of the wedge 2 fits the solder balls 16.

[0041] Since solder ball 16 is formed by wire bonder blade 2 during the formation process, grinding with blade 2 accurately matches the shape of solder ball 16, improving grinding accuracy and stability. The grinding process can be stably controlled, and the vibration energy generated during the grinding process can be accurately transmitted to intermediate layer 13, ensuring that sufficient vibration energy is generated to cause cracks in intermediate layer 13 located below solder ball 16.

[0042] The selection criteria for the wedge 2 for grinding can refer to the selection criteria for the wedge used in the wire bonding process. The inner chamfer diameter of the wedge 2 is obtained by multiplying the pad opening size in the passivation layer 14 by a coefficient, and the corresponding wedge 2 is selected for grinding.

[0043] In other embodiments of the present invention, other fine grinding equipment may also be used to grind the solder ball 16 , and the present invention does not impose any specific limitation thereto. Using the wrench 2 for grinding is only a preferred embodiment of the present invention.

[0044] Further, such as Figure 3 As shown, during the grinding process, the blade 2 is controlled to grind the solder balls 16 in a transverse and / or longitudinal and / or annular direction. During the grinding process, different grinding powers and grinding directions can be selected based on factors such as the material and size of the solder balls 16, or the solder balls 16 can be ground in multiple directions, thereby accurately delivering vibration energy to each intermediate layer 13.

[0045] Furthermore, during the grinding process, the grinding time of blade 2 is controlled, and grinding is continued until the cracks extend to the intact area of ​​intermediate layer 13 corresponding to the bonding pad, while avoiding cracks in metal circuit layer 12. Forming large cracks in intermediate layer 13 corresponding to the bonding pad area makes it easier to remove each intermediate layer 13. In some embodiments of the present invention, to avoid damage to metal circuit layer 12 caused by excessive grinding, grinding can be performed until cracks are formed only in a portion of intermediate layer 13.

[0046] Preferably, in combination with factors such as the commonly used materials and sizes of existing chip solder balls, the number of chip layers, and the materials of each intermediate layer, in this embodiment, the grinding time of the whet knife 2 is controlled to be 100-200 ms, but is not limited thereto.

[0047] Specifically, in this embodiment, for the chip bonding area, the solder balls 16 are ground to form large cracks in the first mask layer 1311 and the corresponding areas of the through-hole layer 132. For the chip non-bonded area, the passivation layer 14 is directly removed by chemical solution etching.

[0048] Once cracks form in the first mask layer 1311, it is removed by etching with a chemical solution. The chemical solution may be a commonly used acidic or alkaline etching solution, such as a sodium hydroxide solution or a nitric acid solution. Due to the large cracks formed in the mask layer 131, in addition to the aforementioned reduction in structural strength and interlayer bonding strength, the contact area between the mask layer 131 and the etching solution is also larger after immersion in the etching solution, resulting in a more complete reaction and easier etching and removal.

[0049] As for the through-hole layer 132 , since the through-hole layer 132 itself has formed a large number of through-hole structures, further cracking it can significantly reduce its structural strength, and it can be peeled off and removed by high-frequency vibration.

[0050] In this embodiment, ultrasonic vibration cleaning is used to peel off the through-hole layer 132 with large-area cracks, and then the through-hole layer 132 is further cleaned to remove part of the remaining through-hole layer 132 structure.

[0051] In other embodiments of the present invention, high-frequency vibration may be applied to the through-hole layer 132 by other equipment to cause the through-hole layer 132 to be peeled off, and the present invention does not impose any specific limitation on this.

[0052] After removing the through-hole layer 132, the second mask layer 1312 structure is obtained. The second mask layer 1312 is then removed by chemical solution corrosion to obtain the metal circuit layer 12, so that the metal circuit layer 12 can be analyzed. In addition, in the process of removing each layer of the intermediate layer 13, the structure of each layer of the intermediate layer 13 can also be inspected and analyzed layer by layer.

[0053] For chips with other numbers of layers, such as a two-layer chip including a metal circuit layer and a mask layer, a three-layer chip including a metal circuit layer, a mask layer and a through-hole layer, etc., those skilled in the art can also refer to the above method flow to remove each layer of the chip. The chip analysis method provided by the present invention can be widely applied to chips of various layer structures.

[0054] In summary, this embodiment generates vibration by grinding solder balls, and by controlling the grinding process parameters, the vibration energy generated during the grinding process is accurately transferred to the intermediate layer, causing cracks to be generated in the intermediate layer including the mask layer and the through-hole layer. The structural strength of the cracked intermediate layer is reduced, and the interlayer bonding force is reduced, making it easier to remove. There is no need to use special chemical solvents or professional grinders, and the method is highly operational and efficient. In addition, by using solder balls as an intermediate medium for transmitting vibration energy, the transmission process of vibration energy is more gentle and controllable, and the solder balls can also play a certain protective function to prevent damage to the metal circuit layer. In addition, the present invention can accurately obtain structural information of each layer including the metal layer and the intermediate layer by combining grinding solder balls and chemical solution corrosion, and has lower cost and wider adaptability.

[0055] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0056] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip structure analysis method, the chip comprising: A substrate, a metal circuit layer formed on the substrate, at least one intermediate layer formed on the metal circuit layer, a passivation layer formed on the intermediate layer, and a pad located in the passivation layer, wherein the intermediate layer includes a mask layer and / or a through-hole layer, wherein the analysis method comprises the steps of: forming solder balls on the surface of the solder pad, grinding the solder balls, and controlling the grinding power during the grinding of the solder balls so that vibrations generated by the grinding are transmitted to the intermediate layer through the solder balls, thereby forming cracks in the intermediate layer; wherein "grinding the solder balls" specifically includes: Grinding the solder balls with a wedge through wire bonding, and controlling the wedge grinding power and the wedge grinding time to continuously grind until cracks extend to the intact area of ​​the middle layer corresponding to the bonding pad, and preventing cracks from occurring in the metal circuit layer; The passivation layer is removed, the intermediate layer where cracks are formed is removed, and the metal circuit layer is analyzed.

2. The chip structure analysis method according to claim 1, characterized in that: Also includes: The wrecking knife is selected according to the size of the solder pad opening in the passivation layer so that the inner chamfered surface of the wrecking knife fits the solder ball.

3. The chip structure analysis method according to claim 2, characterized in that: The method of grinding the solder balls with a whet through wire bonding specifically includes: The cleaver is controlled to grind the solder ball in a transverse direction, a longitudinal direction, or a circular direction.

4. The chip structure analysis method according to claim 1, characterized in that: The controlling of the wedge grinding time specifically includes: The splitting knife is controlled to grind for 100 to 200 ms.

5. The chip structure analysis method according to claim 1, characterized in that: The controlling of the grinding power so that the vibration generated by the grinding is transmitted to the intermediate layer through the solder balls, thereby forming cracks on the intermediate layer, specifically includes: The grinding power is controlled so that vibration generated by grinding is transmitted to the mask layer, thereby forming cracks on the mask layer.

6. The chip structure analysis method according to claim 5, characterized in that: The removing of the intermediate layer where cracks are formed specifically comprises: The crack-forming mask layer is chemically etched.

7. The chip structure analysis method according to claim 1, characterized in that: The controlling of the grinding power so that the vibration generated by the grinding is transmitted to the intermediate layer through the solder balls, thereby forming cracks on the intermediate layer, specifically includes: The grinding power is controlled so that the vibration generated by the grinding is transmitted to the through-hole layer, thereby forming cracks in the through-hole layer.

8. The chip structure analysis method according to claim 7, characterized in that: The removing of the intermediate layer where cracks are formed specifically comprises: The cracked through-hole layer is vibrated and peeled off.

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