Display device

Abstract

Disclosed is a display device including: a substrate including a first pixel region, a second pixel region, and a third pixel region, each of the second and third pixel regions having a smaller surface area than that of the first pixel region and connected to the first pixel region; first to third pixels respectively provided in the first to third pixel regions; first to third lines respectively connected to the first to third pixels; a line connection portion connecting the second and third lines; and a dummy unit, wherein the dummy unit includes a plurality of portions that are superimposed with the line connection portion and spaced apart from each other along a direction in which the line connection portion extends.

Description

[0001] This application is a divisional application of the patent application with application number 201710231716.6, filed on April 11, 2017, and titled "Display device". TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a display device, and more particularly, to a display device including areas having different surface areas from each other. BACKGROUND

[0003] A display device includes a plurality of pixels having display elements, each of which is provided with a wiring and a plurality of transistors connected to the wiring and configured to drive the display elements. The wirings can have different load values according to their lengths, and due to such a difference in load values, a difference in brightness can occur in a final image provided by the display device. SUMMARY

[0004] According to an embodiment of the present disclosure, there is provided a display device including a substrate including a first pixel area, a second pixel area, and a third pixel area, the second and third pixel areas having a smaller surface area than a surface area of the first pixel area and connected to the first pixel area; first to third pixels respectively disposed in the first to third pixel areas; first to third lines respectively connected to the first to third pixels; a line connection part connecting the second and third lines; and a dummy unit superposed with the line connection part and configured to compensate for a difference in load values of the first and second lines. The first line can be longer than the second and third lines.

[0005] In an embodiment of the present disclosure, the display device can further include a data line for providing a data signal to the first to third pixels, the first line can be a first scan line for providing a scan signal to the first pixel, and the second and third lines can be second and third scan lines for providing scan signals to the second and third pixels.

[0006] In an embodiment of the present disclosure, the substrate can further include first to third peripheral areas each surrounding the first to third pixel areas, respectively, and the dummy unit can be in at least one of the second peripheral area, the third peripheral area, and an additional peripheral area connecting the second and third peripheral areas.

[0007] In an embodiment of the present disclosure, each of the second pixel and the third pixel may include a transistor connected to the second scan line and the third scan line and the corresponding data line in the data line, and the transistor may include: an active pattern, arranged on a substrate; a gate electrode, arranged on the active pattern; a gate insulating film, arranged between the active pattern and the gate electrode; an interlayer insulating film, including a first interlayer insulating film covering the gate electrode and a second interlayer insulating film arranged on the first interlayer insulating film; and a source electrode and a drain electrode, arranged on the interlayer insulating film and each of the source electrode and the drain electrode is connected to the active pattern.

[0008] In an embodiment of the present disclosure, the display device may further include a power supply line arranged on the interlayer insulating film and in the first peripheral area, the second peripheral area, the third peripheral area and the additional peripheral area, the power supply line overlapping with the line connection portion, and the line connection portion may be arranged between the first interlayer insulating film and the second interlayer insulating film.

[0009] In an embodiment of the present disclosure, the dummy cell may include an auxiliary power supply pattern connected to a power supply line and arranged between a first interlayer insulating film and a second interlayer insulating film, and the line connection portion may be arranged between the gate insulating film and the first interlayer insulating film.

[0010] In an embodiment of the present disclosure, the display device may further include a power supply line arranged in the first peripheral area, the second peripheral area, the third peripheral area and the additional peripheral area and arranged on the interlayer insulating film and overlapping with the line connection portion, and the dummy pattern may be applied with the same voltage as the voltage of the power supply line.

[0011] In an embodiment of the present disclosure, the display device may further include a data line for providing data signals to the first pixel to the third pixel and a first scan line to a third scan line for providing scan signals to the first pixel to the third pixel. The first line may be a first light-emitting control line for providing a light-emitting control signal to the first pixel, and the second line and the third line may be a second light-emitting control line and a third light-emitting control line for providing a light-emitting control signal to the second pixel and the third pixel.

[0012] In an embodiment of the present disclosure, the second pixel region and the third pixel region may include a plurality of rows in which a plurality of pixels are arranged, and each line connection portion may connect the second line and the third line connecting pixels arranged in the same row.

[0013] In an embodiment of the present disclosure, the length of a line connection portion (hereinafter referred to as a first line connection portion) may be greater than the length of a line connection portion (hereinafter referred to as a second line connection portion), the first line connection portion connecting the second line and the third line having a smaller number of pixels arranged in a row of the line connection portion, and the second line connection portion connecting the second line and the third line having a larger number of pixels arranged in the row.

[0014] In an embodiment of the present disclosure, an overlapping surface area of ​​the first wire connection portion and the dummy pattern may be greater than an overlapping surface area of ​​the second wire connection portion and the dummy pattern.

[0015] In an embodiment of the present disclosure, at least one of the dummy pattern and the power supply line may include a plurality of open areas overlapping the line connection portion and spaced apart from each other.

[0016] In an embodiment of the present disclosure, the second pixel region and the second peripheral region may have shapes that are line-symmetrical with the third pixel region and the third peripheral region based on a center line of the first pixel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0018] FIG. 1A and FIG. 1B A plan view showing a display device according to an embodiment of the present disclosure;

[0019] FIG. 2 Show FIG. 1A an enlarged image of a second pixel area;

[0020] FIG. 3 and FIG. 4 A block diagram illustrating an embodiment of a driver and a pixel according to an embodiment of the present disclosure;

[0021] FIG. 5 A block diagram showing a pixel and a driver according to another embodiment of the present disclosure;

[0022] FIG. 6 A block diagram showing a pixel and a driver according to yet another embodiment of the present disclosure;

[0023] FIG. 7 Show FIG. 3 FIGURE 1 shows an embodiment of a first pixel shown in FIGURE 2;

[0024] FIG. 8 Show FIG. 3 A detailed plan view of a first pixel;

[0025] FIG. 9 Shown along FIG. 8 A sectional view taken along line II';

[0026] FIG. 10 Shown along FIG. 8 A sectional view taken along line II-II';

[0027] FIG. 11 and FIG. 12A plan view illustrating a second region, a third region, and additional peripheral regions according to an embodiment of the present disclosure;

[0028] FIG. 13 Show FIG. 11 An enlarged view of area AA;

[0029] FIG. 14 Shown along FIG. 13 A sectional view taken along line III-III';

[0030] FIG. 15 A plan view illustrating a second region, a third region, and additional peripheral regions according to an embodiment of the present disclosure;

[0031] FIG. 16 Show FIG. 15 An enlarged view of area BB;

[0032] FIG. 17 Shown along FIG. 16 A sectional view taken along line IV-IV';

[0033] FIG. 18 A plan view illustrating a second region, a third region, and additional peripheral regions according to an embodiment of the present disclosure;

[0034] FIG. 19 Show FIG. 18 Magnified view of the area CC;

[0035] FIG. 20 to FIG. 22 Shown along FIG. 19 A sectional view taken along line V-V';

[0036] FIG. 23 A plan view illustrating a second region, a third region, and additional peripheral regions according to an embodiment of the present disclosure;

[0037] FIG. 24 A plan view illustrating a second region, a third region, and additional peripheral regions according to an embodiment of the present disclosure;

[0038] FIG. 25 a plan view showing a region in which dummy cells according to an embodiment of the present disclosure are arranged; and

[0039] FIG. 26 and FIG. 27 Shown along FIG. 25 A cross-sectional view taken along line VI-VI'. DETAILED DESCRIPTION

[0040] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0041] In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element can be directly on the other layer or substrate, or intervening layers may also be present. Additionally, it will be understood that when a layer is referred to as being "between" two layers, the layer can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.

[0042] Terms such as "first" and "second" can be used to explain various construction elements, but the construction elements should not be limited by the above terms. These terms are only used to distinguish one construction element from another construction element. For example, without departing from the scope of this disclosure, a first construction element can be named a second construction element, and similarly, a second construction element can be named a first construction element. Unless otherwise clearly indicated in the context, a singular expression can include a plural expression.

[0043] In this application, it should be understood that terms such as "including" or "having" are used to indicate the presence of features, numbers, steps, operations, structural elements, components, or combinations thereof disclosed in the specification, and do not preclude the presence or possible addition of one or more other features, numbers, steps, operations, structural elements, components, or combinations thereof. In addition, in this specification, when a component such as a layer, film, region, plate, or the like is formed on another component, the forming direction is not limited to the upward direction, but may also include lateral and downward directions.

[0044] Hereinafter, preferred embodiments of the present disclosure will be explained in further detail with reference to the accompanying drawings.

[0045] FIG. 1A and FIG. 1B is a plan view showing a display device according to an embodiment of the present disclosure, FIG. 2 yes FIG. 1A An enlarged view of the second pixel area.

[0046] Reference FIG. 1A 、 FIG. 1B and FIG. 2The display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL, such as PXL1, PXL2, and PXL3, disposed on the substrate SUB, a driver disposed on the substrate SUB and configured to drive the pixels PXL, a power supply portion configured to supply power to the pixels PXL, and a lead portion connecting the pixels PXL and the driver.

[0047] The substrate SUB includes a plurality of regions, at least two of which may have different surface areas. For example, the substrate SUB may have two regions, and the two regions may have different surface areas. In another example, the substrate SUB may have three regions, and the three regions may have different surface areas, or only two of the three regions may have different surface areas. In yet another example, the substrate SUB may have four or more regions.

[0048] In the following embodiments, for ease of explanation, a substrate SUB including three regions (i.e., first to third regions A1, A2, and A3) is described as an example. Each of the first to third regions A1, A2, and A3 can have various shapes. For example, each of the first to third regions A1, A2, and A3 can be configured in various shapes, such as a closed polygonal shape including straight edges, a circular or elliptical shape including curved edges, a semicircular or semi-elliptical shape including both straight and curved edges, and the like.

[0049] For example, each of the first to third areas A1, A2, A3 may have a generally rectangular shape, and may have a shape in which an area adjacent to at least one vertex among the vertices of the rectangular shape is removed. FIG. 1A As shown in FIG, the second area A2 ( FIG. 1A The top left of the layout in the figure can have the triangle corner removed ( FIG. 1A In another example, as FIG. 1B As shown in FIG, the second area A2 ( FIG. 1B The top left of the layout in the figure can have the quadrilateral corners removed ( FIG. 1B The first to third areas A1, A2, and A3 may be divided into a first sub-area corresponding to the removed area and a second sub-area other than the first sub-area. Here, the width of the first sub-area may be greater than the width of the second sub-area.

[0050] The shape of the area adjacent to and removed from at least one of the vertices of the rectangular shape may be one of a triangular shape and a rectangular shape. FIG. 1AAs shown in FIG, the sides corresponding to the removed areas of the first to third areas A1, A2, A3 may have a diagonal line shape or a curved line segment shape inclined with respect to one side of the rectangular shape.

[0051] Each of the first to third areas A1, A2, and A3 may include pixel areas PXA1, PXA2, and PXA3 (hereinafter referred to as PXA) and peripheral areas PPA1, PPA2, and PPA3 (hereinafter referred to as PPA). The pixel areas PXA are regions where pixels PXL for displaying images are provided. Each pixel PXL will be explained later. In an embodiment of the present disclosure, each of the first to third pixel areas PXA1, PXA2, and PXA3 may generally have a shape corresponding to the shapes of the first to third areas A1, A2, and A3, respectively. For example, the pixel area PXA2 may have a rectangular shape with corners removed, where the corners correspond to and overlap with the removed corners of the corresponding second area A2.

[0052] The peripheral area PPA is an area where no pixels PXL are located and, therefore, no image is displayed. A driver for driving the pixels PXL, a power supply for supplying power to the pixels PXL, and a portion of wiring (not shown) connecting the pixels PXL and the driver may be located in the peripheral area PPA. The peripheral area PPA corresponds to the bezel in the final display device, and the width of the bezel is determined by the width of the peripheral area PPA.

[0053] Each of the first to third areas A1, A2, and A3 is explained as follows. The first area A1 may have the largest surface area among the first to third areas A1, A2, and A3. The first area A1 may include a first pixel area PXA1 (i.e., an area displaying an image) and a first peripheral area PPA1 surrounding at least a portion of the first pixel area PXA1.

[0054] The first pixel region PXA1 may be provided in a shape corresponding to that of the first region A1. In an embodiment of the present disclosure, the first pixel region PXA1 may have a first width W1 in a first direction DR1 and a first length L1 in a second direction DR2 crossing the first direction DR1.

[0055] The first peripheral area PPA1 may be provided at least on one side of the first pixel area PXA1. In an embodiment of the present disclosure, the first peripheral area PPA1 may surround the periphery of the first pixel area PXA1, but may be provided in an area other than the portion where the second area A2 and the third area A3 are arranged. In an embodiment of the present disclosure, the first peripheral area PPA1 may include a width portion extending in the width direction and a length portion extending in the longitudinal direction. The length portion of the first peripheral area PPA1 may be provided as a pair spaced apart from each other along the width direction of the first pixel area PXA1.

[0056] The second area A2 may have a surface area smaller than that of the first area A1. The second area A2 may have a second pixel area PXA2 (ie, an area displaying an image) and a second peripheral area PPA2 surrounding at least a portion of the second pixel area PXA2.

[0057] The second pixel region PXA2 may be provided in a shape corresponding to that of the second pixel region A2. In an embodiment of the present disclosure, the second pixel region PXA2 may have a second width W2 that is smaller than the first width W1 of the first pixel region A1. The second pixel region PXA2 may have a second length L2 that is smaller than the first length L1 of the first pixel region A1. The second pixel region PXA2 may be provided so as to protrude from the first pixel region PXA1 and may be directly connected to the first pixel region PXA1. In other words, the edge portion of the second pixel region PXA2 closest to the first pixel region PXA1 may overlap with the edge of the first pixel region PXA1.

[0058] The second peripheral area PPA2 may be provided at least on one side of the second pixel area PXA2. In an embodiment of the present disclosure, the second peripheral area PPA2 may surround the second pixel area PXA2, but may not be provided in the portion where the first pixel area PXA1 and the second pixel area PXA2 are connected to each other. In an embodiment of the present disclosure, the second peripheral area PPA2 may also include a width portion extending in the width direction and a length portion extending in the longitudinal direction. The length portion of the second peripheral area PPA2 may be provided as a pair spaced apart from each other along the width direction of the second pixel area PXA2.

[0059] The third area A3 may have a surface area smaller than that of the first area A1. The third area A3 may have a surface area equal to that of the second area A2. The third area A3 may include a third pixel area PXA3 (i.e., an area displaying an image) and a third peripheral area PPA3 surrounding at least a portion of the third pixel area PXA3.

[0060] The third pixel region PXA3 may be provided in a shape corresponding to that of the third region A3. In an embodiment of the present disclosure, the third pixel region PXA3 may have a third width W3 that is smaller than the first width W1 of the first region A1. The third pixel region PXA3 may have a third length L3 that is smaller than the first length L1 of the first region A1. The second width W2 and the third width W3 may be equal to each other. Furthermore, the second length L2 and the third length L3 may be equal to each other.

[0061] The third pixel region PXA3 may be provided in a protruding form from the first pixel region PXA1 and may be directly connected to the first pixel region PXA1. In other words, in the third pixel region PXA3, an edge portion closest to the first pixel region PXA1 may coincide with an edge of the first pixel region PXA1.

[0062] The third peripheral area PPA3 may be provided at least on one side of the third pixel area PXA3. In an embodiment of the present disclosure, the third peripheral area PPA3 may surround the third pixel area PXA3, but may not be provided in the portion where the first pixel area PXA1 and the third pixel area PXA3 are connected to each other. In an embodiment of the present disclosure, the third peripheral area PPA3 may also include a width portion extending in the width direction and a length portion extending in the longitudinal direction. The length portion of the third peripheral area PPA3 may also be provided as a pair spaced apart from each other along the width direction of the third pixel area PXA3.

[0063] In an embodiment of the present disclosure, the third area A3 may have a shape that is line-symmetrical with respect to the second area A2 based on an imaginary center line passing through the first area A1. Thus, with the exception of some wiring, the arrangement relationship of each component disposed in the third area A3 may be substantially the same as that in the second area A2.

[0064] Furthermore, the substrate SUB may have a shape in which the second area A2 and the third area A3 protrude relative to the first area A1 in a direction opposite to the second direction DR2. Furthermore, since the second area A2 and the third area A3 are arranged so as to be spaced apart from each other in the first direction DR1, the substrate SUB may have a shape in which the space between the second area A2 and the third area A3 is recessed. For example, a portion of the substrate SUB between the second area A2 and the third area A3 may be removed to define the recess. In other words, the substrate SUB may be provided with a notch between the second area A2 and the third area A3.

[0065] In an embodiment of the present disclosure, the length portion of the first peripheral area PPA1 may be connected to a portion of the length portion of the second peripheral area PPA2 and the third peripheral area PPA3, respectively. For example, the left length portion of the first peripheral area PPA1 and the left length portion of the second peripheral area PPA2 may be connected to each other. The right length portion of the first peripheral area PPA1 and the right length portion of the third peripheral area PPA3 may be connected to each other. In addition, the left length portion of the first peripheral area PPA1 and the left length portion of the second peripheral area PPA2 may have the same width W4. The right length portion of the first peripheral area PPA1 and the right length portion of the third peripheral area PPA3 may have the same width W5.

[0066] The width W4 of the left length portion of the first peripheral area PPA1 and the second peripheral area PPA2 may be different from the width W5 of the right length portion of the first peripheral area PPA1 and the third peripheral area PPA3. For example, the width W4 of the left length portion of the first peripheral area PPA1 and the second peripheral area PPA2 may be smaller than the width W5 of the right length portion of the first peripheral area PPA1 and the third peripheral area PPA3.

[0067] In an embodiment of the present disclosure, the second peripheral area PPA2 and the third peripheral area PPA3 may be connected by an additional peripheral area APA. For example, the additional peripheral area APA may connect the right length portion of the second peripheral area PPA2 and the left length portion of the third peripheral area PPA3. That is, the additional peripheral area APA may be provided on one side of the first pixel area PXA1 between the second area A2 and the third area A3.

[0068] Pixels PXL may be arranged on a substrate SUB in pixel areas PXA, namely, in the first to third pixel areas PXA1, PXA2, and PXA3. Each pixel PXL is the minimum unit for displaying an image, and multiple pixels may be provided. Pixels PXL may include a display element that emits color light. For example, the display element may be any of a liquid crystal display (LCD), an electrophoretic display (EPD), an electrowetting display (EWD), and an organic light-emitting diode (OLED) device. For convenience, the following explanation will use an organic light-emitting display as an example of a display element.

[0069] Each pixel PXL may emit one color among red, green, and blue, but is not limited thereto. For example, each pixel PXL may emit colors such as cyan, magenta, yellow, and white.

[0070] The pixels PXL may include a first pixel PXL1 arranged in a first pixel area PXA1, a second pixel PXL2 arranged in a second pixel area PXA2, and a third pixel PXL3 arranged in a third pixel area PXA3. In an embodiment of the present disclosure, a plurality of the first to third pixels PXL1, PXL2, and PXL3 may each be provided and arranged in a matrix along rows extending in a first direction DR1 and along columns extending in a second direction DR2. However, there is no specific limitation on the arrangement of the first to third pixels PXL1, PXL2, and PXL3. Therefore, the first to third pixels PXL1, PXL2, and PXL3 may be arranged in various arrangements. For example, the first pixels PXL1 may be arranged such that the first direction DR1 is a linear direction, while the second pixels PXL2 may be arranged such that a direction different from the first direction DR1 (e.g., a direction oblique to the first direction DR1 (e.g., inclined at an oblique angle to the first direction DR1)) is a linear direction. Furthermore, the third pixels PXL3 may be arranged in the same or different direction as the first pixels PXL1 and / or the second pixels PXL2. In addition, in another embodiment of the present disclosure, the row direction may be the second direction DR2 , and the column direction may be the first direction DR1 .

[0071] Meanwhile, in the second area A2 and the third area A3, the number of the second pixels PXL2 and the third pixels PXL3 may be different depending on the row. For example, in the second area A2 and the third area A3, the number of the second pixels PXL2 and the third pixels PXL3 arranged in the row corresponding to the corner (the corner is formed by the side with the inclined diagonal line) may be smaller than the number of the second pixels PXL2 and the third pixels PXL3 arranged in the row corresponding to the corner (the corner is formed by the side of the straight line). For example, FIG. 2 As shown in FIG, the number of second pixels PXL2 and third pixels PXL3 arranged in a row adjacent to (e.g., aligned with at least a portion of) the missing corner of the rectangular shape of the second and third areas A2 and A3 can be smaller than the number of second pixels PXL2 and third pixels PXL3 arranged in a row between two parallel sides of the rectangular shape of the second and third areas A2 and A3. Furthermore, the number of second pixels PXL2 and third pixels PXL3 arranged in a row can decrease as the length of the row becomes shorter. Consequently, the length of the wiring connecting the second pixels PXL2 and third pixels PXL3 can be shortened.

[0072] In addition, in the second area A2 and the third area A3, the scan lines or light emission control lines corresponding to the second pixel PXL2 and the third pixel PXL3 in the same row can be electrically connected through the scan line connection portion or the light emission control line connection portion. The driver can provide a signal to each pixel through the lead portion and thus control the operation of each pixel PXL. FIG. 1A andFIG. 1B In the figure, for the convenience of explanation, the lead portion is omitted, and the lead portion will be explained in more detail later.

[0073] The driver may include scan drivers SDV1, SDV2, and SDV3 (hereinafter referred to as SDV), light-emitting drivers EDV1, EDV2, and EDV3 (hereinafter referred to as EDV), a data driver DDV, and a timing control unit (not shown). The scan driver SDV provides a scan signal to each pixel along a scan line, the light-emitting driver EDV provides a light-emitting control signal to each pixel along a light-emitting control line, and the data driver DDV provides a data signal to each pixel along a data line. The timing control unit may control the scan drivers SDV, the light-emitting drivers EDV, and the data driver DDV.

[0074] In an embodiment of the present disclosure, the scan driver SDV may include a first scan driver SDV1 connected to the first pixel PXL1, a second scan driver SDV2 connected to the second pixel PXL2, and a third scan driver SDV3 connected to the third pixel PXL3. In an embodiment of the present disclosure, the light emitting driver EDV may include a first light emitting driver EDV1 connected to the first pixel PXL1, a second light emitting driver EDV2 connected to the second pixel PXL2, and a third light emitting driver EDV3 connected to the third pixel PXL3.

[0075] The first scan driver SDV1 may be arranged in a length portion of the first peripheral area PPA1. For example, the first scan driver SDV1 may continuously extend along a linear side of the first area A1 in the second direction DR2 and along a portion of a diagonal direction relative to the second direction DR2 defining a missing corner of the first area A1. FIG. 1A The length portion of the first peripheral area PPA1 is arranged as a pair spaced apart from each other along the width direction of the first pixel area PXA1. Therefore, the first scan driver SDV1 may be arranged at least on one side of the length portion of the first peripheral area PPA1. The first scan driver SDV1 may ultimately extend along the longitudinal direction of the first peripheral area PPA1. Similarly, the second scan driver SDV2 may be arranged in the second peripheral area PPA2, and the third scan driver SDV3 may be arranged in the third peripheral area PPA3.

[0076] In an embodiment of the present disclosure, the light-emitting driver EDV can be directly mounted on the substrate SUB. In the case where the light-emitting driver EDV is directly mounted on the substrate SUB, they can be formed together during the process of forming the pixel PXL. However, there is no limitation on the location or method of providing the light-emitting driver EDV. For example, the light-emitting driver EDV can be formed on a separate chip and provided on the substrate SUB in a chip-on-glass form, or can be mounted on a printed circuit board and connected to the substrate SUB via a connecting member.

[0077] The first light-emitting driver EDV1 may also be arranged in a length portion within the first peripheral area PPA1 in a manner similar to the arrangement of the first scan driver SDV1. For example, the first light-emitting driver EDV1 may extend parallel to the first scan driver SDV1. The first light-emitting driver EDV1 may be arranged in at least one side of the length portion of the first peripheral area PPA1. The first light-emitting driver EDV1 may ultimately extend along the longitudinal direction of the first peripheral area PPA1. In a similar manner, the second light-emitting driver EDV2 may be arranged in the second peripheral area PPA2, and the third light-emitting driver EDV3 may be arranged in the third peripheral area PPA3.

[0078] In the embodiments of the present disclosure, the scan driver SDV and the light-emitting driver EDV are shown as examples, being adjacent to each other and arranged only on one side of a pair of length portions of the peripheral area PPA. However, the arrangement of the scan driver SDV and the light-emitting driver EDV may vary. For example, the first scan driver SDV1 may be arranged on one side of a length portion of the first peripheral area PPA1, while the first light-emitting driver EDV1 may be arranged on the other side of the length portion of the first peripheral area PPA1. Alternatively, the first scan driver SDV1 may be arranged on both sides of the length portion of the first peripheral area PPA1, while the first light-emitting driver EDV1 may be arranged on only one side of the length portion of the first peripheral area PPA1.

[0079] The data driver DDV may be arranged in the first peripheral area PPA1. Specifically, the data driver DDV may be arranged within a width portion of the first peripheral area PPA1. The data driver DDV may ultimately extend along the width direction of the first peripheral area PPA1 (e.g., along the first direction DR1). In an embodiment of the present disclosure, the scan driver SDV, the emission driver EDV, and / or the data driver DDV may be positioned interchangeably.

[0080] The timing control unit can be connected to the first to third scan drivers SDV1, SDV2, SDV3, the first to third light emitting drivers EDV1, EDV2, EDV3, and the data driver DDV through wiring in various methods, and there is no specific limitation on the position of the arrangement. For example, the timing control unit can be mounted on a printed circuit board, and can be connected to the first to third scan drivers SDV1, SDV2, SDV3, the first to third light emitting drivers EDV1, EDV2, EDV3, and the data driver DDV, the printed circuit board can be arranged in various positions, such as at one side of the substrate SUB and on the rear surface of the substrate, and the like.

[0081] Further, in a configuration in which the scan lines or the light emitting control lines of the second pixel PXL2 and the third pixel PXL3 corresponding to the same row are electrically connected through the scan line connection portion or the light emitting control line connection portion, one of the second scan driver SDV2 and the third scan driver SDV3 and one of the second light emitting driver EDV2 and the third light emitting driver EDV3 can be omitted.

[0082] The power supply portion can include at least one power supply line ELVDD, ELVSS. For example, the power supply portion can include a first power supply line ELVDD and a second power supply line ELVSS. The first power supply line ELVDD and the second power supply line ELVSS can supply power to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0083] One of the first power supply line ELVDD and the second power supply line ELVSS (for example, the first power supply line ELVDD) can be arranged to correspond to one side of the first pixel area PXA1. For example, the first power supply line ELVDD can be arranged in an area of the data driver DDV in which the first peripheral area PPA1 is arranged. Further, the first power supply line ELVDD can extend in a width direction of the first pixel area PXA1.

[0084] The other of the first power supply line ELVDD and the second power supply line ELVSS (for example, the second power supply line ELVSS) can be arranged to surround the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3, in addition to an area of the data driver DDV in which the first peripheral area PPA1 is arranged. For example, the second power supply line ELVSS can have a shape extending along a left length portion of the first peripheral area PPA1, the second peripheral area PPA2, the third peripheral area PPA3, the additional peripheral area APA, and a right length portion of the first peripheral area PPA1.

[0085] In the above description, the first power supply line ELVDD is arranged on one side of the first pixel region PXA1 within the first peripheral region PPA1, and the second power supply line ELVSS is arranged in the remaining peripheral regions. However, this is not a limitation. For example, the first power supply line ELVDD and the second power supply line ELVSS may be arranged to surround the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. The voltage applied to the first power supply line ELVDD may be greater than the voltage applied to the second power supply line ELVSS.

[0086] FIG. 3 and FIG. 4 is a block diagram illustrating an embodiment of a driver and a pixel according to an embodiment of the present disclosure.

[0087] Reference FIG. 1A 、 FIG. 1B and FIG. 2 to FIG. 4 , a display device according to an embodiment of the present disclosure includes a pixel PXL, a driver, and a lead portion.

[0088] The pixel PXL includes first to third pixels PXL1, PXL2, and PXL3, and the driver includes first to third scan drivers SDV1, SDV2, and SDV3, first to third light emitting drivers EDV1, EDV2, and EDV3, a data driver DDV, and a timing control unit TC. FIG. 3 In the embodiment, the positions of the first to third scan drivers SDV1, SDV2, SDV3, the first to third light emitting drivers EDV1, EDV2, EDV3, the data driver DDV, and the timing control unit TC are for convenience. Therefore, when the display device is actually implemented, they can be arranged in different positions within the display device. For example, the data driver DDV is arranged closer to the first area A1 than the second area A2 and the third area A3, but is not limited thereto. For example, the data driver DDV can be arranged adjacent to the second area A2 and the third area A3, as shown in FIG. FIG. 4 As shown in .

[0089] The lead portions supply signals of the driver to each of the pixels PXL, and include scan lines, data lines, line connection portions ES, line connection portions EE, emission control lines, power supply lines, and initialization power supply lines. The scan lines include first to third scan lines S11 to S1n, S21 and S22, S31 and S32, each of which is connected to the first to third pixels PXL1, PXL2, PXL3, respectively, and the emission control lines include first to third emission control lines E11 to E1n, E21 and E22, E31 and E32, each of which is connected to the first to third pixels PXL1, PXL2, PXL3, respectively. The data lines D1 to Dm and the power supply lines are connected to the first to third pixels PXL1, PXL2, PXL3.

[0090] Further, the second scan lines S21 and S22 and the third scan lines S31 and S32 are electrically accessed through the scan line connection portions ES. For example, the second scan line S21 is electrically accessed to the third scan line S31 through the first scan line connection portion ES. Further, the second scan line S22 is electrically accessed to the third scan line S32 through the second scan line connection portion ES.

[0091] Further, the second emission control lines E21 and E22 and the third emission control lines E31 and E32 are electrically accessed through the emission control line connection portions EE. For example, the second emission control line E21 is electrically accessed to the third emission control line E31 through the first emission control line connection portion EE. Further, the second emission control line E22 is electrically accessed to the third emission control line E32 through the second emission control line connection portion EE.

[0092] The first pixel PXL1 is provided in the first pixel region PXA1. The first pixel PXL1 is connected to the first scan lines S11 to S1n, the first emission control lines E11 to E1n, and the data lines D1 to Dm. When a scan signal is supplied from the first scan lines S11 to S1n, a data signal from the data lines D1 to Dm is supplied to these first pixels PXL1. The first pixel PXL1 that has received the data signal controls the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the organic light emitting diode.

[0093] The second pixel PXL2 is provided in the second pixel region PXA2. The second pixel PXL2 is connected to the second scan lines S21 and S22, the second emission control lines E21 and E22, and the data lines D1 to D3. When a scan signal is supplied from the second scan lines S21 and S22 and the third scan lines S31 and S32, a data signal from the data lines D1 to D3 is supplied to such a second pixel PXL2. The second pixel PXL2 that has received the data signal controls the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the organic light emitting diode.

[0094] Further, althoughFIG. 3 , six second pixels PXL2 are shown arranged in the second pixel area PXA2 via two second scan lines S21 and S22, two second emission control lines E21 and E22, and three data lines D1 to D3, but the present invention is not limited thereto. That is, the plurality of second pixels PXL2 are arranged to correspond to the size of the second pixel area PXA2, and the number of second scan lines, second emission control lines, and data lines can be variously set to correspond to the number of second pixels PXL2.

[0095] The third pixel PXL3 is disposed in a third pixel area PXA3 defined by the third scan lines S31 and S32, the third emission control lines E31 and E32, and the data lines Dm-2 to Dm. When scan signals are supplied from the third scan lines S31 and S32 and the second scan lines S21 and S22, the data signal from the data lines Dm-2 to Dm is supplied to the third pixel PXL3. Receiving the data signal, the third pixel PXL3 controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode.

[0096] In addition, although FIG. 3 1 and 2 illustrate six third pixels PXL3 arranged in the third pixel area PXA3 via two third scan lines S31 and S32, two third emission control lines E31 and E32, and three data lines Dm-2 to Dm, but the present invention is not limited thereto. Specifically, the plurality of third pixels PXL3 are arranged to correspond to the size of the third pixel area PXA3, and the number of third scan lines, third emission control lines, and data lines can be variously set to correspond to the number of third pixels PXL3.

[0097] The first scan driver SDV1 supplies scan signals to the first scan lines S11 to S1n in response to the first gate control signal GCS1 from the timing control unit TC. For example, the first scan driver SDV1 may sequentially supply scan signals to the first scan lines S11 to S1n. When the scan signals are sequentially supplied to the first scan lines S11 to S1n, the first pixels PXL1 are sequentially selected in units of horizontal lines.

[0098] The second scan driver SDV2 supplies scan signals to the second scan lines S21 and S22 in response to a second gate control signal GCS2 from the timing control unit TC. The scan signals supplied to the second scan lines S21 and S22 are then supplied to the third scan lines S31 and S32 via the scan line connection portion ES. The second scan driver SDV2 can sequentially supply scan signals to the second scan lines S21 and S22. When the scan signals are sequentially supplied to the second scan lines S21 and S22, the second and third pixels PXL2 and PXL3 are sequentially selected in units of horizontal rows.

[0099] The third scan driver SDV3 supplies scan signals to the third scan lines S31 and S32 in response to a third gate control signal GCS3 from the timing control unit TC. The scan signals supplied to the third scan lines S31 and S32 are supplied to the second scan lines S21 and S22 via the scan line connection portion ES. The third scan driver SDV3 can sequentially supply scan signals to the third scan lines S31 and S32. When the scan signals are sequentially supplied to the third scan lines S31 and S32, the second and third pixels PXL2 and PXL3 are sequentially selected in units of horizontal rows.

[0100] Meanwhile, since the second scan lines S21 and S22 and the third scan lines S31 and S32 are electrically connected through the scan line connection portion ES, the scan signal being supplied from the second scan driver SDV2 and the scan signal being supplied from the third scan driver SDV3 are supplied such that they are synchronized with each other.

[0101] For example, the scan signal supplied from the second scan driver SDV2 to the second scan line S21 and the scan signal supplied from the third scan driver SDV3 to the third scan line S31 can be supplied simultaneously. Similarly, the scan signal supplied from the second scan driver SDV2 to the second scan line S22 and the scan signal supplied from the third scan driver SDV3 to the third scan line S32 can be supplied simultaneously.

[0102] When the second scan driver SDV2 and the third scan driver SDV3 are used to supply scan signals to the second scan lines S21 and S22 and the third scan lines S31 and S32, the delay of the scan signals due to the RC delay of the second scan lines S21 and S22 and the third scan lines S31 and S32 can be prevented, and therefore, the desired scan signals can be supplied to the second scan lines S21 and S22 and the third scan lines S31 and S32.

[0103] In addition, the second scan driver SDV2 and the third scan driver SDV3 can be driven so that they are synchronized with each other. Therefore, the second scan driver SDV2 and the third scan driver SDV3 can be driven by the same gate control signal GCS. For example, the third gate control signal GCS3 being supplied to the third scan driver SDV3 can be set to the same signal as the second gate control signal GCS2.

[0104] The first light emitting driver EDV1 supplies light emitting control signals to the first light emitting control lines E11 to E1n in response to the fourth gate control signal GCS4 from the timing control unit TC. For example, the first light emitting driver EDV1 may sequentially supply light emitting control signals to the first light emitting control lines E11 to E1n.

[0105] Here, the light-emission control signal may be set to have a width greater than that of the scan signal. For example, the light-emission control signal supplied to the i-th (i is a natural number) first light-emission control line E1i may be supplied so that it overlaps with the scan signal supplied to the i-1th first scan line S1i-1 and the scan signal supplied to the i-th first scan line S1i for at least a partial period of time.

[0106] The second light emitting driver EDV2 supplies light emitting control signals to the second light emitting control lines E21 and E22 in response to the fifth gate control signal GCS5 from the timing control unit TC. Here, the light emitting control signals supplied to the second light emitting control lines E21 and E22 are supplied to the third light emitting control lines E31 and E32 via the light emitting control line connection portion EE. The second light emitting control driver EDV2 can sequentially supply light emitting control signals to the second light emitting control lines E21 and E22.

[0107] The third light emitting driver EDV3 supplies light emitting control signals to the third light emitting control lines E31 and E32 in response to the sixth gate control signal GCS6 from the timing control unit TC. Here, the light emitting control signals supplied to the third light emitting control lines E31 and E32 are supplied to the second light emitting control lines E21 and E22 via the light emitting control line connection portion EE. The third light emitting driver EDV3 can sequentially supply light emitting control signals to the third light emitting control lines E31 and E32.

[0108] In addition, the light emission control signal can be set to a gate-off voltage (e.g., a high voltage) so that the transistor included in the pixel PXL can be turned off, and the scan signal can be set to a gate-on voltage (e.g., a low voltage) so that the transistor included in the pixel PXL can be turned on.

[0109] At the same time, since the second light-emitting control lines E21 and E22 and the third light-emitting control lines E31 and E32 are electrically connected through the light-emitting control line connection part EE, the light-emitting control signal being supplied from the second light-emitting driver EDV2 and the light-emitting control signal being supplied from the third light-emitting driver EDV3 can be supplied so that they are synchronized with each other.

[0110] For example, the light emitting control signal supplied from the second light emitting driver EDV2 to the second light emitting control line E21 and the light emitting control signal supplied from the third light emitting driver EDV3 to the third light emitting control line E31 may be supplied simultaneously. Similarly, the light emitting control signal supplied from the second light emitting driver EDV2 to the second light emitting control line E22 and the light emitting control signal supplied from the third light emitting driver EDV3 to the third light emitting control line E32 may be supplied simultaneously.

[0111] When the second light-emitting driver EDV2 and the third light-emitting driver EDV3 are used to supply light-emitting control signals to the second light-emitting control lines E21 and E22 and the third light-emitting control lines E31 and E32, delay of the light-emitting control signals due to RC delay of the second light-emitting control lines E21 and E22 and the third light-emitting control lines E31 and E32 can be prevented, and thus desired light-emitting control signals can be supplied to the second light-emitting control lines E21 and E22 and the third light-emitting control lines E31 and E32.

[0112] In addition, the second light emitting driver EDV2 and the third light emitting driver EDV3 can be driven so that they are synchronized with each other. Therefore, the second light emitting driver EDV2 and the third light emitting driver EDV3 can be driven by the same gate control signal GCS. For example, the sixth gate control signal GCS6 being supplied to the third light emitting driver EDV3 can be set to the same signal as the fifth gate control signal GCS5.

[0113] The data driver DDV may supply data signals to the data lines D1 to Dm in response to the data control signal DCS. The data signals supplied to the data lines D1 to Dm are supplied to the pixels PXL selected by the scan signal.

[0114] The timing control unit TC supplies gate control signals GCS1 to GCS6 generated based on timing signals supplied from the outside to the scan driver SDV and the light emitting driver EDV, and supplies the data control signal DCS to the data driver DDV.

[0115] Each of the gate control signals GCS1 to GCS6 includes a start pulse and a clock signal. The start pulse controls the timing of the first scan signal or the first light emitting control signal. The clock signal is used to shift the start pulse.

[0116] The data control signal DCS includes a source start pulse and a clock signal. The source start pulse controls the start time of data sampling. The clock signal is used to control the sampling operation.

[0117] Meanwhile, when the display device is being sequentially driven, the last output signal of the second scan driver SDV2 may be provided as a start pulse to the first scan driver SDV1. Similarly, when the display device is being sequentially driven, the last output signal of the second light-emitting driver EDV2 may be provided as a start pulse to the first light-emitting driver EDV1.

[0118] FIG. 5 is a block diagram showing a pixel and a driver according to another embodiment of the present disclosure. FIG. 5 When, for FIG. 3configurations in FIG. 1, the same reference numerals will be given to the configurations identical with those in FIG. 1, and detailed description thereof will be omitted.

[0119] Referring to FIG. 5 , a display device according to another embodiment of the disclosure includes pixels PXL, drivers, and a lead line portion.

[0120] The pixels PXL include first to third pixels PXL1, PXL2, PXL3, the drivers include first and second scan drivers SDV1, SDV2, first and second emission drivers EDV1, EDV2, a data driver DDV, and a timing control unit TC. The first to third pixels PXL1, PXL2, PXL3 are connected to the first and second scan drivers SDV1, SDV2, the first and second emission drivers EDV1, EDV2, the data driver DDV, and the timing control unit TC. FIG. 5 and FIG. 3 In comparison, in FIG. 5 , the third scan driver SDV3 and the third emission driver EDV3 can be omitted.

[0121] That is, the display device according to another embodiment of the disclosure drives the second scan lines S21 and S22 and the third scan lines S31 and S32 using the second scan driver SDV2 and drives the second emission control lines E21 and E22 and the third emission control lines E31 and E32 using the second emission driver EDV2.

[0122] In more detail, the second scan lines S21 and S22 and the third scan lines S31 and S32 are electrically accessed through the scan line connection portion ES, and the second emission control lines E21 and E22 and the third emission control lines E31 and E32 are electrically accessed through the emission control line connection portion EE. Thus, a scan signal from the second scan driver SDV2 can be supplied to the third scan lines S31 and S32 via the second scan lines S21 and S22 and the scan line connection portion ES. Likewise, an emission control signal from the second emission driver EDV2 can be supplied to the third emission control lines E31 and E32 via the second emission control lines E21 and E22 and the emission control line connection portion EE.

[0123] FIG. 6 is a block diagram illustrating pixels and drivers according to still another embodiment of the disclosure. When explaining FIG. 6 , the same reference numerals will be given to the configurations identical with those in FIG. 1, and detailed description thereof will be omitted. FIG. 3 Referring to

[0124] , a display device according to still another embodiment of the disclosure includes pixels PXL, drivers, and a lead line portion. FIG. 6

[0125] ​The pixel PXL includes first to third pixels PXL1, PXL2, and PXL3, and the driver includes a first scan driver SDV1, a second scan driver SDV2, a third scan driver SDV3, a fourth scan driver SDV4, a first light-emitting driver EDV1, a second light-emitting driver EDV2, a third light-emitting driver EDV3, a fourth light-emitting driver EDV4, a data driver DDV, and a timing control unit TC.

[0126] The fourth scan driver SDV4 supplies scan signals to the first scan lines S11 to S1n in response to the seventh gate control signal GCS7 from the timing control unit TC. For example, the fourth scan driver SDV4 may sequentially supply scan signals to the first scan lines S11 to S1n. When the scan signals are sequentially supplied to the first scan lines S11 to S1n, the first pixels PXL1 are sequentially selected in units of horizontal lines.

[0127] At the same time, the fourth scan driver SDV4 supplies scan signals to the first scan lines S11 to S1n in synchronization with the first scan driver SDV1. For example, the first scan line S11 may be supplied with scan signals from the first scan driver SDV1 and the fourth scan driver SDV4 at the same time. Similarly, the first scan line S1n may be supplied with scan signals from the first scan driver SDV1 and the fourth scan driver SDV4 at the same time.

[0128] When the scan signals are supplied to the first scan lines S11 to S1n using the first scan driver SDV1 and the fourth scan driver SDV4, delay of the scan signals due to RC delay of the first scan lines S11 to S1n can be prevented, and thus desired scan signals can be supplied to the first scan lines S11 to S1n.

[0129] In addition, the first scan driver SDV1 and the fourth scan driver SDV4 can be driven so as to be synchronized with each other. Therefore, the first scan driver SDV1 and the fourth scan driver SDV4 can be driven by the same gate control signal GCS. For example, the seventh gate control signal GCS7 supplied to the fourth scan driver SDV4 can be set to the same signal as the first gate control signal GCS1. At the same time, when the display device is being sequentially driven, the last output signal of the third scan driver SDV3 can be provided as a start pulse to the fourth scan driver SDV4.

[0130] The fourth light emitting driver EDV4 supplies the light emitting control signal to the first light emitting control lines E11 to E1n in response to the eighth gate control signal GCS8 from the timing control unit TC. For example, the fourth light emitting driver EDV4 may sequentially supply the light emitting control signal to the first light emitting control lines E11 to E1n.

[0131] Meanwhile, the fourth light emission driver EDV4 supplies light emission control signals to the first light emission control lines E11 to E1n so that the fourth light emission driver EDV4 is synchronized with the first light emission driver EDV1. For example, the light emission control signals from the first light emission driver EDV1 and the fourth light emission driver EDV4 can be simultaneously supplied to the first light emission control line E11. Likewise, the light emission control signals from the first light emission driver EDV1 and the fourth light emission driver EDV4 can be simultaneously supplied to the last first light emission control line E1n.

[0132] When the light emission control signals are supplied to the first light emission control lines E11 to E1n using the first light emission driver EDV1 and the fourth light emission driver EDV4 as described above, a delay of the light emission control signals due to RC delay of the first light emission control lines E11 to E1n can be prevented, and thus, desired light emission control signals can be supplied to the first light emission control lines E11 to E1n.

[0133] Further, the first light emission driver EDV1 and the fourth light emission driver EDV4 can be driven so that they are synchronized with each other, and thus, they can be driven by the same gate control signal GCS. For example, the eighth gate control signal GCS8 being supplied to the fourth scan driver SDV4 can be set as the same signal as the fourth gate control signal GCS4. Meanwhile, when the display apparatus is sequentially driven, the last output signal of the third light emission driver EDV3 can be provided to the fourth light emission driver EDV4 as a start pulse.

[0134] Further, FIG. 3 to FIG. 6 The drivers SDV1 to SDV4, EDV1 to EDV4 illustrated in FIG. 1 can be variously arranged by a developer. For example, the third scan driver SDV3, the fourth scan driver SDV4, the third light emission driver EDV3, and the fourth light emission driver EDV4 can be arranged in the display apparatus, and the first scan driver SDV1, the second scan driver SDV2, the first light emission driver EDV1, and the second light emission driver EDV2 can be omitted.

[0135] FIG. 7 is a diagram illustrating an example of the first pixel. FIG. 3 In FIG. 1, for convenience of explanation, a pixel connected to the m-th data line Dm and the i-th first scan line S1i is illustrated. FIG. 7

[0136] Referring to FIG. 2, FIG. 7 The first pixel PXL1 according to an embodiment of the disclosure is provided with an organic light emitting diode OLED, first to seventh transistors T1 to T7, and a storage capacitor Cst.

[0137] ​The anode of the organic light emitting diode OLED is connected to the first transistor T1 via the sixth transistor T6, and the cathode of the organic light emitting diode OLED is connected to the second power supply ELVSS. Such an organic light emitting diode OLED generates light of a certain brightness corresponding to the amount of current supplied from the first transistor T1.

[0138] The first power source ELVDD may be set to a voltage higher than that of the second power source ELVSS so that current may flow to the organic light emitting diode OLED.

[0139] The seventh transistor T7 is connected between the initialization power supply Vint and the anode of the organic light-emitting diode OLED. Furthermore, the gate electrode of the seventh transistor T7 is connected to the i-th first scan line S1i. The seventh transistor T7 is turned on when a scan signal is supplied to the i-th first scan line S1i and supplies the voltage of the initialization power supply Vint to the anode of the organic light-emitting diode OLED. The initialization power supply Vint can be set to a voltage lower than the voltage of the data signal.

[0140] The sixth transistor T6 is connected between the first transistor T1 and the organic light-emitting diode OLED. Furthermore, the gate electrode of the sixth transistor T6 is connected to the i-th first light-emission control line E1i. The sixth transistor T6 is turned off when a light-emission control signal is supplied to the i-th first light-emission control line E1i, and is turned on otherwise.

[0141] The fifth transistor T5 is connected between the first power supply ELVDD and the first transistor T1. Furthermore, the gate electrode of the fifth transistor T5 is connected to the i-th first light emission control line E1i. The fifth transistor T5 is turned off when a light emission control signal is supplied to the i-th first light emission control line E1i, and is turned on otherwise.

[0142] A first electrode of a first transistor T1 (driving transistor) is connected to a first power source ELVDD via a fifth transistor T5. A second electrode of the first transistor T1 is connected to the anode of the organic light-emitting diode OLED via a sixth transistor. Furthermore, a gate electrode of the first transistor T1 is connected to a first node N1. The first transistor T1 controls the amount of current flowing from the first power source ELVDD via the organic light-emitting diode OLED to the second power source ELVSS in response to the voltage at the first node N1.

[0143] The third transistor T3 is connected between the second electrode of the first transistor Tl and the first node Nl. Further, the gate electrode of the third transistor T3 is connected to the i-th first scan line Sli. Such a third transistor T3 is turned on when a scan signal is supplied to the i-th first scan line Sli, and electrically connects the second electrode of the first transistor Tl and the first node Nl. Accordingly, when the third transistor T3 is turned on, the first transistor Tl is connected in a diode form.

[0144] The fourth transistor T4 is connected between the first node Nl and the initialization power source Vint. Further, the gate electrode of the fourth transistor T4 is connected to the i-l-th first scan line Sli-l. Such a fourth transistor T4 is turned on when a scan signal is supplied to the i-l-th first scan line Sli-l, and supplies a voltage of the initialization power source Vint to the first node Nl.

[0145] The second transistor T2 is connected between the m-th data line Dm and the first electrode of the first transistor Tl. Further, the gate electrode of the second transistor T2 is connected to the i-th first scan line Sli. Such a second transistor T2 is turned on when a scan signal is supplied to the i-th first scan line Sli, and electrically connects the m-th data line Dm and the first electrode of the first transistor Tl.

[0146] The storage capacitor Cst is connected between the first power source ELVDD and the first node Nl. Such a storage capacitor Cst stores a data signal and a voltage corresponding to a threshold voltage of the first transistor Tl.

[0147] Meanwhile, the second pixel PXL2 and the third pixel PXL3 can be implemented in the same circuit as the circuit of the first pixel PXLl. Accordingly, detailed explanation of the second pixel PXL2 and the third pixel PXL3 will be omitted.

[0148] FIG. 8 is a plan view of the first pixel PXLl, FIG. 3 is a cross-sectional view taken along the line I-I' of FIG. 9 is a cross-sectional view taken along the line II-II' of FIG. 8 . FIG. 10 FIG. 8

[0149] FIG. 8 to FIG. 10 Two first scan lines Sli-l and Sli, a first light emission control line Eil, a power source line PL, and a data line Dj connected to one first pixel PXLl arranged in the i-th row and the j-th column arranged in the first pixel area PXAl are shown. In FIG. 9 and FIG. 10 ​​In the drawings, for ease of explanation, the first scan line of the i-1th row is denoted as "the i-1th first scan line S1i-1", the first scan line of the i-th row is denoted as "the i-th first scan line S1i", the light emitting control line of the i-th row is denoted as "the light emitting control line E1i", the data line of the j-th column is denoted as "the data line Dj", and the j-th power line is denoted as "the power line PL".

[0150] Referring to FIG. 3 to FIG. 10 The display device can include a substrate SUB, a lead portion, and a pixel PXL.

[0151] The substrate SUB can be made of an insulating material such as glass and resin. Also, the substrate SUB can be made of a material having flexibility so that the substrate SUB can be bent or folded, and the substrate SUB can have a single layer structure or a multi-layer structure.

[0152] For example, the substrate SUB can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material constituting the substrate SUB can vary, and can include fiber-reinforced plastic (FRP) or the like.

[0153] The lead portion can supply a signal to each of the first pixels PXL1, and can include the first scan lines S1i-1 and S1i, the first light emitting control line E1i, the power line PL, and the initialization power line IPL.

[0154] The first scan lines S1i-1 and S1i can extend in the first direction DR1. The first scan lines S1i-1 and S1i can include the i-1th first scan line S1i-1 and the i-th first scan line S1i arranged sequentially in the second direction DR2. The first scan lines S1i-1 and S1i can be applied with a scan signal. For example, the i-1th scan signal can be applied to the i-1th first scan line S1i-1, and the i-th scan signal can be applied to the i-th first scan line S1i. The i-th first scan line S1i can be bifurcated into two lines, and the bifurcated i-th first scan line S1i can be connected to different transistors. For example, the i-th first scan line S1i can include an upper i-th first scan line S1i adjacent to the i-1th first scan line S1i-1 and a lower i-th first scan line S1i apart from the i-1th first scan line S1i-1 and the upper i-th first scan line S1i.

[0155] The first light emitting control line E1i may extend in the first direction DR1, be spaced apart from the i-th first scan line S1i between two i-th first scan lines S1i, and be applied with a light emitting control signal.

[0156] The data line Dj may extend in the second direction DR2 and may be applied with a data signal.

[0157] The power line PL may extend in the second direction DR2. The power line PL may be arranged to be spaced apart from the data line Dj. The power line PL may be supplied with a first power source ELVDD.

[0158] The initialization power line IPL may extend in the first direction DR1 and may be disposed between the next i-th first scan line S1i and the i-1-th first scan line S1i-1 of the next row of pixels. The initialization power line IPL may be supplied with initialization power Vint.

[0159] Each of the first pixels PXL1 may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and an organic light emitting diode OLED.

[0160] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , a first drain electrode DE1 , and a connection line CNL.

[0161] The first gate electrode GE1 may be connected to the third drain electrode DE3 of the third transistor T3 and the fourth drain electrode DE4 of the fourth transistor T4. A connection line CNL may connect the first gate electrode GE1, the third drain electrode DE3, and the fourth drain electrode DE4. One end of the connection line CNL may be connected to the first gate electrode GE1 through a first contact hole CH1, and the other end of the connection line CNL may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2.

[0162] In an embodiment of the present disclosure, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor layer doped with impurities or not doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 may be made of a semiconductor layer doped with impurities, while the first active pattern ACT1 may be made of a semiconductor layer not doped with impurities.

[0163] The first active pattern ACT1 may have a strip shape extending in a certain direction, wherein the certain direction bends multiple times along the longitudinal direction of the extension. When viewed from a plan view, the first active pattern ACT1 may overlap the first gate electrode GE1. When the first active pattern ACT1 is finally formed, the channel region of the first transistor T1 may be formed. This increases the driving range of the gate voltage applied to the first transistor T1. As a result, the grayscale of the light subsequently emitted from the organic light-emitting diode OLED can be controlled.

[0164] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may be connected to the third source electrode SE3 of the third transistor T3 and to the sixth source electrode SE6 of the sixth transistor T6.

[0165] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0166] The second gate electrode GE2 can be connected to the i-th first scan line S1i. The second gate electrode GE2 can be provided as a portion of the i-th first scan line S1i or in a shape protruding from the i-th first scan line S1i. In an embodiment of the present disclosure, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 can be formed from a semiconductor layer doped with or undoped with impurities. For example, the second source electrode SE2 and the second drain electrode DE2 can be made of a semiconductor layer doped with impurities, while the second active pattern ACT2 is made of a semiconductor layer undoped with impurities. The second active pattern ACT2 is a portion overlapping the second gate electrode GE2. One end of the second source electrode SE2 can be connected to the second active pattern ACT2. The other end of the second source electrode SE2 can be connected to the data line Dj through the sixth contact hole CH6. One end of the second drain electrode DE2 can be connected to the second active pattern ACT2. The other end of the second drain electrode DE2 can be connected to the first source electrode SE1 of the first transistor T1 and to the fifth drain electrode DE5 of the fifth transistor T5.

[0167] The third transistor T3 can be configured as a dual-gate structure to prevent leakage current. That is, the third transistor T3 can include a 3a-th transistor T3a and a 3b-th transistor T3b. The 3a-th transistor T3a can include a 3a-th gate electrode GE3a, a 3a-th active pattern ACT3a, a 3a-th source electrode SE3a, and a 3a-th drain electrode DE3a. The 3b-th transistor T3b can include a 3b-th gate electrode GE3b, a 3b-th active pattern ACT3b, a 3b-th source electrode SE3b, and a 3b-th drain electrode DE3b. Hereinafter, the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b will be referred to as the third gate electrode GE3, the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b will be referred to as the third active pattern ACT3, the 3a-th source electrode SE3a and the 3b-th source electrode SE3b will be referred to as the third source electrode SE3, and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b will be referred to as the third drain electrode DE3.

[0168] The third gate electrode GE3 may be connected to the upper i-th first scan line S1i. The third gate electrode GE3 may be provided as a portion of the upper i-th first scan line S1i or may be provided in a shape protruding from the upper i-th first scan line S1i. For example, the 3a-th gate electrode GE3a may be provided in a shape protruding from the upper i-th first scan line S1i, and the 3b-th gate electrode GE3b may be provided as a portion of the upper i-th first scan line S1i.

[0169] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be formed from a semiconductor layer doped with or undoped with impurities. For example, the third source electrode SE3 and the third drain electrode DE3 may be formed from a semiconductor layer doped with impurities, while the third active pattern ACT3 may be formed from a semiconductor layer undoped with impurities. The third active pattern ACT3 is a portion overlapping the third gate electrode GE3. One end of the third source electrode SE3 may be connected to the third active pattern ACT3. The other end of the third source electrode SE3 may be connected to the first drain electrode DE1 of the first transistor T1 and to the sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 may be connected to the third active pattern ACT3. The other end of the third drain electrode DE3 may be connected to the fourth drain electrode DE4 of the fourth transistor T4. In addition, the third drain electrode DE3 may be connected to the first gate electrode GE1 of the first transistor T1 via a connection line CNL, a second contact hole CH2, and a first contact hole CH1.

[0170] The fourth transistor T4 can be provided in a dual gate structure to prevent a leakage current. That is, the fourth transistor T4 can include a 4a-th transistor T4a and a 4b-th transistor T4b. The 4a-th transistor T4a can include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a, and the 4b-th transistor can include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. Hereinafter, the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b will be denoted as a fourth gate electrode GE4, the 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b will be denoted as a fourth active pattern ACT4, the 4a-th source electrode SE4a and the 4b-th source electrode SE4b will be denoted as a fourth source electrode SE4, and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b will be denoted as a fourth drain electrode DE4.

[0171] The fourth gate electrode GE4 can be connected to the i-1-th first scan line S1i-1. The fourth gate electrode GE4 can be provided as a part of the i-1-th first scan line S1i-1 or as a shape protruding from the i-1-th first scan line S1i-1. For example, the 4a-th gate electrode GE4a can be provided as a part of the i-1-th first scan line S1i-1. The 4b-th gate electrode GE4b can be provided as a shape protruding from the i-1-th first scan line S1i-1.

[0172] The fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed of a semiconductor layer doped with impurities or not doped with impurities. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 can be made of a semiconductor layer doped with impurities, and the fourth active pattern ACT4 is made of a semiconductor layer not doped with impurities. The fourth active pattern ACT4 is a portion overlapping the fourth gate electrode GE4.

[0173] One end of the fourth source electrode SE4 can be connected to the fourth active pattern ACT4. The other end of the fourth source electrode SE4 can be connected to the initialization power line IPL of the previous row of pixels and to the seventh drain electrode DE7 of the seventh transistor T7 of the previous row of pixels. An auxiliary connection line AUX can be provided between the fourth source electrode SE4 and the initialization power line IPL. One end of the auxiliary connection line AUX can be connected to the fourth source electrode SE4 through the ninth contact hole CH9. The other end of the auxiliary connection line AUX can be connected to the initialization power line IPL of the previous row of pixels through the eighth contact hole of the previous row. One end of the fourth drain electrode DE4 can be connected to the fourth active pattern ACT4. The other end of the fourth drain electrode DE4 is connected to the third drain electrode DE3 of the third transistor T3. The fourth drain electrode DE4 is also connected to the first gate electrode GE1 of the first transistor T1 through the connection line CNL, the second contact hole CH2, and the first contact hole CH1.

[0174] The fifth transistor T5 can include a fifth gate electrode GE5, a fifth active pattern ACT5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0175] The fifth gate electrode GE5 can be connected to the first emission control line E1i. The fifth gate electrode GE5 can be provided as a portion of the first emission control line E1i or as a shape protruding from the first emission control line E1i. The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 are formed of a semiconductor layer doped with impurities or not doped with impurities. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be made of a semiconductor layer doped with impurities, and the fifth active pattern ACT5 is made of a semiconductor layer not doped with impurities. The fifth active pattern ACT5 is a portion that overlaps the fifth gate electrode GE5. One end of the fifth source electrode SE5 can be connected to the fifth active pattern ACT5. The other end of the fifth source electrode SE5 can be connected to the power line PL through the fifth contact hole CH5. One end of the fifth drain electrode DE5 can be connected to the fifth active pattern ACT5. The other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor T1 and to the second drain electrode DE2 of the second transistor T2.

[0176] The sixth transistor T6 can include a sixth gate electrode GE6, a sixth active pattern ACT6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0177] The sixth gate electrode GE6 can be connected to the first light emission control line E1i. The sixth gate electrode GE6 can be disposed as a part of the first light emission control line E1i or as a shape protruding from the first light emission control line E1i. The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 are formed of a semiconductor layer doped with impurities or not doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 can be made of a semiconductor layer doped with impurities, and the sixth active pattern ACT6 is made of a semiconductor layer not doped with impurities. The sixth active pattern ACT6 is a portion overlapping the sixth gate electrode GE6. One end of the sixth source electrode SE6 can be connected to the sixth active pattern ACT6. The other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 can be connected to the sixth active pattern ACT6. The other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor T7.

[0178] The seventh transistor T7 can include a seventh gate electrode GE7, a seventh active pattern ACT7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0179] The seventh gate electrode GE7 can be connected to the lower i-th first scan line S1i. The seventh gate electrode GE7 can be disposed as a part of the lower i-th first scan line S1i or as a shape protruding from the lower i-th first scan line S1i. The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 can be formed of a semiconductor layer doped with impurities or not doped with impurities. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 can be made of a semiconductor layer doped with impurities, and the seventh active pattern ACT7 is made of a semiconductor layer not doped with impurities. The seventh active pattern ACT7 is a portion overlapping the seventh gate electrode GE7. One end of the seventh source electrode SE7 can be connected to the seventh active pattern ACT7. The other end of the seventh source electrode SE7 can be connected to the sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 can be connected to the seventh active pattern ACT7. The other end of the seventh drain electrode DE7 can be connected to the initialization power line IPL. In addition, the seventh drain electrode DE7 can be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel of the next row. The seventh drain electrode DE7 and the fourth source electrode SE4 of the fourth transistor T4 of the pixel of the next row can be connected to each other through the auxiliary connection line AUX, the eighth contact hole CH8, and the ninth contact hole CH9.

[0180] The storage capacitor Cst can include a lower electrode LE and an upper electrode UE. The lower electrode LE can be formed of the first gate electrode GE1 of the first transistor T1.

[0181] The upper electrode UE may overlap the first gate electrode GE1 and may cover the lower electrode LE when viewed from a plan view. By increasing the surface area where the upper and lower electrodes LE overlap, the capacitance of the storage capacitor Cst can be increased. The upper electrode UE may extend in the first direction DR1. In an embodiment of the present disclosure, a voltage of the same level as the voltage of the first power supply ELVDD may be applied to the upper electrode UE. The upper electrode UE may have an opening OPN in the region where the first contact hole CH1, which is touched by the first gate electrode GE1 and the connection line CNL, is formed.

[0182] The organic light emitting diode OLED may include a first electrode AD, a second electrode CD, and a light emitting layer EML disposed between the first electrode AD and the second electrode CD.

[0183] A first electrode AD may be disposed within a light-emitting region corresponding to each first pixel PXL1. The first electrode AD may be connected to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7 and the tenth contact hole CH10. A bridge pattern BRP may be disposed between the seventh contact hole CH7 and the tenth contact hole CH10. The bridge pattern BRP may connect the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD.

[0184] In the following, reference will be made to FIG. 8 to FIG. 10 The structure of the display device according to the embodiment of the present disclosure is explained in a stacking order.

[0185] Active patterns ACT1 to ACT7 (hereinafter referred to as ACT) may be disposed on a base substrate BS. The active patterns may include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 may be made of a semiconductor material.

[0186] A buffer layer (not shown) may be disposed between the base substrate BS and the first to seventh active patterns ACT1 to ACT7 .

[0187] On the base substrate BS where the first to seventh active patterns ACT1 to ACT7 are formed, a gate insulating film GI may be disposed.

[0188] On the gate insulating film GI, an i-1th first scan line S1i-1, an i-th first scan line S1i, a light emission control line E1i, and first to seventh gate electrodes GE1 to GE7 may be provided. The first gate electrode GE1 may be a lower electrode LE of the storage capacitor Cst. The second gate electrode GE2 and the third gate electrode GE3 may be integrally formed with the i-th first scan line S1i. The fourth gate electrode GE4 may be integrally formed with the i-1th first scan line S1i-1. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be integrally formed with the light emission control line E1i. The seventh gate electrode GE7 may be integrally formed with the i-th first scan line S1i.

[0189] On the base substrate BS where the i-1th first scan line S1i-1 and the like are formed, a first interlayer insulating film IL1 may be provided.

[0190] On the first interlayer insulating film IL1, an upper electrode UE of a storage capacitor Cst and an initialization power line IPL may be provided. The upper electrode UE may cover the lower electrode LE. The upper electrode UE may constitute a storage capacitor Cst together with the lower electrode LE and the first interlayer insulating film IL1 provided therebetween.

[0191] On the base substrate BS where the upper electrode UE and the like are formed, a second interlayer insulating film IL2 may be provided.

[0192] On the second interlayer insulating film IL2 , the data line Dj, the power line PL, the connection line CNL, the auxiliary connection line AUX, and the bridge pattern BRP may be disposed.

[0193] The data line Dj may be connected to the second source electrode SE2 through a sixth contact hole CH6 penetrating the first interlayer insulating film IL1, the second interlayer insulating film IL2, and the gate insulating film GI. The power line PL may be connected to the upper electrode UE of the storage capacitor Cst through a third contact hole CH3 and a fourth contact hole CH4 penetrating the second interlayer insulating film IL2.

[0194] The power line PL may also be connected to the fifth source electrode SE5 through a fifth contact hole CH5 penetrating the first interlayer insulating film IL1 , the second interlayer insulating film IL2 , and the gate insulating film GI.

[0195] The connection line CNL may be connected to the first gate electrode GE1 through a first contact hole CH1 penetrating the first interlayer insulating film IL1 and the second interlayer insulating film IL2. In addition, the connection line CNL may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2 penetrating the gate insulating film GI, the first interlayer insulating film IL1, and the second interlayer insulating film IL2.

[0196] The auxiliary connection line AUX can be connected to the initialization power supply line IPL through an eighth contact hole CH8 that penetrates the second interlayer insulating film IL2. Further, the auxiliary connection line AUX can be connected to the seventh drain electrode DE7 and the fourth source electrode SE4 of the preceding row through a ninth contact hole CH9 that penetrates the gate insulating film GI, the first interlayer insulating film IL1, and the second interlayer insulating film IL2.

[0197] The bridge pattern BRP can be a pattern provided as an intermediary between the sixth drain electrode DE6 and the first electrode AD to connect the sixth drain electrode DE6 and the first electrode AD. The bridge pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 that penetrates the gate insulating film GI, the first interlayer insulating film IL1, and the second interlayer insulating film IL2.

[0198] On the base substrate BS on which the data line Dj and the like are formed, a protective layer PSV can be provided.

[0199] On the protective layer PSV, an organic light emitting diode OLED can be provided. The organic light emitting diode OLED can include a first electrode AD, a second electrode CD, and an emission layer EML provided between the first electrode AD and the second electrode CD.

[0200] The first electrode AD can be provided on the protective layer PSV. The first electrode AD can be connected to the bridge pattern BRP through a tenth contact hole CH10 that penetrates the protective layer PSV. Since the bridge pattern BRP is connected to the sixth drain electrode DE6 and to the seventh source electrode SE7 through the seventh contact hole CH7, the first electrode AD can be ultimately connected to the sixth drain electrode DE6 and to the seventh source electrode SE7.

[0201] On the base substrate BS on which the first electrode AD and the like are formed, a pixel defining film PDL for dividing an emission region into pixels PXL corresponding to each pixel PXL can be provided. The pixel defining film PDL can protrude from the base substrate BS along the periphery of the pixel PXL while exposing the upper surface of the first electrode AD.

[0202] In the emission region surrounded by the pixel defining film PDL, the emission layer EML is provided, and on the emission layer EML, the second electrode CD can be provided. On the second electrode CD, an encapsulation film SLM that covers the second electrode CD can be provided.

[0203] One of the first electrode AD and the second electrode CD can be an anode electrode, and the other can be a cathode electrode. For example, the first electrode AD can be an anode electrode, and the second electrode CD can be a cathode electrode.

[0204] Furthermore, at least one of the first electrode AD and the second electrode CD may be a transmissive electrode. For example, if the organic light-emitting diode OLED is a rear-surface emitting organic light-emitting diode, the first electrode AD may be a transmissive electrode, and the second electrode CD may be a reflective electrode. If the organic light-emitting diode OLED is a front-surface emitting organic light-emitting diode, the first electrode AD may be a reflective electrode, and the second electrode CD may be a transmissive electrode. If the organic light-emitting diode OLED is a double-sided emitting organic light-emitting diode, both the first electrode AD and the second electrode CD may be transmissive electrodes. This embodiment is explained assuming that the organic light-emitting diode OLED is a front-surface emitting organic light-emitting diode and that the first electrode AD is an anode electrode.

[0205] The first electrode AD may include a reflective film (not shown) capable of reflecting light and a transparent conductive film (not shown) disposed on an upper portion or a lower portion of the reflective film. At least one of the transparent conductive film and the reflective film may be connected to the drain electrode DE.

[0206] The reflective film may include a material capable of reflecting light. For example, the reflective film may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and alloys thereof.

[0207] The transparent conductive film may include a transparent conductive oxide. For example, the transparent conductive film may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0208] The pixel-defining layer (PDL) may include an organic insulating material. For example, the pixel-defining layer (PDL) may be at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylene ether (PAE), a heterocyclic polymer, parylene, epoxy resin, benzocyclobutene (BCB), a siloxane-based resin, and a silane-based resin.

[0209] The light-emitting layer (EML) may be disposed on the exposed surface of the first electrode AD. The light-emitting layer (EML) may have a multilayer thin-film structure including at least a light-generating layer. For example, the light-emitting layer (EML) may include a hole injection layer (HIL) for injecting holes, a hole transport layer (HTL), a light-generating layer for emitting light through recombination of injected electrons and holes, a hole blocking layer (HBL) for limiting the migration of holes that cannot be combined in the light-generating layer, an electron transport layer (ETL) for smoothly transporting electrons to the light-generating layer, and an electron injection layer (EIL) for injecting electrons. The hole transport layer (HTL) has excellent hole transport capability and is configured to increase the chance of recombination of holes and electrons by limiting the migration of electrons that cannot be combined in the light-generating layer.

[0210] The color of the light generated in the light generation layer may be one of red, green, blue, and white, but is not limited thereto in the present embodiment. For example, the color of the light generated in the light generation layer may be one of magenta, cyan, and yellow.

[0211] The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be common films connected in light emitting regions adjacent to each other.

[0212] The second electrode CD may be a semi-transmissive reflective film. For example, the second electrode CD may be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting layer EML. The second electrode CD may transmit a portion of the light emitted from the light-emitting layer EML while reflecting the remaining portion of the light emitted from the light-emitting layer EML.

[0213] The second electrode CD may include a material having a lower work function than that of the transparent conductive film. For example, the second electrode CD may include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0214] A portion of the light emitted from the light-emitting layer (EML) may not be transmitted through the second electrode (CD), and the light reflected by the second electrode (CD) may be reflected again by the reflective film. In other words, the light emitted from the light-emitting layer (EML) may resonate between the reflective film and the second electrode (CD). This light resonance improves the light extraction efficiency of the organic light-emitting diode (OLED).

[0215] The distance between the reflective film and the second electrode CD may be different according to the color of light emitted from the light emitting layer EML. That is, the distance between the reflective film and the second electrode CD may be adjusted to be suitable for the resonance distance according to the color of light emitted from the light emitting layer EML.

[0216] The encapsulating film (SLM) can prevent oxygen and moisture from penetrating the organic light-emitting diode (OLED). The encapsulating film (SLM) may include multiple inorganic films (not shown) and multiple organic films (not shown). For example, the encapsulating film (SLM) may include multiple unit encapsulating layers, each including an inorganic film and an organic film disposed on the inorganic film. Furthermore, inorganic films may be disposed on the lowermost and uppermost portions of the encapsulating film (SLM). The inorganic films may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0217] In an embodiment of the present disclosure, the second pixel PXL2 disposed in the second pixel area PXA2 and the third pixel PXL3 disposed in the third pixel area PXA3 have substantially the same pixel structure as that of the first pixel PXL1 , and thus repeated explanation thereof is omitted.

[0218] FIG. 11 and FIG. 12 is a plan view showing a second region, a third region, and an additional peripheral region according to an embodiment of the present disclosure, FIG. 13 yes FIG. 11 An enlarged view of area AA, FIG. 14 It is along FIG. 13 A cross-sectional view taken along line III-III'. FIG. 11 to FIG. 14 , only some construction elements are shown for convenience.

[0219] Reference FIG. 8 to FIG. 14 , the load value of the scan line connected to each of the second pixel PXL2 in the second area A2 and the third pixel PXL3 in the third area A3 can be different from the load value of the scan line connected to the first pixel PXL1 in the first area A1. This is because the number of pixels and the length of the corresponding scan line in each of the second area A2 and the third area A3 are different from the number of pixels and the length of the corresponding scan line in the first area A1. In other words, the load value of the scan line in the first area A1 can be greater than the load value of the scan line in each of the second area A2 and the third area A3.

[0220] Therefore, in an embodiment of the present disclosure, in order to compensate for the difference in load values ​​between pixel regions, a parasitic capacitance of a different structure may be applied to each pixel region using a dummy cell. That is, in order to compensate for the difference in load values ​​of the scan lines in the second pixel region PXA2 and the third pixel region PXA3 relative to the load value of the scan lines in the first pixel region PXA1, a dummy cell is not provided in the first peripheral area PPA1 corresponding to the first pixel region PXA1, but a dummy cell is provided in the additional peripheral area APA connecting the second peripheral area PPA2 corresponding to the second pixel region PXA2 and the third peripheral area PPA3 corresponding to the third pixel region PXA3.

[0221] Specifically, in an embodiment of the present disclosure, a dummy unit DU is defined in an additional peripheral area APA connecting the second peripheral area PPA2 and the third peripheral area PPA3, such that the parasitic capacitance of the dummy unit DU compensates for a difference in load values ​​of the scan lines in the second pixel area PXA2 and the third pixel area PXA3 relative to the load values ​​of the scan lines in the first pixel area PXA1. That is, in the dummy unit DU, a parasitic capacitor is formed by the overlap between the power supply portion and the scan line connection portion ES and / or the emission control line connection portion EE in the additional peripheral area APA to compensate for the load values, as will be described in more detail below.

[0222] In the additional peripheral area APA, e.g. FIG. 3 and FIG. 11 As shown in FIG, at least one scan line connection portion ES may be provided to connect the second scan lines S21 and S22 of the second area A2 and the third scan lines S31 and S32 of the third area A3 arranged in the same row. FIG. 11 As shown in FIG, in the additional peripheral area APA, a plurality of scan line connection portions ES for connecting each of the second scan lines S21, S22 and the third scan lines S31, S32 may be provided. FIG. 16 As shown in FIG, in the additional peripheral area APA, a scan line connection portion ES may be provided to connect the second scan lines S21 and S22 with the third scan lines S31 and S32. However, some of the second scan lines S21 and S22 and some of the third scan lines S31 and S32 are not connected to the scan line connection portion ES. Similarly, in the additional peripheral area APA, at least one light emission control line connection portion EE may be provided to connect the second light emission control lines E21 and E22 of the second area A2 and the third light emission control lines E31 and E32 of the third area A3, which are arranged in the same row.

[0223] In an embodiment of the present disclosure, a dummy unit DU may be provided in a region where the scan line connection portion ES or the emission control line connection portion EE overlaps with a power supply portion. The power supply portion may be one of a first power supply line ELVDD and a second power supply line ELVSS. Hereinafter, for convenience, the explanation will be based on the assumption that the dummy unit DU is provided in a region where the scan line connection portion ES or the emission control line connection portion EE overlaps with the second power supply line ELVSS.

[0224] The scan line connection portion ES and the light-emitting control line connection portion EE can be made of the same material as the initialization power line IPL and the upper electrode UE of the storage capacitor Cst and manufactured in the same process. Therefore, the scan line connection portion ES and the light-emitting control line connection portion EE can be formed on the same layer as the initialization power line IPL and the upper electrode UE. In the embodiments of the present disclosure, the explanation is based on the following assumption: the scan line connection portion ES and the light-emitting control line connection portion EE are formed on the same layer as the initialization power line IPL and the upper electrode UE, but is not limited to this. For example, the scan line connection portion ES and the light-emitting control line connection portion EE can be formed on the same layer as the second scan lines S21 and S22.

[0225] The second power supply line ELVSS can be made of the same material as the connection line CNL, the bridge pattern BRP, and the power line PL, and can be manufactured using the same process. Therefore, the second power supply line ELVSS, the connection line CNL, the bridge pattern BRP, and the power line PL can be formed on the same layer, for example, on the second interlayer insulating film IL2. In the embodiments of the present disclosure, the explanation is based on the assumption that the second power supply line ELVSS, the connection line CNL, the bridge pattern BRP, and the power line PL are formed on the same layer, but this is not limiting. For example, the second power supply line ELVSS can be formed on the same layer as the initialization power line IPL and the upper electrode UE.

[0226] In the dummy unit DU, the overlap between the second power supply line ELVSS and the scan line connection portion ES forms a parasitic capacitor. The parasitic capacitance of the parasitic capacitor can increase the load of the second scan lines S21, S22, and the third scan lines S31, S32, thereby compensating for the load values ​​of the second scan lines S21, S22, and the third scan lines S31, S32. As a result, the load values ​​of the second scan lines S21, S22, and the third scan lines S31, S32 can be the same as or similar to the load values ​​of the first scan lines S11 to S1n of the first pixel area PXA1. In embodiments of the present disclosure, the parasitic capacitance formed by the dummy unit DU can be set differently depending on the load values ​​of the scan lines for compensation.

[0227] Similarly, the dummy unit DU can compensate for the load values ​​of the second emission control lines E21 and E22 of the second pixel area PXA2 and the third emission control lines E31 and E32 of the third pixel area PXA3. For example, in the dummy unit DU, the second power supply line ELVSS and the emission control line connection portion EE form a parasitic capacitor. The parasitic capacitance of the parasitic capacitor can increase the load of the second emission control lines E21, E22, and the third emission control lines E31 and E32, thereby compensating for the load of the second emission control lines E21, E22, and the third emission control lines E31 and E32. As a result, the load values ​​of the second emission control lines E21, E22, and the third emission control lines E31 and E32 can be the same as or similar to the load values ​​of the first emission control lines E11 to E1n of the first pixel area PXA1.

[0228] In an embodiment of the present disclosure, the length of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (where the number of second pixels PXL2 and third pixels PXL3 arranged in the row is small) can be shorter than the length of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (where the number of second pixels PXL2 and third pixels PXL3 arranged in the row is large). Among the scan line connection portions ES, the length of the scan line connection portion ES connected to the short second scan lines S21, S22 or third scan lines S31, S32 can be longer than the length of the scan line connection portion ES connected to the long second scan lines S21, S22 or third scan lines S31, S32.

[0229] Since the dummy unit DU is arranged in the region where the second power supply line ELVSS and the scan line connection portion ES overlap each other, the surface area where the second power supply line ELVSS and the long scan line connection portion ES overlap can be larger than the surface area where the second power supply line ELVSS and the short scan line connection portion ES overlap. The parasitic capacitance of the parasitic capacitor formed by the overlap of the second power supply line ELVSS and the long scan line connection portion ES can be larger than the parasitic capacitance of the parasitic capacitor formed by the overlap of the second power supply line ELVSS and the short scan line connection portion ES.

[0230] Therefore, in the second pixel area PXA2, the load values ​​of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (wherein the number of second pixels PXL2 and third pixels PXL3 arranged in the row is small) and the load values ​​of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (wherein the number of second pixels PXL2 and third pixels PXL3 arranged in the row is large) may be the same or similar.

[0231] The parasitic capacitance can be set differently according to the load value of the scan line connection portion ES for compensation. The load value can be obtained by varying the surface area of ​​overlap between the second power supply line ELVSS and the scan line connection portion ES. Similarly, the load value of the light-emitting control line connection portion can also be obtained by varying the surface area of ​​overlap between the second power supply line ELVSS and the light-emitting control line connection portion.

[0232] In addition, in this embodiment, FIG. 12 As shown in FIG, the scan lines or emission control lines of the pixel rows not connected to the scan line connection portion ES or the emission control line connection portion EE may not have their load values ​​compensated by the dummy units DU. The scan lines or emission control lines of the pixel rows not connected to the scan line connection portion ES or the emission control line connection portion EE may have dummy units DU added at their ends to have their load values ​​compensated.

[0233] FIG. 15 is a plan view showing a second region, a third region, and an additional peripheral region according to an embodiment of the present disclosure, FIG. 16 yes FIG. 15 An enlarged view of area BB, FIG. 17 It is along FIG. 16 A sectional view taken along line IV-IV'.

[0234] Reference FIG. 8 to FIG. 10 and FIG. 15 to FIG. 17 , a load value of a scan line connected to each of the second pixel PXL2 of the second area A2 and the third pixel PXL3 of the third area A3 and a load value of a scan line connected to the first pixel PXL1 of the first area A1 may be different from each other.

[0235] Therefore, in an embodiment of the present disclosure, in order to compensate for the difference in load values ​​between pixel regions, a parasitic capacitance of a different structure may be applied to each pixel region using a dummy cell. That is, in order to compensate for the difference in load values ​​of the scan line between the first pixel region PXA1 and the second and third pixel regions PXA2 and PXA3, the dummy cell may not be provided in the first peripheral area PPA1 corresponding to the first pixel region PXA1, but may be provided in the additional peripheral area APA connecting the second peripheral area PPA2 corresponding to the second pixel region PXA2 and the third peripheral area PPA3 corresponding to the third pixel region PXA3.

[0236] In the additional peripheral area APA, at least one scan line connection portion ES may be provided to connect the second scan lines S21 and S22 of the second area A2 arranged in the same row with the third scan lines S31 and S32 of the third area A3. Similarly, in the additional peripheral area APA, at least one light emission control line connection portion EE may be provided to connect the second light emission control lines E21 and E22 of the second area A2 arranged in the same row with the third light emission control lines E31 and E32 of the third area A3.

[0237] In an embodiment of the present disclosure, the dummy unit may be provided in an area where the scan line connection portion ES or the light emission control line connection portion EE overlaps with the power supply portion. The power supply portion may be one of the first power supply line ELVDD and the second power supply line ELVSS, for example, the second power supply line ELVSS.

[0238] Furthermore, the dummy cell may include an auxiliary power supply pattern AUP connected to the second power supply line ELVSS. The auxiliary power supply pattern AUP may be arranged between the scan line connection portion ES or the emission control line connection portion EE and the second power supply line ELVSS, and may overlap the scan line connection portion ES or the emission control line connection portion EE and the second power supply line ELVSS. For example, the auxiliary power supply pattern AUP may be made of the same material as the initialization power line IPL and the upper electrode UE of the storage capacitor Cst, and may be manufactured in the same process. Therefore, the auxiliary power supply pattern AUP may be formed on the same layer as the initialization power line IPL and the upper electrode UE. That is, the auxiliary power supply pattern AUP may be arranged between the first interlayer insulating film IL1 and the second interlayer insulating film IL2.

[0239] The scan line connection portion ES and the emission control line connection portion EE can be made of the same material as the second scan lines S21, S22 or the second emission control lines E21, E22 and manufactured using the same process. Therefore, the scan line connection portion ES and the emission control line connection portion EE can be formed on the same layer as the second scan lines S21, S22 or the second emission control lines E21, E22. In other words, the scan line connection portion ES and the emission control line connection portion EE can be arranged between the gate insulating film GI and the first interlayer insulating film IL1.

[0240] In the dummy cell, the auxiliary power supply pattern AUP may overlap the scan line connection portion ES and the light emitting control line connection portion EE to form a parasitic capacitor.

[0241] The parasitic capacitance of the parasitic capacitor may increase the load of the second scan lines S21, S22 and the third scan lines S31, S32, thereby compensating for the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32. As a result, the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32 may be the same as or similar to the load values ​​of the first scan lines S11 to S1n of the first pixel area PXA1.

[0242] Likewise, the dummy cells may compensate for the load values ​​of the second light emitting control lines E21 and E22 of the second pixel area PXA2 and the third light emitting control lines E31 and E32 of the third pixel area PXA3 .

[0243] FIG. 18 is a plan view showing a second region, a third region, and an additional peripheral region according to an embodiment of the present disclosure, FIG. 19 yes FIG. 18 A magnified view of the CC region, FIG. 20 to FIG. 22 It is along FIG. 19 For ease of explanation, FIG. 18 to FIG. 22 Only some construction elements are shown.

[0244] First, refer to FIG. 8 to FIG. 10 and FIG. 18 to FIG. 20 , a load value of a scan line connected to each of the second pixel PXL2 of the second area A2 and the third pixel PXL3 of the third area A3 and a load value of a scan line connected to the first pixel PXL1 of the first area A1 may be different from each other.

[0245] Therefore, in an embodiment of the present disclosure, in order to compensate for the difference in load values ​​caused by pixel regions, a parasitic capacitance of a different structure may be applied to each pixel region using a dummy cell. That is, in order to compensate for the difference in load values ​​of the scan line between the first pixel region PXA1 and the second and third pixel regions PXA2 and PXA3, the dummy cell may not be provided in the first peripheral area PPA1 corresponding to the first pixel region PXA1, but the dummy cell may be provided in the additional peripheral area APA connecting the second peripheral area PPA2 corresponding to the second pixel region PXA2 and the third peripheral area PPA3 corresponding to the third pixel region PXA3.

[0246] In an embodiment of the present disclosure, in the additional peripheral area APA, at least one scan line connection portion ES connecting the second scan lines S21 and S22 of the second area A2 and the third scan lines S31 and S32 of the third area A3 arranged in the same row may be provided.

[0247] Likewise, in the additional peripheral area APA, at least one light emitting control line connection portion EE connecting the second light emitting control lines E21 and E22 of the second area A2 and the third light emitting control lines E31 and E32 of the third area A3 arranged in the same row may be provided.

[0248] In an embodiment of the present disclosure, the dummy unit may be provided in an area where the scan line connection portion ES or the light emission control line connection portion EE overlaps with the power supply portion. The power supply portion may be one of the first power supply line ELVDD and the second power supply line ELVSS, for example, the second power supply line ELVSS.

[0249] The second power supply line ELVSS may be made of the same material and in the same process as the connection line CNL, the bridge pattern BRP, and the power line PL. Therefore, the second power supply line ELVSS may be formed on the same layer (e.g., the second interlayer insulating film IL2) as the connection line CNL, the bridge pattern BRP, and the power line PL.

[0250] The scan line connection portion ES and the emission control line connection portion EE may be made of the same material as the initialization power line IPL and the upper electrode UE of the storage capacitor Cst and may be manufactured in the same process. Therefore, the scan line connection portion ES and the emission control line connection portion EE may be formed on the same layer as the initialization power line IPL and the upper electrode UE. The second power supply line ELVSS may overlap with the scan line connection portion ES or the emission control line connection portion EE to form a parasitic capacitor.

[0251] Furthermore, the dummy cell may be connected to the second power supply line ELVSS and may include a dummy pattern DMP overlapping the second power supply line ELVSS. The dummy pattern DMP may be made of the same material as the active pattern arranged in each pixel and manufactured in the same process. The dummy pattern DMP may be formed on the same layer as the active pattern. That is, the dummy pattern DMP may be arranged between the substrate SUB and the gate insulating film GI and may be formed of a semiconductor layer doped with impurities.

[0252] The dummy pattern DMP can be connected to the second power supply line ELVSS via a contact hole CNT penetrating the gate insulating film GI, the first interlayer insulating film IL1, and the second interlayer insulating film IL2. A voltage equal to that of the second power supply line ELVSS can be applied to the dummy pattern DMP. Therefore, the dummy pattern DMP can overlap with the scan line connection portion ES to form a parasitic capacitor. Therefore, the dummy cell can include a parasitic capacitor formed by the scan line connection portion ES and the second power supply line ELVSS, as well as a parasitic capacitor formed by the scan line connection portion ES and the dummy pattern DMP.

[0253] The parasitic capacitance of the parasitic capacitor formed by the dummy unit can increase the load of the second scan lines S21, S22 and the third scan lines S31, S32, thereby compensating for the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32. As a result, the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32 can be the same as or similar to the load values ​​of the first scan lines S11 to S1n of the first pixel area PXA1.

[0254] In an embodiment of the present disclosure, parasitic capacitance formed by the dummy unit may be differently set according to a load value of the scan line for compensation.

[0255] Similarly, the dummy cells can compensate for the load values ​​of the second emission control lines E21 and E22 of the second pixel area PXA2 and the third emission control lines E31 and E32 of the third pixel area PXA3. For example, the emission control line connection portion EE can be arranged in the additional peripheral area APA, and the second power supply line ELVSS, the dummy pattern DMP, and the emission control line connection portion EE can form a parasitic capacitor. The parasitic capacitor can increase the load of the second emission control lines E21, E22, and the third emission control lines E31 and E32, thereby compensating for the load values ​​of the second emission control lines E21, E22, and the third emission control lines E31 and E32. As a result, the load values ​​of the second emission control lines E21, E22, and the third emission control lines E31 and E32 can be the same or similar to the load values ​​of the first emission control lines E11 to E1n of the first pixel area PXA1.

[0256] In the embodiments of the present disclosure, the dummy cells can be implemented in various ways. In the above embodiments, the dummy pattern DMP arranged on the same layer as the active pattern uses parasitic capacitors between the second power supply line ELVSS and the scan line connection portion ES and the emission control line connection portion EE to compensate for the load values ​​of the scan line and the emission control line, but the present invention is not limited thereto.

[0257] In an embodiment of the present disclosure, the dummy pattern DMP can be arranged on the same layer as the second scan lines S21 and S22. Therefore, the dummy cell can include a parasitic capacitor formed by the scan line connection portion ES, the emission control line connection portion EE, and the second power supply line ELVSS, as well as a parasitic capacitor formed by the scan line connection portion ES, the emission control line connection portion EE, and the dummy pattern DMP. The dummy cell can use the parasitic capacitor to compensate for differences in load values ​​between the scan lines and the emission control lines.

[0258] Next, refer to FIG. 8 to FIG. 10 、 FIG. 18 、 FIG. 19 and FIG. 21The second power supply line ELVSS may overlap with the scan line connection portion ES and the emission control line connection portion EE to form a parasitic capacitor. The scan line connection portion ES and the emission control line connection portion EE may be made of the same material as the initialization power line IPL and the upper electrode UE of the storage capacitor Cst and manufactured in the same process. That is, the scan line connection portion ES and the emission control line connection portion EE may be formed on the same layer as the initialization power line IPL and the upper electrode UE.

[0259] The dummy unit may include a dummy pattern DMP overlapping the scan line connection portion ES or the emission control line connection portion EE. The dummy pattern DMP may be made of the same material as the second scan lines S21 and S22 and manufactured in the same process. Therefore, the dummy pattern DMP may include a dummy pattern DMP overlapping the scan line connection portion ES or the emission control line connection portion EE. The dummy pattern DMP may be made of the same material as the second scan lines S21 and S22 and manufactured in the same process. Therefore, the dummy pattern DMP and the second scan lines S21 and S22 may be formed on the same layer. That is, the dummy pattern DMP may be arranged between the gate insulating film GI and the first interlayer insulating film IL1.

[0260] The dummy pattern DMP may be connected to the second power supply line ELVSS through a contact hole CNT penetrating the first interlayer insulating film IL1 and the second interlayer insulating film IL2. Therefore, the dummy pattern DMP may be applied with the same voltage as the second power supply line ELVSS. Therefore, the dummy pattern DMP may overlap with the scan line connection portion ES to form a parasitic capacitor.

[0261] In addition, the scan line connection portion ES and the second power supply line ELVSS may form a parasitic capacitor.

[0262] Therefore, the parasitic capacitance of the parasitic capacitor can increase the load of the second scan lines S21, S22 and the third scan lines S31, S32, thereby compensating for the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32. As a result, the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32 can be the same as or similar to the load values ​​of the first scan lines S11 to S1n of the first pixel area PXA1.

[0263] In an embodiment of the present disclosure, parasitic capacitance formed by the dummy unit may be set differently according to the load value of the scan line for compensation.

[0264] Similarly, the dummy cells may include parasitic capacitors formed when the dummy pattern DMP and the light-emission control line connection portion EE overlap, as well as parasitic capacitors formed when the light-emission control line connection portion EE and the second power supply line ELVSS overlap. Therefore, the dummy cells can compensate for the load values ​​of the second light-emission control lines E21 and E22 of the second pixel region PXA2 and the third light-emission control lines E31 and E32 of the third pixel region PXA3 through the parasitic capacitance of the parasitic capacitors. As a result, the load values ​​of the second light-emission control lines E21 and E22 and the third light-emission control lines E31 and E32 can be the same or similar to the load values ​​of the first light-emission control lines E11 to E1n of the first pixel region PXA1.

[0265] Next, refer to FIG. 8 to FIG. 10 and FIG. 19 to FIG. 22 , the second power supply line ELVSS may overlap the scan line connection portion ES and the light emitting control line connection portion EE to form a parasitic capacitor.

[0266] The scan line connection portion ES can be made of the same material as the second scan lines S21 and S22 and manufactured in the same process. Therefore, the scan line connection portion ES and the second scan lines S21 and S22 can be formed on the same layer. In other words, the scan line connection portion ES can be arranged between the gate insulating film GI and the first interlayer insulating film IL1.

[0267] The light-emission control line connection portion EE can be made of the same material as the second light-emission control lines E21 and E22 and manufactured using the same process. Therefore, the light-emission control line connection portion EE and the second light-emission control lines E21 and E22 can be formed on the same layer. In other words, the light-emission control line connection portion EE can be arranged between the first interlayer insulating film IL1 and the second interlayer insulating film IL2.

[0268] The dummy cell may be provided in a region where the scan line connection portion ES or the emission control line connection portion EE overlaps the second power supply line ELVSS. The dummy cell may include a dummy pattern DMP overlapping the scan line connection portion ES or the emission control line connection portion EE. The dummy pattern DMP may be disposed between the substrate SUB and the gate insulating film GI and may be formed of a semiconductor layer doped with impurities.

[0269] The dummy pattern DMP can be connected to the second power supply line ELVSS through a contact hole CNT that penetrates the gate insulating film GI, the first interlayer insulating film IL1, and the second interlayer insulating film IL2. Therefore, the dummy pattern DMP can be applied with the same voltage as the second power supply line ELVSS. Therefore, the dummy pattern DMP can overlap with the scan line connection portion ES to form a parasitic capacitor.

[0270] The dummy cell may include a parasitic capacitor formed by the scan line connection portion ES and the second power supply line ELVSS and a parasitic capacitor formed by the scan line connection portion ES and the dummy pattern DMP.

[0271] The parasitic capacitance of the parasitic capacitor formed by the dummy unit can increase the load of the second scan lines S21, S22 and the third scan lines S31, S32, thereby compensating for the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32. As a result, the load values ​​of the second scan lines S21, S22 and the third scan lines S31, S32 can be the same as or similar to the load values ​​of the first scan lines S11 to S1n of the first pixel area PXA1.

[0272] In an embodiment of the present disclosure, parasitic capacitance formed by the dummy unit may be set differently according to the load value of the scan line for compensation.

[0273] Similarly, the dummy cells may include parasitic capacitors formed when the dummy pattern DMP and the light-emission control line connection portion EE overlap, as well as parasitic capacitors formed when the light-emission control line connection portion EE and the second power supply line ELVSS overlap. Therefore, the dummy cells can compensate for the load values ​​of the second light-emission control lines E21 and E22 of the second pixel region PXA2 and the third light-emission control lines E31 and E32 of the third pixel region PXA3 through the parasitic capacitance of the parasitic capacitors. As a result, the load values ​​of the second light-emission control lines E21 and E22 and the third light-emission control lines E31 and E32 can be the same or similar to the load values ​​of the first light-emission control lines E11 to E1n of the first pixel region PXA1.

[0274] FIG. 23 is a plan view illustrating a second region, a third region, and an additional peripheral region according to an embodiment of the present disclosure.

[0275] Reference FIG. 1A 、 FIG. 1B 、 FIG. 2 to FIG. 10 and FIG. 23 In the right length portion of the second peripheral area PPA2 and in the left length portion of the third peripheral area PPA3, a scan line connection portion ES that connects the second scan lines S21, S22 connected to the second pixel PXL2 of the second pixel area PXA2 and the third scan lines S31, S32 connected to the third pixel PXL3 of the third pixel area PXA3 may be arranged.

[0276] The length of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (where the number of second pixels PXL2 and third pixels PXL3 arranged in the row is small) may be shorter than the length of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (where the number of second pixels PXL2 and third pixels PXL3 arranged in the row is large).

[0277] Among the scan line connection portions ES, the length of the scan line connection portion ES connected to the short second scan line S21, S22 or the third scan line S31, S32 may be greater than the length of the scan line connection portion ES connected to the long second scan line S21, S22 or the third scan line S31, S32.

[0278] The dummy cell may be arranged in an area where the scan line connection portion ES or the emission control line connection portion EE overlaps the second power supply line ELVSS. The dummy cell may include a dummy pattern DMP overlapping the scan line connection portion ES. The dummy pattern DMP may have a shape extending to the right length portion of the second peripheral area PPA2 and to the left length portion of the third peripheral area PPA3.

[0279] The dummy cell may include a parasitic capacitor formed by the scan line connection portion ES and the second power supply line ELVSS and a parasitic capacitor formed by the scan line connection portion ES and the dummy pattern DMP.

[0280] Furthermore, the surface area of ​​the overlap between the long scan line connection portion ES and the dummy pattern DMP may be greater than the surface area of ​​the overlap between the short scan line connection portion ES and the dummy pattern DMP. Therefore, the parasitic capacitance formed by the overlap between the long scan line connection portion ES and the dummy pattern DMP may be greater than the parasitic capacitance formed by the overlap between the short scan line connection portion ES and the dummy pattern DMP.

[0281] Therefore, in the second pixel area PXA2, the load values ​​of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (wherein the number of second pixels PXL2 and third pixels PXL3 arranged in the row is small) and the load values ​​of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (wherein the number of second pixels PXL2 and third pixels PXL3 arranged in the row is large) may be the same or similar.

[0282] The parasitic capacitance may be set differently according to the load value of the scan line connection portion for compensation, and the load value may be obtained by having different surface areas overlapped by the dummy pattern and the scan line connection portion.

[0283] Likewise, the difference in the load value of the light-emitting control line connection portion can be obtained by having different surface areas of overlap between the dummy pattern and the light-emitting control line connection portion.

[0284] FIG. 24 is a plan view of a second region, a third region, and an additional peripheral region according to an embodiment of the present disclosure.

[0285] Reference FIG. 1A 、 FIG. 1B 、 FIG. 2 to FIG. 10 and FIG. 24 In the right length portion of the second peripheral area PPA2, in the additional peripheral area APA, and in the left length portion of the third peripheral area PPA3, a scan line connection portion ES that connects the second scan lines S21, S22 connected to the second pixel PXL2 of the second pixel area PXA2 and the third scan lines S31, S32 connected to the third pixel PXL3 of the third pixel area PXA3 may be arranged.

[0286] The length of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (where the number of second pixels PXL2 and third pixels PXL3 arranged in the row is small) may be shorter than the length of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (where the number of second pixels PXL2 and third pixels PXL3 arranged in the row is large).

[0287] Among the scan line connection portions ES, the length of the scan line connection portion ES connected to the short second scan line S21, S22 or the third scan line S31, S32 may be greater than the length of the scan line connection portion ES connected to the long second scan line S21, S22 or the third scan line S31, S32.

[0288] The dummy cell may be provided in an area where the scan line connection portion ES or the emission control line connection portion EE overlaps the second power supply line ELVSS. The dummy cell may include a dummy pattern DMP overlapping the scan line connection portion ES. The dummy pattern DMP may have a shape extending to the right length portion of the second peripheral area PPA2 and to the left length portion of the third peripheral area PPA3.

[0289] The dummy cell may include a parasitic capacitor formed by the scan line connection portion ES and the second power supply line ELVSS and a parasitic capacitor formed by the scan line connection portion ES and the dummy pattern DMP.

[0290] In the dummy pattern DMP, among the second scan lines S21 and S22, the width of the region overlapping the scan line connection portion ES connected to the shorter scan line S21 may be greater than the width of the region overlapping the scan line connection portion ES connected to the longer second scan line S22. For example, the dummy pattern DMP may have a trapezoidal shape whose width increases as it moves away from the first pixel area PXA1.

[0291] An overlapping surface area of ​​the long scan line connection portion ES and the dummy pattern DMP may be greater than an overlapping surface area of ​​the short scan line connection portion ES and the dummy pattern DMP.

[0292] A parasitic capacitance formed by an overlap of a long scan line connection portion ES and a dummy pattern DMP may be greater than a parasitic capacitance formed by an overlap of a short scan line connection portion ES and a dummy pattern DMP.

[0293] Therefore, in the second pixel area PXA2, the load values ​​of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (wherein the number of second pixels PXL2 and third pixels PXL3 arranged in the row is small) and the load values ​​of the second scan lines S21, S22 or the third scan lines S31, S32 arranged in a row (wherein the number of second pixels PXL2 and third pixels PXL3 arranged in the row is large) may be the same or similar.

[0294] The parasitic capacitance may be set differently according to the load value of the scan line connection portion for compensation, and the load value may be obtained by having different surface areas overlapped by the dummy pattern and the scan line connection portion.

[0295] Likewise, the difference in the load value of the light-emitting control line connection portion can also be obtained by having different overlapping surface areas of the dummy pattern and the light-emitting control line connection portion.

[0296] FIG. 25 is a plan view showing a region in which dummy cells are arranged according to an embodiment of the present disclosure, FIG. 26 and FIG. 27 It is along FIG. 25 A sectional view taken along line IV-IV'.

[0297] Reference FIG. 1A 、 FIG. 1B 、 FIG. 2 to FIG. 10 and FIG. 25 to FIG. 27 In the second peripheral area PPA2, a second scan driver SDV2 and a second light emitting driver EDV2 may be provided. In addition, in the third peripheral area PPA3, a third scan driver SDV3 and a third light emitting driver EDV3 may be provided.

[0298] At least one of the dummy pattern DMP and the second power supply line ELVSS may include a plurality of open areas OP, OP' arranged such that they are spaced apart from each other.

[0299] The opening regions OP and OP' may overlap with the scan line connection portion ES or the light emission control line connection portion EE. The scan line connection portion ES or the light emission control line connection portion EE may overlap with at least two opening regions OP and OP'.

[0300] The opening areas OP and OP' can be used as laser irradiation areas for repairing short-circuit defects in the scan line connection portion ES or the emission control line connection portion EE. For example, when a short circuit occurs in the scan line connection portion ES or the emission control line connection portion EE, laser irradiation can be performed through the opening areas OP and OP' corresponding to the point where the short circuit occurred in the scan line connection portion ES or the emission control line connection portion EE. When laser irradiation is performed through the opening areas OP and OP', the scan line connection portion ES or the emission control line connection portion EE corresponding to these opening areas OP and OP' can be disconnected. Therefore, defects caused by short circuits in the scan line connection portion ES or the emission control line connection portion EE can be prevented.

[0301] In summary and review, embodiments provide a display device with consistent (e.g., uniform) brightness regardless of region. Specifically, the display device may include two or more regions having different surface areas, and dummy cells overlapping the lines in the region with the smaller surface area of ​​the two or more regions. The dummy cells compensate for differences in load values ​​between the lines in the two or more regions. In this manner, the display device provides uniform brightness across the two or more regions, regardless of the surface area or the lines thereon.

[0302] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art as of the date of filing this application that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, comprising: a substrate including a first pixel region, a second pixel region, and a third pixel region, the third pixel region being spaced apart from the second pixel region, each of the second pixel region and the third pixel region having a surface area smaller than that of the first pixel region and connected to the first pixel region; A first pixel, a second pixel, and a third pixel are respectively arranged in the first pixel area to the third pixel area; A first line, a second line, and a third line are connected to the first pixel to the third pixel, respectively; a wire connecting portion connecting the second wire and the third wire; as well as a dummy unit, disposed between the second pixel region and the third pixel region, The dummy unit includes a plurality of portions overlapping the line connection portion to form a parasitic capacitor to compensate for a load value and spaced apart from each other along a direction in which the line connection portion extends.

2. The display device according to claim 1, wherein The dummy unit includes a plurality of opening areas overlapping the line connection portion and spaced apart from each other, and The plurality of parts are separated from each other by the plurality of opening areas.

3. The display device according to claim 1, wherein: The first line provides a scan signal or a light emitting control signal to the first pixel, The second line provides the scan signal or the light emitting control signal to the second pixel, and The third line supplies the scan signal or the light emitting control signal to the third pixel.

4. The display device according to claim 1, wherein Each of the second pixel and the third pixel includes a transistor having an active pattern on the substrate, and The dummy cells are on the same layer as the active patterns and include the same material as that of the active patterns.

5. The display device according to claim 4, wherein The transistor also has: a gate electrode on the active pattern; a gate insulating film between the active pattern and the gate electrode; an interlayer insulating film including a first interlayer insulating film covering the gate electrode and a second interlayer insulating film arranged on the first interlayer insulating film; as well as a source electrode and a drain electrode disposed on the substrate and each of the source electrode and the drain electrode connected to the active pattern, and The line connection portion is between the first interlayer insulating film and the second interlayer insulating film.

6. The display device according to claim 5, further comprising a power supply line on the interlayer insulating film, in, The power supply line overlaps the line connection portion.

7. The display device according to claim 6, wherein: A first power supply voltage and a second power supply voltage are supplied to the first to third pixels, wherein the first power supply voltage is greater than the second power supply voltage, and The first power supply voltage is applied to the power supply line.

8. The display device according to claim 6, wherein: The dummy cell is connected to the power supply line through a contact hole penetrating the interlayer insulating film.

9. The display device according to claim 1, wherein The first line is longer than each of the second line and the third line.

10. The display device according to claim 1, wherein The substrate further includes a peripheral area between the second pixel area and the third pixel area, and Wherein, the wire connection portion is arranged in the peripheral area.

11. The display device according to claim 1, wherein Each of the second pixel area and the third pixel area includes a plurality of rows in which a plurality of pixels are arranged, and The line connection portion connects pixels arranged in the same row.

12. The display device according to claim 1, wherein The length of the line connection portion is longer because the number of pixels electrically connected to the second line is smaller.

13. The display device according to claim 1, wherein An overlapping area of ​​the line connection portion and the dummy cell is larger because the number of pixels electrically connected to the second line is smaller.

14. A display device, comprising: a substrate including a first pixel region, a second pixel region, and a third pixel region, the third pixel region being spaced apart from the second pixel region, each of the second pixel region and the third pixel region having a surface area smaller than that of the first pixel region and connected to the first pixel region; A first pixel, a second pixel, and a third pixel are respectively arranged in the first pixel area to the third pixel area; A first line, a second line, and a third line are connected to the first pixel to the third pixel, respectively; a wire connecting portion connecting the second wire and the third wire; as well as a dummy unit, overlapping the line connection portion to form a parasitic capacitor to compensate for a load value, and provided between the second pixel region and the third pixel region, wherein each of the second pixel and the third pixel comprises a transistor having an active pattern on the substrate, and The dummy cells are on the same layer as the active patterns and include the same material as that of the active patterns.

15. The display device according to claim 14, wherein The transistor also has: a gate electrode on the active pattern; a gate insulating film between the active pattern and the gate electrode; an interlayer insulating film including a first interlayer insulating film covering the gate electrode and a second interlayer insulating film arranged on the first interlayer insulating film; as well as a source electrode and a drain electrode disposed on the substrate and each of the source electrode and the drain electrode connected to the active pattern, and The line connection portion is between the first interlayer insulating film and the second interlayer insulating film.

16. The display device according to claim 15, further comprising a power supply line on the interlayer insulating film, in, The power supply line overlaps the line connection portion.

17. The display device according to claim 16, wherein: A first power supply voltage and a second power supply voltage are supplied to the first to third pixels, wherein the first power supply voltage is greater than the second power supply voltage, and The first power supply voltage is applied to the power supply line.

18. The display device according to claim 16, wherein: The dummy cell is connected to the power supply line through a contact hole penetrating the interlayer insulating film.

19. A display device, comprising: a substrate including a first pixel region, a second pixel region, and a third pixel region, the third pixel region being spaced apart from the second pixel region, each of the second pixel region and the third pixel region having a surface area smaller than that of the first pixel region and connected to the first pixel region; A first pixel, a second pixel, and a third pixel are respectively arranged in the first pixel area to the third pixel area; A first line, a second line, and a third line are connected to the first pixel to the third pixel, respectively; a wire connecting portion connecting the second wire and the third wire; a dummy unit, overlapping the line connection portion to form a parasitic capacitor to compensate for a load value, and disposed between the second pixel region and the third pixel region; as well as A power supply line overlaps the line connection portion.

20. The display device according to claim 19, wherein A first power supply voltage and a second power supply voltage are supplied to the first to third pixels, wherein the first power supply voltage is greater than the second power supply voltage, and The first power supply voltage is applied to the power supply line.

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