Gate driver and electroluminescent display device including the same

Abstract

The present application provides a gate driver and an electroluminescent display device including the gate driver. The gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes: a carry generation circuit, which outputs a second carry signal whose phase is later than the phase of the first carry signal based on a first clock signal and a second clock signal having different phases and a first carry signal synchronized with a pulse of one of the first clock signal and the second clock signal, and a scan generation circuit, which outputs a scan signal having a phase different from the phases of the first and second carry signals based on the first clock signal, the second clock signal and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal and the second carry signal is a P-type pulse whose voltage at the pulse interval is lower than the voltage at the non-pulse interval, and the scan signal is an N-type pulse whose voltage at the pulse interval is higher than the voltage at the non-pulse interval.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 187,927 filed on May 12, 2021 and U.S. Patent Application No. 17 / 742,011 filed on May 11, 2022, which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present disclosure relates to a gate driver and an electroluminescent display device including the gate driver. Background Art

[0004] The electroluminescent display device includes pixels arranged in a matrix form, and image data synchronized with a scan signal is provided to the pixels to adjust the brightness of the pixels. The electroluminescent display device generates a scan signal by using a gate driver including a plurality of gate levels. Each gate level of the gate driver is connected to a gate line of a display panel. Each gate level includes a plurality of transistors, and outputs a scan signal swinging between a scan-on voltage and a scan-off voltage to the gate line of the display panel.

[0005] The scanning signal should be applied to each pixel without distortion. When the scanning signal is distorted, abnormal image data may be sampled, and image quality defects may occur. In addition, the structure of the gate level should be simplified. When the structure of the gate level is complicated, it is difficult to reduce the border of the electroluminescent display device. Summary of the invention

[0006] In order to overcome the above-mentioned problems of the related art, the present disclosure may provide a gate driver and an electroluminescent display device including the same, in which a gate level configuration is simplified and a scan signal distortion is reduced.

[0007] To achieve these and other advantages and in accordance with the intent of the present disclosure, as embodied and generally described herein, a gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes: a carry generation circuit that outputs a second carry signal based on a first clock signal and a second clock signal having different phases and a first carry signal that is synchronized with a pulse of one of the first clock signal and the second clock signal, and a scan generation circuit that outputs a scan signal having a pulse different from that of the first carry signal and the second carry signal based on the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal is a P-type pulse whose voltage at a pulse interval is lower than that at a non-pulse interval, and the scan signal is an N-type pulse whose voltage at a pulse interval is higher than that at a non-pulse interval.

[0008] The second carry signal may be synchronized with a pulse of the other clock signal of the first clock signal and the second clock signal.

[0009] A pulse width of the scan signal may be determined based on a pulse width of the first clock signal and a pulse width of the second clock signal.

[0010] The pulse interval of the scanning signal may be an interval between a rising edge of the first clock signal and a falling edge of the second clock signal, and

[0011] The rising edge of the first clock signal and the falling edge of the second clock signal may be adjacent to each other.

[0012] Each of the carry generation circuit and the scan generation circuit may include a plurality of P-type transistors.

[0013] The scan generation circuit may include: a scan output node outputting the scan signal; a first transistor including a gate electrode connected to the first scan control node, a first electrode connected to the input terminal of the second clock signal, and a second electrode connected to the scan output node; a second transistor including a gate electrode connected to the second scan control node, a first electrode connected to the scan output node, and a second electrode connected to an input terminal of a gate low voltage; a third transistor including a gate electrode connected to the input terminal of the second clock signal, a first electrode connected to the input terminal of the first carry signal, and a second electrode connected to the first scan control node; a fourth transistor including a gate electrode connected to the input terminal of the first clock signal, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of a gate high voltage higher than the gate low voltage; a fifth transistor including a gate electrode connected to the first scan control node, a first electrode connected to the second scan control node, and a second electrode connected to an input terminal of the gate high voltage; and a sixth transistor including a gate electrode connected to the input terminal of the first clock signal, a first electrode connected to the second scan control node, and a second electrode connected to the input terminal of the gate low voltage.

[0014] The scan generation circuit may further include a stabilizing capacitor, which includes a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and the DC voltage terminal is an input terminal of the gate high voltage or an input terminal of the gate low voltage.

[0015] The scan generation circuit may further include a seventh transistor including a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

[0016] The scan generation circuit may further include: a bootstrap capacitor, including a first electrode connected to the scan output node and a second electrode connected to the second scan control node; and an N-type seventh transistor, including a gate electrode connected to the input terminal of the gate low voltage, a first electrode connected to the second scan control node, and a second electrode connected to the second electrodes of the fifth transistor and the sixth transistor.

[0017] The scan generation circuit may further include a stabilizing capacitor, which includes a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and the DC voltage terminal is an input terminal of the gate high voltage or an input terminal of the gate low voltage.

[0018] The scan generation circuit may further include an eighth transistor including a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

[0019] The scan generation circuit may further include: a bootstrap capacitor, including a first electrode connected to the scan output node and a second electrode connected to the second scan control node; and a seventh transistor, including a gate electrode connected to an input terminal of a gate intermediate voltage, a first electrode connected to the second scan control node, and a second electrode connected to the second electrodes of the fifth transistor and the sixth transistor, and the gate intermediate voltage is a voltage between the gate low voltage and the gate high voltage.

[0020] The scan generation circuit may further include a stabilizing capacitor, which includes a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and the DC voltage terminal is an input terminal of the gate high voltage, an input terminal of the gate low voltage, or an input terminal of the gate intermediate voltage.

[0021] The scan generation circuit may further include an eighth transistor including a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

[0022] The scan generation circuit may include: a scan output node, outputting the scan signal; a first transistor, including a gate electrode connected to the first scan control node, a first electrode connected to the input terminal of the second clock signal, and a second electrode connected to the scan output node; a second transistor, including a gate electrode connected to the second scan control node, a first electrode connected to the scan output node, and a second electrode connected to the input terminal of the gate intermediate voltage; a third transistor, including a gate electrode and a first electrode connected to the input terminal of the second clock signal, and a second electrode connected to the first scan control node; a fourth transistor, including a gate electrode connected to the input terminal of the first clock signal, a first electrode connected to the first scan control node, and a second electrode connected to a voltage higher than the gate intermediate voltage. a second electrode connected to an input terminal of a gate high voltage of a gate intermediate voltage; a fifth transistor, including a gate electrode connected to the first scan control node, a first electrode connected to a secondary node, and a second electrode connected to an input terminal of the gate high voltage; a sixth transistor, including a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the secondary node, and a second electrode connected to an input terminal of a gate low voltage lower than the gate intermediate voltage; a bootstrap capacitor, including a first electrode connected to the scan output node and a second electrode connected to the second scan control node; and a seventh transistor, including a gate electrode connected to an input terminal of the gate intermediate voltage, a first electrode connected to the second scan control node, and a second electrode connected to the secondary node.

[0023] The scan generation circuit may further include a stabilizing capacitor, which includes a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and the DC voltage terminal is an input terminal of the gate high voltage, an input terminal of the gate low voltage, or an input terminal of the gate intermediate voltage.

[0024] The scan generation circuit may further include an eighth transistor including a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

[0025] The scan generation circuit may include: a carry output node, outputting the second carry signal; a first carry transistor, including a gate electrode connected to a first carry control node, a first electrode connected to an input terminal of the first clock signal, and a second electrode connected to the carry output node; a second carry transistor, including a gate electrode connected to a second carry control node, a first electrode connected to the carry output node, and a second electrode connected to an input terminal of a gate high voltage; a third carry transistor, including a gate electrode connected to an input terminal of the second clock signal, a first electrode connected to an input terminal of the first carry signal, and a second electrode connected to a first secondary node; a fourth carry transistor, including a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the first secondary node, and a second electrode connected to a second secondary node; a fifth carry transistor, including a gate electrode connected to the second carry control node, a first electrode connected to the input terminal of the first clock signal, a first electrode connected to the first secondary node, and a second electrode connected to the second secondary node. a first electrode connected to the second secondary node, and a second electrode connected to the input terminal of the gate high voltage; a sixth carry transistor, including a gate electrode connected to the input terminal of the second clock signal, a first electrode connected to the input terminal of a gate low voltage lower than the gate high voltage, and a second electrode connected to the second carry control node; a seventh carry transistor, including a gate electrode connected to the first secondary node, a first electrode connected to the input terminal of the second clock signal, and a second electrode connected to the second carry control node; an eighth carry transistor, including a gate electrode connected to the input terminal of the gate low voltage, a first electrode connected to the first secondary node, and a second electrode connected to the first carry control node; a first carry capacitor connected between the first carry control node and the carry output node; and a second carry capacitor connected between the second carry control node and the input terminal of the gate high voltage.

[0026] In another aspect of the present disclosure, an electroluminescent display device includes: a gate line, a pixel including an N-type transistor, the N-type transistor including a gate electrode connected to the gate line, and a gate driver outputting a scan signal to the gate line.

[0027] In another aspect of the present disclosure, a gate driver may include multiple gate stages for driving multiple gate lines of a display panel, each gate stage being connected to a corresponding gate line connected to one or more transistors in the display panel, the gate stage including: a carry generation circuit including a group of first-type transistors, the carry generation circuit being configured to receive a first clock signal, a second clock signal and a first carry signal of a previous stage, and to generate a second carry signal for a next stage, the pulse interval of the second carry signal being later than the pulse interval of the first carry signal; and a scan generation circuit including another group of first-type transistors, the scan generation circuit being configured to receive the first clock signal, the second clock signal and the first carry signal, and to generate a scan signal for supplying to the one or more transistors of the second type in the display panel, wherein the pulse intervals of the first carry signal, the first clock signal and the second clock signal are configured to turn on the one or more transistors of the first type in the carry generation circuit and the scan generation circuit in a first logic state, and wherein the scan signal is configured to turn on the one or more transistors of the second type in the display panel in a second logic state.

[0028] The one group of transistors of the first type and the other group of transistors may be P-type transistors, and the one or more transistors of the second type in the display panel are N-type transistors, wherein the first logic state occurs when the voltage of a pulse interval is lower than the voltage of a non-pulse interval, and wherein the second logic state occurs when the voltage of a pulse interval is higher than the voltage of a non-pulse interval.

[0029] The one group of transistors and the another group of transistors may be configured as P-type low temperature polysilicon (LTPS) transistors, and the one or more transistors in the display panel may be configured as N-type oxide transistors.

[0030] Each gate stage may include multiple first input terminals and multiple second input terminals, wherein the multiple first input terminals for the gate stage are configured to receive the first clock signal and the multiple second input terminals for the gate stage are configured to receive the second clock signal, and the multiple first input terminals for the next gate stage are configured to receive the second clock signal and the multiple second input terminals for the next gate stage are configured to receive the first clock signal.

[0031] The pulse interval of the gate signal may be an interval between a rising edge of the first clock signal and a falling edge of the second clock signal.

[0032] The pulse interval of the gate signal may be when a non-pulse interval of the first clock signal overlaps with a non-pulse interval of the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The included drawings provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. These drawings illustrate one or more embodiments of the present disclosure and together with the description are used to explain the principles of the present disclosure. In the drawings:

[0034] Figure 1 is a schematic diagram showing an electroluminescent display device according to an embodiment of the present disclosure;

[0035] Figure 2 is a diagram schematically showing an equivalent circuit of a pixel provided on a display panel;

[0036] Figure 3 is another diagram schematically showing an equivalent circuit of a pixel provided on a display panel;

[0037] Figure 4 It shows the Figure 2 or a diagram of an N-type scanning signal of a pixel of 3;

[0038] Figure 5 It shows that the Figure 1 A diagram showing a connection configuration between gate stages in a gate driver;

[0039] Figure 6 is a diagram showing a connection concept of a gate stage and a pixel according to one embodiment of the present disclosure;

[0040] Fig. 7A is a diagram showing a phase relationship between first and second clock signals and a scan signal in odd-numbered gate stages;

[0041] Figure 7B is a diagram showing a phase relationship between first and second clock signals and a scan signal in even-numbered gate stages;

[0042] Figure 8 and Fig. 9 is a diagram showing a carry generation circuit included in a gate stage;

[0043] Fig.10 It shows Fig. 9 A diagram of the operating waveform of the carry generation circuit;

[0044] Figure 11 to Figure 22 are diagrams showing first to twelfth embodiments of a scan generation circuit connected to a carry generation circuit in a gate stage; and

[0045] Fig.23 It is shown Figure 11 to Figure 22 Illustration of the working waveform of the scan generation circuit. DETAILED DESCRIPTION

[0046] The advantages and features of the present disclosure and its implementation methods will be illustrated by the embodiments described below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the present disclosure comprehensive and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0047] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings describing the embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. The same reference numerals always refer to the same elements. In the following description, in this specification, the same elements are represented by the same reference numerals. Unless the term "only" is used, the terms "including", "having", "comprising", etc. used herein imply that other parts may be added. Unless the context clearly indicates otherwise, the singular forms "one", "an", and "the" used herein are also intended to include plural forms.

[0048] Even if not explicitly described, the elements in the various embodiments of the present disclosure should be interpreted as including errors including error margins.

[0049] When describing a positional relationship, for example, when describing a positional order as “on,” “above,” “below,” and “after,” one or more other parts may be provided between the two parts unless “just” or “directly” is used.

[0050] It should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and the second element may also be referred to as the first element.

[0051] In an embodiment of the present disclosure, the transistor described herein may include a three-electrode element having a gate, a source, and a drain. The source and drain of the transistor may switch between the source and the drain based on a voltage applied to the source and the drain. Therefore, in the following description, one of the source and the drain will be described as a first electrode, and the other of the source and the drain will be described as a second electrode.

[0052] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the following embodiments, as an example of an electroluminescent display device, an organic light-emitting display device including an organic light-emitting material will be mainly described. However, the inventive concept is not limited to the organic light-emitting display device and can be applied to an inorganic light-emitting display device including an inorganic light-emitting material.

[0053] Figure 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 is a diagram schematically showing an equivalent circuit of a pixel provided in a display panel. Figure 3 is another diagram schematically showing an equivalent circuit of a pixel provided in a display panel. Figure 4 It shows the Figure 2 or Figure 3 Illustration of the N-type scanning signal of a pixel.

[0054] refer to Figures 1 to 4 , an electroluminescent display device according to one embodiment of the present disclosure may include a display panel 100 , a timing controller 110 , a data driver 120 , a gate driver 130 , and a level shifter 150 .

[0055] refer to Figure 1 , a pixel array can be set in the display area AA of the display panel 100. Pixels PXL connected to the data lines DL and the gate lines Gla, GLb and GLc can be arranged in the form of a matrix in the pixel array. A plurality of horizontal pixel lines can be provided in the pixel array, and a plurality of pixels PXL horizontally adjacent to each other and connected to the same gate line can be arranged in each horizontal pixel line. Here, a horizontal pixel line can represent a set of pixels of a line realized by pixels PXL horizontally adjacent to each other. A set of pixels of a line can be driven simultaneously by the same gate signal SC or WC. A power line can be included in the pixel array, and the power line transmits a high-level pixel power VDDEL and a low-level pixel power VSSEL to the pixel PXL.

[0056] Each pixel PXL can be designed with a structure optimized for low-speed driving. Since the refresh interval of the image data increases in low-speed driving, the data voltage Vdata charged into the pixel PXL may not be maintained at the target level and may leak. In order to reduce the leakage of the data voltage Vdata, each of some transistors included in the pixel PXL can be implemented as an oxide thin film transistor (TFT) with good cut-off current characteristics, and another transistor of the pixel PXL can be implemented as a low-temperature polysilicon (LTPS) TFT.

[0057] As in Figure 2 and Figure 3 As in the embodiment of the present invention, each pixel PXL may include a driving transistor DT and an organic light emitting diode EL. Each pixel PXL may further include a compensation circuit for compensating for changes in the electrical characteristics of the driving transistor DT. The compensation circuit may be implemented with a plurality of switching transistors and at least one capacitor. The compensation circuit may reflect the threshold voltage of the driving transistor DT in the gate-source voltage of the driving transistor DT during pixel driving, and thus compensation may be performed so that the pixel current flowing in the driving transistor DT is not affected by changes in the threshold voltage of the driving transistor DT.

[0058] The compensation circuit may be implemented as a source follower type or a diode connection type.

[0059] Figure 2 The source follower type pixel PXL in the embodiment may include a first switching transistor ST1 connected between a gate and a source (Ng-Ns) of a driving transistor DT, a second switching transistor ST2 connected between a drain Nd of the driving transistor DT and a data line DL, and a storage capacitor Cst connected to the gate Ng of the driving transistor DT. The first switching transistor ST1 may be turned on based on a first gate signal WC provided through a first gate line GLa, and the second switching transistor ST2 may be turned on based on a second gate signal SC provided through a second gate line GLb.

[0060] Figure 3 The diode connection type pixel PXL in the embodiment may include a first switching transistor ST1 connected between the gate and source (Ng-Nd) of the driving transistor DT, a second switching transistor ST2 connected between the source Ns of the driving transistor DT and the data line DL, a storage capacitor Cst connected to the gate Ng of the driving transistor DT, and a third switching transistor ST3 connected between the storage capacitor Cst and the source Ns of the driving transistor DT. The first switching transistor ST1 may be turned on based on a first gate signal WC provided through the first gate line GLa, the second switching transistor ST2 may be turned on based on a second gate signal SC provided through the second gate line GLb, and the third switching transistor ST3 may be turned on based on a third gate signal EM provided through the third gate line GLc.

[0061] exist Figure 2 and Figure 3In the embodiment, each of the first switching transistor ST1 and the second switching transistor ST2 can be implemented as an N-type oxide TFT to reduce leakage of the data voltage Vdata and perform an accurate compensation operation. In addition, the driving transistor DT and the third switching transistor ST3 can be implemented as a P-type or N-type LTPS TFT with high electron mobility, but are not limited thereto.

[0062] The pixels PXL may include an R pixel for realizing red, a G pixel for realizing green, and a B pixel for realizing blue. The R, G, and B pixels PXL may be repeatedly and alternately arranged in one horizontal pixel line.

[0063] Figure 4 The second gate signal SC in the image may determine the charging time of each data voltage Vdata provided to the R, G, and B pixels PXL. The second gate signal SC may require a turn-on time (or pulse interval) less than one horizontal period 1H. When the turn-on time of the second gate signal SC is greater than one horizontal period 1H, image defects may occur due to sampling of abnormal data voltage Vdata. Hereinafter, for ease of description, the second gate signal may be referred to as a scan signal, and the first and third gate signals may be referred to as gate signals.

[0064] refer to Figure 1 , the data driver 120 may receive the image data DATA and the source timing control signal DDC from the timing controller 110. In response to the source timing control signal DDC, the data driver 120 may convert the image data DATA into a gamma compensation voltage to generate a data voltage Vdata, and may supply the data voltage Vdata to the data line of the display panel 100 based on the scan signal supply timing. The data driver 120 may be connected to the data line of the display panel 100 through a chip on glass (COG) process or a tape automated bonding (TAB) process. The data driver 120 may be implemented with one or more integrated circuits (ICs).

[0065] refer to Figure 1 The level shifter 150 may generate a gate timing control signal GDC110 for driving a switching transistor of a pixel based on an on / off control clock having a transistor-transistor logic (TTL) level input from a timing controller. The gate timing control signal GDC may include a start signal and a clock signal, and the start signal and the clock signal swing between an on level and an off level. The level shifter 150 may provide the gate timing control signal GDC to the gate driver 130.

[0066] refer to Figure 1The gate driver 130 may operate based on the gate timing control signal GDC input from the level shifter 150 and may generate a scan signal and a gate signal required to drive the pixel PXL. Also, the gate driver 130 may provide the scan signal and the gate signal to different gate lines.

[0067] The gate driver 130 may be directly provided on the lower substrate of the display panel 100 based on a gate in panel (GIP) type. The gate driver 130 may be provided in a non-display area (i.e., a bezel area BZ) outside the display area AA in the display panel 100. In the GIP type, the level shifter 150 may be mounted on a printed circuit board (PCB) 140 together with the timing controller 110.

[0068] refer to Figure 1 The timing controller 110 may be connected to an external host system based on various interface types known to those skilled in the art. The timing controller 110 may receive image data DATA from the host system, and may correct the image data DATA by using an image processing circuit included in the timing controller 110, and then may transmit the corrected image data to the data driver 120.

[0069] The timing controller 110 can receive timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK, and can generate an on / off control clock required for a source timing control signal DDC and a gate timing control signal GDC based on the timing signals.

[0070] Figure 5 It shows that the Figure 1 Schematic diagram of the connection configuration between gate stages in a gate driver. Figure 6 is a diagram showing a connection concept of a gate stage and a pixel according to one embodiment of the present disclosure. Fig. 7A is a diagram showing the phase relationship between the first and second clock signals and the scan signal in odd-numbered gate stages. Figure 7B is a diagram showing the phase relationship between the first and second clock signals and the scan signal in the even-numbered gate stages.

[0071] refer to Figure 5 In the gate driver 130, a plurality of gate stages ST1 to STn may be connected to each other in a cascade type so as to construct a gate shift register. Figure 5 The gate stages ST1 to STn of the embodiment can output scanning signals SC(1) to SC(n) having sequentially delayed phases. Figure 2 and 3The gate signals of the pixels PXL may be generated by other gate stages included in the gate driver 130. The following embodiments relate to gate stages ST1 to STn for generating scan signals SC(1) to SC(n).

[0072] The first gate stage ST1 among the gate stages ST1 to STn can start working based on the start signal VST. In addition, each gate stage ST2 to STn except the first gate stage ST1 can start working based on the carry output of the previous gate stage that worked before (i.e., one of the carry signals CRY(1) to CRY(n-1)).

[0073] Each gate stage ST can be provided with a gate high voltage VGH and a gate low voltage VGL through different power lines. Each gate stage ST can be further provided with a gate intermediate voltage VSL through another power line. The gate high voltage VGH can be higher than the gate low voltage VGL. The gate intermediate voltage VSL can be lower than the gate high voltage VGH and can be higher than the gate low voltage VGL.

[0074] Each gate stage ST may be provided with bi-phase clock signals CLKA and CLKB through different clock supply lines. The bi-phase clock signals CLKA and CLKB may have different phases.

[0075] Each gate stage ST may include a plurality of first input terminals receiving a first clock signal and a plurality of second input terminals receiving a second clock signal. In an odd-numbered gate stage, a clock signal CLKA may be input to the plurality of first input terminals as a first clock signal, and a clock signal CLKB may be input to the plurality of second input terminals as a second clock signal. On the other hand, in an even-numbered gate stage, a clock signal CLKB may be input to the plurality of first input terminals as a first clock signal, and a clock signal CLKA may be input to the plurality of second input terminals as a second clock signal.

[0076] Each gate stage ST may include a carry generation circuit 10 and a scan generation circuit 20. The carry generation circuit 10 may generate a carry signal CRY synchronized with one of the first clock signal and the second clock signal, and the scan generation circuit 20 may generate a scan signal SC having a different phase from the carry signal CRY. The scan generation circuit 20 may output the scan signal SC to a scan output node connected to a gate line of the display panel. The carry generation circuit 10 may output the carry signal CRY to a carry output node connected to the next stage. Since the carry output node of the carry generation circuit 10 is not connected to the gate line of the display panel, the carry signal CRY may be independent of the panel load. In other words, the carry signal CRY will not be distorted due to the panel load. As a result, the operation start time of the scan generation circuit 20 based on the carry signal CRY of the previous stage may be stabilized.

[0077] Since the carry generation circuit 10 and the scan generation circuit 20 share the two-phase clock signals CLKA and CLKB, the gate stages ST1 and STn only need two clock supply lines. When the number of clock supply lines is small, the size of the frame area required to implement the gate driver 130 will be reduced.

[0078] In one embodiment, the carry generation circuit 10 may include a group of transistors of the first type. The carry generation circuit 10 is configured to receive a carry signal CRY, a first clock signal, and a second clock signal of a previous stage, and generate a carry signal CRY for a next stage. The scan generation circuit 20 may include another group of transistors of the second type. The scan generation circuit 20 is configured to receive a first clock signal, a second clock signal, and a carry signal CRY from a previous stage, and generate a scan signal SC to a scan output node.

[0079] In one embodiment, the pulse intervals of the carry signal CRY, the first clock signal, and the second clock signal are configured to turn on one or more first type transistors in the carry generation circuit 10 and the scan generation circuit 20 in a first logic state, and the pulse intervals of the scan signal SC are configured to turn on one or more second type transistors in the display panel in a second logic state.

[0080] Specifically, the carry generation circuit 10 and the scan generation circuit 20 of each gate level ST can be implemented by a P-type LTPS TFT process with relatively simple process steps, and thus the manufacturing cost can be reduced. Therefore, the carry generation circuit 10 may include at least one group of transistors, the group of transistors being P-type transistors, and the scan generation circuit 20 may include at least another group of transistors, the other group of transistors being P-type transistors. Unlike the N-type LTPS TFT, it is possible that a lightly doped drain (LDD) structure does not need to be implemented by an additional mask process in the P-type LTPS TFT. The reason may be that although there is no LDD structure, since a plurality of carriers are holes and the electron mobility of holes in the P-type LTPS TFT is lower than that of electrons, the leakage current in the N+ boundary surface is not very large. Accordingly, in the P-type LTPS TFT, it is possible that a mask process for forming an LDD structure does not need to be added, and thus the process steps can be simplified on this basis.

[0081] refer to Figure 6 In order to drive the P-type LTPS TFT of each gate stage ST, each of the bi-phase clock signals CLKA and CLKB and the carry signal CRY may be a P-type pulse in which the voltage of the pulse interval is lower than the voltage of the non-pulse interval. Therefore, each of the bi-phase clock signals CLKA and CLKB and the carry signal CRY may be configured to turn on the P-type transistor in a first logic state, in which, for example, the voltage of the pulse interval is lower than the voltage of the non-pulse interval.

[0082] In addition, an N-type oxide TFT ( Figure 2 and Figure 3 ST2) may require an N-type scan signal SC for driving. For this purpose, the scan generation circuit 20 included in each gate stage ST can output a scan signal SC of an N-type pulse with a voltage of a pulse interval higher than a voltage of a non-pulse interval. Therefore, the scan signal SC can be configured to turn on the N-type transistor in the second logic state, in which, for example, the voltage of the pulse interval is higher than the voltage of the non-pulse interval.

[0083] Moreover, although the remainder of the specification primarily describes instances in which the first type of transistor is a P-type TFT and the second type of transistor is an N-type TFT, the embodiments are not limited thereto, and it is recognized that the present disclosure may be applied to other configurations in which a gate stage in a gate driver supplies a scan signal SC based on a first type of transistor to a second type of transistor in a display panel.

[0084] The scan generation circuit 20 can receive the P-type biphase clock signals CLKA and CLKB required for the operation of the carry generation circuit 10 to output the N-type scan signal SC. Since the scan generation circuit 20 does not need to receive an additional clock signal other than the P-type biphase clock signals CLKA and CLKB to output the N-type scan signal SC, the circuit configuration of the scan generation circuit 20 can be simplified.

[0085] The pulse width of the N-type scan signal SC output from the scan generation circuit 20 can be determined based on the pulse width of each of the first clock signal and the second clock signal constituting the P-type biphase clock signals CLKA and CLKB. The pulse width of the N-type scan signal SC output from the scan generation circuit 20 can be determined to be inversely proportional to the pulse width of each of the first clock signal and the second clock signal constituting the P-type biphase clock signals CLKA and CLKB. In one horizontal period, the pulse width of the N-type scan signal SC can be adjusted based on the design model and the design specification. In this case, when adjusting the pulse width of the P-type biphase clock signals CLKA and CLKB, the pulse width of the N-type scan signal SC can also be adjusted accordingly, and thus it is easy to change the model and specification.

[0086] The pulse interval (high voltage interval) of the N-type scan signal SC output from the scan generation circuit 20 can be the same as the overlapping interval between the non-pulse interval (high voltage interval) of the first clock signal of the P-type bi-phase clock signals CLKA and CLKB and the non-pulse interval (high voltage interval) of the second clock signal of the P-type bi-phase clock signals CLKA and CLKB.

[0087] In detail, Fig. 7A , the pulse interval (high voltage interval) of the N-type scan signal SC output from the scan generation circuit 20 of the odd-numbered stage may be a first interval P-INT between a rising edge RE of the first clock signal CLKA of the P-type bi-phase clock signals CLKA and CLKB and a falling edge FE of the second clock signal CLKB of the P-type bi-phase clock signals CLKA and CLKB. In this case, the rising edge RE of the first clock signal CLKA may be adjacent to the falling edge FE of the second clock signal CLKB.

[0088] In addition, Figure 7B, the pulse interval (high voltage interval) of the N-type scan signal SC output from the scan generation circuit 20 of the even-numbered stage may be the second interval P-INT between the rising edge RE of the first clock signal CLKB of the P-type biphase clock signals CLKA and CLKB and the falling edge FE of the second clock signal CLKA of the P-type biphase clock signals CLKA and CLKB. In this case, the rising edge RE of the first clock signal CLKB may be adjacent to the falling edge FE of the second clock signal CLKA.

[0089] Detailed embodiments of the carry generation circuit 10 and the scan generation circuit 20 constituting the gate stage ST will be described below. In the following embodiments, the clock signal CLKA will be described as a first clock signal and the clock signal CLKB will be described as a second clock signal. However, the concept of the present invention can be applied to a case where the clock signal CLKB is the first clock signal and the clock signal CLKA is the second clock signal.

[0090] Figure 8 and Fig. 9 is a diagram showing a carry generation circuit included in a gate stage. Fig.10 It shows Fig. 9 Illustration of the operating waveform of the carry generation circuit.

[0091] refer to Figure 8 and Fig. 9 According to the present embodiment, the carry generation circuit 10 may include a first carry transistor T1, a second carry transistor T2, a first carry capacitor CQ and a node controller NCON. In addition, the carry generation circuit 10 may generate a second carry signal CRY(n) (the signal is a P-type pulse) and may output the second carry signal CRY(n) to the next gate level through the carry output node Nx.

[0092] A gate electrode of the first carry transistor T1 may be connected to the first carry control node Q, a first electrode of the first carry transistor T1 may be connected to an input terminal of the first clock signal CLKA, and a second electrode of the first carry transistor T1 may be connected to the carry output node Nx.

[0093] A gate electrode of the second carry transistor T2 may be connected to the second carry control node QB, a first electrode of the second carry transistor T2 may be connected to the carry output node Nx, and a second electrode of the second carry transistor T2 may be connected to the input terminal of the gate high voltage VGH.

[0094] The first carry capacitor CQ may be connected to the first carry control node Q and the carry output node Nx.

[0095] The node controller NCON may control a voltage of the first carry control node Q and a voltage of the second carry control node QB based on the first and second clock signals CLKA and CLKB and a first carry signal CRY(n-1) inputted from a previous gate stage. Fig. 9 The node controller NCON in may include third to eighth carry transistors T3 to T7 and Ta1 and a second carry capacitor CQB.

[0096] A gate electrode of the third carry transistor T3 may be connected to the input terminal of the second clock signal CLKB, a first electrode of the third carry transistor T3 may be connected to the input terminal of the first carry signal CRY(n-1), and a second electrode of the third carry transistor T3 may be connected to the first secondary node Q1.

[0097] A gate electrode of the fourth carry transistor T4 may be connected to the input terminal of the first clock signal CLKA, a first electrode of the fourth carry transistor T4 may be connected to the first secondary node Q1, and a second electrode of the fourth carry transistor T4 may be connected to the second secondary node Q2.

[0098] A gate electrode of the fifth carry transistor T5 may be connected to the second carry control node QB, a first electrode of the fifth carry transistor T5 may be connected to the second secondary node Q2, and a second electrode of the fifth carry transistor T5 may be connected to the input terminal of the gate high voltage VGH.

[0099] A gate electrode of the sixth carry transistor T6 may be connected to the input terminal of the second clock signal CLKB, a first electrode of the sixth carry transistor T6 may be connected to the input terminal of a gate low voltage VGL lower than the gate high voltage VGH, and a second electrode of the sixth carry transistor T6 may be connected to the second secondary node QB.

[0100] A gate electrode of the seventh carry transistor T7 may be connected to the first secondary node Q1 , a first electrode of the seventh carry transistor T7 may be connected to the input terminal of the second clock signal CLKB, and a second electrode of the seventh carry transistor T7 may be connected to the second carry control node QB.

[0101] A gate electrode of the eighth carry transistor Ta1 may be connected to the input terminal of the gate low voltage VGL, a first electrode of the eighth carry transistor Ta1 may be connected to the first secondary node Q1 , and a second electrode of the eighth carry transistor Ta1 may be connected to the first carry control node Q.

[0102] The second carry capacitor CQB may be connected between the second carry control node QB and an input terminal of the gate low voltage VGL.

[0103] All transistors included in the carry generation circuit 10 may be implemented as P-type LTPS TFTs, and each of the first and second clock signals CLKA and CLKB and the first carry signal CRY(n-1) may be a P-type pulse swinging between a gate high voltage VGH and a gate low voltage VGL.

[0104] refer to Fig.10 , the first carry signal CRY(n-1) may be synchronized with the first pulse of the second clock signal CLKB, and the second carry signal CRY(n) may be synchronized with the first pulse of the first clock signal CLKA. The first pulse of the first clock signal CLKA may be a phase later than the first pulse of the second clock signal CLKB. Therefore, the phase of the second carry signal CRY(n) may be later than the phase of the first carry signal CRY(n-1).

[0105] The voltage of the first carry control node Q may be lowered to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input in synchronization with the first pulse of the second clock signal CLKB, and then, the voltage of the first carry control node Q may be raised to the gate high voltage VGH by the first carry signal CRY(n-1) of the gate high voltage VGH input in synchronization with the second pulse after the first pulse of the second clock signal CLKB. The voltage of the first carry control node Q may be bootstrapped to a voltage lower than the gate low voltage VGL synchronized with the first pulse of the first clock signal CLKA, and then may be raised to the gate low voltage VGL.

[0106] The voltage of the second carry control node QB may maintain the gate high voltage VGH only in an interval between the first pulse and the second pulse of the second clock signal CLKB, and may maintain the gate low voltage VGL in other intervals.

[0107] On the other hand, the first carry transistor T1 and the second carry transistor T2 can be turned on / off based on the voltages of the first carry control node Q and the second carry control node QB, and thus, the P-type second carry signal CRY(n) synchronized with the first pulse of the first clock signal CLKA can be output to the carry output node Nx.

[0108] Fig.11 is a diagram showing a first embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0109] refer to Fig.11According to the first embodiment, the scan generation circuit 20-1 may include a plurality of P-type transistors (e.g., first to eighth transistors) T8 to T13, and it may also generate a scan signal SC(n) (the scan signal SC(n) is an N-type pulse), and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0110] The first transistor T8 can be turned on / off by the voltage of the first scan control node QBN. The gate electrode of the first transistor T8 can be connected to the first scan control node QBN, the first electrode of the first transistor T8 can be connected to the input terminal of the second clock signal CLKB, and the second electrode of the first transistor T8 can be connected to the scan output node Ny.

[0111] The second transistor T9 can be turned on / off by the voltage of the second scan control node QN. The gate electrode of the second transistor T9 can be connected to the second scan control node QN, the first electrode of the second transistor T9 can be connected to the scan output node Ny, and the second electrode of the second transistor T9 can be connected to the input terminal of the gate low voltage VGL.

[0112] The third transistor T10 can be turned on / off based on the second clock signal CLKB. The gate electrode of the third transistor T10 can be connected to the input terminal of the second clock signal CLKB, the first electrode of the third transistor T10 can be connected to the input terminal of the first carry signal CRY(n-1), and the second electrode of the third transistor T10 can be connected to the first scan control node QBN.

[0113] The fourth transistor T11 can be turned on / off by the first clock signal CLKA. A gate electrode of the fourth transistor T11 can be connected to the input terminal of the first clock signal CLKA, a first electrode of the fourth transistor T11 can be connected to the first scan control node QBN, and a second electrode of the fourth transistor T11 can be connected to the input terminal of the gate high voltage VGH higher than the gate low voltage VGL.

[0114] The fifth transistor T12 can be turned on / off by the voltage of the first scan control node QBN. The gate electrode of the fifth transistor T12 can be connected to the first scan control node QBN, the first electrode of the fifth transistor T12 can be connected to the second scan control node QN, and the second electrode of the fifth transistor T12 can be connected to the input terminal of the gate high voltage VGH.

[0115] The sixth transistor T13 can be turned on / off by the first clock signal CLKA. A gate electrode of the sixth transistor T13 can be connected to the input terminal of the first clock signal CLKA, a first electrode of the sixth transistor T13 can be connected to the second scan control node QN, and a second electrode of the sixth transistor T13 can be connected to the input terminal of the gate low voltage VGL.

[0116] refer to Fig.23 The driving waveform of the first scan control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input in synchronization with the first pulse of the second clock signal CLKB, and then the voltage of the first scan control node QBN can be increased to the gate high voltage VGH in synchronization with the second pulse of the first clock signal CLKA after the first pulse. In other words, the voltage of the first scan control node QBN can be reduced to the gate low voltage VGL in synchronization with the falling edge FE of the first pulse, and then can be increased to the gate high voltage VGH in synchronization with the falling edge FE of the second pulse.

[0117] The voltage of the second scan control node QN may be shifted to be opposite to the voltage of the first scan control node QBN. The voltage of the second scan control node QN may increase to the gate high voltage VGH in synchronization with the falling edge FE of the first pulse, and then may decrease to the gate low voltage VGL in synchronization with the falling edge FE of the second pulse.

[0118] On the other hand, the first and second transistors T8 and T9 can be turned on / off based on the voltages of the first and second scan control nodes QBN and QN, and thus can have a gate high voltage VGH only in the interval between the rising edge RE of the second pulse and the falling edge FE of the first pulse adjacent to each other, and can output an N-type pulse (i.e., the scan signal SC(n)) with a gate low voltage VGL to the scan output node Ny in other intervals.

[0119] Fig.12 is a diagram showing a second embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0120] refer to Fig.12 According to the second embodiment, the scan generation circuit 20-2 may include a plurality of P-type LTPS transistors T8 to T13, and further, it may generate a scan signal SC(n) (which is an N-type pulse), and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0121] and Fig.11Compared with the scan generation circuit 20-1 of the embodiment, the scan generation circuit 20-2 according to the second embodiment is different in that the scan generation circuit 20-2 further includes a stabilizing capacitor CX connected to the first scan control node QBN. In addition to the stabilizing capacitor CX, the other elements of the scan generation circuit 20-2 according to the second embodiment are the same as those of the embodiment. Fig.11 Those elements of the scan generation circuit 20-1 may be substantially the same.

[0122] A first electrode of the stabilization capacitor CX may be connected to the first scan control node QBN, and a second electrode of the stabilization capacitor CX may be connected to a direct current (DC) voltage terminal DC. Fig.23 The driving waveform of the first scan control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). After the second clock signal CLKB is reversed from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the stabilization capacitor CX can stably maintain the gate low voltage of the first scan control node QBN for a predetermined time.

[0123] The DC voltage terminal DC can be connected to an input terminal of the gate high voltage VGH or an input terminal of the gate low voltage VGL, and in this case, the number of power supplies required for the scan generation circuit 20-2 can be minimized. The DC voltage terminal DC can be connected to a DC power supply different from the gate high voltage VGH and the gate low voltage VGL.

[0124] Fig.13 is a diagram showing a third embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0125] refer to Fig.13 According to the third embodiment, the scan generation circuit 20-3 may include a plurality of P-type LTPS transistors T8 to T13, and further it may generate a scan signal SC(n) (which is an N-type pulse), and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0126] and Fig.11 Compared with the scan generation circuit 20-1 of the present invention, the scan generation circuit 20-3 according to the third embodiment is different in that the scan generation circuit 20-3 further includes a seventh transistor T14 connected to the first scan control node QBN. In addition to the seventh transistor T14, the other elements of the scan generation circuit 20-3 according to the third embodiment are the same as those of the present invention. Fig.11 Those elements of the scan generation circuit 20-1 may be substantially the same.

[0127] The gate electrode of the seventh transistor T14 may be connected to the second scan control node QN, the first electrode of the eighth transistor T14 may be connected to the first scan control node QBN, and the second electrode of the seventh transistor T14 may be connected to the input terminal of the gate low voltage VGL. The seventh transistor T14 may be implemented as an N-type oxide transistor to stabilize the voltage of the first scan control node QBN.

[0128] refer to Fig.23 The driving waveform of the first scan control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). At this time, since the fifth transistor T12 is turned on, the voltage of the second scan control node QN can be increased to the gate high voltage VGH. After the second clock signal CLKB is reversed from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the seventh transistor T14 can remain in the on state based on the gate high voltage VGH of the second scan control node QN, and thereby the gate low voltage VGL of the first scan control node QBN can be stably maintained for a predetermined time.

[0129] Fig.14 is a diagram showing a fourth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0130] refer to Fig.14 According to the fourth embodiment, the scan generation circuit 20-4 may include a plurality of P-type LTPS transistors T8 to T13, and further, it may generate a scan signal SC(n) (which is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0131] and Fig.11 Compared with the scan generation circuit 20-1 of the fourth embodiment, the scan generation circuit 20-4 according to the fourth embodiment is different in that the scan generation circuit 20-4 further includes a bootstrap capacitor Cbst and a seventh transistor Ta connected to the second scan control node QN. In addition to the bootstrap capacitor Cbst and the seventh transistor Ta, the other elements of the scan generation circuit 20-4 according to the fourth embodiment are the same as those of the present invention. Fig.11 Those elements of the scan generation circuit 20-1 may be substantially the same.

[0132] A first electrode of the bootstrap capacitor Cbst may be connected to the scan output node Ny, and a second electrode of the bootstrap capacitor Cbst may be connected to the second scan control node QN. A gate electrode of the seventh transistor Ta may be connected to an input terminal of the gate low voltage VGL, a first electrode of the seventh transistor Ta may be connected to the second scan control node QN, and a second electrode of the seventh transistor Ta may be connected to the secondary node QN1. Second electrodes of the fifth transistor T12 and the sixth transistor T13 may be further connected to the secondary node QN1.

[0133] refer to Fig.23 The driving waveform of the first scan control node QBN and the voltage of the second scan control node QN can be changed to be opposite to each other. The first transistor T8 and the second transistor T9 can be turned on / off based on the voltage of the first scan control node QBN and the second scan control node QN, and thus can have a gate high voltage VGH only in the interval between the rising edge RE of the second clock signal CLKB and the falling edge FE of the first clock signal CLKA, and can output the N-type scan signal SC(n) having the gate low voltage VGL to the scan output node Ny in other intervals.

[0134] When the second transistor T9 is turned on, the bootstrap capacitor Cbst and the seventh transistor Ta can bootstrap the voltage of the second scan control node QN to a voltage lower than the gate low voltage VGL. When the voltage of the second scan control node QN is lower than the gate low voltage VGL, the electrical connection between the second scan control node QN and the secondary node QN1 is disconnected by the turned-off seventh transistor Ta, and thus the bootstrap operation can be stably implemented.

[0135] Based on this bootstrap operation, the falling time of the N-type scan signal SC(n) (ie, the time when the gate high voltage is converted to the gate low voltage) can be minimized. In other words, the waveform of the N-type scan signal SC(n) can be prevented from being distorted.

[0136] Fig.15 is a diagram showing a fifth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0137] refer to Fig.15 According to the fifth embodiment, the scan generation circuit 20-5 may include a plurality of P-type LTPS transistors T8 to T13 and Ta, and further it may generate a scan signal SC(n) (which is an N-type pulse), and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0138] and Fig.14Compared with the scan generation circuit 20-4 of the present invention, the scan generation circuit 20-5 according to the fifth embodiment is different in that the scan generation circuit 20-5 further includes a stabilization capacitor CX connected to the first scan control node QBN. In addition to the stabilization capacitor CX, other elements of the scan generation circuit 20-5 according to the fifth embodiment are the same as those of the present invention. Fig.14 Those elements of the scan generation circuit 20-4 may be substantially the same.

[0139] A first electrode of the stabilization capacitor CX may be connected to the first scan control node QBN, and a second electrode of the stabilization capacitor CX may be connected to the DC voltage terminal DC. Fig.23 The driving waveform of the gate low voltage VGL is synchronously inputted by the first pulse of the second clock signal CLKB (i.e., the gate low voltage having the on-level) through the first carry signal CRY(n-1), and the voltage of the first scan control node QBN can be reduced to the gate low voltage VGL. In a predetermined time after the second clock signal CLKB is reversed from the on-level (i.e., the gate low voltage) to the off-level (i.e., the gate high voltage), the stabilization capacitor CX can stably maintain the gate low voltage VGL of the first scan control node QBN.

[0140] The DC voltage terminal DC can be connected to an input terminal of the gate high voltage VGH or an input terminal of the gate low voltage VGL, and in this case, the number of power supplies required for the scan generation circuit 20-5 can be minimized. The DC voltage terminal DC can be connected to a DC power supply different from the gate high voltage VGH and the gate low voltage VGL.

[0141] Fig.16 is a diagram showing a sixth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0142] refer to Fig.16 According to the sixth embodiment, the scan generation circuit 20-6 may include a plurality of P-type LTPS transistors T8 to T13 and Ta. In addition, it may also generate a scan signal SC(n) (which is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0143] and Fig.14 Compared with the scan generation circuit 20-4 of the embodiment, the scan generation circuit 20-6 according to the sixth embodiment is different in that the scan generation circuit 20-6 further includes an eighth transistor T14 connected to the first scan control node QBN. In addition to the eighth transistor T14, the other elements of the scan generation circuit 20-6 according to the sixth embodiment are the same as those of the embodiment. Fig.14 Those elements in the scan generation circuit 20-4 may be substantially the same.

[0144] The gate electrode of the eighth transistor T14 may be connected to the second scan control node QN, the first electrode of the seventh transistor T14 may be connected to the first scan control node QBN, and the second electrode of the eighth transistor T14 may be connected to the input terminal of the gate low voltage VGL. The eighth transistor T14 may be implemented as an N-type oxide transistor to stabilize the voltage of the first scan control node QBN.

[0145] refer to Fig.23 The driving waveform of the first scanning control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). At this time, since the fifth transistor T12 and the seventh transistor Ta are turned on, the voltage of the second scanning control node QN can be increased to the gate high voltage VGH. After the second clock signal CLKB is reversed from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the eighth transistor T14 can remain in the on state based on the gate high voltage VGH of the second scanning control node QN, and thus the gate low voltage VGL of the first scanning control node QBN can be stably maintained for a predetermined time.

[0146] Fig.17 is a diagram showing a seventh embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0147] refer to Fig.17 According to the seventh embodiment, the scan generation circuit 20-7 may include a plurality of P-type LTPS transistors T8 to T13. In addition, it may generate a scan signal SC(n) (which is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0148] and Fig.11 Compared with the scan generation circuit 20-1 of the embodiment, the scan generation circuit 20-7 according to the seventh embodiment is different in that the scan generation circuit 20-7 further includes a bootstrap capacitor Cbst and a seventh transistor Ta connected to the second scan control node QN. In addition to the bootstrap capacitor Cbst and the seventh transistor Ta, the other elements of the scan generation circuit 20-7 according to the seventh embodiment are the same as those of the embodiment. Fig.11 Those elements of the scan generation circuit 20-1 may be substantially the same.

[0149] The first electrode of the bootstrap capacitor Cbst may be connected to the scan output node Ny, and the second electrode of the bootstrap capacitor Cbst may be connected to the second scan control node QN. The gate electrode of the seventh transistor Ta may be connected to the input terminal of the gate intermediate voltage VSL, the first electrode of the seventh transistor Ta may be connected to the second scan control node QN, and the second electrode of the seventh transistor Ta may be connected to the secondary electrode QN1. The second electrodes of the fifth and sixth transistors T12 and T13 may be further connected to the secondary electrode QN1. The gate intermediate voltage VSL may be higher than the gate low voltage VGL and lower than the gate high voltage VGH. The gate intermediate voltage VSL may be a voltage between the gate low voltage VGL and the gate high voltage VGH.

[0150] refer to Fig.23 The driving waveform of the first scan control node QBN and the voltage of the second scan control node QN can be changed to be opposite to each other. The first and second transistors T8 and T9 can be turned on / off based on the voltages of the first scan control node QBN and the second scan control node QN, and thus can have a gate high voltage VGH only in an interval between a rising edge RE of the second clock signal CLKB and a falling edge FE of the first clock signal CLKA, and can output an N-type scan signal SC(n) having a gate low voltage VGL to the scan output node Ny in other intervals.

[0151] When the second transistor T9 is turned on, the bootstrap capacitor Cbst and the seventh transistor Ta can bootstrap the voltage of the second scan control node QN to a voltage lower than the gate low voltage VGL. When the voltage of the second scan control node QN is lower than the gate low voltage VGL, the electrical connection between the second scan control node QN and the secondary node QN1 is disconnected by the seventh transistor Ta that is turned off, and thus the bootstrap operation can be stably implemented. In addition, when the gate intermediate voltage VSL higher than the gate low voltage VSL is applied to the gate electrode of the seventh transistor Ta, the bootstrap operation can be stably maintained for a long time through the enhanced reverse bias applied by the seventh transistor Ta. .

[0152] Based on this bootstrap operation, the falling time of the N-type scan signal SC(n) (ie, the time for the gate high voltage to switch to the gate low voltage) can be minimized. In other words, the waveform distortion of the N-type scan signal SC(n) can be prevented.

[0153] Fig.18 is a diagram showing an eighth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0154] refer to Fig.18According to the eighth embodiment, the scan generation circuit 20-8 may include a plurality of P-type LTPS transistors T8 to T13 and Ta. In addition, it may also generate a scan signal SC(n) (which is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0155] and Fig.17 Compared with the scan generation circuit 20-7 of the eighth embodiment, the scan generation circuit 20-8 according to the eighth embodiment is different in that the scan generation circuit 20-8 further includes a stabilizing capacitor CX connected to the first scan control node QBN. In addition to the stabilizing capacitor CX, the other elements of the scan generation circuit 20-8 according to the eighth embodiment are the same as those of the first embodiment. Fig.17 Those elements of the scan generation circuit 20-7 may be substantially the same.

[0156] A first electrode of the stabilization capacitor CX may be connected to the first scan control node QBN, and a second electrode of the stabilization capacitor CX may be connected to the DC voltage terminal DC. Fig.23 The driving waveform of the first scan control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). After the second clock signal CLKB is inverted from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the stabilization capacitor CX can stably maintain the gate low voltage VGL of the first scan control node QBN for a predetermined time.

[0157] The DC voltage terminal DC may be connected to an input terminal of the gate high voltage VGH or an input terminal of the gate low voltage VGL, and in this case, the number of power supplies required for the scan generation circuit 20-5 may be minimized. The DC voltage terminal DC may be connected to a DC power supply different from the gate high voltage VGH and the gate low voltage VGL.

[0158] Fig.19 is a diagram showing a ninth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0159] refer to Fig.19 According to the ninth embodiment, the scan generation circuit 20-9 may include a plurality of P-type LTPS transistors T8 to T13 and Ta. In addition, it may also generate a scan signal SC(n) (which is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0160] and Fig.17Compared with the scan generation circuit 20-7 of the present invention, the scan generation circuit 20-9 according to the ninth embodiment is different in that the scan generation circuit 20-9 further includes an eighth transistor T14 connected to the first scan control node QBN. In addition to the eighth transistor T14, the other elements of the scan generation circuit 20-7 according to the ninth embodiment are the same as those of the present invention. Fig.17 Those elements of the scan generation circuit 20-7 may be substantially the same.

[0161] The gate electrode of the eighth transistor T14 may be connected to the second scan control node QN, the first electrode of the seventh transistor T14 may be connected to the first scan control node QBN, and the second electrode of the eighth transistor T14 may be connected to the input terminal of the gate low voltage VGL. The eighth transistor T14 may be implemented as an N-type oxide transistor to stabilize the voltage of the first scan control node QBN.

[0162] refer to Fig.23 The driving waveform of the first scanning control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). At this time, since the fifth transistor T12 and the seventh transistor Ta are turned on, the voltage of the second scanning control node QN can be increased to the gate high voltage VGH. After the second clock signal CLKB is reversed from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the eighth transistor T14 can remain in the on state based on the gate high voltage VGH of the second scanning control node QN, and thus the gate low voltage VGL of the first scanning control node QBN can be stably maintained for a predetermined time.

[0163] Fig. 20 is a diagram showing a tenth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0164] refer to Fig. 20 According to the tenth embodiment, the scan generation circuit 20-10 may include a plurality of P-type LTPS transistors T8 to T13 and Ta and a bootstrap capacitor Cbst. In addition, it may generate a scan signal SC(n) (which is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0165] and Fig.17 The scan generation circuit 20-10 according to the tenth embodiment is different from the scan generation circuit 20-7 according to the embodiment except for the connection configuration of the second transistor T9. Fig.17 The scan generation circuits 20 - 7 may be substantially the same.

[0166] The second transistor T9 can be turned on / off with the voltage of the second scan control node QN. The gate electrode of the second transistor T9 can be connected to the second scan control node QN, the first electrode of the second transistor T9 can be connected to the scan output node Ny, and the second electrode of the second transistor T9 can be connected to the input end of the gate intermediate voltage VSL. The gate intermediate voltage VSL can be higher than the gate low voltage VGL and lower than the gate high voltage VGH. The gate intermediate voltage VSL can be a voltage between the gate low voltage VGL and the gate high voltage VGH.

[0167] Since the second electrode of the second transistor T9 is connected to the input terminal for the gate intermediate voltage VSL, the N-type scan signal SC(n) can swing between the gate high voltage VGH and the gate intermediate voltage VSL. The gate intermediate voltage VSL of the N-type scan signal SC(n) can be a voltage for turning off the N-type second switch transistor ST2 included in the pixel. The gate low voltage VGL can be a voltage that is too low to turn off the second switch transistor ST2. When the second electrode of the second transistor T9 is connected to the input terminal of the gate intermediate voltage VSL, the swing width, power consumption and fall time of the N-type scan signal SC(n) are reduced.

[0168] Fig.21 is a diagram showing an eleventh embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0169] refer to Fig.21 According to the eleventh embodiment, the scan generation circuit 20-11 may include a plurality of P-type LTPS transistors T8 to T13 and Ta and a bootstrap capacitor Cbst. In addition, it may also generate a scan signal SC(n) (the scan signal SC(n) is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0170] and Fig. 20 Compared with the scan generation circuit 20-10 of the embodiment of the present invention, the scan generation circuit 20-11 according to the eleventh embodiment may be different in that the scan generation circuit 20-11 further includes a stabilization capacitor CX connected to the first scan control node QBN. In addition to the stabilization capacitor CX, other elements of the scan generation circuit 20-11 according to the eleventh embodiment are the same as those of the embodiment of the present invention. Fig. 20 Those elements of the scan generation circuit 20-10 may be substantially the same.

[0171] A first electrode of the stabilization capacitor CX may be connected to the first scan control node QBN, and a second electrode of the stabilization capacitor CX may be connected to the DC voltage terminal DC. Fig.23The driving waveform of the first scan control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). After the second clock signal CLKB is inverted from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the stabilization capacitor CX can stably maintain the gate low voltage VGL of the first scan control node QBN for a predetermined time.

[0172] The DC voltage terminal DC can be connected to an input terminal of the gate high voltage VGH, an input terminal of the gate low voltage VGL, or an input terminal of the gate intermediate voltage VSL, and in this case, the number of power supplies required for the scan generation circuit 20-5 can be minimized. The DC voltage terminal DC can be connected to a DC power supply different from the gate high voltage VGH, the gate low voltage VGL, and the gate intermediate voltage VSL.

[0173] Fig. 22 is a diagram showing a twelfth embodiment of a scan generation circuit connected to a carry generation circuit in a gate stage.

[0174] refer to Fig. 22 According to the twelfth embodiment, the scan generation circuit 20-12 may include a plurality of P-type LTPS transistors T8 to T13 and Ta and a bootstrap capacitor Cbst. In addition, it may also generate a scan signal SC(n) (the scan signal SC(n) is an N-type pulse) and may output the scan signal SC(n) to the gate line through the scan output node Ny.

[0175] and Fig. 20 Compared with the scan generation circuit 20-10 of the embodiment, the scan generation circuit 20-12 according to the twelfth embodiment is different in that the scan generation circuit 20-12 further includes an eighth transistor T14 connected to the first scan control node QBN. In addition to the eighth transistor T14, the other elements of the scan generation circuit 20-12 according to the twelfth embodiment are the same as those of the embodiment. Fig. 20 Those elements of the scan generation circuit 20-10 may be substantially the same.

[0176] The gate electrode of the eighth transistor T14 may be connected to the second scan control node QN, the first electrode of the seventh transistor T14 may be connected to the first scan control node QBN, and the second electrode of the eighth transistor T14 may be connected to the input terminal of the gate low voltage VGL. The eighth transistor T14 may be implemented as an N-type oxide transistor to stabilize the voltage of the first scan control node QBN.

[0177] refer to Fig.23The driving waveform of the first scan control node QBN can be reduced to the gate low voltage VGL by the first carry signal CRY(n-1) of the gate low voltage VGL input synchronously with the first pulse of the second clock signal CLKB (i.e., the gate low voltage with the on level). At this time, since the fifth transistor T12 and the seventh transistor Ta are turned on, the voltage of the second scan control node QN can be increased to the gate high voltage VGH. After the second clock signal CLKB is reversed from the on level (i.e., the gate low voltage) to the off level (i.e., the gate high voltage), the eighth transistor T14 can remain in the on state based on the gate high voltage VGH of the second scan control node QN, and thus the gate low voltage VGL of the first scan control node QBN can be stably maintained for a predetermined time.

[0178] In the gate driver and the electroluminescent display device including the gate driver according to the embodiments of the present disclosure, the configuration of the gate stage can be simplified, and thus the frame size of the display panel can be reduced, thereby reducing the distortion of the scan signal.

[0179] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0180] While the present disclosure has been particularly shown and described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined in the following claims.

Claims

1. A gate driver comprising a plurality of gate stages, each of the plurality of gate stages comprising: a carry generation circuit that outputs a second carry signal having a phase later than that of the first carry signal based on a first clock signal and a second clock signal having different phases and a first carry signal synchronized with a pulse of one of the first clock signal and the second clock signal; as well as a scan generation circuit that outputs a scan signal having a phase different from that of the first carry signal and the second carry signal based on the first clock signal, the second clock signal, and the first carry signal, wherein each of the first clock signal, the second clock signal, the first carry signal and the second carry signal is a P-type pulse whose voltage at a pulse interval is lower than that at a non-pulse interval, and The scanning signal is an N-type pulse in which the voltage of the pulse interval is higher than the voltage of the non-pulse interval, wherein the pulse interval of the scanning signal is the interval between the rising edge of the first clock signal and the falling edge of the second clock signal, and The rising edge of the first clock signal and the falling edge of the second clock signal are adjacent to each other. 2 . The gate driver of claim 1 , wherein the second carry signal is synchronized with a pulse of the other clock signal of the first clock signal and the second clock signal. 3 . The gate driver of claim 1 , wherein a pulse width of the scan signal is determined based on a pulse width of the first clock signal and a pulse width of the second clock signal. 4 . The gate driver of claim 1 , wherein each of the carry generation circuit and the scan generation circuit comprises a plurality of P-type transistors.

5. The gate driver of claim 1 , wherein the scan generation circuit comprises: Scanning output nodes to output the scanning signal; a first transistor including a gate electrode connected to a first scan control node, a first electrode connected to an input terminal of the second clock signal, and a second electrode connected to the scan output node; a second transistor including a gate electrode connected to the second scan control node, a first electrode connected to the scan output node, and a second electrode connected to an input terminal of a gate low voltage; a third transistor including a gate electrode connected to an input terminal of the second clock signal, a first electrode connected to an input terminal of the first carry signal, and a second electrode connected to the first scan control node; a fourth transistor including a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of a gate high voltage higher than the gate low voltage; a fifth transistor including a gate electrode connected to the first scan control node, a first electrode connected to the second scan control node, and a second electrode connected to an input terminal of the gate high voltage; as well as A sixth transistor includes a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the second scan control node, and a second electrode connected to an input terminal of the gate low voltage.

6. The gate driver of claim 5 , wherein the scan generation circuit further comprises a stabilizing capacitor including a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and The DC voltage terminal is an input terminal of the gate high voltage or an input terminal of the gate low voltage.

7. The gate driver of claim 5, wherein the scan generation circuit further comprises a seventh transistor, the seventh transistor comprising a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

8. The gate driver of claim 5, wherein the scan generation circuit further comprises: a bootstrap capacitor including a first electrode connected to the scan output node and a second electrode connected to the second scan control node; as well as The N-type seventh transistor includes a gate electrode connected to the input terminal of the gate low voltage, a first electrode connected to the second scan control node, and a second electrode connected to the second electrodes of the fifth transistor and the sixth transistor.

9. The gate driver of claim 8, wherein the scan generation circuit further comprises a stabilizing capacitor including a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and The DC voltage terminal is an input terminal of the gate high voltage or an input terminal of the gate low voltage.

10. The gate driver of claim 8, wherein the scan generation circuit further comprises an eighth transistor, the eighth transistor comprising a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

11. The gate driver of claim 5, wherein the scan generation circuit further comprises: a bootstrap capacitor including a first electrode connected to the scan output node and a second electrode connected to the second scan control node; as well as a seventh transistor including a gate electrode connected to an input terminal of a gate intermediate voltage, a first electrode connected to the second scan control node, and a second electrode connected to the second electrodes of the fifth transistor and the sixth transistor, and The gate middle voltage is a voltage between the gate low voltage and the gate high voltage.

12. The gate driver of claim 11 , wherein the scan generation circuit further comprises a stabilization capacitor including a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and The DC voltage terminal is an input terminal of the gate high voltage, an input terminal of the gate low voltage, or an input terminal of the gate intermediate voltage.

13. The gate driver of claim 11, wherein the scan generation circuit further comprises an eighth transistor, the eighth transistor comprising a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

14. The gate driver of claim 1, wherein the scan generation circuit comprises: Scanning output nodes to output the scanning signal; a first transistor including a gate electrode connected to a first scan control node, a first electrode connected to an input terminal of the second clock signal, and a second electrode connected to the scan output node; a second transistor including a gate electrode connected to the second scan control node, a first electrode connected to the scan output node, and a second electrode connected to an input terminal of a gate intermediate voltage; a third transistor including a gate electrode and a first electrode connected to an input terminal of the second clock signal, and a second electrode connected to the first scan control node; a fourth transistor including a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of a gate high voltage higher than the gate intermediate voltage; a fifth transistor including a gate electrode connected to the first scan control node, a first electrode connected to the secondary node, and a second electrode connected to an input terminal of the gate high voltage; a sixth transistor including a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the secondary node, and a second electrode connected to an input terminal of a gate low voltage lower than the gate middle voltage; a bootstrap capacitor including a first electrode connected to the scan output node and a second electrode connected to the second scan control node; as well as A seventh transistor includes a gate electrode connected to the input terminal of the gate intermediate voltage, a first electrode connected to the second scan control node, and a second electrode connected to the secondary node.

15. The gate driver of claim 14, wherein the scan generation circuit further comprises a stabilizing capacitor including a first electrode connected to the first scan control node and a second node connected to a direct current (DC) voltage terminal, and The DC voltage terminal is an input terminal of the gate high voltage, an input terminal of the gate low voltage, or an input terminal of the gate intermediate voltage.

16. The gate driver of claim 14, wherein the scan generation circuit further comprises an eighth transistor, the eighth transistor comprising a gate electrode connected to the second scan control node, a first electrode connected to the first scan control node, and a second electrode connected to an input terminal of the gate low voltage.

17. The gate driver of claim 1, wherein the carry generation circuit comprises: A carry output node, outputting the second carry signal; a first carry transistor including a gate electrode connected to a first carry control node, a first electrode connected to an input terminal of the first clock signal, and a second electrode connected to the carry output node; a second carry transistor including a gate electrode connected to a second carry control node, a first electrode connected to the carry output node, and a second electrode connected to an input terminal of a gate high voltage; a third carry transistor including a gate electrode connected to an input terminal of the second clock signal, a first electrode connected to an input terminal of the first carry signal, and a second electrode connected to a first secondary node; a fourth carry transistor including a gate electrode connected to an input terminal of the first clock signal, a first electrode connected to the first secondary node, and a second electrode connected to a second secondary node; a fifth carry transistor including a gate electrode connected to the second carry control node, a first electrode connected to the second secondary node, and a second electrode connected to an input terminal of the gate high voltage; a sixth carry transistor including a gate electrode connected to an input terminal of the second clock signal, a first electrode connected to an input terminal of a gate low voltage lower than the gate high voltage, and a second electrode connected to the second carry control node; a seventh carry transistor including a gate electrode connected to the first secondary node, a first electrode connected to an input terminal of the second clock signal, and a second electrode connected to the second carry control node; an eighth carry transistor comprising a gate electrode connected to the input terminal of the gate low voltage, a first electrode connected to the first secondary node, and a second electrode connected to the first carry control node; a first carry capacitor connected between the first carry control node and the carry output node; as well as A second carry capacitor is connected between the second carry control node and an input terminal of the gate high voltage.

18. An electroluminescent display device comprising: Gate lines; a pixel including an N-type transistor including a gate electrode connected to the gate line; as well as The gate driver according to any one of claims 1 to 17, wherein the gate driver outputs a scan signal to the gate line.

19. A gate driver comprising a plurality of gate stages for driving a plurality of gate lines of a display panel, each gate stage being connected to a corresponding gate line connected to one or more transistors in the display panel, the gate stage comprising: a carry generation circuit, comprising a group of transistors of a first type, the carry generation circuit being configured to receive a first clock signal, a second clock signal and a first carry signal of a previous stage, and to generate a second carry signal for a next stage, wherein a pulse interval of the second carry signal is later than a pulse interval of the first carry signal; as well as a scan generation circuit comprising another set of transistors of the first type, the scan generation circuit being configured to receive the first clock signal, the second clock signal and the first carry signal, and to generate a scan signal for supplying to the one or more transistors of the second type in the display panel, wherein the pulse intervals of the first carry signal, the first clock signal, and the second clock signal are configured to turn on one or more transistors of the first type in the carry generation circuit and the scan generation circuit in a first logic state, and wherein the scan signal is configured to turn on the one or more transistors of the second type in the display panel in a second logic state, wherein the pulse interval of the scanning signal is the interval between the rising edge of the first clock signal and the falling edge of the second clock signal, and The rising edge of the first clock signal and the falling edge of the second clock signal are adjacent to each other.

20. The gate driver according to claim 19, wherein the one or more transistors of the first type and the another group of transistors are P-type transistors, and the one or more transistors of the second type in the display panel are N-type transistors, Wherein the first logic state occurs when the voltage of the pulse interval is lower than the voltage of the non-pulse interval, and wherein the second logic state occurs when the voltage of the pulse interval is higher than the voltage of the non-pulse interval.

21. The gate driver of claim 20, wherein the one set of transistors and the another set of transistors are configured as P-type low temperature polysilicon (LTPS) transistors, and the one or more transistors in the display panel are configured as N-type oxide transistors.

22. The gate driver according to claim 19, Each gate stage includes a plurality of first input terminals and a plurality of second input terminals, wherein the plurality of first input terminals for the gate stage are configured to receive the first clock signal, and the plurality of second input terminals for the gate stage are configured to receive the second clock signal, and The plurality of first input terminals for a next gate stage are configured to receive the second clock signal, and the plurality of second input terminals for the next gate stage are configured to receive the first clock signal.

23. The gate driver of claim 19, wherein the pulse interval of the scan signal is when a non-pulse interval of the first clock signal overlaps with a non-pulse interval of the second clock signal.

Images