Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the invention relate to semiconductor devices and methods of manufacturing the same. In a method of manufacturing a semiconductor device, a first conductive layer is formed over a substrate. A first photoresist layer is formed over the first conductive layer. The first conductive layer is etched with the first photoresist layer as an etch mask to form an island pattern of the first conductive layer spaced apart from a busbar pattern of the first conductive layer by an annular trench. A connection pattern is formed to connect the island pattern and the busbar pattern. A second photoresist layer is formed over the first conductive layer and the connection pattern. The second photoresist layer includes an opening over the island pattern. A second conductive layer is formed on the island pattern in the opening. The second photoresist layer is removed and the connection pattern is removed, thereby forming a bump structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] As consumer devices become smaller to meet consumer demand and offer better performance, the size of their components inevitably shrinks as well. Semiconductor devices, the main components of consumer devices such as mobile phones and tablets, have become increasingly smaller. This reduction in semiconductor device size is accompanied by advancements in semiconductor manufacturing technology, such as the formation of connections between semiconductor devices and other electronic components or circuit boards. Summary of the Invention

[0003] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a lower conductive pattern, the lower conductive pattern comprising a first column pattern of a plurality of conductive patterns arranged in a first direction and a second column pattern of a plurality of conductive patterns arranged in a first direction, the first column and the second column being adjacent to each other in a second direction intersecting the first direction; and forming an upper conductive pattern, the upper conductive pattern comprising a third column pattern of a plurality of conductive patterns arranged in a first direction and a fourth column pattern of a plurality of conductive patterns arranged in a first direction, the third column and the fourth column being adjacent to each other in a second direction, wherein: the first column and the third column at least partially overlap each other in a planar view, the second column and the fourth column at least partially overlap each other in a planar view, and the upper conductive pattern being formed such that a first center line extending in the first direction of the first column and the second column is offset in a second direction from a second center line extending in the first direction of the third column and the fourth column by an offset greater than 0.1 μm.

[0004] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a plurality of first conductive patterns arranged in a first direction and embedded in a first dielectric layer; forming a second dielectric layer over the plurality of first conductive patterns and the first dielectric layer; forming a plurality of openings in the second dielectric layer by a first patterning operation, each opening being located over a corresponding one of the plurality of first conductive patterns; forming a blanket layer of conductive material over the second dielectric layer and in the plurality of openings; patterning the blanket layer of conductive material by a second patterning operation to form a plurality of second conductive patterns connected to a corresponding one of the plurality of first conductive patterns; and forming a third dielectric layer over the plurality of second conductive patterns, wherein, in the first patterning operation, the plurality of openings as a whole are offset from the plurality of first conductive patterns as a whole in a planar view in a first direction by an offset greater than 0.1 μm.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor circuit disposed above a substrate; a lower conductive pattern disposed above and electrically coupled to the semiconductor circuit, the lower conductive pattern comprising a first column of a plurality of conductive patterns arranged in a first direction and a second column of a plurality of conductive patterns arranged in a first direction, the first column and the second column being adjacent in a second direction intersecting the first direction in a plan view; a first dielectric layer disposed above the lower conductive pattern; an upper conductive pattern disposed above the lower conductive pattern, the upper conductive pattern comprising a third column of a plurality of conductive patterns arranged in a first direction and a fourth column of a plurality of conductive patterns arranged in a first direction, the third column and the fourth column being adjacent in a second direction in a plan view; and a second dielectric layer disposed above the upper conductive pattern, wherein: in the plan view, a first center line extending in a first direction between the first column and the second column is offset in a second direction from a second center line extending in a first direction between the third column and the fourth column. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0008] Figure 2 One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0009] Figure 3 One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0010] Figure 4 One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0011] Figure 5 One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0012] Figure 6A and Figure 6B One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0013] Figure 7One stage of sequential manufacturing operations of a semiconductor device according to an embodiment of this disclosure is shown.

[0014] Figure 8A and Figure 8B A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0015] Figure 9A and Figure 9B A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0016] Figure 10 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0017] Figure 11 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0018] Figure 12 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0019] Figure 13 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0020] Figure 14 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0021] Figure 15 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0022] Figure 16 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0023] Figure 17 A view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0024] Figure 18 A flow chart of sequential manufacturing operations for a semiconductor device according to embodiments of the present disclosure is shown.

[0025] Figure 19 A flow chart of sequential manufacturing operations for a photomask according to an embodiment of the present disclosure is shown.

[0026] Figure 20 The beneficial effects of embodiments of this disclosure are shown. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, for ease of description, spaced relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spaced relation terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spaced relation descriptors used herein may be interpreted accordingly. Furthermore, the term “consisting of” may mean “including” or “comprises of.” The values, ranges, dimensions, materials, processes, configurations, and / or arrangements described below are merely examples and are not limited to those disclosed, and other values, ranges, dimensions, materials, processes, configurations, and / or arrangements may be within the scope of this disclosure unless otherwise stated.

[0029] As the electronics industry has developed three-dimensional integrated circuits (3DICs) based on through-silicon via (TSV) technology, the processing and reliability of the top electrodes (such as pad electrodes or bumps on pad electrodes) used for interconnecting stacked chips are being actively investigated. Pad electrodes are covered by one or more passivation insulating films to protect the semiconductor device formed beneath them. The reliability of the passivation layer is also a critical factor in the fabrication of semiconductor devices. In some embodiments, bump electrodes are formed on the pad electrodes, while in other embodiments, bonding wires are directly attached to the pad electrodes.

[0030] This disclosure provides a new technique for forming pad electrodes and passivation layers that can improve the reliability of semiconductor devices.

[0031] Figures 1 to 7 Various views illustrating sequential manufacturing operations of a bump structure above a semiconductor circuit according to embodiments of the present disclosure are shown. It will be understood that... Figures 1 to 7Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0032] like Figure 1 As shown, a plurality of topmost wiring patterns 20 on which bump electrodes are to be formed are formed in an interlayer dielectric (ILD) or intermetallic dielectric (IMD) layer 18 above a semiconductor circuit 15 formed on a substrate 10. The topmost wiring patterns 20 are formed of a suitable conductive metal, including aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and / or multilayers thereof. In some embodiments, the topmost wiring patterns 20 are made of Cu or Cu alloys in which a majority (more than 50%) of the material is Cu. The topmost wiring patterns 20 are formed by a suitable metal deposition operation, including electroplating or electroless plating, physical vapor deposition (PVD) (including sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, or electron beam evaporation. In some embodiments, the topmost wiring patterns 20 are formed using a damascene technique.

[0033] In some embodiments, the semiconductor circuit 15 includes transistors (e.g., field-effect transistors (FETs)), capacitors, inductors, resistors, or similar devices in some embodiments. The topmost wiring pattern 20 is electrically coupled to the semiconductor circuit 15 through an underlying interconnect layer, which includes wiring layers and vias formed in a dielectric layer (such as an ILD layer or IMD layer in some embodiments). The wiring layers and vias of the interconnect layer can be formed of copper or a copper alloy (e.g., AlCu), aluminum, tungsten, nickel, or any other suitable metal. A damascene process can be used to form the wiring layers and vias.

[0034] In some embodiments, the substrate 10 is formed of at least one selected from the group consisting of silicon, diamond, germanium, SiGe, SiGeSn, SiGeC, GeSn, SiSn, GaAs, InGaAs, InAs, InP, InSb, GaAsP, GaInP, and SiC. In some embodiments, the semiconductor substrate 10 is a silicon wafer or a silicon substrate. In some embodiments, the ILD or IMD layer 18 comprises one or more of silicon oxide, silicon nitride, SiOC, SiON, SiOCN, SiCN, a low-k dielectric material, or any other suitable dielectric material.

[0035] In some embodiments, such as Figure 2As shown, one or more top dielectric layers 22 are formed above the topmost wiring pattern 20. The top dielectric layer 22 comprises one or more layers of silicon oxide, silicon nitride, SiON, SiC, SiOCN, SiCN, or any other suitable insulating layer. In some embodiments, the thickness of the top dielectric layer 22 is in the range of about 0.1 μm to about 2.0 μm, and in the range of about 0.2 μm to about 1.0 μm. The top dielectric layer 22 is formed by a suitable metal deposition operation including PVD, CVD, or ALD.

[0036] The top dielectric layer 22 is patterned using appropriate photolithography and etching operations to form the opening 24. For example... Figure 2 As shown, a photoresist pattern 25 with openings is formed on the top dielectric layer 22, and the top dielectric layer 22 is patterned by one or more etching operations. Figure 3 As shown, the topmost wiring pattern 20 is exposed by etching. In some embodiments, the opening 24 has the following characteristics: Figure 3 The cone shape shown.

[0037] Then, as Figure 4 As shown, one or more conductive layers 30L are formed as a blanket layer above a top conductive layer 22 and an exposed topmost wiring pattern 20. In some embodiments, the blanket conductive layer 30L is formed by a suitable metal deposition operation, including electroplating, PVD (including sputtering), CVD, ALD, thermal evaporation, and electron beam evaporation. In some embodiments, the blanket conductive layer 30L comprises a suitable conductive metal, including aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and / or multilayers thereof. In some embodiments, the blanket conductive layer 30L is made of Al or an Al alloy wherein the majority (more than 50%) is Al. In some embodiments, the thickness of the blanket conductive layer 30L above the top dielectric layer 22 is in the range of about 0.5 μm to about 5.0 μm, and in other embodiments, in the range of about 1.0 μm to about 3.0 μm. In some embodiments, as Figure 4 As shown, a recess or pit 32 reflecting the shape of the top dielectric layer 22 is formed above the opening 24. In some embodiments, the recess or pit 32 has a V-shape, a U-shape, or an inverted trapezoidal shape. In some embodiments, the depth of the recess or pit 32 is in the range of about 0.05 μm to about 0.5 μm, and in other embodiments, it is in the range of about 0.1 μm to about 0.4 μm.

[0038] In some embodiments, one or more barrier layers are formed prior to the formation of the blanket conductive layer 30L. In some embodiments, the barrier layers include Ti, TiN, Ta, TaN, or TiW.

[0039] Furthermore, such as Figure 5As shown, a photoresist pattern 35 is formed over the blanket conductive layer 30L, and the blanket conductive layer 30L is patterned into pad electrodes 30 using one or more etching operations. In some embodiments, such as Figure 6A As shown, the pad electrode 30 has a tapered shape with a cone angle that ranges from about 5 degrees to about 15 degrees relative to the normal direction toward the upper surface of the topmost wiring pattern 20. In other embodiments, such as Figure 6B As shown, the pad electrode 30 has an inverted cone shape with a cone angle that is in the range of about -5 degrees to about -15 degrees relative to the normal direction.

[0040] Next, as Figure 7 As shown, a passivation layer 40 is formed over the pad electrode 30 and the top dielectric layer 22. In some embodiments, the passivation layer 40 comprises one or more layers of silicon oxide, silicon nitride, SiOC, SiON, SiOCN, SiCN, or any other suitable dielectric material. In some embodiments, silicon nitride is used as the passivation layer 40. In some embodiments, the thickness of the passivation layer 40 from the top of the pad electrode 30 is in the range of about 1.0 μm to about 10 μm, and in the range of about 2.0 μm to about 5.0 μm. The passivation layer 40 is formed by a suitable deposition operation including PVD, CVD, or ALD. Figure 7 As shown, the passivation layer 40 has peaks above the pad electrode 30 and valleys between the pad electrode 30.

[0041] In addition, in some embodiments, the passivation layer 40 is patterned by one or more photolithography and etching operations to form an opening above the pad electrode 30 for external electrical connection (by wiring or by bumps).

[0042] In such Figure 8AIn some embodiments shown, the topmost wiring pattern 20 is arranged in a row-column (XY) configuration. In some embodiments, the topmost wiring pattern 20 has a rectangle having a first side (width L1) along the row (X) direction and a second side (width L2) along the column (Y) direction in a plan view. In some embodiments, 0.8 ≤ L1 / L2 ≤ 1.2, and in other embodiments, 0.95 ≤ L1 / L2 ≤ 1.05 (basic square). In some embodiments, L1 and L2 are in the range of about 2 μm to 10 μm, and in other embodiments, in the range of about 4 μm to 6 μm. In some embodiments, the rectangle or square of the topmost wiring pattern 20 has rounded corners in a plan view. In some embodiments, a plurality of topmost wiring patterns 20 are arranged in a row-column configuration with a pitch P1 of about 2.5 μm to about 15 μm (the spacing between adjacent wiring patterns 20 is in the range of about 0.5 μm to about 5.0 μm). In some embodiments, the pitch along the row direction may be the same as or different from the pitch along the column direction. In some embodiments, the thickness of the topmost wiring pattern 20 is in the range of about 1.0 μm to about 5.0 μm, and in other embodiments, it is in the range of about 3.0 μm to about 4.0 μm.

[0043] The topmost wiring pattern 20 is arranged in a 2×4 pattern. Figure 8A As shown, but not limited to a 2×4 arrangement. In some embodiments, the arrangement is a 2×N arrangement, where N is 4 or greater (e.g., up to 100). Other arrangements comprising fewer or more rows or columns of top wiring patterns 20 are included within the scope of this disclosure. For example, the arrangement may be an M×N arrangement, where M and N are natural numbers, and at least one of M and N is 2 or up to about 100. In some embodiments, at the same wiring level within a distance L0 from the M×N arrangement, the M×N arrangement has no other wiring patterns, where L0 is two to ten times the pitch of the M×N arrangement. In some embodiments, at least one of the row lengths or column lengths of the matrix of the topmost wiring patterns 20 is in the range of about 200 μm to 2 mm.

[0044] Similarly, in such Figure 8AIn some embodiments shown, the pad electrodes 30 are arranged in a row-column configuration. In some embodiments, since the pad electrodes 30 are formed above the topmost wiring pattern 20, the arrangement or layout of the pad electrodes 30 is substantially the same as that of the topmost wiring pattern 20. In some embodiments, in a plan view, the pad electrodes 30 are rectangular, having a first side (width L3) along the row direction and a second side (width L4) along the column direction. In some embodiments, 0.8 ≤ L3 / L4 ≤ 1.2, and in other embodiments, 0.95 ≤ L3 / L4 ≤ 1.05 (a substantially square). In some embodiments, the rectangle or square of the pad electrodes 30 has rounded corners in a plan view. In some embodiments, L3 and L4 are in the range of about 2 μm to 10 μm, and in other embodiments, in the range of about 4 μm to 6 μm. In some embodiments, L3 and L4 are smaller than L1 and L2, respectively.

[0045] like Figure 8B As shown, the passivation layer 40 has peaks above the pad electrodes 30 and valleys between the pad electrodes 30. In some embodiments, the bottom of the valley is located at the level between the top of the topmost wiring pattern 20 and the top of the pad electrodes 30. When the center lines of two adjacent rows of pad electrodes 30 (the upper portion above the top dielectric layer) and the center lines of two adjacent rows of topmost wiring patterns 20 (two rows of pad electrodes 30 formed thereon) are substantially aligned with each other (difference less than 0.1 μm), the bottom of the valley is located above the gap between the topmost wiring patterns 20, as shown. Figure 8B As shown.

[0046] In some embodiments of this disclosure, such as Figure 9A As shown, the center lines of two adjacent columns of pad electrodes 30 are offset from the center lines of the two adjacent columns of topmost wiring patterns 20, for example, in the + row direction. In some embodiments, the offset D1 is greater than 0.1 μm. In some embodiments, D1 is equal to or greater than S1 / 2 (half of S1), where S1 is the interval between adjacent topmost wiring patterns 20 in the row direction (see...). Figure 10 When the offset D1 is equal to or greater than S1 / 2, the center lines of two adjacent columns of pad electrodes 30 overlap with one of the adjacent columns of the topmost wiring pattern, such as... Figure 9A and Figure 9B As shown. Therefore, the bottom of the valley of passivation layer 40 is also located above one of the adjacent columns of the topmost wiring pattern, as... Figure 9B As shown. In some embodiments, the offset D1 is S1 / 2+Δ, where Δ is in the range of about 0.1 μm to about 1.0 μm (e.g., 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm).

[0047] When the column length in the column direction is long, for example, greater than about 200 μm, long valleys are formed in the passivation layer 40 along the interval between two columns in the column direction. Such long valleys may cause cracks 45 in the passivation layer, such as... Figure 10 As shown. However, in Figure 9A and Figure 9B In the illustrated embodiment, since the bottom of the valley, which may be the origin of the crack, is located above the topmost wiring pattern 20, the crack 45 (if formed) stops at the surface of the topmost wiring pattern 20, and thus, the crack can be prevented from reaching the circuit region below the topmost wiring layer 20. Along the column direction, the crack may penetrate into the top dielectric layer 22 and the ILD / IMD layer at the intervals between adjacent topmost wiring patterns 20. Since the intervals between adjacent topmost wiring patterns 20 are sufficiently smaller than the size of the topmost wiring pattern 20, the crack 45 will not penetrate deep into the top dielectric layer 22 and / or the ILD / IMD layer. In some embodiments, the bottom of the crack 45 is located between the top and bottom surfaces of the topmost wiring pattern 20 in the intervals between the topmost wiring patterns in the column direction.

[0048] In some embodiments, the width L11 of the topmost wiring pattern 20 is in the range of about 2 μm to 10 μm, and in other embodiments, it is in the range of about 4 μm to 6 μm. In some embodiments, the width L21 of the bottom of the pad electrode 30 is in the range of about 1.2 μm to 6 μm, and in other embodiments, it is in the range of about 2.4 μm to 3.6 μm. In some embodiments, the maximum width L22 of the pad electrode 30 is in the range of about 1.6 μm to 8 μm, and in other embodiments, it is in the range of about 3.2 μm to 4.8 μm. In some embodiments, the spacing S1 is in the range of about 0.5 μm to 2.0 μm, and in other embodiments, it is in the range of about 0.8 μm to 1.2 μm.

[0049] In some embodiments, the offset D1 is set such that the outer edge of the opening 24 is within the topmost wiring pattern 20. In some embodiments, when Figure 5 When the photoresist pattern 35 of the pad electrode 30 shown is aligned with the opening 24, D1 corresponds to the opening 24 (see...). Figure 3The difference between the center of the topmost wiring pattern 20 and the center of the topmost wiring pattern 20. In other words, the lower portion of the pad electrode 30 (embedded in the top dielectric layer 22) and the upper portion of the pad electrode 30 (above the upper surface of the top dielectric layer 22) are substantially aligned with each other (in some embodiments, the overlap error is less than 0.1 μm). In some embodiments, D1 is equal to or greater than S1 / 2 (half of S1) and equal to or less than (L11-L21) / 2. In some embodiments, the upper portion of the pad electrode 30 has a greater thickness than the lower portion of the pad electrode 30.

[0050] In other embodiments, such as Figure 11 As shown, the lower portion of the pad electrode 30 (embedded in the top dielectric layer 22) is substantially aligned with the topmost wiring layer 20 (in some embodiments, the overlap error is less than 0.1 μm), and the upper portion of the pad electrode 30 is offset by an offset D1. In some embodiments, D1 is equal to or greater than S1 / 2 (half of S1) and equal to or less than (L22-L21') / 2, where the width L21' is the width of the top of the lower portion of the pad electrode 30. In some embodiments, D1 is equal to or greater than S1 / 2+Δ, where Δ is approximately 0.1 μm.

[0051] In other embodiments, both the lower and upper portions of the pad electrode 30 are offset relative to the topmost wiring pattern 20, such that the upper portion of the pad electrode 30 is offset from the topmost wiring layer 20 by an amount D1.

[0052] Figure 12 Another embodiment is shown, wherein the pad electrodes 30 have an inverted conical shape. Similar to the previous embodiment, the pad electrodes 30 are offset relative to the topmost wiring pattern 20 such that the center lines of two adjacent rows of pad electrodes 30 overlap with one or two rows of the topmost wiring pattern 20, and the two rows of pad electrodes 30 are formed on the topmost wiring pattern 20. Therefore, the valley of the passivation layer 40 is located exactly above the topmost wiring pattern 20.

[0053] As from Figure 8A and Figure 9A The understanding in the middle, Figures 9A to 11 The structure shown is achieved by offsetting one or both of the photoresist patterns of the opening 24 and the pad electrode 30 relative to the topmost wiring pattern 20. This pattern offset can be achieved by inputting an overlay adjustment value (different from machine error or other than machine error, so-called "overlay error") to a photolithography apparatus using a primary photomask designed to perfectly align with the underlying pattern (e.g., the topmost wiring pattern). In this case, it is not necessary to fabricate additional photomasks for patterning the opening 24 and / or the pad electrode 30, and all patterns formed using the photomask are offset by the same amount.

[0054] In other embodiments, a new photomask with an intentional pattern offset is fabricated, and no overlay offset (other than minor adjustments) is input into the photolithography apparatus when the photoresist pattern is formed. In some embodiments, only certain necessary portions of the pattern are offset.

[0055] Figure 13 and Figure 14 A pattern layout according to an embodiment of the present disclosure is shown.

[0056] In some embodiments, the topmost wiring pattern 20 and the pad electrode 30 include not only the matrix pattern MX, but also one or more island patterns IL, such as Figure 13 and Figure 14 As shown. In some embodiments, the island pattern IL is separated from the matrix pattern or from the nearest pattern by a distance L0, where L0 is two to ten times or more the pitch of the matrix arrangement. When the passivation layer 40 is formed, the passivation layer forms a gentle upper surface profile over the island pattern IL, so that virtually no valleys are formed around the island pattern due to the sufficiently long distance from the adjacent (e.g., nearest) pattern.

[0057] In some embodiments, such as Figure 13 As shown, the pad electrodes 30 of both the matrix pattern MX and the island pattern IL are offset in the row direction relative to the topmost wiring pattern 20. Figure 13 As shown, the center line CL of two adjacent columns of pad electrodes 30 in the matrix pattern overlaps with one column of the two topmost wiring patterns 20 in the plan view. As described above, this can be achieved by inputting an overlay adjustment value into a photolithography apparatus using either a raw photomask or a specially manufactured photomask. In some embodiments, such as... Figure 13 As shown, the topmost wiring pattern 20 includes one or more patterns on which no pad electrodes are formed.

[0058] In other embodiments, such as Figure 14 As shown, although the pad electrodes 30 of the matrix pattern MX are offset in the row direction relative to the topmost wiring pattern 20, the pad electrodes 30 of the island pattern IL are essentially aligned with the corresponding topmost wiring pattern 20 (no offset or an offset of less than 0.1 μm, which may be caused by machine error (so-called "overlay error")). As mentioned above, this can be achieved by using a specially manufactured photomask.

[0059] In some embodiments, island patterns that do not require pattern offset comprise small matrices with row or column lengths of less than 100 μm. In some embodiments, such as Figure 13 or Figure 14The one or more island-shaped patterns IL shown are pseudo-patterns (parts of patterns or test circuits used for measurement (overlay or alignment)) set on the scribe lines surrounding the semiconductor chip.

[0060] Figure 15 and Figure 16 A pattern layout according to an embodiment of the present disclosure is shown.

[0061] In some embodiments, the pattern matrix of the topmost wiring pattern 20 and the pad electrode 30 is arranged in an M×N pattern, where M and N are four or greater, and / or the row length and / or column length is greater than 100 μm.

[0062] In some embodiments, such as Figure 15 As shown, the overall matrix of the pad electrodes 30 is offset in only one direction (e.g., the row direction), such that the center line CL of two adjacent columns of pad electrodes 30 overlaps with one of the two columns of topmost wiring patterns 20 that form the two columns of pad electrodes 30. In some embodiments, the center (geometric center or centroid) of the matrix of the pad electrodes 30 (particularly the upper portion) is offset in one direction relative to the center of the matrix of the topmost wiring pattern 20.

[0063] In other embodiments, such as Figure 16 As shown, the entire matrix of pad electrodes 30 is offset in the row and column directions such that the center lines CL of two adjacent columns of pad electrodes 30 overlap with one column of the two topmost wiring patterns 20, and the center lines CL' of two adjacent rows of pad electrodes 30 overlap with one row of the two topmost wiring patterns 20. In some embodiments, the center of the matrix of pad electrodes 30 (particularly the upper portion) is offset in both directions relative to the center of the matrix of the topmost wiring patterns 20.

[0064] Figure 17 A pattern layout according to an embodiment of the present disclosure is shown.

[0065] In some embodiments, the pad electrodes 30 are arranged around the periphery of the semiconductor chip, such as... Figure 17 As shown. In some embodiments, the periphery or peripheral region of the semiconductor chip is a region within 500 μm of the boundary distance between the chip region (circuit region) and the scribe line. In some embodiments, two columns of pad electrodes are arranged on the left and right sides of the semiconductor chip, and two rows of pad electrodes are arranged on the top and bottom sides of the semiconductor chip.

[0066] In some embodiments, the columns of pad electrodes 30 located on the left and right sides of the semiconductor chip are offset along the row direction (from left to right) such that the center lines of two adjacent columns of pad electrodes 30 overlap with one column of the two topmost wiring patterns 20 on which the two columns of pad electrodes 30 are formed. In some embodiments, the rows of pad electrodes 30 located at the top and bottom of the semiconductor chip are offset along the column direction (from top to bottom) such that the center lines of two adjacent rows of pad electrodes 30 overlap with one row of the two topmost wiring patterns 20 on which the two rows of pad electrodes 30 are formed.

[0067] In some embodiments, the offset direction of the column of pad electrodes 30 located on the left side of the semiconductor chip is the same as the offset direction of the column of pad electrodes 30 located on the right side, for example, to the left relative to the topmost wiring pattern, such as... Figure 17 As shown. In other embodiments, the offset direction of the column of pad electrodes 30 located on the left side of the semiconductor chip relative to the topmost wiring pattern is different from the offset direction of the column of pad electrodes 30 located on the right side. A similar arrangement is applied to the rows of pad electrodes located at the top and bottom of the semiconductor chip. In some embodiments, the pad electrodes 30 are offset towards the outside of the semiconductor chip relative to the topmost wiring patterns on the four sides of the semiconductor chip, and in other embodiments, the pad electrodes are offset towards the inside of the semiconductor chip relative to the topmost wiring patterns on the four sides of the semiconductor chip.

[0068] In some embodiments, the rows and columns of the pad electrodes 30 are similar to Figure 16 Offset relative to the topmost wiring pattern in both row and column directions.

[0069] Figure 18 A flowchart illustrating the manufacture of a semiconductor device according to embodiments of the present disclosure is shown. It will be understood that... Figure 18 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated in other embodiments of the method. The order of operations / processes may be interchanged.

[0070] In the above embodiments, pattern 20 is the topmost wiring pattern, which is the wiring layer closest to the pad electrode in the vertical direction and connected to the pad electrode, and pattern 30 is the pad electrode. However, the configuration is not limited to this. In other embodiments, pattern 30 is a bump under-metallization (UBM) layer on which bump electrodes are formed.

[0071] At process block S801, a wiring pattern, such as the topmost wiring pattern 20 as described above, is formed in the ILD layer above the substrate. At process block S802, a first dielectric layer, such as the top dielectric layer 22 as described above, is formed above the wiring pattern formed in the ILD layer. At process block S803, a first photoresist pattern for forming an opening / window (e.g., opening 24 as described above) is formed above the first dielectric layer. In some embodiments, in the photolithography process, an overlay offset OL1 is implemented in addition to an overlay compensation value caused by defects in the alignment process. In some embodiments, an overlay offset OL1 of less than 0.1 μm is implemented in the photolithography process. In some embodiments, OL1 is set relative to the wiring pattern. At process block S804, the first dielectric layer is patterned using the first photoresist pattern as an etch mask to form an opening above the wiring pattern, such as opening 24 as described above. At process block S805, a blanket conductive layer, such as conductive layer 30L as described above, is formed in the opening and on the first dielectric layer. At process block S806, a second photoresist pattern for forming electrodes (e.g., pad electrodes 30 as described above) is formed over the conductive layer. In some embodiments, in the photolithography process, in addition to an overlay compensation value (approximately less than 0.1 μm) caused by defects in the alignment process, an overlay offset OL2 is also implemented. At process block S807, the second photoresist pattern is used as an etch mask to pattern the blanket conductive layer to form electrodes, such as pad electrodes 30 as described above. At process block S808, a second dielectric layer, such as a passivation layer 40 as described above, is formed over the first dielectric layer and the patterned electrodes.

[0072] In some embodiments, one or both of the photomasks used in process frames S804 and S806 are designed such that the electrodes or electrodes and openings are aligned with the corresponding wiring patterns. In this case, the overlay offset OL2 is set to be greater than 0.1 μm relative to the wiring pattern, or is set to S1 / 2 + Δ, where S1 is the spacing between the wiring patterns, and Δ is in the range of about 0.1 μm to about 1.0 μm. In some embodiments, OL1 is zero. In other embodiments, the sum of the overlay offsets OL1 + OL2 is set to be greater than 0.1 μm relative to the wiring pattern, or is set to S1 / 2 + Δ, where S1 is the spacing between the wiring patterns, and Δ is in the range of about 0.1 μm to about 1.0 μm when OL2 is set relative to the opening.

[0073] In some embodiments, one or both of the photomasks used in process frames S804 and S806 are designed such that the electrodes are offset relative to the corresponding wiring pattern. In this case, both OL1 and OL2 are zero, and only overlay compensation values ​​caused by alignment process defects are input to the lithography apparatus if necessary.

[0074] Figure 19 A flowchart illustrating the fabrication of a photomask according to an embodiment of this disclosure is shown. It will be understood that it can be... Figure 19 Additional operations are provided before, during, and after the process shown. For other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0075] At process frame S901, a preliminary layout of the opening pattern (e.g., opening 24) (first photoresist pattern 25) and the electrode pattern (e.g., pad electrode 30) are prepared. In the preliminary layout, the opening pattern and electrode pattern are designed to align with the patterns below (such as wiring patterns that form openings thereon, e.g., the topmost wiring pattern 20). Similar to... Figure 8A In the embodiment shown, the center lines of two adjacent rows of electrode patterns are aligned with the center lines of two adjacent rows of wiring patterns.

[0076] At process frame S902, one or more sets of electrode patterns (rows and / or columns) that will create long valleys (e.g., exceeding 200 μm) on the overlying insulating layer are searched and detected. In some embodiments, an electrode pattern set is determined to create long valleys on the overlying insulating layer when the electrode patterns are arranged in at least two rows and / or two columns, the spacing between adjacent rows / columns is within a predetermined range, and the length of the rows / columns is greater than a threshold length. This can be achieved through one or more sizing adjustments and / or Boolean operations on the patterns. For example, by extending the pattern in one direction (both sides), spacing smaller than the threshold length is eliminated to form a continuous pattern, and then the length of the continuous pattern is determined to be greater than the threshold length. In some embodiments, the predetermined range is from about 0.5 μm to 2.0 μm, and in other embodiments it is from about 0.8 μm to 1.2 μm. In some embodiments, the threshold length is about 200 μm, and in other embodiments it is about 400 μm.

[0077] At process frame S903, when a critical pattern group is found, the electrode pattern group is offset by an offset in the direction passing through the valley (which will appear in other ways). The offset is determined such that the center line of the adjacent row / column of the electrode pattern overlaps with the wiring pattern below, as explained above.

[0078] In some embodiments, at process frame S904, an offset that is the same as or different from the offset of the electrode pattern corresponds to the opening pattern of the critical electrode pattern group.

[0079] Then, at process frame S905, the modified layout is output as mask data, and one or more photomasks are manufactured based on the mask data. The manufactured photomasks are used, for example, for... Figure 18 In the process shown.

[0080] In some embodiments, Figure 19 The processes shown (especially S901-S904) can be executed by a computer system comprising one or more processors and a storage medium (memory) storing a program. When the program is executed, the program being executed can perform... Figure 19 At least a portion of the operation shown.

[0081] In some embodiments, one or more of process blocks S901-S904 are executed by a computer system. In some embodiments, the computer system is equipped with a computer including an optical disc read-only memory (e.g., CD-ROM or DVD-ROM) drive and a disk drive, a keyboard, a mouse, and a monitor. In addition to the optical disc drive and disk drive, the computer is also equipped with: one or more processors (such as a microprocessor unit (MPU)), a ROM storing programs such as boot programs, random access memory (RAM) connected to the MPU and temporarily storing application commands and providing temporary storage areas therein, a hard disk storing application programs, system programs, and data, and a bus connecting the MPU, ROM, etc. Note that the computer system may include a network card (not shown) for providing a connection to a LAN. The program that enables the computer system to perform the functions of the means for performing the mask data generation operation described above may be stored on an optical disc or disk inserted into the optical disc drive or disk drive and sent to the hard disk. Optionally, the program may be transferred to the computer via a network (not shown) and stored on the hard disk. During execution, the program is loaded into RAM. The program may be loaded from an optical disc or disk, or directly from a network. The program does not necessarily have to include, for example, an operating system (OS) or third-party programs to enable the computer to perform the functions of the photomask data generation apparatus in the foregoing embodiments. The program may only include a command portion to invoke appropriate functions (modules) in controlled mode and obtain the desired results.

[0082] Figure 20 The beneficial effects of this embodiment are illustrated. Various samples with different row / column lengths (“PRL”) and different offsets were fabricated, and the number of cases where cracks in the passivation layer (200 nm silicon nitride) reached below the topmost wiring pattern was counted. The pattern spacing S1 between adjacent topmost wiring layers was 0.75 μm.

[0083] like Figure 20 As shown, when the row / column length is long (e.g., 400 μm or more), cracks that penetrate to the bottom of the topmost wiring pattern occur (about 0.2%), but according to embodiments of this disclosure, such cracks are eliminated when sufficient overlay (OVL) offset is introduced.

[0084] In the foregoing embodiments, even though the morphology of the rows and / or columns of the pad electrode pattern forms long valley portions in the passivation layer (which may be the origin of cracks), the valleys are located above the underlying wiring pattern because the rows and / or columns of the pad electrode pattern are offset relative to the underlying wiring pattern, which may prevent cracks from penetrating below the wiring pattern. In some embodiments, this pattern offset is achieved by introducing an overlay offset in the exposure apparatus and does not require a new photomask.

[0085] It should be understood that not all advantages need to be discussed herein, all embodiments or examples do not require specific advantages, and other embodiments or examples may provide different advantages.

[0086] According to one aspect of this disclosure, in a method of manufacturing a semiconductor device, a lower conductive pattern is formed. The lower conductive pattern includes a first column pattern of multiple conductive patterns arranged in a first direction and a second column pattern of multiple conductive patterns arranged in the first direction, and in a plan view, the first column and the second column are adjacent to each other in a second direction intersecting the first direction. An upper conductive pattern is formed. The upper conductive pattern includes a third column pattern of multiple conductive patterns arranged in a first direction and a fourth column pattern of multiple conductive patterns arranged in the first direction, and in a plan view, the third column and the fourth column are adjacent to each other in a second direction. The first column and the third column at least partially overlap each other in the plan view, the second column and the fourth column at least partially overlap each other in the plan view, and the upper conductive pattern is formed such that a first center line extending in the first direction of the first column and the second column is offset in a second direction from the second center lines extending in the first direction of the third column and the fourth column by an offset greater than 0.1 μm. In one or more of the foregoing or following embodiments, the second center line overlaps with the second column in the plan view. In one or more of the foregoing or following embodiments, forming the upper conductive pattern includes forming a photoresist pattern corresponding to the upper conductive pattern using a photolithography apparatus, and during the photolithography operation, inputting a non-zero overlay offset in a second direction to the photolithography apparatus such that a first center line extending in the directions of the first and second columns is offset in the second direction from a second center line extending in the directions of the third and fourth columns. In one or more of the foregoing or following embodiments, an insulating layer is also formed above the upper conductive pattern. In one or more of the foregoing or following embodiments, the insulating layer includes peaks above the third and fourth columns and valleys between the third and fourth columns. In one or more of the foregoing or following embodiments, the valleys overlap with the second column. In one or more of the foregoing or following embodiments, the insulating layer includes cracks from the valleys to at least one of the plurality of conductive patterns in the second column. In one or more of the foregoing or following embodiments, the spacing between the first and second columns is smaller than the spacing between the third and fourth columns. In one or more of the foregoing or following embodiments, the offset is greater than half the spacing between the first and second columns. In one or more of the foregoing or following embodiments, the spacing between the first and second columns is in the range of 0.8 μm to 1.2 μm, the spacing between the third and fourth columns is in the range of 1.6 μm to 2.4 μm, and the offset is in the range of 0.8 μm to 1.0 μm. In one or more of the foregoing or following embodiments, the total length of the first column is greater than 200 μm. In one or more of the foregoing or following embodiments, each of the plurality of conductive patterns in the first and second columns has a square shape with rounded corners. In one or more of the foregoing or following embodiments, each of the plurality of conductive patterns in the third and fourth columns has a square shape with rounded corners in a planar view.

[0087] According to another aspect of this disclosure, in a method of manufacturing a semiconductor device, a plurality of first conductive patterns are formed, arranged in a first direction and embedded in a first dielectric layer. A second dielectric layer is formed over the plurality of first conductive patterns and the first dielectric layer. A plurality of openings are formed in the second dielectric layer by a first patterning operation, each opening being located above a corresponding one of the plurality of first conductive patterns. A blanket layer of conductive material is formed over the second dielectric layer and in the plurality of openings. The blanket layer of conductive material is patterned by a second patterning operation to form a plurality of second conductive patterns connected to a corresponding one of the plurality of first conductive patterns. A third dielectric layer is formed over the plurality of second conductive patterns. In the first patterning operation, the plurality of openings as a whole are offset from the plurality of first conductive patterns as a whole in a planar view in a first direction by an offset greater than 0.1 μm. In one or more of the foregoing or following embodiments, the center lines of two adjacent first conductive patterns in the first direction in the planar view are offset from the center lines of two adjacent second conductive patterns in the first direction by an offset in the first direction. In one or more of the foregoing or following embodiments, the thickness of the plurality of first conductive patterns is greater than the thickness of the plurality of second conductive patterns over the second dielectric layer. In one or more of the foregoing or following embodiments, the thickness of the plurality of first conductive patterns is in the range of 3 μm to 5 μm, and the thickness of the plurality of second conductive patterns above the second dielectric layer is in the range of 1.0 μm to 3.0 μm. In one or more of the foregoing or following embodiments, the top dimension of each of the plurality of openings is smaller than the maximum width of each of the plurality of second conductive patterns.

[0088] According to another aspect of this disclosure, in a method of manufacturing a semiconductor device, a lower conductive pattern is formed in a column-row matrix arrangement, wherein a first spacing between adjacent columns is in the range of 0.8 μm to 1.2 μm. A first dielectric layer is formed over the lower conductive pattern. Upper conductive patterns are formed over the lower conductive pattern and arranged in a column-row matrix, and a second spacing between adjacent columns is greater than the first spacing. In a plan view, the center lines of adjacent columns of the lower conductive pattern are offset from the center lines of adjacent columns of a plurality of upper conductive patterns in the row direction by an offset greater than 0.1 μm. In one or more of the foregoing or following embodiments, a first island pattern is disposed at the same level as the lower conductive pattern, a second island pattern is disposed at the same level as the upper conductive pattern, and the center of the first island pattern is aligned with the center of the second island pattern.

[0089] According to another aspect of this disclosure, a semiconductor device includes: a semiconductor circuit disposed above a substrate; a lower conductive pattern disposed above and electrically coupled to the semiconductor circuit, the lower conductive pattern comprising a first column of a plurality of conductive patterns arranged in a first direction and a second column of a plurality of conductive patterns arranged in a first direction, the first column and the second column being adjacent in a second direction intersecting the first direction in a plan view; a first dielectric layer disposed above the lower conductive pattern; an upper conductive pattern disposed above the lower conductive pattern, the upper conductive pattern comprising a third column of a plurality of conductive patterns arranged in a first direction and a fourth column of a plurality of conductive patterns arranged in a first direction, the third column and the fourth column being adjacent in a second direction in a plan view; and a second dielectric layer disposed above the upper conductive pattern, wherein: in a plan view, a first center line extending in a first direction between the first column and the second column is offset in a second direction from a second center line extending in a first direction between the third column and the fourth column. In one or more of the foregoing or following embodiments, the second center line overlaps with one of the first column or the second column.

[0090] According to another aspect of this disclosure, a semiconductor device includes: a semiconductor circuit disposed above a substrate; a lower conductive pattern disposed above and electrically coupled to the semiconductor circuit, the lower conductive pattern comprising a first column of a plurality of conductive patterns arranged in a first direction and a second column of a plurality of conductive patterns arranged in a first direction, the first column and the second column being adjacent in a second direction intersecting the first direction in a plan view; a first dielectric layer disposed above the lower conductive pattern; an upper conductive pattern disposed above the lower conductive pattern, the upper conductive pattern comprising a third column of a plurality of conductive patterns arranged in a first direction and a fourth column of a plurality of conductive patterns arranged in a first direction, the third column and the fourth column being adjacent in a second direction in a plan view; and a second dielectric layer disposed above the upper conductive pattern. In the plan view, a first center line extending in a first direction between the first column and the second column is offset in a second direction from a second center line extending in a first direction between the third column and the fourth column by an offset greater than 0.1 μm. In one or more of the foregoing or following embodiments, the second center line overlaps with one of the first column or the second column. In one or more of the foregoing or following embodiments, the offset is greater than S / 2, where S is the interval between the first column and the second column. In one or more of the foregoing or following embodiments, the offset is greater than S / 2 + 0.1 μm. In one or more of the foregoing or following embodiments, S is in the range of 0.8 μm to 1.2 μm. In one or more of the foregoing or following embodiments, the second dielectric layer includes peaks located above the third and fourth columns and valleys located between the third and fourth columns. In one or more of the foregoing or following embodiments, the valleys overlap with one of the first or second columns in the planar view. In one or more of the foregoing or following embodiments, the second dielectric layer includes a crack from the valley to at least one of a plurality of conductive patterns in the second column. In one or more of the foregoing or following embodiments, the crack does not penetrate below the bottom of the lower conductive pattern. In one or more of the foregoing or following embodiments, the lower conductive pattern has a rectangular shape in the planar view, the rectangular shape having a first side with a width L1 along a first direction and a second side with a width L2 along a second direction, and 0.95 ≤ L1 / L2 ≤ 1.05. In one or more of the foregoing or following embodiments, the upper conductive pattern has a rectangular shape in a plan view, the rectangular shape having a first side with a width L3 along a first direction and a second side with a width L4 along a second direction, and 0.95 ≤ L3 / L4 ≤ 1.05. In one or more of the foregoing or following embodiments, the widths L3 and L4 are smaller than the widths L1 and L2.

[0091] According to another aspect of this disclosure, a semiconductor device includes: a semiconductor circuit disposed above a substrate; a wiring pattern embedded in a first interlayer dielectric (ILD) layer and disposed above and electrically coupled to the semiconductor circuit; a second ILD layer disposed above the wiring pattern; pad electrodes disposed above and connected to the wiring pattern; and a passivation layer disposed above the pad electrodes. Each of the pad electrodes includes a lower portion embedded in the second ILD layer and an upper portion located above the surface of the second ILD layer. The wiring pattern includes a first matrix of patterns, and the upper portion of the pad electrode includes a second matrix of patterns. The center of the second matrix is ​​laterally offset relative to the center of the first matrix in a planar view by an offset greater than 0.1 μm. In one or more of the foregoing or following embodiments, the first matrix and the second matrix are each M×N matrices, where M and N are natural numbers, at least one of M or N is 4 or greater, and at least one of the column lengths and column lengths of the M×N matrix is ​​greater than 100 μm. In one or more of the foregoing or following embodiments, M is 2 and N is 4 or greater. In one or more of the foregoing or following embodiments, the offset is greater than S / 2 + 0.1 μm, where S is the spacing between adjacent wiring patterns. In one or more of the foregoing or following embodiments, the wiring patterns are made of Cu or a Cu-based alloy, and the pad electrodes are made of Al or an Al-based alloy.

[0092] According to another aspect of this disclosure, a semiconductor device includes: a semiconductor circuit disposed above a substrate; a wiring pattern disposed on a peripheral region, wherein the wiring pattern is embedded in a first interlayer dielectric (ILD) layer and disposed above and electrically coupled to the semiconductor circuit; a second ILD layer disposed above the wiring pattern; pad electrodes disposed on the peripheral region and respectively disposed above and connected to the wiring pattern; and a passivation layer disposed above the pad electrodes. The wiring pattern comprises a 2×N matrix, and the pad electrodes comprise a 2×N matrix, where N is a natural number of 4 or greater. The center of the second matrix is ​​laterally offset relative to the center of the first matrix in a planar view towards the outside or inside of the peripheral region by an offset greater than 0.1 μm. In one or more of the foregoing or following embodiments, the peripheral region has a frame shape. In one or more of the foregoing or following embodiments, the offset is greater than S / 2 + 0.1 μm, where S is the spacing between adjacent wiring patterns.

[0093] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A method for manufacturing a semiconductor device, comprising: A lower conductive pattern is formed, the lower conductive pattern comprising a first column pattern of multiple conductive patterns arranged in a first direction and a second column pattern of multiple conductive patterns arranged in the first direction, the first column and the second column being adjacent to each other in a second direction intersecting the first direction; as well as An upper conductive pattern is formed, comprising a third column of conductive patterns arranged in the first direction and a fourth column of conductive patterns arranged in the first direction, wherein the third column and the fourth column are adjacent to each other in the second direction, wherein: The first column and the third column at least partially overlap each other in the plan view. The second column and the fourth column at least partially overlap each other in the plan view, and The upper conductive pattern is formed such that a first center line extending in the first direction of the first column and the second column is offset in the second direction from a second center line extending in the first direction of the third column and the fourth column by an offset greater than 0.1 μm. as well as An insulating layer is formed above the upper conductive pattern. The insulating layer includes peaks above the third and fourth columns and valleys between the third and fourth columns. The valley described in the plan view overlaps with the second column, and The insulating layer includes cracks that penetrate the insulating layer from the valley to the top surface of at least the lower conductive pattern of the plurality of conductive patterns.

2. The method according to claim 1, wherein, The second center line overlaps with the second column in the plan view.

3. The method according to claim 1, wherein: The formation of the upper conductive pattern includes forming a photoresist pattern corresponding to the upper conductive pattern using a photolithography apparatus, and In the photolithography operation, a non-zero overlay offset in the second direction is input to the photolithography apparatus, such that the first center line extending in the directions of the first column and the second column is offset in the second direction from the second center line extending in the directions of the third column and the fourth column.

4. The method according to claim 1, wherein, The bottom of the valley from which the crack originates is located above the lower conductive pattern.

5. The method according to claim 4, wherein, The crack stops at the topmost surface.

6. The method according to claim 1, wherein, The bottom of the crack is located above the bottom surface of the lower conductive pattern.

7. The method according to claim 6, wherein, The bottom of the crack is located between the bottom surface and the top surface of the lower conductive pattern.

8. The method according to claim 1, wherein, The interval between the first column and the second column is smaller than the interval between the third column and the fourth column.

9. The method according to claim 8, wherein, The offset is greater than half the interval between the first column and the second column.

10. The method according to claim 9, wherein: The spacing between the first column and the second column is in the range of 0.8 µm to 1.2 µm. The spacing between the third and fourth columns is in the range of 1.6 μm to 2.4 μm, and The offset is in the range of 0.8 μm to 1.0 μm.

11. The method according to claim 1, wherein, The total length of the first column is greater than 200 μm.

12. The method according to claim 1, wherein, Each of the plurality of conductive patterns in the first and second columns has a square shape with rounded corners.

13. The method according to claim 12, wherein, Each of the plurality of conductive patterns in the third and fourth columns has a square shape with rounded corners in the plan view.

14. A method for manufacturing a semiconductor device, comprising: A plurality of first conductive patterns are formed in a first direction and embedded in a first dielectric layer, and a plurality of second conductive patterns are formed in the first direction and embedded in the first dielectric layer, wherein the second conductive patterns are spaced apart from the first conductive patterns along a second direction intersecting the first direction. A second dielectric layer is formed over the plurality of first conductive patterns and the first dielectric layer; Multiple openings are formed in the second dielectric layer by a first patterning operation, with each opening located above a corresponding one of the plurality of first conductive patterns and the plurality of second conductive patterns; A blanket layer of conductive material is formed above the second dielectric layer and in the plurality of openings; The conductive material is patterned in a blanket layer by a second patterning operation to form a plurality of third conductive patterns connected to a corresponding one of the plurality of first conductive patterns, and a plurality of fourth conductive patterns connected to a corresponding one of the plurality of second conductive patterns; and A third dielectric layer is formed over the plurality of second conductive patterns. In the first patterning operation, the plurality of openings in the planar view are offset from the plurality of first conductive patterns in the first direction by an offset greater than 0.1 μm. In the plan view, the center line between the adjacent third and fourth conductive patterns extending in the second direction overlaps with the first and second conductive patterns.

15. The method according to claim 14, wherein, In the plan view, the center lines of two adjacent first conductive patterns in the first direction are offset from the center lines of two adjacent third conductive patterns in the first direction by the offset amount.

16. The method of claim 14, wherein, The thickness of the plurality of first conductive patterns is greater than the thickness of the plurality of third conductive patterns above the second dielectric layer.

17. The method of claim 16, wherein: The thickness of the plurality of first conductive patterns is in the range of 3 μm to 5 μm, and The thickness of the plurality of third conductive patterns above the second dielectric layer is in the range of 1.0 micrometer to 3.0 micrometer.

18. The method according to claim 14, wherein, The top dimension of each of the plurality of openings is smaller than the maximum width of each of the plurality of second conductive patterns.

19. A semiconductor device, comprising: Semiconductor circuitry, disposed above a substrate; A lower conductive pattern is disposed above the semiconductor circuit and electrically coupled to the semiconductor circuit. The lower conductive pattern includes a first column of a pattern in a first direction and a second column of a pattern in the first direction. The first column and the second column are adjacent in a second direction intersecting the first direction in a plan view. A first dielectric layer is disposed above the lower conductive pattern; An upper conductive pattern is disposed above the lower conductive pattern. The upper conductive pattern includes a third column of a pattern in which multiple conductive patterns are arranged in the first direction and a fourth column of a pattern in which multiple conductive patterns are arranged in the first direction. The third column and the fourth column are adjacent in the second direction in the plan view. as well as A second dielectric layer is disposed above the upper conductive pattern, wherein: In the plan view, a first center line extending in the first direction between the first column and the second column is offset in the second direction from a second center line extending in the first direction between the third column and the fourth column.

20. The semiconductor device according to claim 19, wherein, The second center line overlaps with either the first column or the second column.

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