3D chip packaging structure and packaging method

Abstract

The application belongs to the technical field of chip packaging, and particularly relates to a 3D chip packaging structure and a packaging method. The application aims to solve the technical problems of complex packaging process and high total packaging cost. The 3D chip packaging structure comprises a chip body, and the chip body comprises: a first chip having a first surface; a second chip arranged on the first surface of the first chip; a first insulating packaging layer arranged on the first surface and wrapping the surface of the second chip; and a first electric connection structure penetrating through the first insulating packaging layer and electrically connected between the first chip and the second chip. The application can improve the transmission speed of the first chip and the second chip, optimize the packaging size, simplify the packaging process of the first chip and the second chip, reduce the complexity of the packaging process, and thus reduce the total packaging cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and in particular to a 3D chip packaging structure and a packaging method. BACKGROUND

[0002] With the increasing requirements of high performance, high transmission rate, small size, high reliability and ultra-low power consumption in chips and electronic products, advanced packaging technology is constantly breaking through and developing. In order to improve the transmission rate of the chip and optimize the packaging size of the chip, the demand for three-dimensional (3D) packaging is becoming more and more intense.

[0003] In the related art, 3D chip packaging usually needs to form a packaging groove on a packaging silicon substrate, and set a chip to be packaged in the packaging groove, and then stack and package another chip to be packaged with the packaging silicon substrate by bonding or other means, and electrically connect between the two chips through an electrical connection structure.

[0004] However, in the related art, the packaging process of the 3D chip packaging is complex, and the total packaging cost is high. SUMMARY

[0005] The present application provides a 3D chip packaging structure and a packaging method, which can improve the transmission speed of the chip, optimize the packaging size, simplify the packaging process, and reduce the packaging cost.

[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] The first aspect of the present application provides a 3D chip packaging structure, comprising: a chip body, the chip body comprising:

[0008] a first chip having a first surface;

[0009] a second chip disposed on the first surface of the first chip;

[0010] a first insulating packaging layer disposed on the first surface and wrapping the surface of the second chip; and

[0011] a first electrical connection structure penetrating the first insulating packaging layer, and the first electrical connection structure being electrically connected between the first chip and the second chip.

[0012] Compared with the related art, the 3D chip packaging structure provided by the first aspect of the present application has the following advantages:

[0013] The 3D chip packaging structure provided by the embodiment of the present application comprises a first chip, a second chip, a first insulating packaging layer and a first electrical connection structure. The first chip has a first surface. The second chip is arranged on the first surface of the first chip. The first insulating packaging layer is arranged on the first surface and wraps the surface of the second chip. The first electrical connection structure penetrates the first insulating packaging layer and is electrically connected between the first chip and the second chip. In the above scheme, by arranging the second chip on the first surface of the first chip and forming the first insulating packaging layer on the first surface and wrapping the surface of the second chip, the transmission speed of the chip can be improved, the packaging size can be optimized, the packaging process of the first chip and the second chip can be simplified, the complexity of the packaging process can be reduced, and thus the total packaging cost can be reduced.

[0014] As an improvement of the above structure of the present application, the projection of the second chip on the first chip is located inside the edge of the first surface.

[0015] As an improvement of the above structure of the present application, the first insulating packaging layer extends to the edge of the first surface.

[0016] As an improvement of the above structure of the present application, the edge of the first insulating packaging layer is flush with the edge of the first surface.

[0017] As an improvement of the above structure of the present application, the first insulating packaging layer is an epoxy organic layer.

[0018] As an improvement of the above structure of the present application, pins are arranged on the first chip and the second chip, and the pins are connected with the first electrical connection structure.

[0019] As an improvement of the above structure of the present application, the pins comprise first pins arranged on the first chip. The first pins are arranged on the first surface, and the positions of the first pins and the second chip do not overlap with each other.

[0020] As an improvement of the above structure of the present application, the pins further comprise second pins arranged on the second chip. The second pins are located on the side surface of the second chip which is away from the first chip.

[0021] As an improvement of the above structure of the present application, an adhesive layer is arranged between the first chip and the second chip. The adhesive layer is configured to adhere the first chip and the second chip.

[0022] As an improvement of the above structure of the present application, an optical lens is further included. The first chip has a light ray sensing surface which faces away from the second chip. The optical lens is adhered to the light ray sensing surface by optical adhesive.

[0023] As an improvement of the above structure of the present application, the first electrical connection structure comprises a first electrical contact penetrating through opposite sides of the first insulating encapsulation layer and a second electrical contact penetrating through opposite sides of the first chip, and the first electrical contact is in contact with the second chip and the second electrical contact respectively.

[0024] As an improvement of the above structure of the present application, an insulating layer is further provided, and the insulating layer is arranged on a side surface of the first insulating encapsulation layer away from the first chip.

[0025] As an improvement of the above structure of the present application, a second insulating encapsulation layer is further provided, and the second insulating encapsulation layer wraps at least part of the outer surface of the chip body.

[0026] As an improvement of the above structure of the present application, the second insulating encapsulation layer wraps the outer surface of the first chip and the remaining surface of the first insulating encapsulation layer which is not provided with the insulating layer.

[0027] As an improvement of the above structure of the present application, the second chip is at least two, and the at least two second chips are arranged on the first surface.

[0028] As an improvement of the above structure of the present application, the first chip is at least two.

[0029] As an improvement of the above structure of the present application, a second electrical connection structure is further provided, and the second electrical connection structure penetrates through the insulating layer, and the second electrical connection structure is in contact with the first electrical connection structure.

[0030] As an improvement of the above structure of the present application, a pad is arranged on a surface of a side of the insulating layer away from the second chip, and the pad is in contact with the second electrical connection structure.

[0031] As an improvement of the above structure of the present application, an electrical contact bump protruding from the surface of the insulating layer is further arranged on the pad.

[0032] The second aspect of the present application provides a 3D chip encapsulation method applied to the above-provided 3D chip encapsulation structure, and the method comprises:

[0033] arranging a second chip on a first surface of a first chip;

[0034] arranging a first insulating encapsulation layer on the first surface, and the first insulating encapsulation layer wraps a surface of the second chip;

[0035] forming a first electrical connection structure on the first insulating encapsulation layer, and the first electrical connection structure is electrically connected between the first chip and the second chip.

[0036] The second aspect of the present application provides a 3D chip packaging method, comprising: disposing a second chip on a first surface of a first chip; disposing a first insulating packaging layer on the first surface, the first insulating packaging layer wrapping a surface of the second chip; and forming a first electrical connection structure on the first insulating packaging layer, the first electrical connection structure being connected between the first chip and the second chip. In the above method, the second chip is first disposed on the first surface of the first chip, and then the first insulating packaging layer is formed on the first surface, so that the first insulating packaging layer wraps the surface of the second chip, and the first electrical connection structure is formed on the first insulating packaging layer, so that the first electrical connection structure is electrically connected between the first chip and the second chip, thereby realizing 3D packaging of the first chip and the second chip, improving the transmission speed of the first chip and the second chip, optimizing the packaging size, simplifying the packaging process of the first chip and the second chip, reducing the complexity of the packaging process, and thus reducing the total packaging cost.

[0037] As an improvement of the above packaging method of the present application, the first electrical connection structure formed on the first insulating packaging layer specifically comprises:

[0038] etching an electrical connection hole on the first insulating packaging layer, wherein one end of the electrical connection hole exposes a first pin on the surface of the first chip, and the other end of the electrical connection hole exposes a second pin on the surface of the second chip;

[0039] forming an electrical connection body in the electrical connection hole to form the first electrical connection structure, the first electrical connection structure being electrically connected between the first pin of the first chip and the second pin of the second chip.

[0040] As an improvement of the above packaging method of the present application, before the second chip is disposed on the first surface of the first chip, the method further comprises:

[0041] forming a first pin on the first surface of the first chip and a second pin on the surface of the second chip away from the first surface.

[0042] As an improvement of the above packaging method of the present application, after the first electrical connection structure is formed on the first insulating packaging layer, the method further comprises:

[0043] grinding the side of the first chip away from the first surface to have a predetermined thickness.

[0044] As an improvement of the above packaging method of the present application, after the side of the first chip away from the first surface is ground, the method further comprises:

[0045] forming an adhesive film on the side of the first chip away from the first surface.

[0046] As an improvement of the above packaging method of the present application, the disposing the second chip on the first surface of the first chip further comprises:

[0047] grinding the second incoming wafer containing a plurality of second chips to a preset thickness;

[0048] cutting and separating the second incoming wafer ground to the preset thickness to form a plurality of single second chips.

[0049] In addition to the above described technical problems solved by the present application, technical features constituting the technical solutions, and beneficial effects brought by these technical features, other technical problems solved by the 3D chip packaging structure and packaging method provided by the present application, other technical features included in the technical solutions, and beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments of the present application or the prior art will be briefly introduced. Obviously, the drawings in the following description are only a part of the embodiments of the present application, and these drawings and the written description are not intended to limit the scope of the present application concept in any way, but to illustrate the present application concept to those skilled in the art by referring to specific embodiments. Those skilled in the art can also obtain other drawings without creative labor on the basis of these drawings.

[0051] Figure 1 is a cross-sectional view of a 3D chip packaging structure in the related art;

[0052] Figure 2 is a cross-sectional view of one structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0053] Figure 3 is a cross-sectional view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0054] Figure 4 is a cross-sectional view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0055] Figure 5 is a cross-sectional view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0056] Figure 6 is a cross-sectional view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0057] Figure 7 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0058] Figure 8 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0059] Figure 9 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0060] Figure 10 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0061] Figure 11 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0062] Figure 12 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0063] Figure 13 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0064] Figure 14 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application;

[0065] Figure 15 A cross-sectional schematic view of another structure of a 3D chip packaging structure provided by an embodiment of the present application; Figure 2 A flowchart of a 3D chip packaging method provided by an embodiment of the present application;

[0066] Figures 16-22 A cross-sectional schematic view of a packaging process provided by an embodiment of the present application. Figure 2

[0067] Legend of reference signs:

[0068] 100: 3D chip packaging structure; 110: first chip; 11: first incoming wafer;

[0069] 120: second chip; 12: second incoming wafer; 121: adhesive layer;

[0070] 130: first insulating packaging layer; 131: electrically connecting hole; 140: first electrically connecting structure;

[0071] 141: first pin; 142: second pin; 143: first electrically contacting part;

[0072] ​144: second electrical contact; 151: optical lens; 152: optical adhesive;

[0073] 160: insulating layer; 170: second insulating encapsulating layer; 180: second electrical connection structure;

[0074] 181: pad; 182: electrical contact bump; 190: back adhesive film;

[0075] 200-organic layer; 210: conductive layer; 300: silicon substrate. DETAILED DESCRIPTION

[0076] In the related art, the 3D chip packaging process is complex, and the main reason for the high total packaging cost is that, for example, Figure 1 The packaging process of the 3D packaging structure 100 in the related art is as follows: step 1: providing a silicon substrate 300 and forming an encapsulating groove on the silicon substrate 300; step 2: disposing a second chip 120 ground to a preset thickness in the encapsulating groove; step 3: forming a first electrical connection structure 140 penetrating the silicon substrate 300 on the silicon substrate 300, and disposing the silicon substrate 300 provided with the second chip 120 on the surface of a first chip 110 on a first wafer, and bonding or adhering the silicon substrate 300 to the first chip 110, and the first electrical connection structure 140 is electrically connected between the first chip 110 and the second chip 120; and finally, the first chip 110 is ground to a preset thickness, the back adhesive film is pasted on the side of the first chip 110 away from the second chip 120, and the first chip 110 is cut into a single chip, and finally formed as a 3D packaging structure as shown in Figure 1

[0077] However, when packaging the first chip and the second chip, an encapsulating groove of a preset depth needs to be formed on the silicon substrate 300, but the depth of the encapsulating groove is difficult to control when it is formed. In order to ensure the size accuracy of the encapsulating groove, there are technical problems of complex packaging process and high total packaging cost.

[0078] Therefore, the researchers propose a 3D chip packaging structure and a packaging process, which can improve the transmission speed of the chip, optimize the packaging size, simplify the packaging process, and reduce the packaging cost. The researchers change the packaging process, do not process the encapsulating groove on the silicon substrate, but dispose the second chip on the first surface of the first chip, form a first insulating encapsulating layer on the first surface, so that the first insulating encapsulating layer wraps the surface of the second chip, and then form a first electrical connection structure penetrating the first insulating layer on the first insulating encapsulating layer, so that the first electrical connection structure is electrically connected between the first chip and the second chip, thereby realizing the 3D packaging of the first chip and the second chip. In this way, the encapsulating groove on the silicon substrate can be avoided, thereby simplifying the packaging process and reducing the total packaging cost.

[0079] ​The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0080] Example 1

[0081] Figure 2 This is a cross-sectional schematic diagram of the 3D chip packaging structure provided in Embodiment 1 of this application.

[0082] Combination Figure 2 This application provides a 3D chip packaging structure 100, including a chip body. The chip body includes a first chip 110, a second chip 120, a first insulating encapsulation layer 130, and a first electrical connection structure 140. The first chip 110 has a first surface, the second chip 120 is disposed on the first surface of the first chip 110, the first insulating encapsulation layer 130 is disposed on the first surface and wraps around the surface of the second chip 120, and the first electrical connection structure 140 penetrates the first insulating encapsulation layer 130 and is electrically connected between the first chip 110 and the second chip 120.

[0083] It is understood that the first surface of the first chip 110 refers to the surface of the first chip 110 facing the second chip 120.

[0084] In the above solution, by placing the second chip 120 on the first chip 110 and forming the first insulating encapsulation layer 130 on the first surface and wrapping it around the surface of the second chip 120, the first chip 110 and the second chip 120 are encapsulated. The first electrical connection structure 140 penetrates the first insulating encapsulation layer 130, so that the first electrical connection structure 140 is electrically connected between the first chip 110 and the second chip 120. By stacking the first chip 110 and the second chip 120, the distance of the transmission line between the first chip 110 and the second chip 120 can be shortened, thereby improving the chip transmission speed and optimizing the package size. In addition, the packaging process of the first chip 110 and the second chip 120 can be simplified, the complexity of the packaging process can be reduced, and the total packaging cost can be reduced.

[0085] In one possible implementation, there are multiple first electrical connection structures 140, and the first chip 110 and the second chip 120 can be electrically connected through the first electrical connection structures 140 (e.g., ...). Figure 2As shown in the diagram, the first electrical connection structure 140 is then electrically led out to the contact solder joint outside the chip body; or, the first chip 110 can also be led out to the contact solder joint outside the chip body through a single first electrical connection structure 140, and the second chip 120 can also be led out to the contact solder joint outside the chip body through another electrical connection structure 140, so that the first chip 110 and the second chip 120 are electrically connected outside the chip body.

[0086] In some embodiments, the first insulating encapsulation layer 130 may be an epoxy organic layer made of epoxy organic material; for example, the material of the epoxy organic layer may be epoxy resin. Since epoxy resin has good physical and mechanical properties, electrical insulation properties and adhesive properties, it has better economic advantages compared with silicon substrates made of silicon material, thereby reducing the total cost of encapsulation while ensuring encapsulation performance.

[0087] Of course, the epoxy organic layer can also be other epoxy organic materials, and this application does not impose specific limitations on this.

[0088] In some embodiments, the projection of the second chip 120 onto the first chip 110 is located inside the edge of the first surface, that is, the cross-sectional dimension of the second chip 120 parallel to the first surface is smaller than the cross-sectional dimension of the first chip 110. In this way, the overall size of the 3D chip structure can be further optimized.

[0089] In some embodiments, the first insulating encapsulation layer 130 extends to the edge of the first surface. That is, when the second chip 120 is disposed on the first chip 110, the first insulating encapsulation layer 130 is located on the first surface and wraps around the surface of the second chip 120, and the first insulating encapsulation layer 130 extends to the edge of the first chip 110. In other words, the area of ​​the first insulating encapsulation layer 130 on the first surface is less than or equal to that of the first surface. In this way, the overall size of the packaged 3D chip package structure 100 can be reduced to optimize the size of the 3D chip package structure 100.

[0090] In some embodiments, the edge of the first insulating encapsulation layer 130 is flush with the edge of the first surface, thereby reducing the overall size of the packaged 3D chip packaging structure 100 while improving the overall reliability of the 3D chip packaging structure 100.

[0091] It is understandable that when the projection of the second chip 120 on the first chip 110 is located inside the edge of the first surface, by setting the first insulating encapsulation layer 130 on the first surface and wrapping the surface of the second chip, sufficient space can be provided for subsequent metal rewiring such as circuits and signal lines between the first chip 110 and the second chip 120. Of course, the surface of the second chip 120 can also be protected, thereby improving the working reliability of the second chip 120.

[0092] In other embodiments, the projection of at least one side of the second chip 120 onto the first chip 110 may also be located outside the edge of the first surface. It is understood that at least one side of the second chip 120 is suspended relative to the first chip 110. In this case, in order to improve the support stability of the second chip 120, the first insulating encapsulation layer 130 disposed on the first surface of the first chip 110 wraps the second chip 120 to support and protect the second chip 120, thereby improving the working reliability of the second chip 120. In addition, it can also provide a sufficiently large space for subsequent metal rewiring between the first chip 110 and the second chip 120.

[0093] In some embodiments, both the first chip 110 and the second chip 120 are provided with pins, which are connected to the first electrical connection structure 140. That is, the first electrical connection structure 140 is wired on the first insulating encapsulation layer 130 according to actual needs to bring out the pins on the first chip 110 and the second chip 120, so that the first electrical connection structure 140 is electrically connected to the first chip 110 and the second chip 120 respectively through the pins, thereby improving the connection reliability between the first electrical connection structure 140 and the first chip 110 and the second chip 120.

[0094] For example, the pins include a first pin 141 disposed on the first chip 110, the first pin 141 being disposed on the first surface, and the position of the first pin 141 not overlapping the position of the second chip 120, so that the first electrical connection structure 140 is electrically connected to the first chip 110 through the first pin 141.

[0095] The pin may also include a second pin 142 disposed on the second chip 120, the second pin 142 being located on the side surface of the second chip 120 opposite to the first chip 110, so that the first electrical connection structure 140 is electrically connected to the second chip 120 through the second pin 142.

[0096] exist Figure 2In the first chip 110, a first pin 141 is provided on the first surface, and a second pin 142 is provided on the side surface of the second chip 120 opposite to the first chip 110. A first electrical connection structure 140 is electrically connected between the first pin 141 and the second pin 142, so that the first chip 110 and the second chip 120 are electrically connected.

[0097] In some embodiments, the first pin 141 and the second pin 142 may be Ni / Au-modified to improve the reliability of the electrical connection.

[0098] In some embodiments, after the second chip 120 is disposed on the first surface of the first chip 110, the second chip 120 can be connected to the first chip 110 by adhesive bonding.

[0099] As in Figure 2 In this process, an adhesive layer 121 is provided between the first surface of the second chip 120 and the first surface of the first chip 110, so that the second chip 120 is bonded to the first surface of the first chip 110 through the adhesive layer 121; wherein, the adhesive layer 121 can be made of an adhesive material, as long as it can achieve the bonding of the first chip 110 and the second chip 120, and there is no specific limitation.

[0100] In some embodiments, there may be at least two second chips 120, each second chip 120 being disposed on the first surface. For example, as in... Figure 3 In this design, there are two second chips 120, which are disposed on the first surface of the first chip 110. Each second chip 120 can be bonded to the first surface via an adhesive layer 121. The adhesive layer 121 corresponding to each second chip 120 can be independent or a shared adhesive layer; this application does not impose specific limitations on this. Furthermore, the two second chips 120 can be identical or different. Preferably, a gap is provided between each second chip 120.

[0101] In the above scheme, by placing at least two second chips 120 on the first surface, the chip integration can be improved.

[0102] In some embodiments, combined with Figure 2 , Figure 3 and Figure 11 As shown, the first electrical connection structure 140 can be a conductive lead that penetrates the first insulating encapsulation layer 130, so that one end of the first electrical connection structure 140 is connected to the first chip 110 and the other end of the first electrical connection structure 140 is connected to the second chip 120, so as to realize electrical conduction between the first chip 110 and the second chip 120.

[0103] The first electrical connection structure 140 can be processed using metal coating processes such as sputtering, electroplating, and vapor deposition. The material of the first electrical connection structure 140 can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, silver, nickel, or a composite or alloy of the above metals.

[0104] In some embodiments, the 3D chip packaging structure 100 further includes an insulating layer 160, which is disposed on the surface of the first insulating packaging layer 130 on the side opposite to the first chip 110.

[0105] Combination Figures 2-5 As shown, the 3D chip packaging structure 100 also includes a second electrical connection structure 180. The second electrical connection structure 180 can be metal redistributed in the insulating layer 160, and the second electrical connection structure 180 is in contact with the first electrical connection structure 140. In this way, by setting the second electrical connection structure 180 to metal redistribute in the insulating layer 160, the electrical connection point between the first electrical connection structure 140 and external devices can be changed to adapt to the connection requirements of different products.

[0106] The second electrical connection structure 180 can be processed using metal coating processes such as sputtering, electroplating, and vapor deposition. The material of the second electrical connection structure 180 can be conductive materials such as molybdenum, ruthenium, gold, silver, nickel, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or composites or alloys of the above metals.

[0107] To improve the connection reliability between external devices and the second electrical connection structure 180, combined with Figure 4 As shown in this application, at least a portion of the pads 181 are provided on the surface of the insulating layer 160 facing away from the second chip 120, and at least a portion of the pads 181 are in contact with the second electrical connection structure 180. The pads 181 are directly exposed on the surface of the insulating layer 160 so that external devices can be electrically connected to the 3D chip package structure 100 through the pads 181.

[0108] Among them, pad 181 can be Ni / Au-modified to improve the reliability of electrical connections.

[0109] To further improve the reliability of the electrical connection between external devices and the second electrical connection structure 180, in this embodiment, the pad 181 is further provided with electrical contact bumps 182 protruding from the surface of the insulating layer 160, for example, in Figure 2 and Figure 3 In this design, the electrical contact bump 182 can be a solder ball, which serves as a solder joint for electrical connection with external devices to improve the reliability of the electrical connection. The solder ball can be made of materials such as tin.

[0110] Of course, instead of providing pads 181 on the insulating layer 160, electrical contact bumps 182 that are electrically connected to the second electrical connection structure 180 can be directly provided on the surface of the insulating layer 160, such as... Figure 6 As shown, this can simplify the process and reduce costs.

[0111] Specifically, the 3D chip packaging structure 100 can be electrically connected to other external devices via solder balls. To accommodate the electrical connection between devices and solder balls in different locations, the position of the solder balls can be adaptively adjusted according to changes in the metal redistribution structure. To meet different metal redistribution requirements, in this embodiment, the insulating layer 160 can be at least one layer; that is, the insulating layer 160 can be one or more layers. When the insulating layer 160 is multiple layers, the second electrical connection structure 180 can undergo multiple metal redistributions so that the electrical contact bumps 182 are positioned appropriately as needed; for example, in Figure 5 In the middle, the insulation layer 160 is a single-layer structure; while in... Figure 2 , Figure 3 , Figure 4 , Figures 6-14 In the middle, the insulating layer 160 has a double-layer structure. Of course, the insulating layer 160 can also be set to two or more layers as needed to further rewire the second electrical connection structure 180.

[0112] In some embodiments, the 3D chip packaging structure 100 can be a photosensitive chip, such as... Figure 7 As shown, it also includes an optical lens 151. The first chip 110 has a light-sensing surface on the side opposite to the second chip 120. That is, the optical lens 151 is disposed on the side of the first chip 110 opposite to the first surface. The optical lens 151 is bonded to the light-sensing surface by optical adhesive 152. The optical lens 151 can be optical glass or the like.

[0113] In some embodiments, the optical adhesive 152 has good light transmittance to improve light transmission and thus improve the operational reliability of photosensitive chips.

[0114] It should be noted that the projection of the optical adhesive 152 onto the light-sensing surface of the first chip 110 covers the entire surface of the light-sensing surface. In this way, the optical adhesive 152 not only achieves bonding between the first chip 110 and the optical lens 151 and improves light transmittance, but also supports the first chip 110 and the optical lens 151 to enhance the strength of the first chip 110 and avoid the problem of lower strength due to the thinning of the first chip 110.

[0115] exist Figure 7In the first electrical connection structure 140, there are a first electrical contact portion 143 penetrating through the opposite sides of the first insulating encapsulation layer 130 and a second electrical contact portion 144 penetrating through the opposite sides of the first chip 110. The first electrical contact portion 143 is in contact with the second chip 120 and the second electrical contact portion 144 respectively.

[0116] In some embodiments, the first electrical contact 143 can be a conductive lead penetrating the first insulating encapsulation layer 130. Since the first chip 110 is made of semiconductor materials such as silicon, a TSV (Through Silicon Via) hole penetrating the first chip 110 can be provided on the first chip 110, so that the TSV hole exposes the pins on the upper surface (i.e., the first surface) of the first chip 110, and conductive metal is filled in the TSV hole to form a second electrical contact 144. A portion of the second electrical contact 144 can be led out to the first surface of the first chip 110, so that the second electrical contact 144 is electrically connected to the pins on the first chip 110.

[0117] Please refer to Figure 8 As shown, in some embodiments, a second insulating encapsulation layer 170 is also included. The second insulating encapsulation layer 170 wraps around at least a portion of the outer surface of the chip body. Thus, the second insulating encapsulation layer 170 can protect the outer surface of the chip body from damage caused by external forces, thereby improving the operational reliability of the chip body. Furthermore, by providing the second insulating encapsulation layer 170, the area of ​​metal redistribution in the 3D chip packaging structure 100 can be increased, allowing the 3D chip packaging structure 100 to adapt to the arrangement requirements of electrical connection points of different external devices. Figure 8 In this process, by setting a second insulating encapsulation layer 170 and fabricating electrical contact bumps 182 (solder joints) on top of the second insulating encapsulation layer 170, more electrical contact bumps 182 can be made, thereby increasing the range of applications.

[0118] In some embodiments, the second insulating encapsulation layer 170 covers the outer surface of the first chip 110 and the remaining surfaces of the first insulating encapsulation layer 130 where the insulating layer 160 is not disposed, such as... Figure 8 As shown, the second insulating encapsulation layer 170 can protect and support the exposed portions of the first chip 110 and the first insulating encapsulation layer 130; in addition, the projection of the insulating layer 160 on the second insulating encapsulation layer 170 covers the second insulating encapsulation layer 170, so that multiple solder joints can be led out on the upper surface of the insulating layer 160 to accommodate external devices with different structures.

[0119] In other embodiments, the second insulating encapsulation layer 170 wraps around the outer surface of the first chip 110, such as... Figure 9As shown in the embodiment of this application, an organic layer 200 is provided between the first chip 110 and the first insulating encapsulation layer 130. When the position of the first pin 141 on the first chip 110 is not set properly or the area of ​​the first chip 110 is small, the organic layer 200 can be provided to allow for metal rewiring above the organic layer 200, thereby meeting the product's packaging requirements.

[0120] In other embodiments, a conductive layer 210 is disposed on the organic layer 200. The conductive layer 210 is electrically connected between the first electrical connection structure 140 and the first pin 141. A portion of the conductive layer 210 can be led out to the side of the organic layer 200 facing away from the first surface, so that the first electrical connection structure 140 can be perpendicularly connected to the conductive layer 210. The electrical connection point between the first electrical connection structure 140 and the conductive layer 210 does not overlap with the electrical connection point between the conductive layer 210 and the first pin on the first chip 110. Thus, by performing metal redistribution above the organic layer 200, the position of the electrical connection point between the first electrical connection structure 140 and the first pin 141 can be adjusted, thereby improving its applicability.

[0121] It is understood that in the above embodiments, the organic layer 200 can be multiple layers, and the conductive layer 210 can be multiple layers.

[0122] In some embodiments, there may be at least two first chips 110, and at least two first chips 110 are packaged with a second chip 120. This can increase the integration of the 3D chip package structure 100 while increasing effects such as storage capacity.

[0123] For example, in Figure 10 In this configuration, there are two first chips 110. Preferably, the first surfaces of the two first chips 110 are located on the same plane. The two first chips 110 may be identical or different. Preferably, a gap is provided between each first chip 110.

[0124] In addition, the outer surface of each first chip 110 is covered with a second insulating encapsulation layer 170 to protect the outer surface of the first chip 110, thereby improving the working reliability of the first chip 110. Furthermore, by setting the second insulating encapsulation layer 170, the support reliability of the second chip 120 can be improved, and the area of ​​metal rewiring of the electrical connection structure in the chip body can also be increased.

[0125] In some embodiments, such as Figure 12As shown, there is one first chip 110, and a second chip 120 is disposed on the first chip 110. To perform metal rewiring on the first electrical connection structure 140, so that the first electrical connection structure 140 is electrically connected to the first pin 141 on the first chip 110, an organic layer 200 can be disposed between the first chip 110 and the second chip 120. Metal rewiring of the first electrical connection structure 140 is achieved above the organic layer 200. Figure 12 In the first electrical connection structure 140, the position of the first electrical connection structure 140 vertically connected on the first chip 110 does not overlap with the position of the first pin 141. Therefore, the first electrical connection structure 140 and the first pin 141 are electrically connected by metal rewiring.

[0126] Of course, when the positions of the first electrical connection structure 140 and the second pin 142 on the second chip 120 do not overlap, an organic layer 200 can also be provided on the side of the second chip 120 away from the first surface, such as... Figure 13 As shown, by rewiring the first electrical connection structure 140 with metal overlays above the organic layer 200, an electrical connection is achieved between the first electrical connection structure 140 and the second pin 142 on the second chip 120.

[0127] Alternatively, when the first electrical connection structure 140 is vertically connected to the first chip 110 and the first electrical connection structure 140 is vertically connected to the second chip 120, and these locations do not overlap with the locations of the first pin 141 and the second pin 142, an organic layer 200 can be provided between the first chip 110 and the second chip 120, and an organic layer 200 can also be provided on the side of the second chip 120 facing away from the first surface. Figure 14 As shown, by rewiring the first electrical connection structure 140 with metal over the organic layer 200, the first electrical connection structure 140 is electrically connected to the first pin 141 and the second pin 142 respectively, thereby improving the wiring flexibility of the first electrical connection structure 140 and effectively improving space utilization.

[0128] In the above embodiments, a backing film 190 can also be formed on the surface of the first chip 110 facing away from the second chip 120 to protect the surface of the first chip 110, such as... Figure 2 As shown, since the thickness of the adhesive film 190 is very small, it is possible to improve the safety and reliability of the first chip 110 while ensuring the size of the 3D chip packaging structure 100 is reduced.

[0129] Example 2

[0130] Figure 15This is a schematic flowchart illustrating a 3D chip packaging method provided in an embodiment of this application. In this embodiment, [the method is described in the original text]. Figure 2 The 3D chip packaging method provided in this application will be illustrated by taking the packaging method of the structure in the middle as an example.

[0131] Reference Figure 15 As shown, this application provides a 3D chip packaging method applied to the 3D chip packaging structure 100 provided in the above embodiment. The method includes:

[0132] Step S101: Place the second chip on the first surface of the first chip.

[0133] Specifically, such as Figure 16 and Figure 17 As shown, before the second chip 120 is disposed on the first surface of the first chip 110, a first incoming wafer 11 and a second incoming wafer 12 are provided. The first incoming wafer 11 contains a plurality of first chips 110, and the second incoming wafer 12 contains a plurality of second chips 120.

[0134] It should be noted that the first pin 141 and the second pin 142 have been pre-fabricated on the first incoming wafer 11 and the second incoming wafer 12, respectively, as shown below. Figure 16 and Figure 17 As shown in the figure; in addition, before the second chip 120 is disposed on the first surface of the first chip 110, the second incoming wafer 12 is first ground to a preset thickness through processes such as grinding. The preset thickness can be adaptively designed according to actual needs, and no specific limitation is made here.

[0135] Then the second incoming wafer 12 is cut into individual second chips 120, such as... Figure 18 This involves grinding the second incoming wafer 12 to a preset thickness and then cutting it into a single second chip 120.

[0136] The cut second chip 120 is attached to the first chip 110 on the first incoming wafer 11 using adhesive or other bonding layers. Figure 19 The structure shown is such that the second chip 120 is attached to at least one first chip 110 on the first incoming wafer 11.

[0137] Step S102: A first insulating encapsulation layer is formed on the first surface, and the first insulating encapsulation layer is wrapped around the surface of the second chip.

[0138] like Figure 20As shown, after the second chip 120 is attached to the first chip 110, a first insulating encapsulation layer 130 can be formed on the first surface of the first chip 110 through an extrusion molding process. This first insulating encapsulation layer 130 then wraps around the surface of the second chip 120, thereby encapsulating the first chip 110 and the second chip 120. The encapsulation process is simple, thus reducing encapsulation costs. Of course, the first insulating encapsulation layer 130 can also be formed on the first surface of the first chip 110 through processes such as spraying, spin coating, film application, or screen printing; no specific limitations are imposed on this.

[0139] Step S103: A first electrical connection structure is formed in the first insulating encapsulation layer, and the first electrical connection structure is electrically connected between the first chip and the second chip.

[0140] like Figure 21 As shown, after the first insulating encapsulation layer 130 is formed on the first surface of the first chip 110, electrical connection holes 131 can be formed on the first insulating encapsulation layer 130 by processes such as laser, machining, plasma, and etching, so that one end of the electrical connection hole 131 exposes the pins on the first surface of the first chip 110, and the other end of the electrical connection hole 131 exposes the pins on the surface of the second chip 120.

[0141] After an electrical connection hole 131 is formed on the first insulating encapsulation layer 130, an electrical connector can be formed in the electrical connection hole 131 by metal coating processes such as sputtering, electroplating, and vapor deposition to form a first electrical connection structure 140, so that the first electrical connection structure 140 is electrically connected to the pins of the first chip 110 and the second chip 120 respectively.

[0142] After the first electrical connection structure 140 is formed, as Figure 22As shown, the lines of the first electrical connection structure 140 can be brought out using wafer-level chip-scale packaging (WLCSP) technology, such as 2P2M, 1P1M, 2P1M, xPyM, etc. Among these, 2P2M, 2P1M, and xPyM (where x>1, y≥1) are techniques for growing electrical contact bumps 182 at appropriate locations on the chip through metal redistribution. These techniques include photolithography, sputtering, etching, electroplating, resist removal, and reflow. In this embodiment, 2P2M or 1P1M can be used. The P1M process forms an insulating layer 160 on the first insulating package layer 130 and a second electrical connection structure 180 on the insulating layer 160, so that the pads 181 or electrical contact bumps on the insulating layer 160 can be formed at appropriate positions on the chip body by means of metal redistribution. The specific design can be adapted as needed. The specific formation of the insulating layer 160 and the second electrical connection structure 180 through the insulating layer 160 by the 2P2M or 1P1M process can be referred to the relevant technology, which will not be elaborated here.

[0143] It should be noted that in xPyM, the x layer represents an organic layer and the y layer represents a metal layer. If the insulating layer 160 is prepared by processes such as 2P2M, 1P1M, 2P1M, and xPyM, then the insulating layer 160 is multi-layered, and the multi-layered insulating layer 160 is formed by alternating layers of organic and metal layers.

[0144] After the first electrical connection structure 140 is formed in the first insulating encapsulation layer 130, the method further includes grinding the side of the first chip 110 away from the first surface by a process such as grinding, so that the first chip 110 has a preset thickness; wherein, the preset thickness of the first chip 110 can be adaptively designed as needed, and no specific limitation is made here.

[0145] After the first chip 110 is ground to a preset thickness, the ground first chip 110 is used as a reference unit to cut and separate the cutting channels between adjacent first chips 110 to form an independent 3D chip packaging structure.

[0146] After the first chip 110 is ground to a preset thickness and before cutting, an adhesive film 190 can be formed on the side of the first chip 110 facing away from the first surface, such as... Figure 2 As shown, the surface of the first chip 110 is protected by the adhesive film 190, thereby improving the safety and reliability of the first chip 110. Of course, the adhesive film 190 may not be formed on the side of the first chip 110 facing away from the first surface.

[0147] and Figures 3-11 The corresponding 3D chip packaging method can be referred to the above packaging method. The following only introduces the packaging method.Figures 3-11 Zhongyu Figure 2 The structure varies depending on the different steps in the preparation process.

[0148] Figure 3 The structure and Figure 2 The manufacturing process is the same for both structures, except that when the second chip 120 is placed on the first chip 110, the number of second chips 120 can be two or more, depending on the specific requirements. They are then attached to the first chip 110 by bonding. The two second chips 120 can be the same chip or different chips.

[0149] Figure 8 The structure and Figure 2 The difference in the fabrication process lies in the fact that after the first electrical connection structure 140 is formed in the first insulating encapsulation layer 130 (e.g. Figure 19 As shown in the diagram, the first incoming wafer 11 is first cut and separated into individual first chips 110. Then, the upper surface (i.e., the first surface) of the first chip 110 is placed face down on another carrier plate. The carrier plate can be a bare silicon wafer, carrier glass, or other structures. Then, a second insulating encapsulation layer 170 is formed on the surface of the first chip 110 and the first insulating encapsulation layer 130. After the second insulating encapsulation layer 170 is formed, the first chip 110 is peeled off from the carrier plate. Then, an insulating layer 160 is formed on the surface of the first insulating encapsulation layer 130 that is opposite to the first chip 110, so that the insulating layer 160 covers the surface of the second insulating encapsulation layer 170. A second electrical connection structure 180 and other structures are fabricated in the insulating layer 160.

[0150] Figure 9 The structure and Figure 2 The difference in the fabrication process of the structure is as follows: Before the second chip 120 is attached to the first incoming wafer 11, the first incoming wafer 11 is first ground to a preset thickness, and then the first incoming wafer 11 is cut into individual first chips 110. Then, the upper surface (i.e., the first surface) of the first chip 110 is placed face down on another carrier plate, and then a second insulating encapsulation layer 170 is formed on the exposed outer surface of the first chip 110. After the second insulating encapsulation layer 170 is formed, the first chip 110 is peeled off from the carrier plate. Then, an organic layer 200 is formed on the surface of the first chip 110 that is not covered by the second insulating encapsulation layer 170, and a conductive layer 210 is made on the organic layer 200. Then, the second chip 120 is placed on the side of the organic layer 200 away from the first chip 110, and a first insulating encapsulation layer 130 is formed on the surface of the organic layer 200, so that the first insulating encapsulation layer 130 covers the surface of the second chip 120, and a first electrical connection structure 140 is formed on the first insulating encapsulation layer 130.

[0151] Figure 10 and Figure 9 The manufacturing process is the same, except that there are two first chips 110. Of course, there can also be multiple first chips 110.

[0152] The 3D chip packaging structure provided in this application includes a first chip, a second chip, a first insulating encapsulation layer, and a first electrical connection structure. The first chip has a first surface, the second chip is disposed on the first surface of the first chip, the first insulating encapsulation layer is disposed on the first surface and covers the surface of the second chip, and the first electrical connection structure penetrates the first insulating encapsulation layer and is electrically connected between the first chip and the second chip. In the above solution, by disposing the second chip on the first surface of the first chip and forming the first insulating encapsulation layer on the first surface and covering the surface of the second chip, the chip's transmission speed can be improved, the package size optimized, and the packaging process of the first and second chips simplified, reducing the complexity of the packaging process and thus reducing the total packaging cost.

[0153] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0154] In the above description, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A 3D chip packaging structure, characterized in that, Includes a chip body, the chip body comprising: The first chip has a first surface; The second chip is disposed on the first surface of the first chip; A first insulating encapsulation layer is disposed on the first surface and covers the surface of the second chip; and A first electrical connection structure, which penetrates the first insulating encapsulation layer and is electrically connected between the first chip and the second chip; The first chip is provided with pins, and the pins include a first pin provided on the first chip; An organic layer is provided between the first chip and the first insulating encapsulation layer. A conductive layer is provided on the organic layer. The conductive layer is electrically connected between the first electrical connection structure and the first pin. A portion of the conductive layer is led out to the side of the organic layer opposite to the first surface, so that the first electrical connection structure is perpendicularly connected to the conductive layer, and the electrical connection point between the first electrical connection structure and the conductive layer does not overlap with the electrical connection point between the conductive layer and the first pin on the first chip. It also includes an insulating layer disposed on the side surface of the first insulating encapsulation layer opposite to the first chip; It also includes a second insulating encapsulation layer, which wraps around the outer surface of the first chip and the remaining surface of the first insulating encapsulation layer where the insulating layer is not disposed.

2. The 3D chip packaging structure according to claim 1, characterized in that, The projection of the second chip onto the first chip is located inside the edge of the first surface.

3. The 3D chip packaging structure according to claim 1, characterized in that, The first insulating encapsulation layer extends to the edge of the first surface.

4. The 3D chip packaging structure according to claim 3, characterized in that, The edge of the first insulating encapsulation layer is flush with the edge of the first surface.

5. The 3D chip packaging structure according to claim 1, characterized in that, The first insulating encapsulation layer is an epoxy organic layer.

6. The 3D chip packaging structure according to any one of claims 1-5, characterized in that, The second chip has pins that are connected to the first electrical connection structure.

7. The 3D chip packaging structure according to claim 6, characterized in that, The first pin is disposed on the first surface, and the position of the first pin does not overlap with the position of the second chip.

8. The 3D chip packaging structure according to claim 6, characterized in that, The pin also includes a second pin disposed on the second chip, the second pin being located on the side surface of the second chip opposite to that of the first chip.

9. The 3D chip packaging structure according to any one of claims 1-5, characterized in that, An adhesive layer is provided between the first chip and the second chip, and the adhesive layer is configured to bond the first chip and the second chip together.

10. The 3D chip packaging structure according to any one of claims 1-5, characterized in that, It also includes an optical lens, wherein the first chip has a light-sensing surface facing away from the second chip, and the optical lens is bonded to the light-sensing surface by optical adhesive.

11. The 3D chip packaging structure according to claim 10, characterized in that, The first electrical connection structure includes a first electrical contact portion penetrating through opposite sides of the first insulating encapsulation layer and a second electrical contact portion penetrating through opposite sides of the first chip. The first electrical contact portion makes contact and conduction with the second chip and the second electrical contact portion, respectively.

12. The 3D chip packaging structure according to claim 1, characterized in that, The second chip comprises at least two chips, and at least two second chips are disposed on the first surface.

13. The 3D chip packaging structure according to claim 1, characterized in that, The first chip consists of at least two chips.

14. The 3D chip packaging structure according to claim 1, characterized in that, It also includes a second electrical connection structure that penetrates the insulating layer and is in contact with the first electrical connection structure.

15. The 3D chip packaging structure according to claim 14, characterized in that, A pad is provided on the surface of the insulating layer on the side opposite to the second chip, and the pad is in contact with the second electrical connection structure.

16. The 3D chip packaging structure according to claim 15, characterized in that, The pads are also provided with electrical contact bumps that protrude from the surface of the insulating layer.

17. A 3D chip packaging method, applied to the 3D chip packaging structure according to any one of claims 1-16, characterized in that, The method includes: The second chip is disposed on the first surface of the first chip; A first insulating encapsulation layer is formed on the first surface, and the first insulating encapsulation layer wraps around the surface of the second chip; A first electrical connection structure is formed in the first insulating encapsulation layer, and the first electrical connection structure is electrically connected between the first chip and the second chip.

18. The 3D chip packaging method according to claim 17, characterized in that, The formation of the first electrical connection structure in the first insulating encapsulation layer specifically includes: Electrical connection holes are etched on the first insulating encapsulation layer; wherein one end of the electrical connection hole exposes a portion of a first pin on the surface of the first chip, and the other end of the electrical connection hole exposes a portion of a second pin on the surface of the second chip; An electrical connector is formed in the electrical connection hole to form the first electrical connection structure, which is electrically connected between a first pin of the first chip and a second pin of the second chip.

19. The 3D chip packaging method according to claim 17, characterized in that, Before placing the second chip on the first surface of the first chip, the method further includes: A first pin is formed on a first surface of the first chip, and a second pin is formed on a surface of the second chip opposite to the first surface.

20. The 3D chip packaging method according to claim 17, characterized in that, After the first electrical connection structure is formed in the first insulating encapsulation layer, the method further includes: The side of the first chip facing away from the first surface is ground to give the first chip a predetermined thickness.

21. The 3D chip packaging method according to claim 20, characterized in that, After grinding the side of the first chip opposite to the first surface, the process further includes: An adhesive film is formed on the side of the first chip that is away from the first surface.

22. The 3D chip packaging method according to claim 17, characterized in that, Before placing the second chip on the first surface of the first chip, the method further includes: The second incoming wafer containing multiple second chips is ground to a preset thickness; The second incoming wafer, ground to a preset thickness, is cut and separated to form multiple individual second chips.

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