Semiconductor memory structure and method of forming the same

Abstract

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, the stack including vertically alternating first and second dielectric layers. The method further includes forming first dielectric pillars through the stack, and etching the stack to form a first trench. The sidewalls of the first dielectric pillars are exposed in the first trench. The method further includes removing the first dielectric pillars to form through-holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps. Embodiments of this application provide semiconductor memory structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor memory structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuits than the previous one. Throughout IC evolution, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. This scaling down also increases the complexity of IC fabrication and manufacturing, requiring similar advancements in IC processing and manufacturing to achieve these progresses.

[0003] Memory devices are a type of device designed to increase capacity and integration. Two-dimensional (2D) memory arrays are ubiquitous in electronic devices and can include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random access memory (DRAM) arrays, etc. However, 2D memory arrays have reached scaling limitations, and therefore also memory density limitations. Three-dimensional (3D) memory arrays are promising candidates for increasing memory density and can include, for example, 3D NAND flash memory arrays, 3D NOR flash memory arrays, etc. Summary of the Invention

[0004] In some embodiments, a method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, the stack including vertically alternating first and second dielectric layers. The method further includes forming first dielectric pillars through the stack, and etching the stack to form a first trench. Sidewalls of the first dielectric pillars are exposed in the first trench. The method further includes removing the first dielectric pillars to form through-holes, removing second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductors in the gaps.

[0005] In some embodiments, a semiconductor memory structure is provided. The semiconductor memory structure includes a strip, and the strip includes dielectric layers and first conductive lines alternately stacked on a substrate. The semiconductor memory structure also includes a second conductive line extending perpendicularly along a first side of the strip, a channel layer sandwiched between the strip and the second conductive line, and a dielectric pillar extending perpendicularly along a second side of the strip, the second side being opposite to the first side of the strip.

[0006] In some embodiments, a semiconductor memory structure is provided. The semiconductor memory structure includes first and second word lines laterally spaced from a first word line, a first and second channel layer between the first and second word lines, and dielectric pillars located between the first and second word lines and between the first and second channel layers. Each dielectric pillar includes a first protrusion extending into the first word line and a second protrusion extending into the second word line. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J , Figure 1K , Figure 1L , Figure 1M and Figure 1N This is a perspective view illustrating the formation of a semiconductor memory structure according to some embodiments of the present invention.

[0009] Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 , Figure 1J-1 , Figure 1K-1 , Figure 1L-1 , Figure 1M-1 and Figure 1N-1 This is a plan view illustrating the formation of a semiconductor memory structure according to some embodiments of the present disclosure.

[0010] Figure 1G-2 , Figure 1H-2 , Figure 1I-2 , Figure 1K-2 , Figure 1M-2 and Figure 1N-2 According to some embodiments of this disclosure, respectively along Figure 1G-1 , Figure 1H-1 , Figure 1I-1 , 1K-1 The cross-sectional views taken from line II shown in 1M-1 and 1N-1.

[0011] Figure 1H-3 , Figure 1K-3 , Figure 1M-3 and Figure 1N-3 According to some embodiments of this disclosure, respectively along Figure 1H-1 , 1K-1 The cross-sectional view taken from line II-II shown in 1M-1 and 1N-1.

[0012] Figure 2 This is a cross-sectional view of a semiconductor memory structure according to some embodiments of the present disclosure.

[0013] Figure 3A and Figure 3B This is a cross-sectional view showing the formation of a semiconductor memory structure according to some embodiments of the present disclosure.

[0014] Figure 4A and Figure 4B This is a cross-sectional view showing the formation of a semiconductor memory structure according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0016] Some variations of the embodiments are described. In the various views and illustrative embodiments, similar reference numerals are used to denote similar elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0017] Furthermore, when using terms such as "about," "approximately," etc., to describe numbers or ranges of numbers, the terms are intended to cover numbers within a reasonable range that includes the described number, such as + / - 10% of the described quantity or other values ​​understood by those skilled in the art. For example, the term "about 5nm" includes a size range from 4.5nm to 5.5nm.

[0018] 3D NOR memory is a type of flash memory where memory cells are vertically stacked to provide significantly higher storage density and lower cost per gigabyte than existing memories. The density of 3D memory is increased by stacking more memory gates used to form word lines or transistor layers. The gate stack is vertically cut into several strips and trenches between the strips. For example, the aspect ratio (height / width) of the trenches can be greater than about 20. However, as the strips including the gates become narrower, the risk of strip collapse and / or wobble increases, thus reducing the manufacturing yield of the memory device.

[0019] Furthermore, the dielectric layer of the strip is replaced with the gate film using an etch-deposition-etch-back process. The gate film is typically subjected to lateral indentation and has a recessed etched surface, which can lead to higher resistance. In addition, the channel layer formed along the strip may also have an uneven profile (also known as the bird's beak problem), thereby degrading the performance of the memory device.

[0020] Embodiments for forming semiconductor memory structures are provided. According to some embodiments, the method of forming a semiconductor memory structure may include forming a stack comprising alternating first and second dielectric layers, forming first dielectric pillars through the stack, and etching the stack to form a plurality of first trenches and stripes between the trenches. According to some embodiments, the first dielectric pillars may support the stripes, thereby reducing the risk of strip collapse and / or wobbling. Therefore, the manufacturing yield of the resulting semiconductor memory device can be improved.

[0021] Furthermore, the method includes forming a sacrificial layer in the trench, replacing the second dielectric layer with a conductive wire, and forming a channel layer along a strip comprising the conductive wire and the first dielectric layer. Therefore, the conductive wire can be formed with substantially flat sidewalls, and the channel layer formed thereon also has a substantially flat profile. Thus, the performance of the resulting semiconductor memory device can be improved.

[0022] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J , Figure 1K , Figure 1L , Figure 1M and Figure 1N This is a perspective view showing the formation of a semiconductor memory structure 100 according to some embodiments. Figure 1B-1 , Figure 1C-1 , Figure 1D-1 , Figure 1E-1 , Figure 1F-1 , Figure 1G-1 , Figure 1H-1 , Figure 1I-1 , Figure 1J-1 , Figure 1K-1 , Figure 1L-1 , Figure 1M-1 and Figure 1N-1 This is a plan view of a semiconductor memory structure 100 with horizontal cuts through the second dielectric layer 106 or the first wire 122 according to some embodiments.

[0023] Figure 1A A semiconductor memory structure 100 according to some embodiments is described. According to some embodiments, the semiconductor memory structure 100 includes a substrate 102. In some embodiments, the substrate 102 is a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 102 includes elemental semiconductors such as germanium; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0024] In some embodiments, substrate 102 includes a semiconductor device formed on a semiconductor substrate. For example, the semiconductor device may be a peripheral circuit, which may include various devices such as metal-oxide-semiconductor (MOS) FETs, fin FETs, nanostructure FETs (e.g., gate-all-around (GAA) FETs) or other suitable types of semiconductor devices.

[0025] In some embodiments, substrate 102 may further include interconnect structures comprising a plurality of dielectric layers and conductive components (e.g., contacts, metal lines, and / or conductive vias) within the dielectric layers. Peripheral circuitry can be operated through the conductive components of the interconnect structures to access and / or control devices of the memory cell array formed thereon (e.g., performing read / write / erase operations).

[0026] To better understand the semiconductor memory structure 100, XYZ coordinate references are provided in the accompanying drawings of this disclosure. The X and Y axes are generally oriented in a transverse (or horizontal) direction parallel to the main surface of the substrate 102. The Y axis intersects (e.g., is substantially perpendicular to) the X axis. The Z axis is generally oriented in a vertical direction perpendicular to the main surface (or XY plane) of the substrate 102.

[0027] According to some embodiments, such as Figure 1AAs shown, a stack comprising a first dielectric layer 104 and a second dielectric layer 106 is formed over a substrate 102. In some embodiments, the semiconductor memory structure 100 may include various device regions, such as logic regions, memory cell array regions, analog regions, peripheral regions, another suitable region, and / or combinations thereof. According to some embodiments, the stack is formed in the memory cell array region of the semiconductor memory structure 100.

[0028] According to some embodiments, a first dielectric layer 104 and a second dielectric layer 106 are stacked vertically alternately. In some embodiments, the second dielectric layer 106 is configured as a sacrificial layer to be replaced by a conductor (e.g., a word line). In some embodiments, the first dielectric layer 104 is configured as an insulating layer to physically and electrically isolate the conductors from each other.

[0029] In some embodiments, the number of first dielectric layers 104 is one more than the number of second dielectric layers 106. That is, both the top and bottom layers of the stack are first dielectric layers 104. Although Figure 1A Five first dielectric layers 104 and four second dielectric layers 106 are shown. The number of first dielectric layers 104 and second dielectric layers 106 is not limited to this and can range from 2 to about 100.

[0030] In some embodiments, the thickness of each first dielectric layer 104 is in the range of about 10 nm to about 200 nm. In some embodiments, the uppermost first dielectric layer 104 is thicker than the other first dielectric layers 104. In some embodiments, the thickness of each second dielectric layer 106 is in the range of about 10 nm to about 200 nm.

[0031] In some embodiments, the first dielectric layer 104 and the second dielectric layer 106 are made of dielectric materials, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbide (SiOCN), or combinations thereof. In some embodiments, the first dielectric layer 104 and the second dielectric layer 106 are made of different materials and have different etch selectivity. In some embodiments, the first dielectric layer 104 is made of an oxide-based dielectric material (e.g., silicon oxide), while the second dielectric layer 106 is made of a nitride-based dielectric material (e.g., silicon nitride).

[0032] In some embodiments, the first dielectric layer 104 and the second dielectric layer 106 utilize atomic layer deposition (ALD), chemical vapor deposition (CVD) [e.g., low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD)], another suitable technique, and / or a combination thereof. In some embodiments, the formation of the stack can be integrated into a CMOS manufacturing process, such as a back-end process (BEOL). For example, the stack can be located on the fifth (M5) and / or the sixth (M6) metal layer of the interconnect structure.

[0033] Figure 1B and Figure 1B-1 The formation of a first through hole 108 according to some embodiments is shown.

[0034] According to some embodiments, such as Figure 1B and Figure 1B-1 As shown, a first through-hole 108 is formed through a stack comprising a first dielectric layer 104 and a second dielectric layer 106. In some embodiments, forming the first through-hole 108 includes forming a patterned mask layer (not shown) having an opening pattern corresponding to the first through-hole 108 over the stack, and then etching the stack using the patterned mask layer to transfer the opening pattern into the stack until the substrate 102 is exposed. In some embodiments, the patterned mask layer is a patterned photoresist layer formed by a photolithography process. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, and / or combinations thereof.

[0035] In some alternative embodiments, the patterned mask layer is a patterned hard mask layer formed by depositing a dielectric layer, forming a patterned photoresist layer over the dielectric layer, and etching the dielectric layer to transfer the opening pattern of the photoresist layer to the dielectric layer. The patterned mask layer can be removed during the etching process or by additional processes such as etching, wet stripping, and / or ashing.

[0036] According to some embodiments, the first through holes 108 are arranged in a row / column configuration. For example, the rows of the first through holes 108 extend in the X direction, and the columns of the first through holes 108 extend in the Y direction. In some embodiments, the first through holes 108 in adjacent columns may be staggered (e.g., they do not overlap in the X direction).

[0037] In some embodiments, the first through-hole 108 has a dimension D1 measured along the X direction. In some embodiments, dimension D1 is in the range of about 50 nm to about 300 nm. In some embodiments, the first through-hole 108 has a dimension D2 measured along the Y direction. In some embodiments, dimension D2 is in the range of about 50 nm to about 500 nm.

[0038] In some embodiments, the first through hole 108 is at an X-pitch P X Arranged (in the X direction), it ranges from about 150 nm to about 500 nm. In some embodiments, the first through-hole 108 is at a Y-pitch P Y Arranged (in the Y direction), ranging from approximately 500 nm to approximately 10 μm. In some embodiments, the Y-pitch P Y The ratio of size D2 to (P) Y / D2) is in the range of approximately 1 to approximately 50.

[0039] Figure 1C and Figure 1C-1 The formation of a first dielectric post 110 according to some embodiments is shown.

[0040] According to some embodiments, such as Figure 1C and 1C-1 As shown, a first dielectric post 110 is formed in a first through-hole 108. According to some embodiments, the first dielectric post 110 penetrates the stack and contacts the substrate 102. According to some embodiments, the first dielectric post 110 is configured to support subsequently formed strips from collapse and / or wobbling.

[0041] In some embodiments, the first dielectric pillar 110 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), or combinations thereof. In some embodiments, the first dielectric pillar 110 is made of the same material as the second dielectric layer 106, such as a nitride-based dielectric material (e.g., silicon nitride).

[0042] In some embodiments, the first dielectric pillar 110 is formed by depositing dielectric material to overfill the first through-hole 108, followed by planarizing the dielectric material to remove portions of the dielectric material formed on top of the stack until the uppermost first dielectric layer 104 is exposed. The deposition process can be ALD, CVD (e.g., LPCVD, PECVD, HDP-CVD, High Aspect Ratio Processing (HARP), Flowable CVD (FCVD)), another suitable technique, and / or a combination thereof. The planarization process can be an etch-back process and / or chemical mechanical polishing (CMP).

[0043] According to some embodiments, the first dielectric pillars 110 are arranged in a row / column configuration. For example, rows of the first dielectric pillars 110 extend in the X direction, and columns of the first dielectric pillars 110 extend in the Y direction. In some embodiments, the first dielectric pillars 110 in adjacent columns may be staggered (e.g., not overlapping in the X direction).

[0044] In some embodiments, the first dielectric post 110 further has a dimension D1 measured along the X direction. In some embodiments, the dimension D1 is in the range of about 50 nm to about 300 nm. In some embodiments, the first dielectric post 110 also has a dimension D2 measured along the Y direction. In some embodiments, the dimension D2 is in the range of about 50 nm to about 500 nm.

[0045] In some embodiments, the first dielectric post 110 has an X-pitch P X Arranged (in the X direction), it ranges from about 150 nm to about 500 nm. In some embodiments, the first dielectric pillar 110 has a Y-pitch P Y Arranged (in the Y direction), ranging from about 500 nm to about 10 μm. In some embodiments, the Y-pitch P Y The ratio of size D2 to (P) Y / D2) is in the range of approximately 1 to approximately 50. If the ratio (P) Y / D2) or Y-pitch P Y If it's too small, the areal density of the storage cells may decrease. If the ratio (P) Y / D2) or Y-pitch P Y If it is too large, the risk of subsequent strip collapse and / or oscillation may increase.

[0046] Figure 1D and Figure 1D-1 The formation of a first trench 112 according to some embodiments is shown.

[0047] According to some embodiments, such as Figure 1D and Figure 1D-1 As shown, a first trench 112 is formed through the stack including a first dielectric layer 104 and a second dielectric layer 106. In some embodiments, the first trench 112 extends in the Y direction and is aligned with the column of the first dielectric pillars 110. In some embodiments, each of the first trenches 112 is formed between two adjacent first dielectric pillars 110 in the column and exposes the two adjacent first dielectric pillars 110.

[0048] In some embodiments, forming the first trench 112 includes forming a patterned mask layer (not shown) having a trench pattern corresponding to the first trench 112 over the stack, and then etching the stack using the patterned mask layer to transfer the trench pattern into the stack until the substrate 102 is exposed. According to some embodiments, the stack is cut into a plurality of strips 114 protruding from between the first trenches 112. In some embodiments, the patterned mask layer is a patterned photoresist layer formed by a photolithography process. The etching process can be anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, wet chemical etching, and / or combinations thereof.

[0049] According to some embodiments, each of the first dielectric pillars 110 can support two adjacent strips 114, thereby reducing the risk of strip 114 collapse and / or wobbling. Therefore, the manufacturing yield of the resulting semiconductor memory device can be improved.

[0050] In some alternative embodiments, the patterned mask layer is a patterned hard mask layer formed by depositing a dielectric layer, forming a patterned photoresist layer over the dielectric layer, and etching the dielectric layer to transfer the trench pattern of the photoresist layer into the dielectric layer. The patterned mask layer can be removed during the etching process or by additional processes such as etching, wet stripping, and / or ashing.

[0051] In some embodiments, the strip includes alternating stacked first dielectric layers 104 and second dielectric layers 106. In some embodiments, the strip 114 extends in the Y direction and is arranged parallel in the X direction. That is, the strip 114 has a longitudinal axis parallel to the Y direction. In some embodiments, the strip 114 has a dimension D3 measured along the X direction. In some embodiments, the dimension D3 is in the range of about 50 nm to about 250 nm. In some embodiments, the strip 114 (or the first trench 112) also has an X-pitch P. X (In the X direction), it is in the range of about 150 nm to about 500 nm.

[0052] Figure 1E and Figure 1E-1 The formation of the sacrificial layer 116 according to some embodiments is shown.

[0053] According to some embodiments, such as Figure 1E and Figure 1E-1As shown, a sacrificial layer 116 is formed in the first trench 112. According to some embodiments, each sacrificial layer 116 is formed between two adjacent first dielectric pillars 110 and between two adjacent strips 114 in a column. According to some embodiments, the sacrificial layer 116 contacts the first dielectric pillars 110, the strips 114, and the substrate 102. According to some embodiments, the sacrificial layer 116 is configured as a retaining wall to constrain subsequently formed conductors to have sidewalls with a desired profile.

[0054] In some embodiments, the sacrificial layer 116 is made of a semiconductor material, such as silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe); and / or a metal oxide, such as zirconium dioxide (ZrO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), or combinations thereof. In some embodiments, the sacrificial layer 116 has different etch selectivity than the first dielectric layer 104, the second dielectric layer 106, the first dielectric pillar 110, and the subsequently formed conductive lines.

[0055] In some embodiments, the sacrificial layer 116 is formed by depositing material for the sacrificial layer 116 to overfill the first trench 112, and then planarizing the material for the sacrificial layer 116 to remove the portion of the material for the sacrificial layer 116 formed above the strip 114 until the uppermost first dielectric layer 104 is exposed. The deposition process can be ALD, CVD (e.g., LPCVD, PECVD, HDP-CVD, HARP, and FCVD), another suitable technique, and / or a combination thereof. The planarization process can be an etch-back process and / or chemical mechanical polishing (CMP).

[0056] Figure 1F and Figure 1F-1 The formation of a second through hole 118 according to some embodiments is shown.

[0057] According to some embodiments, such as Figure 1F and Figure 1F-1 As shown, a second through-hole 118 is formed through the stack by removing the first dielectric pillar 110. The removal process can be an isotropic etching process such as wet chemical etching, dry chemical etching, or remote plasma etching, an anisotropic etching process such as dry plasma etching, and / or combinations thereof. According to some embodiments, the second through-hole 118 exposes the sacrificial layer 116, the strip 114, and the substrate 102.

[0058] According to some embodiments, the second through holes 118 are arranged in a row / column configuration. For example, the rows of the second through holes 118 extend in the X direction, and the columns of the second through holes 118 extend in the Y direction. In some embodiments, the second through holes 118 in adjacent columns may be staggered (e.g., they do not overlap in the X direction).

[0059] In some embodiments, the second through-hole 118 further has a dimension D1 measured along the X direction. In some embodiments, dimension D1 is in the range of about 50 nm to about 300 nm. In some embodiments, the second through-hole 118 also has a dimension D2 measured along the Y direction. In some embodiments, dimension D2 is in the range of about 50 nm to about 500 nm.

[0060] In some embodiments, the second through-hole 118 has an X-pitch P in the range of about 150 nm to about 500 nm. X (In the X direction). In some embodiments, the second through hole 118 has a Y-pitch P. Y (In the Y direction), it ranges from approximately 500 nm to approximately 10 μm. In some embodiments, the Y-pitch P Y The ratio of size D2 to (P) Y / D2) is in the range of approximately 1 to approximately 50.

[0061] Figure 1G and Figure 1G-1 The formation of gap 120 according to some embodiments is shown.

[0062] According to some embodiments, an etching process is performed to remove the second dielectric layer 106 of stripe 114, thereby forming gap 120, as... Figure 1G and Figure 1G-1 As shown. According to some embodiments, the gap 120 is defined by a first dielectric layer 104 and a sacrificial layer 116 of strip 114. The etching process can be an isotropic etching process, such as wet chemical etching, dry chemical etching, or remote plasma etching, and / or combinations thereof.

[0063] According to some embodiments, during the etching process, an etchant is introduced into the second through-hole 118 to laterally etch away the second dielectric layer. Figure 1F The first dielectric layer 104 and the sacrificial layer 116 have different etching selectivity than the second dielectric layer in the etching process, so the first dielectric layer 104 and the sacrificial layer 116 remain essentially unetched.

[0064] Figure 1G-2 According to some embodiments Figure 1G-1The cross-sectional view taken from line II is shown. Gap 120 also has a dimension D3 measured along the X direction. In some embodiments, dimension D3 is in the range of about 50 nm to about 250 nm. As measured in the Z direction, gap 120 has a dimension D4 (substantially the same thickness as the second dielectric layer 106). In some embodiments, dimension D4 is in the range of about 10 nm to about 200 nm. In some embodiments, dimensions D3 and D4 of gap 120 are smaller than dimension D1 of the second through-hole 118.

[0065] Figure 1H and Figure 1H-1 The formation of a first wire 122 according to some embodiments is shown.

[0066] According to some embodiments, the first wire 122 is formed in the gap ( Figure 1G In 120), such as Figure 1H and Figure 1H-1 As shown. Therefore, according to some embodiments, the second dielectric layer 106 of the strip is replaced by the first conductive line 122. The replaced strip is designated as strip 114'. According to some embodiments, the first conductive line 122 extends in the Y direction and is separated from each other in the Z and X directions. According to some embodiments, the first conductive line 122 contacts the first dielectric layer 104 and the sacrificial layer 116. In some embodiments, the first conductive line 122 is the gate electrode of a storage transistor and serves as a word line for the resulting semiconductor memory device (e.g., NOR flash memory).

[0067] Figure 1H-2 and Figure 1H-3 According to some embodiments Figure 1H-1 The diagram shows cross-sectional views taken by lines II and II-II and illustrates details of the formation of the first conductor 122. In some embodiments, the first conductor 122 is made of one or more conductive materials. In some embodiments, the first conductor 122 has a multilayer structure, including, for example, a barrier layer / adhesive layer, a metal bulk layer, another suitable layer, and / or combinations thereof.

[0068] According to some embodiments, for example, first along the exposed gap ( Figure 1F The sacrificial layer 116 of the second through-hole 118 and the surface of the first dielectric layer 104 are deposited with a barrier layer 124 to partially fill the gap. Figure 1F 120) and a second through-hole 118. Barrier layer 124 is used to prevent metal in subsequently formed metallic material from diffusing into dielectric material (e.g., first dielectric layer 104).

[0069] The barrier layer 124 can be made of titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), cobalt tungsten (CoW), another suitable material, and / or combinations thereof. The barrier layer can be omitted if the subsequently formed metallic material does not readily diffuse into the dielectric material. The deposition process can be ALD, CVD, PVD, electron beam evaporation, ECP, ELD, another suitable method, or combinations thereof.

[0070] According to some embodiments, a bulk metal layer 126 is then deposited on the barrier layer 124. In some embodiments, due to the gap ( Figure 1F The dimensions D3 and D4 of 120) Figure 1G-2 The size D1 is smaller than that of the second through hole 118. Figure 1G-2 The deposition process can be controlled to allow the bulk metal layer 126 to overfill the gap 120 and partially fill the second through hole 118.

[0071] In some embodiments, the bulk metal layer 126 is made of a conductive material with low resistance and good gap-filling ability, such as tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), tantalum (Ta), molybdenum (Mo), another suitable metallic material, and / or combinations thereof. The deposition process can be ALD, CVD, PVD, electron beam evaporation, ECP, ELD, another suitable method, or a combination thereof.

[0072] After the deposition of bulk metal layer 126, an etch-back process is performed to remove the interstitial material. Figure 1F The portion of the barrier layer 124 and the bulk metal layer 126, excluding the 120). The etching process can be an isotropic etching process, such as wet chemical etching, dry chemical etching, or remote plasma etching, and / or combinations thereof. According to some embodiments, such as Figure 1H-2 As shown, since the second through-hole 118 is partially filled, during the etching process, etchant is introduced into the remaining portion of the second through-hole 118 to laterally etch away the barrier layer 124 and the bulk metal layer 126, until the sidewalls of the first dielectric layer 104, initially covered by the barrier layer 124 and the bulk metal layer 126, are once again exposed to the second through-hole 118. According to some embodiments, the gap ( Figure 1F A portion of the barrier layer 124 and the metal block layer 126 within (120) are used as the first conductor 122.

[0073] In some embodiments, the first conductive line 122 further has a maximum dimension D3 measured along the X direction. In some embodiments, the dimension D3 is in the range of about 150 nm to about 500 nm. The first conductive line 122 has a sidewall 122B that intersects with (or is covered by) the sacrificial layer 116, so that the sidewall 122B remains substantially flat after the etching process, as... Figure 1H-1 , Figure 1H-2 and Figure 1H-2 As shown, according to some embodiments, the channel layer will be formed on the substantially flat sidewall 122B of the first conductor 122.

[0074] like Figure 1H-2 As shown, in some embodiments, due to the characteristics of the etching process, in the etch-back process, the portion of the first conductor 122 exposed to the second through-hole 118 can be laterally recessed, for example, etched laterally to a maximum depth D5, thereby forming a notch 119. In some embodiments, the depth D5 is less than 50 nm, for example, in the range from about 0 nm to about 5.0 nm. In some embodiments, the ratio of the depth D5 of the recess 119 to the dimension D3 of the first conductor 122 (D5 / D3) is in the range of about 0.5 to about 0.95.

[0075] The sidewall of the first conductor 122 has a recess 122A exposed from the second through hole 118, such as Figure 1H-1 and Figure 1H-2 As shown. According to some embodiments, the channel layer will not be formed on the recessed portion 122A of the sidewall of the first conductor 122.

[0076] Therefore, by forming the sacrificial layer 116 and the second through-hole 118, the first conductor 122 can be formed with sidewalls, most of which are substantially flat and a small portion of which are recessed. Thus, the first conductor 122 can be formed to have a larger cross-sectional area (in the XY plane), thereby improving the performance of the resulting semiconductor memory device (e.g., lower resistance).

[0077] Figure 1I and Figure 1I-1 The formation of a second dielectric post 128 according to some embodiments is shown.

[0078] According to some embodiments, a second dielectric post 128 is formed in the second through hole ( Figure 1H In 118), such as Figure 1I and Figure 1I-1As shown. According to some embodiments, the second dielectric pillar 128 contacts the first conductor 122, sacrificial layer 116, and substrate 102 of the first dielectric layer 104 and strip 114'. According to some embodiments, the second dielectric pillar 128 is configured to support strip 114' from collapsing and / or wobbling during and after subsequent etching processes.

[0079] In some embodiments, the second dielectric pillar 128 is made of a dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), or a combination thereof. In some embodiments, the second dielectric pillar 128 is made of the same material as the first dielectric layer 104, such as an oxide-based dielectric material (e.g., silicon oxide).

[0080] In some embodiments, a dielectric material is deposited to overfill the second through-hole. Figure 1H The dielectric material is then planarized to remove portions of the dielectric material formed above stripe 114' until sacrificial layer 116 is exposed, forming the second dielectric pillar 128. The deposition process can be ALD, CVD (e.g., LPCVD, PECVD, HDP-CVD, HARP, and FCVD), another suitable technique, and / or a combination thereof. The planarization process can be an etch-back process and / or chemical mechanical polishing (CMP).

[0081] According to some embodiments, the second dielectric pillars 128 are arranged in a row / column configuration. For example, rows of the second dielectric pillars 128 extend in the X direction, and columns of the second dielectric pillars 128 extend in the Y direction. In some embodiments, the second dielectric pillars 128 in adjacent columns may be staggered (e.g., not overlapping in the X direction).

[0082] In some embodiments, the second dielectric post 128 has a maximum dimension D1' measured along the X direction. In some embodiments, dimension D1' is in the range of about 50 nm to about 300 nm. In some embodiments, the second dielectric post 128 also has a dimension D2 measured along the Y direction. In some embodiments, dimension D2 is in the range of about 50 nm to about 500 nm.

[0083] In some embodiments, the second dielectric post 128 is at an X-pitch P X Arranged (in the X direction), it ranges from about 150 nm to about 500 nm. In some embodiments, the second dielectric pillar 128 is at a Y-pitch P Y Arranged (in the Y direction), ranging from approximately 500 nm to approximately 10 μm. In some embodiments, the Y-pitch P Y The ratio of size D2 to (P) Y / D2) is in the range of approximately 1 to approximately 50. If the ratio (P) Y / D2) or Y-pitch P Y If it's too small, the areal density of the storage cells may decrease. If the ratio (P) Y / D2) or Y-pitch P Y If it is too large, the risk of collapse and / or swaying of the strip 114' including the first conductor 122 may increase.

[0084] Figure 1I-2 According to some embodiments Figure 1I-1 The cross-sectional view shown is taken from line II. According to some embodiments, the second dielectric post 128 includes a protrusion filled in the notch. Figure 1H-2 (119). According to some embodiments, such as Figure 1I-2 As shown, the protruding portion of the second dielectric post 128 has a convex side surface 128A, which mates with and engages with the recessed portion 122A of the sidewall of the first conductor 122. In some embodiments, the convex side surface 128A contacts both the barrier layer 124 and the metal bulk layer 126 of the first conductor 122.

[0085] According to some embodiments, the second dielectric pillar 128 also has a substantially flat side surface 128B that is bonded to the first dielectric layer 104. According to some embodiments, the convex side surface 128A and the substantially flat side surface 128B are arranged alternately.

[0086] Figure 1J and Figure 1J-1 The removal of the sacrificial layer 116 according to some embodiments is shown.

[0087] According to some embodiments, an etching process is performed to remove the sacrificial layer ( Figure 1I (116), thus forming the second groove 130, such as Figure 1J and Figure 1J-1 As shown. The etching process can be anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, wet chemical etching, and / or combinations thereof.

[0088] According to some embodiments, each of the second dielectric pillars 128 can support two adjacent strips 114', thereby reducing the risk of strip 114' collapse and / or wobbling. Therefore, the manufacturing yield of the resulting semiconductor memory device can be improved.

[0089] In some embodiments, the second trench 130 extends in the Y direction and is formed to align with the columns of the second dielectric pillars 128. In some embodiments, each second trench 130 is formed between two adjacent second dielectric pillars 128 located in a column and exposes the two adjacent second dielectric pillars 128. In some embodiments, the second trench 130 also exposes the first dielectric layer 104 and the first conductor 122 of the strip 114'.

[0090] Figure 1K and Figure 1K-1 The formation of a ferroelectric (FE) layer 132, a channel layer 134, an insulating layer 136, and a capping layer 138 according to some embodiments is shown.

[0091] like Figure 1K and Figure 1K-1 As shown, the ferroelectric layer 132, the channel layer 134, the insulating layer 136, and the capping layer 138 are sequentially deposited above the semiconductor memory structure 100 to partially fill the second trench. Figure 1J 130), according to some embodiments. The remaining portion of the second trench ( Figure 1J 130) is represented by 131.

[0092] In some embodiments, the ferroelectric layer 132 is made of a ferroelectric material, such as hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HfZrO), another suitable material, or a combination thereof. In some embodiments, ALD, CVD (e.g., LPCVD, PECVD, and HDP-CVD), another suitable technique, and / or a combination thereof are used along the second trench ( Figure 1J Ferroelectric layers 132 are deposited on the sidewalls and bottom surface of (130).

[0093] In some embodiments, the channel layer 134 is made of a semiconductor material, such as indium gallium oxide (InGaO), indium gallium zirconium oxide (InGaZrO), indium gallium zinc oxide (IGZO), polycrystalline silicon, germanium, another suitable material, or a combination thereof. In some embodiments, the channel layer 134 is deposited on the ferroelectric layer 132 using ALD, CVD (e.g., LPCVD, PECVD, and HDP-CVD), another suitable technique, and / or a combination thereof.

[0094] In some embodiments, the insulating layer 136 is made of a dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), another suitable material, and / or combinations thereof. In some embodiments, the insulating layer 136 is deposited on the channel layer 134 using ALD, CVD (e.g., LPCVD, PECVD, and HDP-CVD), another suitable technique, and / or combinations thereof.

[0095] In some embodiments, the capping layer 138 is made of a dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), another suitable material, and / or combinations thereof. In some embodiments, the capping layer 138 is made of the same material as the first dielectric layer 104, such as an oxide-based dielectric material (e.g., silicon oxide). In some embodiments, the capping layer 138 is deposited on the insulating layer 136 using ALD, CVD (e.g., LPCVD, PECVD, and HDP-CVD), another suitable technique, and / or combinations thereof.

[0096] According to some embodiments, after the material deposition of the capping layer 138, an etch-back process is performed on the ferroelectric layer 132, the channel layer 134, the insulating layer 136, and the capping layer 138 to open the bottom of the second trench 131, such that the second trench 131 extends to the substrate 102. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, or wet chemical etching, and / or a combination thereof.

[0097] According to some embodiments, the etch-back process also removes portions of the ferroelectric layer 132, channel layer 134, insulating layer 136, and capping layer 138 formed above the upper surface of strip 114', and further recesses portions of the capping layer 138 and insulating layer 136, channel layer 134, and ferroelectric layer 132 formed in the second trench 131.

[0098] In some embodiments, such as Figure 1K-1 As shown, each of the ferroelectric layer 132, the channel layer 134, the insulating layer 136, and the capping layer 138 has a closed-loop profile.

[0099] Figure 1K-2 and Figure 1K-3 According to some embodiments Figure 1K-1The cross-sectional views taken by lines II and II-II are shown. According to some embodiments, the channel layer 134 is formed along the generally flat sidewall 122B of the first conductor 122, as shown... Figure 1K , Figure 1K-1 , Figure 1K-2 and Figure 1K-3 As shown. According to some embodiments, because the recessed portion 122A of the sidewall of the first conductor 122 is covered by the second dielectric pillar 128, the channel layer 134 is not formed along the recessed portion 122A. Therefore, the channel layer 134 can also have a flat profile, thereby improving the performance of the resulting semiconductor memory device.

[0100] Figure 1L and Figure 1L-1 The formation of a fill layer 140 according to some embodiments is shown.

[0101] According to some embodiments, such as Figure 1L and Figure 1L-1 As shown, a fill layer 140 is formed above the semiconductor memory structure 100 to fill the second trench ( Figure 1K (131). In some embodiments, the fill layer 140 is made of a dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), another suitable material, and / or combinations thereof. In some embodiments, the fill layer 140 is made of the same material as the first dielectric layer 104, such as an oxide-based dielectric material (e.g., silicon oxide).

[0102] In some embodiments, a fill layer 140 is formed by depositing a dielectric material to overfill the second trench 131, followed by planarizing the dielectric material to remove portions of the dielectric material formed above the strip. The deposition process can be ALD, CVD (e.g., LPCVD, PECVD, HDP-CVD, HARP, and FCVD), another suitable technique, and / or a combination thereof. The planarization process can be an etch-back process and / or chemical mechanical polishing (CMP).

[0103] Figure 1M and Figure 1M-1 The formation of a third through hole 142 according to some embodiments is shown. Figure 1M-2 and Figure 1M-3 According to some embodiments along Figure 1M-1 The cross-sectional views shown are taken from lines II and II-II.

[0104] According to some embodiments, after the fill layer 140 is formed, a planarization process is performed on the semiconductor memory structure 100 until the ferroelectric layer 132, the channel layer 134, the insulating layer 136, and the capping layer 138 are exposed. The planarization process may be an etch-back process and / or chemical mechanical polishing (CMP).

[0105] According to some embodiments, such as Figure 1M , 1M-1 As shown in 1M-2 and 1M-3, a third through-hole 142 is then formed through the filler layer 140, the cover layer 138, and the insulating layer 136. In some embodiments, the closed-loop profiles of the insulating layer 136 and the cover layer 138 are interrupted by the third through-hole 142, while the closed-loop profiles of the ferroelectric layer 132 and the channel layer 134 remain intact (or continuous), as shown in 1M-2 and 1M-3. Figure 1M-1 As shown. In some embodiments, according to some examples, the third through-hole 142 exposes the channel layer 134 and the substrate 102.

[0106] In some embodiments, forming the third via 142 includes forming a patterned mask layer (not shown) having an opening pattern corresponding to the third via 142 over the semiconductor memory structure 100, and then etching the semiconductor memory structure 100 using the patterned mask layer to transfer the opening pattern into the fill layer 140, the capping layer 138, and the insulating layer 136 until the substrate 102 is exposed. In some embodiments, the patterned mask layer is a patterned photoresist layer formed by a photolithography process. The etching process can be anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, wet chemical etching, and / or combinations thereof.

[0107] In some alternative embodiments, the patterned mask layer is a patterned hard mask layer formed by depositing a dielectric layer, forming a patterned photoresist layer over the dielectric layer, and etching the dielectric layer to transfer the opening pattern of the photoresist layer into the dielectric layer. The patterned mask layer can be removed during the etching process or by additional processes such as etching, wet stripping, and / or ashing.

[0108] According to some embodiments, the third through-hole 142 is arranged in a row / column configuration. For example, the rows of the third through-hole 142 extend along the X direction, and the columns of the third through-hole 142 extend along the Y direction. In some embodiments, the third through-hole 142 is not formed at the location where the second dielectric post 128 has been provided. Although Figure 1M-1 Nine third through holes 142 are shown formed between two adjacent second dielectric pillars 128, but the number of third through holes 142 between two adjacent second dielectric pillars 128 is not limited to this and may depend on design requirements and / or performance considerations.

[0109] Figure 1Nand Figure 1N-1 The diagram illustrates the formation of a second conductor 144 according to some embodiments. Figure 1N-2 and Figure 1N-3 According to some embodiments Figure 1N-1 The cross-sectional views shown are taken from lines II and II-II.

[0110] According to some embodiments, the second conductor 144 is formed in the third through hole ( Figure 1M In 142), such as Figure 1N , Figure 1N-1 , Figure 1N-2 and Figure 1N-3 As shown. According to some embodiments, the second wire 144 extends in the Z direction and contacts the channel layer 134 and the substrate 102. In some embodiments, the second wire 144 is the source / drain electrode of a storage transistor and serves as the source line or bit line of the resulting semiconductor memory device (e.g., NOR flash memory).

[0111] In some embodiments, the second conductor 144 is made of one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), tantalum (Ta), molybdenum (Mo), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), cobalt tungsten (CoW), other suitable materials and / or combinations thereof.

[0112] According to some embodiments, the formation of the second conductor 144 includes depositing a conductive material for the second conductor 144 to overfill the third through-hole. Figure 1M 142), and then the conductive material is planarized to remove portions of the conductive material formed on the ferroelectric layer 132, channel layer 134, insulating layer 136, and capping layer 138 until the ferroelectric layer 132, channel layer 134, insulating layer 136, and capping layer 138 are exposed. The deposition process can be ALD, CVD, PVD, electron beam evaporation, ECP, ELD, another suitable method, or a combination thereof. The planarization process can be an etch-back process and / or chemical mechanical polishing (CMP).

[0113] In some embodiments, the first wire 122, the ferroelectric layer 132, the channel layer 134, and the second wire 144 are combined to form a memory transistor (e.g., a flash memory transistor) to serve as a memory cell. According to some embodiments, the memory cells are operable for data storage and are arranged in the X, Y, and Z directions to form a memory cell array. In some embodiments, the second wire 144 is electrically connected to peripheral circuitry formed in the substrate 102.

[0114] According to some embodiments, additional CMOS manufacturing processes can be formed. For example, according to some embodiments, an intermetallic dielectric layer and a metal layer and vias can be formed over the semiconductor memory structure 100.

[0115] As described above, by forming the first dielectric pillar 110 and the second dielectric pillar 128, the risk of collapse and / or wobbling of the strips 114 and 114' can be reduced. Therefore, the manufacturing yield of the resulting semiconductor memory device can be improved. Furthermore, by forming the sacrificial layer 116, the first conductive line 122 can be formed with generally flat sidewalls, and the channel layer 134 formed thereon also has a generally flat profile. Therefore, the performance of the resulting semiconductor memory device can be improved.

[0116] Figure 2 This is a cross-sectional view of a semiconductor memory structure 200 according to some embodiments of the present disclosure. Figure 2 The embodiments are similar to Figure 1N , Figure 1N-1 , Figure 1N-2 and Figure 1N-3 In addition to the embodiments, Figure 2 This further illustrates the semiconductor substrate, the interconnect structure above the semiconductor substrate, and the memory cell array on the semiconductor substrate.

[0117] According to some embodiments, a semiconductor substrate 202 is provided, such as Figure 2 As shown. In some embodiments, the semiconductor substrate 202 is a silicon substrate. In some embodiments, the semiconductor substrate 202 includes elemental semiconductors such as germanium; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0118] According to some embodiments, such as Figure 2 As shown, peripheral circuitry 204 is formed on semiconductor substrate 202. Peripheral circuitry 204 can constitute control circuitry for operating the memory cell array vertically formed above it. Peripheral circuitry 204 may include, but is not limited to, boost circuitry, page buffer circuitry, column decoder, row decoder, error correction circuitry, write assist circuitry, interface circuitry for interfacing between memory cell types, bus control circuitry, and the like.

[0119] In some embodiments, peripheral circuitry 204 includes a MOSFET, such as a p-type MOSFET (P-MOSFET) or an n-type MOSFET (N-MOSFET). The MOSFET may be a planar transistor, a fin-type transistor (e.g., FinFET), and / or another suitable transistor. In some embodiments, peripheral circuitry 204 is a planar transistor. According to some embodiments, peripheral circuitry 204 each includes a gate structure formed above the upper surface of semiconductor substrate 202 and source / drain regions formed on or at least partially embedded in semiconductor substrate 202 on opposite sides of the gate structure.

[0120] In some embodiments, the gate structure may include a gate dielectric layer and a gate electrode layer above the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer of dielectric material, such as silicon oxide (SiO2), hafnium silicon oxide (HfSiO), or silicon oxynitride (SiON). The interface layer may be formed using chemical oxidation, thermal oxidation, ALD, CVD, and / or another suitable method. In some embodiments, the gate dielectric layer comprises a high-k gate dielectric layer of a high-k dielectric material, such as hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, thermal oxidation, and / or other suitable methods.

[0121] In some embodiments, the gate electrode layer comprises a conductive material, such as a doped semiconductor, metal, metal alloy, or metal silicide. In some embodiments, the gate electrode layer comprises a single layer or optionally a multilayer structure. The gate electrode layer may be made of polysilicon, germanium, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, another suitable conductive material, or multiples thereof. The gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes.

[0122] In some embodiments, the source / drain region is a region of the substrate 302 that has been appropriately doped using an implantation process. In some embodiments, the source / drain region is a source / drain region epitaxially grown using an epitaxial growth process.

[0123] According to some embodiments, an interconnect structure is formed over a semiconductor substrate 202. According to some embodiments, such as... Figure 2 As shown, the interconnect structure includes contacts 208, a metal layer 210, and vias 212 in one or more inter-metal dielectric (IMD) layers 206. According to some embodiments, the interconnect structure is used to electrically couple lower-level peripheral circuitry 204 to an upper-level memory cell array.

[0124] One or more intermetallic dielectric layers 206 are made of one or more dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (SiCN:O), silicon carbide (SiOC), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxides such as borosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials.

[0125] According to some embodiments, contacts 208 are formed in and / or through one or more inter-metal dielectric layers 206 and are located on the gate structure of the peripheral circuitry 204. In some alternative embodiments, contacts 208 are located on the source / drain regions. In some embodiments, contacts 208 are made of one or more conductive materials, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), ruthenium (Ru), molybdenum (Mo), TiN, TaN, and / or combinations thereof.

[0126] According to some embodiments, the metal layer 210 and the via 212 are formed in and / or through one or more inter-metal dielectric layers 206. According to some embodiments, the metal layer 210 provides horizontal routing for one or more signals generated by the peripheral circuitry 204. According to some embodiments, the via 212 provides vertical routing for one or more signals generated by the peripheral circuitry 204. In some embodiments, the metal layer 210 and the via 212 are made of copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), titanium (Ti), alloys thereof, nitrides of these materials, multilayers thereof, and / or combinations thereof, or other suitable conductive materials.

[0127] Subsequently, according to some embodiments, such as Figure 2 As shown, execute the above regarding Figures 1A to 1N-1 The described steps form a memory cell array over an interconnect structure. In some embodiments, the second conductor 144 of the memory cell array is electrically connected to the peripheral circuitry 204 through the interconnect structure. Although Figure 2As not shown, the first conductor 122 can also be electrically connected to the peripheral circuit 204 via an interconnect structure. According to some embodiments, the semiconductor memory structure 200 is referred to as a peripheral circuit (PUA) device under a memory array.

[0128] Figures 3A-3B This is a cross-sectional view illustrating the formation of the semiconductor memory structure 300 at various intermediate stages, according to some embodiments of this disclosure, wherein... Figure 3A and Figure 3B yes Figure 1H-2 and Figure 1N-2 Variations. According to some embodiments, Figure 3A and Figure 3B Corresponding to Figure 1H-1 and Figure 1N-1 Line II is shown in the diagram. Figures 3A-3B Implementation examples and Figures 1A to 1N-3 The embodiments are similar, except that the etching depth D51-D54 of the notch 119 varies with the height of the first conductor 122.

[0129] After the deposition of the barrier layer 124 and the bulk metal layer 126, an etch-back process is performed to remove a portion of the barrier layer 124 and the bulk metal layer 126 outside the gap 120, thereby forming the first conductive line 122. In some embodiments, such as Figure 3A As shown, due to the characteristics of the etching process, the portion of the first conductor 122 exposed to the second through-hole 118 can be laterally recessed, for example, to a maximum depth D51-D54. In some embodiments, the depth D51-D54 decreases as the position of the first conductor 122 decreases (or the level of the first conductor 122 decreases).

[0130] According to some embodiments, such as Figure 3B As shown, execute the above instructions regarding... Figures 1I to 1N-3 The described steps result in the formation of a second dielectric post 128, a ferroelectric layer 132, a channel layer 134, an insulating layer 136, a capping layer 138, a filler layer 140, and a second conductor 144 connected together. According to some embodiments, the second dielectric post 128 includes a protrusion filled in a recess 119. In some embodiments, the size of the protrusion (in the X direction) decreases as the position of the first conductor 122 decreases (or the horizontal level of the first conductor 122 decreases).

[0131] Figures 4A-4B This is a cross-sectional view showing the formation of a semiconductor memory structure 400 at various intermediate stages, according to some embodiments of the present disclosure, wherein... Figure 4A and Figure 4B According to some embodiments Figure 1H-2 and Figure 1N-2 A variant of . Figure 4A and Figure 4B Corresponding to Figure 1H-1 and Figure 1N-1 Line II is shown in the diagram. Figures 4A-4B The embodiments are similar to Figures 1A to 1N-3 The embodiment differs in that the sidewall of the first conductor 122 does not have a recessed portion.

[0132] After depositing the barrier layer 124 and the bulk metal layer 126, an etch-back process is performed to remove portions of the barrier layer 124 and the bulk metal layer 126 outside the gap 120, thereby forming the first conductive line 122. In some embodiments, due to the characteristics of the etching process, the sidewall of the first conductive line 122 facing the second through-hole 118 is also generally flat.

[0133] According to some embodiments, such as Figure 4B As shown, execute the above instructions regarding... Figures 1I to 1N-3 The described steps form a second dielectric pillar 128, a ferroelectric layer 132, a channel layer 134, an insulating layer 136, a cover layer 138, a filler layer, a second conductor 140, and a second conductor 144.

[0134] As described above, the method of forming a semiconductor memory structure includes forming a stack comprising alternating first dielectric layers 104 and second dielectric layers 106, forming first dielectric pillars 110 through the stack, and etching the stack to form a plurality of first trenches 112 and stripes 114 between the first trenches 112. According to some embodiments, the first dielectric pillars 110 may support the stripes 114, thereby reducing the risk of stripe 114 collapse and / or wobbling. Therefore, the manufacturing yield of the resulting semiconductor memory device can be improved.

[0135] Furthermore, the method also includes forming a sacrificial layer 116 in the first trench 112, replacing the second dielectric layer 106 with a first conductive line 122, and forming a channel layer 134 along a strip 114' comprising the first conductive line 122 and the dielectric layer 104. Therefore, the first conductive line 122 can be formed with generally flat sidewalls, and the channel layer 134 formed thereon also has a generally flat profile. Thus, the performance of the resulting semiconductor memory device can be improved.

[0136] Embodiments of semiconductor memory structures can be provided. The semiconductor memory structure may include a strip comprising alternating stacked dielectric layers and a first conductive line, a second conductive line extending perpendicularly along a first side of the strip, and dielectric pillars extending perpendicularly along a second side of the strip. The dielectric pillars can support the strip, thereby reducing the risk of strip folding and / or wobbling. Therefore, the manufacturing yield of the resulting semiconductor memory device can be improved.

[0137] In some embodiments, a method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, the stack including vertically alternating first and second dielectric layers. The method further includes forming first dielectric pillars through the stack, and etching the stack to form a first trench. Sidewalls of the first dielectric pillars are exposed in the first trench. The method further includes removing the first dielectric pillars to form through-holes, removing second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductors in the gaps.

[0138] In some embodiments, the method further includes: forming a sacrificial layer in the first trench before removing the first dielectric pillar; and removing the sacrificial layer to form a second trench after forming the first conductor in the gap. In some embodiments, the method further includes: forming a ferroelectric layer in the second trench; forming a channel layer over the ferroelectric layer in the second trench; and forming an insulating layer over the channel layer in the second trench. In some embodiments, the method further includes: forming a second conductor perpendicularly penetrating the insulating layer. In some embodiments, removing the second dielectric layer of the stack includes introducing an etchant into the via to etch the second dielectric layer of the stack laterally. In some embodiments, the method further includes: filling the via with a second dielectric pillar. In some embodiments, forming the first conductor in the gap includes: forming a barrier layer to partially fill the gap; forming a bulk metal layer to overfill the remaining portion of the gap; and etching back the barrier layer and the bulk metal layer. In some embodiments, one of the first conductors has a sidewall exposed to one of the vias, and the sidewall is concave. In some embodiments, the stack is etched to form strips between the first trenches, and the first dielectric pillar contacts the sidewall of the strip.

[0139] In some embodiments, a semiconductor memory structure is provided. The semiconductor memory structure includes a strip, and the strip includes dielectric layers and first conductive lines alternately stacked on a substrate. The semiconductor memory structure also includes a second conductive line extending perpendicularly along a first side of the strip, a channel layer sandwiched between the strip and the second conductive line, and a dielectric pillar extending perpendicularly along a second side of the strip, the second side being opposite to the first side of the strip.

[0140] In some embodiments, the first conductor has a sidewall located on the second side of the strip, the sidewall having a recessed portion, and the dielectric pillar includes a protrusion that engages with the recessed portion of the sidewall of the first conductor. In some embodiments, the size of the protrusion of the dielectric pillar decreases as the layer level of the first conductor decreases. In some embodiments, one of the first conductors has a substantially flat sidewall on the first side of the strip. In some embodiments, the semiconductor memory structure further includes a ferroelectric layer sandwiched between the strip and the channel layer. In some embodiments, one of the first conductors includes a barrier layer and a bulk metal layer nested within the barrier layer, wherein the barrier layer and the bulk metal layer are made of different materials. In some embodiments, both the barrier layer and the bulk metal layer are in contact with the dielectric pillar.

[0141] In some embodiments, a semiconductor memory structure is provided. The semiconductor memory structure includes first and second word lines laterally spaced from a first word line, a first and second channel layer between the first and second word lines, and dielectric pillars located between the first and second word lines and between the first and second channel layers. Each dielectric pillar includes a first protrusion extending into the first word line and a second protrusion extending into the second word line.

[0142] In some embodiments, in a plan view, each of the first channel layer and the second channel layer has a closed-loop profile. In some embodiments, the semiconductor memory structure further includes: a plurality of first wires disposed within the closed-loop profile of the first channel layer; and a plurality of second wires disposed within the closed-loop profile of the second channel layer. In some embodiments, the semiconductor memory structure further includes: a transistor located above a substrate; and an interconnect structure located above the transistor, wherein the plurality of first wires are formed above the interconnect structure and electrically connected to the transistor through the interconnect structure.

[0143] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor memory structure, comprising: A stack is formed over a substrate, the stack comprising a first dielectric layer and a second dielectric layer arranged vertically alternately. Forming a first dielectric pillar through the stack; The stack is etched to form a first trench, wherein the sidewalls of the first dielectric pillar are exposed in the first trench; Remove the first dielectric pillar to form a through-hole; Remove the second dielectric layer of the stack to form a gap between the first dielectric layers; as well as A first conductor is formed in the gap.

2. The method for forming a semiconductor memory structure according to claim 1, further comprising: A sacrificial layer is formed in the first trench before the first dielectric pillar is removed; as well as After the first conductor is formed in the gap, the sacrificial layer is removed to form the second trench.

3. The method for forming a semiconductor memory structure according to claim 2, further comprising: A ferroelectric layer is formed in the second trench; A channel layer is formed above the ferroelectric layer in the second trench; as well as An insulating layer is formed above the channel layer in the second trench.

4. The method for forming a semiconductor memory structure according to claim 3, further comprising: A second conductor is formed that penetrates the insulation layer vertically.

5. The method of forming a semiconductor memory structure according to claim 1, wherein removing the second dielectric layer of the stack comprises introducing an etchant into the through-hole to laterally etch the second dielectric layer of the stack.

6. The method for forming a semiconductor memory structure according to claim 1, further comprising: The through-hole is filled with a second dielectric pillar.

7. The method of forming a semiconductor memory structure of claim 1, wherein, Forming the first conductor in the gap includes: A barrier layer is formed to partially fill the gap; Forming a bulk metal layer to overfill the remaining portion of the gap; and Etch back the barrier layer and the bulk metal layer.

8. The method for forming a semiconductor memory structure according to claim 1, wherein, One of the first conductors has a sidewall with a portion exposed to one of the through holes, and the portion of the sidewall is concave.

9. The method for forming a semiconductor memory structure according to claim 1, wherein, The stack is etched to form strips between the first trenches, and the first dielectric pillar contacts the sidewall of the strip.

10. A semiconductor memory structure, comprising: A strip, comprising alternating stacked first conductive lines and dielectric layers on a substrate; The second conductor extends perpendicularly along the first side of the strip; A channel layer, sandwiched between the strip and the second conductor; as well as Dielectric pillars extend perpendicularly along a second side of the strip opposite to the first side of the strip. One of the first conductors includes: a barrier layer; and a metal bulk layer, the metal bulk layer being nested within the barrier layer, wherein the barrier layer and the metal bulk layer are made of different materials.

11. The semiconductor memory structure according to claim 10, wherein, The first conductor has a sidewall located on the second side of the strip, the sidewall having a recessed portion, and the dielectric post includes a protrusion that engages with the recessed portion of the sidewall of the first conductor.

12. The semiconductor memory structure according to claim 11, wherein, The size of the protruding portion of the dielectric pillar decreases as the layer of the first conductor decreases.

13. The semiconductor memory structure according to claim 10, wherein, One of the first conductors has a substantially flat sidewall on the first side of the strip.

14. The semiconductor memory structure according to claim 10, further comprising: The ferroelectric layer is sandwiched between the strip and the channel layer.

15. The semiconductor memory structure according to claim 10, wherein, The first wire and the second wire are the gate electrodes of the storage transistor.

16. The semiconductor memory structure according to claim 15, wherein both the barrier layer and the metal bulk layer are in contact with the dielectric pillar.

17. A semiconductor memory structure, comprising: The first character line and the second character line that are horizontally separated from the first character line; The first channel layer and the second channel layer are located between the first word line and the second word line; as well as A dielectric pillar is located between the first word line and the second word line, and between the first channel layer and the second channel layer, wherein the dielectric pillar includes a first protrusion extending into the first word line and a second protrusion extending into the second word line. In the planar view, each of the first channel layer and the second channel layer has a closed-loop profile.

18. The semiconductor memory structure according to claim 17, wherein, The gate electrode of the storage transistor is used as the first word line and the second word line.

19. The semiconductor memory structure according to claim 18, further comprising: Multiple first conductors are arranged within the closed-loop profile of the first channel layer; as well as Multiple second conductors are arranged within the closed-loop profile of the second channel layer.

20. The semiconductor memory structure according to claim 19, further comprising: Transistors, located above the substrate; as well as An interconnect structure is located above the transistor, wherein a plurality of first wires are formed above the interconnect structure and electrically connected to the transistor through the interconnect structure.

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