semiconductor structure

Abstract

The present invention provides a semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer and a first field plate structure. The first well and the second well are arranged in the substrate. The first doped region is arranged in the first well. The second doped region is arranged in the second well. The first gate structure is arranged between the first doped region and the second doped region. The first insulating layer covers part of the first well and part of the first gate structure. The first field plate structure is arranged on the first insulating layer and partially overlaps with the first gate structure, wherein the first field plate structure is divided into a first partial field plate and a second partial field plate separated from each other along a first direction. The present application can flexibly configure the on-resistance and the total gate charge by dividing the field plate based on design requirements to obtain the required device performance. In addition, the on-resistance and the total gate charge can also be flexibly configured to obtain the best optimization indicators.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a field plate. Background Art

[0002] High-voltage semiconductor devices use gate voltage to create a channel and control the current flowing between the source and drain. In traditional high-voltage semiconductor devices, to prevent the punch-through effect between the source and drain, the channel length of the transistor must be extended. However, this increases the device size, resulting in increased chip area, and also increases the transistor's on-resistance (Ron). Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor structure comprising a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first well is disposed in the substrate and has a first conductivity type. The second well is disposed in the substrate and is adjacent to the first well and has a second conductivity type opposite to the first conductivity type. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first doped region and the second doped region. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer and partially overlaps with the first gate structure, wherein the first field plate structure is divided into a first partial field plate and a second partial field plate separated from each other along a first direction. The present application can flexibly configure the on-resistance and the total gate charge by dividing the field plate based on design requirements to obtain the desired device performance. In addition, the on-resistance and the total gate charge can also be flexibly configured to obtain the best optimization index. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 FIG. 4 is a top view of the semiconductor structure of the present invention.

[0005] Figure 2A The semiconductor structure of the present invention is along Figure 1 Cross-section of line segment AA.

[0006] Figure 2B The semiconductor structure of the present invention is along Figure 1 Cross-section of line segment BB.

[0007] Figure 2C The semiconductor structure of the present invention is along Figure 1 Cross-sectional view of line segment CC.

[0008] Figure 3FIG. 4 is a top view of the semiconductor structure of the present invention.

[0009] Figure 4 The semiconductor structure of the present invention is along Figure 4 Cross-sectional view of line segment CC.

[0010] Figure 5 FIG. 4 is a top view of the semiconductor structure of the present invention.

[0011]

Explanation of symbols

[0012] 100: Semiconductor Structure

[0013] 121-123, 127, 128, 129A-129D, 130A-130D, 131A-131D: Doped regions

[0014] 129,130,131: Ring structure

[0015] 140,145: Gate structure

[0016] 160,165,460,465,760,765: Field plate structure

[0017] 161~163,166~168,461~463,466~468,761,762,766,767: Part of the field plate

[0018] AA,BB,CC: Line segment

[0019] L1~L8: Length

[0020] 101: Substrate

[0021] 102: buried layer

[0022] 111,113A~113D,115A~115D,117A~117D: Well

[0023] 141,146: Gate dielectric layer

[0024] 142,147: Gate electrode layer

[0025] 150,155: Insulation layer

[0026] 170: Trench Isolator

[0027] 180: Insulation layer

[0028] 190: Conductive layer

[0029] 201A~211A,201B~211B: Through hole

[0030] 221A~231A,221B~231B:Electrode

[0031] 241-246: Internal connection DETAILED DESCRIPTION

[0032] To make the objectives, features, and advantages of the present invention more readily apparent, the following examples are presented and described in detail with reference to the accompanying drawings. This specification provides various examples to illustrate the technical features of various embodiments of the present invention. The configurations of the various components in the examples are for illustrative purposes only and are not intended to limit the present invention. Furthermore, some duplication of figure numerals in the examples is for simplification and does not imply a correlation between the different examples.

[0033] Figure 1 FIG. 4 is a top view of the semiconductor structure of the present invention. Figure 2A The semiconductor structure of the present invention is along Figure 1 Cross-section of line segment AA. Figure 2B The semiconductor structure of the present invention is along Figure 1 Cross-section of line segment BB. Figure 2C The semiconductor structure of the present invention is along Figure 1 It should be noted that, in order to simplify the description and make it clear and understandable, some features and / or reference symbols are shown in FIG. Figure 1 and Figure 2C is omitted. Please refer to Figure 1 and Figures 2A to 2C In some embodiments, the semiconductor structure 100 includes a substrate 101, a well 111, a well 113A, a doped region 121, a doped region 122, a doped region 123, a doped region 129A, a gate structure 140, an insulating layer 150, and a field plate structure 160. In other embodiments, the semiconductor structure further includes wells 113B, 113C, 113D, 115A, 115B, 115C, 115D, 117A, 117B, 117C, 117D, doped regions 130A, 131A, 127, 128, 129B, 130B, 131B, 129C, 130C, 131C, 129D, 130D, 131D, a gate structure 145, an insulating layer 155, and a field plate structure 165.

[0034] The substrate 101 may be a semiconductor substrate, such as a silicon substrate. Furthermore, the semiconductor substrate may also be an elemental semiconductor, including germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon-germanium alloy (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), gallium indium phosphide alloy (GaInP), and / or gallium indium arsenide phosphide alloy (GaInAsP), or a combination of the above materials. Furthermore, the substrate 101 may also be a semiconductor on an insulator (SIO). In some embodiments, the substrate 101 may be an undoped substrate. However, in other embodiments, the substrate 101 may also be a lightly doped substrate, such as a lightly doped P-type or N-type substrate.

[0035] Wells 111 and 113A are formed in substrate 101. In some embodiments, wells 113B-113D, 115A-115D, and 117A-117D are also formed in substrate 101. In some embodiments, wells 111, 113A-113D, 115A-115D, and 117A-117D are all high-voltage wells, wherein wells 111 and 115A-115D have a first conductivity type, while wells 113A-113D and 117A-117D have a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, an N-type well can be formed by implanting phosphorus ions or arsenic ions, and a P-type well can be formed by implanting boron ions or indium ions. Similarly, when the first conductivity type is P type and the second conductivity type is N type, an N type well can be formed by implanting phosphorus ions or arsenic ions, and a P type well can be formed by implanting boron ions or indium ions.

[0036] In some embodiments, wells 113A, 113B, 113C, and 113D collectively form a first ring structure that surrounds well 111 (in the XY plane). In some other embodiments, wells 113A-113D do not form a ring structure. In these embodiments, wells 113A-113D may be electrically isolated from one another. In some embodiments, semiconductor structure 100 includes only one, two, or three of wells 113A-113D. In some embodiments, wells 115A, 115B, 115C, and 115D collectively form a second ring structure that surrounds the first ring structure (in the XY plane). In some other embodiments, wells 115A-115D do not form a ring structure. In these embodiments, wells 115A-115D may be electrically isolated from one another. In some embodiments, semiconductor structure 100 includes only one, two, or three of wells 115A-115D. In some embodiments, wells 117A, 117B, 117C, and 117D collectively form a third ring structure that surrounds (in the XY plane) the second ring structure. In some other embodiments, wells 117A-117D do not form a ring structure. In these embodiments, wells 117A-117D may be electrically isolated from one another. In certain embodiments, semiconductor structure 100 includes only one, two, or three of wells 117A-117D.

[0037] In some embodiments, the semiconductor structure 100 further includes a buried layer 102 having a first conductivity type. The buried layer 102 is disposed in the substrate 101 and below the wells 111, 113A-113D, and 115A-115D.

[0038] The doped region 121 is disposed in the well 111 and has a first conductivity type. Figures 2A to 2C In the embodiment shown, the doping concentration of the doping region 121 is higher than the doping concentration of the well 111. The doping regions 122, 123 and 129A are disposed in the well 113A, wherein the doping region 122 has a first conductivity type, and the doping regions 123 and 129A have a second conductivity type. Figures 2A to 2C In the embodiment shown, the doping concentration of doped region 122 is higher than that of well 111 , and the doping concentrations of doped regions 123 and 129A are higher than that of well 113 A. In some embodiments, doped region 122 is adjacent to doped region 123 .

[0039] In some embodiments, doped regions 127, 128, and 129B are disposed in well 113B, wherein doped region 127 has a first conductivity type, and doped regions 128 and 129B have a second conductivity type. In addition, doped region 130A having a first conductivity type is disposed in well 115A, doped region 131A having a second conductivity type is disposed in well 117A, doped region 130B having a first conductivity type is disposed in well 115B, and doped region 131B having a second conductivity type is disposed in well 117B. Figures 2A to 2C In the illustrated embodiment, the doping concentrations of doped regions 130A, 127, and 130B are higher than the doping concentration of well 111, and the doping concentrations of doped regions 131A, 128, 129B, and 131B are higher than the doping concentration of well 113A. In some embodiments, doped region 127 is adjacent to doped region 128. It should be noted that although the figures of the present invention depict the first conductivity type as N-type (e.g., doped region 121) and the second conductivity type as P-type (e.g., doped region 123), this is for illustrative purposes only. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0040] In some embodiments, the semiconductor structure 100 further includes a plurality of trench isolators 170 formed by a shallow trench isolation (STI) process. The trench isolators 170 are used to separate different doped regions. For example, the trench isolators 170 separate the doped region 123 from the doped region 129A, the doped region 129A from the doped region 130A, the doped region 130A from the doped region 131A, the doped region 128 from the doped region 129B, the doped region 129B from the doped region 130B, and the doped region 130B from the doped region 131B. However, any other suitable method may be used to separate the different doped regions, such as forming a field oxide layer using a conventional field oxidation method (LOCOS) to separate the different doped regions.

[0041] In some embodiments, doped regions 129A, 129B, 129C, and 129D collectively form a ring structure 129, which surrounds (in the XY plane) doped regions 121, 122, 123, 127, and 128. In some other embodiments, doped regions 129A-129D do not form a ring structure. In these embodiments, doped regions 129A-129D may be electrically isolated from each other. In some embodiments, semiconductor structure 100 includes only one, two, or three of doped regions 129A-129D. In some embodiments, doped regions 130A, 130B, 130C, and 130D collectively form a ring structure 130, which surrounds (in the XY plane) ring structure 129. In some other embodiments, doped regions 130A-130D do not form a ring structure. In these embodiments, doped regions 130A-130D may be electrically isolated from each other. In some embodiments, the semiconductor structure 100 includes only one, two, or three of the doped regions 130A-130D. In some embodiments, the doped regions 131A, 131B, 131C, and 131D collectively form a ring structure 131, which surrounds the ring structure 130 (in the XY plane). In some other embodiments, the doped regions 131A-131D do not form a ring structure. In these embodiments, the doped regions 131A-131D may be electrically isolated from each other. In some embodiments, the semiconductor structure 100 includes only one, two, or three of the doped regions 131A-131D.

[0042] The gate structure 140 is disposed on the substrate 101 and partially overlaps with the wells 111 and 113A. Figure 1 and Figures 2A to 2C In some embodiments, the gate structure 140 is disposed on a portion of the surface of the wells 111 and 113A and between the doped region 121 and the doped region 122. The gate structure 140 includes a gate dielectric layer 141 and a gate electrode layer 142. In some embodiments, the gate dielectric layer 141 can be formed on the wells 111 and 113A, and the gate electrode layer 142 can be formed on the gate dielectric layer 141 by a deposition process. For example, the deposition process can include a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a coating process, other suitable processes, or a combination thereof.

[0043] The gate dielectric layer 141 may include a commonly used dielectric material such as oxide, nitride, oxynitride, oxycarbide, or a combination thereof. The gate dielectric layer 141 may also include a high-k dielectric material (dielectric constant greater than 8), such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO4), yttrium oxide (Y2O3), lanthalum oxide (La2O3), cerium oxide (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), or a combination thereof.

[0044] In some embodiments, the gate electrode layer 142 comprises silicon or polysilicon. The gate electrode layer 142 may be doped with dopants to reduce its sheet resistance. In other embodiments, the gate electrode layer 142 comprises other materials, such as amorphous silicon, aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), ruthenium (Ru), palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten silicide (WSi), titanium silicide (TiSi2), other suitable conductive materials, or combinations thereof. Furthermore, a metal silicide may optionally be formed on the surface of the gate electrode layer 142. In some embodiments, a gap is formed between the gate structure 140 and the doped region 121. In other words, the gate structure 140 does not contact the doped region 121.

[0045] exist Figure 1 and Figures 2A to 2CIn the illustrated embodiment, gate structure 140 and doped regions 121 and 122 form a first transistor. The present invention is not limited to the type of the first transistor. In a preferred embodiment, the first transistor is a laterally diffused metal oxide semiconductor (LDMOS) transistor. In this embodiment, gate structure 140 serves as the gate of the first transistor, doped region 121 serves as the drain of the first transistor, and doped region 122 serves as the source of the first transistor. In some other embodiments, doped region 123 is connected to doped region 122 and together serves as the source of the first transistor.

[0046] In some embodiments, the semiconductor structure 100 further includes a gate structure 145. The gate structure 145 is disposed on the substrate 101 and partially overlaps the wells 111 and 113B. Figure 1 and Figures 2A to 2C In the illustrated embodiment, a gate structure 145 is disposed on portions of the surfaces of the wells 111 and 113B, and between the doped regions 121 and 127. The gate structure 145 includes a gate dielectric layer 146 and a gate electrode layer 147. In these embodiments, the gate dielectric layer 146 and the gate electrode layer 147 can be formed using the same or similar processes as those used to form the gate dielectric layer 141 and the gate electrode layer 142. The gate dielectric layer 146 can include the same or similar materials as the gate dielectric layer 141, and the gate electrode layer 147 can include the same or similar materials as the gate electrode layer 142.

[0047] exist Figure 1 and Figures 2A to 2C In the embodiment shown, the gate structure 145, the doped regions 121 and 127 form a second transistor that is identical or similar to the first transistor. In this embodiment, the gate structure 145 serves as the gate of the second transistor, the doped region 121 serves as the drain of the second transistor, and the doped region 127 serves as the source of the second transistor. In some other embodiments, the doped region 128 is connected to the doped region 127 and together serves as the source of the second transistor. It should be noted that although Figure 1 and Figures 2A to 2C Only two transistors (a first transistor and a second transistor) are drawn in FIG. 1 , but the semiconductor structure 100 may include any number of transistors.

[0048] The insulating layer 150 is disposed on the substrate and partially overlaps with the gate structure 140. Figure 1 and Figures 2A to 2CIn some embodiments, the insulating layer 150 overlaps and directly contacts a portion of the well 111 and a portion of the gate electrode layer 142. The insulating layer 150 may be formed by the aforementioned deposition process, including oxide, nitride, oxynitride, a low-k dielectric material, any other suitable insulating material, or a combination thereof. In some embodiments, the insulating layer 150 is thicker than the gate dielectric layer 141.

[0049] In one embodiment, the semiconductor structure 100 further includes an insulating layer 155. The insulating layer 155 is disposed on the substrate and partially overlaps the gate structure 145. The insulating layer 155 overlaps and directly contacts a portion of the well 111 and a portion of the gate electrode layer 147. The insulating layer 155 may comprise the same or similar material as the insulating layer 150. The insulating layer 155 may be formed using the same process as the insulating layer 150.

[0050] The field plate structure 160 is disposed on the insulating layer 150 and partially overlaps with the gate structure 140. Figure 1 and Figures 2A to 2C In some embodiments, the field plate structure 160 directly contacts the insulating layer 150 and partially overlaps the insulating layer 150 and the gate structure 140. The field plate structure 160 can be used to uniformize the electric field distribution. When the field plate structure 160 overlaps the gate structure 140, better electric field distribution can be achieved. In some embodiments, the field plate structure 160 is made of polysilicon. In some other embodiments, the field plate structure 160 is made of the same or similar material as the gate structure 140.

[0051] In one embodiment, semiconductor structure 100 further includes a field plate structure 165. Field plate structure 165 is disposed on insulating layer 155 and partially overlaps gate structure 145. Field plate structure 165 directly contacts insulating layer 155 and partially overlaps insulating layer 155 and gate structure 145. In some embodiments, field plate structure 165 is made of polysilicon. In other embodiments, field plate structure 165 is made of the same or similar material as gate structure 140.

[0052] In some embodiments, the semiconductor structure 100 further includes an insulating layer 180. Figure 1 and Figures 2A to 2CIn the illustrated embodiment, insulating layer 180 covers wells 111, 113A-113D, 115A-115D, 117A-117D, doped regions 121, 122, 123, 127, 128, 129A-129D, 130A-130D, 131A-131D, trench isolation 170, gate structures 140 and 145, insulating layers 150 and 155, and field plate structures 160 and 165. In some embodiments, insulating layer 150 (and insulating layer 155) are formed in separate steps from insulating layer 180. For example, after forming insulating layers 150 and 155, field plate structures 160 and 165 are formed on insulating layers 150 and 155 before forming insulating layer 180.

[0053] In some embodiments, the semiconductor structure 100 further includes a conductive layer 190. The conductive layer 190 includes a plurality of electrodes and a plurality of interconnects. The electrodes are interconnected via the interconnects. The electrodes are electrically connected to features of the semiconductor structure via through holes in the insulating layer 180. In some embodiments, electrodes 221A and 221B are electrically connected to the doped region 121 via through holes 201A and 201B, respectively, and serve as drain contacts. Electrodes 222A and 222B are electrically connected to the field plate structure 160 via through holes 202A and 202B, respectively, and serve as field plate contacts. Electrodes 223A and 223B are electrically connected to the gate electrode layer 142 via through holes 203A and 203B, respectively, and serve as gate contacts. Electrodes 224A and 224B are electrically connected to the doped region 122 via through holes 204A and 204B, respectively, and serve as source contacts. In some other embodiments, electrodes 225A and 225B are electrically connected to doped region 123 via through-holes 205A and 205B, respectively, and serve as source contacts together with electrodes 224A and 224B. Electrodes 226A and 226B are electrically connected to doped region 129A via through-holes 206A and 206B, respectively.

[0054] In some embodiments, electrodes 227A and 227B are electrically connected to the field plate structure 165 via through-holes 207A and 207B, respectively, and serve as field plate contacts. Electrodes 228A and 228B are electrically connected to the gate electrode layer 147 via through-holes 208A and 208B, respectively, and serve as gate contacts. Electrodes 229A and 229B are electrically connected to the doped region 127 via through-holes 209A and 209B, respectively, and serve as source contacts. In some other embodiments, electrodes 230A and 230B are electrically connected to the doped region 128 via through-holes 210A and 210B, respectively, and together with electrodes 229A and 229B, serve as source contacts. Electrodes 231A and 231B are electrically connected to the doped region 129B via through-holes 211A and 211B, respectively.

[0055] The present invention improves the performance of semiconductor devices (e.g., the first transistor and / or the second transistor mentioned above) by introducing a field plate. Generally speaking, when the field plate is tied (or electrically connected) to the gate, it can reduce the on-resistance (Ron) of the semiconductor structure and increase the current, but it will increase the total gate charge (Qg) of the semiconductor structure and thus reduce the switching speed. When the field plate is electrically connected to the source, the on-resistance will increase and the total gate charge will decrease. In view of this, the present invention provides a structure and method for obtaining better on-resistance and total gate charge by segmenting the field plate into multiple partial field plates and electrically connecting them to the gate or source respectively. At the same time, by electrically connecting partial field plates of different lengths to the gate and / or source, different on-resistances and / or total gate charges can be obtained. According to the present invention, the on-resistance and total gate charge can be flexibly configured based on design requirements by segmenting the field plate to obtain the required device performance. In addition, the on-resistance and total gate charge can be flexibly configured to obtain the best optimization index (figure of merit, FOM, defined as Ron*Qg), and the smaller the optimization index, the better.

[0056] In some embodiments, as Figure 1 and Figure 2C As shown, the field plate structure 160 is divided (along the Y direction) into separate partial field plates 161, 162 and 163, each having a length L1, L2 and L3, respectively. Figure 1 and Figure 2C In the illustrated embodiment, lengths L1 and L3 are greater than length L2. In some embodiments, field plate structure 165 is divided (along the Y direction) into separate partial field plates 166, 167, and 168. Partial field plates 166, 167, and 168 have the same or similar configuration and length as partial field plates 161, 162, and 163.

[0057] In one embodiment, the partial field plates 161, 163 and / or 166, 168 with a longer length are electrically connected to the source to obtain a smaller total gate charge. And the partial field plates 162 and / or 167 with a shorter length are electrically connected to the gate to obtain a smaller on-resistance, with an optimization index of about 290 to 300 (Ω×pC), where Ω is ohm and pC is pico-coulomb. The present invention does not limit how the partial field plates with a longer length (for example, the partial field plates 161, 163, 166 and 168) are electrically connected to the source. In one possible embodiment (such as Figure 2AAs shown in FIG, the partial field plate 161 of the field plate structure 160 can be electrically connected to the electrode 224A serving as the source contact terminal via the through hole 202A, the electrode 222A, and the interconnect 241; and the partial field plate 166 of the field plate structure 165 can be electrically connected to the electrode 229A serving as the source contact terminal via the through hole 207A, the electrode 227A, and the interconnect 242. Similarly, the present invention does not limit how the shorter partial field plates (e.g., partial field plates 162 and 167) are electrically connected to the gate. In one possible embodiment (e.g., FIG. Figure 2B As shown, a portion of the field plate 162 of the field plate structure 160 can be electrically connected to the electrode 223B serving as the gate contact via a through-hole 202B, an electrode 222B, and an interconnect 243. A portion of the field plate 167 of the field plate structure 165 can be electrically connected to the electrode 228B serving as the gate contact via a through-hole 207B, an electrode 227B, and an interconnect 245. In some embodiments, electrodes 224B, 225B, and 226B are interconnected via an interconnect 244, while electrodes 229B, 230B, and 231B are interconnected via an interconnect 246. In one embodiment, lengths L1 and L3 are approximately 90 to 120 micrometers (μm), and length L2 is approximately 10 to 30 μm. However, these lengths are not limited thereto and can be adjusted by those skilled in the art based on actual needs. In a comparative embodiment, the longer portion of the field plates 161, 163, and / or 166, 168 is electrically connected to the gate to achieve lower on-resistance, while the shorter portion of the field plates 162 and / or 167 is electrically connected to the source to achieve lower total gate charge. The optimized performance index is approximately 300-310 (Ω×pC). The main difference between the optimized performance index measurements, the embodiment, and the comparative embodiment lies in the different electrical connection methods; the component composition and size are essentially the same.

[0058] Figure 3 FIG. 4 is a top view of the semiconductor structure of the present invention. Figure 4 The semiconductor structure of the present invention is along Figure 3 It should be noted that, in order to simplify the description and make it clear and understandable, some features and / or reference symbols are shown in FIG. Figure 3 and Figure 4 is omitted. In addition, Figure 3 and Figure 4 Some of the characteristics of Figure 1 and Figures 2A to 2C The same or similar parts are therefore denoted by the same reference symbols throughout this document.

[0059] In some embodiments, as Figure 3 and Figure 4 As shown, the field plate structure 460 is divided (along the Y direction) into separate partial field plates 461, 462 and 463, each having a length of L4, L5 and L6. Figure 3 and Figure 4 In the illustrated embodiment, length L5 is greater than length L4 and length L6. In some embodiments, field plate structure 465 is divided (along the Y direction) into separate partial field plates 466, 467, and 468. Partial field plates 466, 467, and 468 have the same or similar configuration and length as partial field plates 461, 462, and 463.

[0060] In one embodiment, the shorter portion of the field plates 461, 463 and / or 466, 468 is electrically connected to the source to obtain a smaller total gate charge. And the longer portion of the field plates 462 and / or 467 is electrically connected to the gate to obtain a smaller on-resistance. For example, similar to Figure 2A The shorter field plates 461, 463 and / or 466, 468 can be electrically connected to the source contact electrode via the through hole, the electrode and the interconnection. Figure 2B The longer portion of the field plate 462 and / or 467 may be electrically connected to the electrode serving as the gate contact terminal via the through hole, the electrode, and the interconnection line.

[0061] In a comparative embodiment, the shorter portion of the field plates 461, 463, and / or 466, 468 is electrically connected to the gate to achieve lower on-resistance, while the longer portion of the field plates 462 and / or 467 is electrically connected to the source to achieve lower total gate charge. The main difference between the above embodiment and the comparative embodiment lies in the different electrical connection methods; the component composition and size of the two are substantially the same.

[0062] Figure 5 It should be noted that some features and / or reference symbols are omitted in the figure to simplify the description and make it clear and understandable. Figure 5 is omitted. In addition, Figure 5 Some of the characteristics of Figure 1 and Figures 2A to 2C The same or similar parts are therefore denoted by the same reference symbols throughout this document.

[0063] In some embodiments, as Figure 5 As shown, the field plate structure 760 is divided (along the Y direction) into separate field plate portions 761 and 762 , each having a length L7 and a length L8 . Figure 5 In the illustrated embodiment, length L7 is less than length L8. However, in other embodiments, length L7 may be greater than or equal to length L8. In some embodiments, field plate structure 765 is divided (along the Y direction) into separate partial field plates 766 and 767. Partial field plates 766 and 767 have the same or similar configuration and length as partial field plates 761 and 762.

[0064] In one embodiment, part of the field plate 761 and / or 766 is electrically connected to the source to obtain a smaller total gate charge. And part of the field plate 762 and / or 767 is electrically connected to the gate to obtain a smaller on-resistance. For example, similar to Figure 2A , part of the field plate 761 and / or 766 can be electrically connected to the electrode serving as the source contact terminal through the through hole, the electrode and the interconnection. Figure 2B Part of the field plate 762 and / or 767 can be electrically connected to the electrode serving as the gate contact terminal through the through hole, the electrode and the interconnection.

[0065] In a comparative embodiment, portions of field plates 761 and / or 766 are electrically connected to the gate to achieve lower on-resistance, while portions of field plates 762 and / or 767 are electrically connected to the source to achieve lower total gate charge. The primary difference between the aforementioned embodiment and the comparative embodiment lies in the electrical connection method; the component composition and size of the two are substantially the same.

[0066] Although the figures of the present invention only depict embodiments in which the field plate structure is divided into two or three partial field plates, it should be understood that the present invention also encompasses embodiments in which the field plate structure is divided into four or more partial field plates. In these embodiments, each field plate structure can be individually electrically connected to the source or gate to obtain a desired total gate charge and on-resistance.

[0067] Although the semiconductor structure 100 is depicted as having two transistors in the figures of the present invention, the semiconductor structure 100 may have any number of transistors. For example, the semiconductor structure 100 may include one, three, or more transistors. Furthermore, in the semiconductor structure 100, different field plate structures may have different configurations. For example, different field plate structures may be divided into different numbers of partial field plates, and / or the partial field plates of different field plate structures may have different lengths to achieve desired device performance.

[0068] According to the present invention, a field plate can be divided into multiple partial field plates and electrically connected to the gate or source respectively to obtain a better on-resistance and total gate charge. At the same time, the divided partial field plates can be set to different lengths to obtain different combinations of on-resistance and total gate charge. In this way, the on-resistance and total gate charge can be flexibly configured based on design requirements by dividing the field plates to obtain the required device performance. In addition, the on-resistance and total gate charge can also be flexibly configured to obtain the best optimization figure (FOM).

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) are as commonly understood by those skilled in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, dictionary definitions of terms should be interpreted as consistent with their meanings in the relevant technical field and should not be construed as idealized or overly formal. While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another.

[0070] While the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Any skilled artisan may make modifications and variations without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate; a first well disposed in the substrate and having a first conductivity type; a second well disposed in the substrate and adjacent to the first well, and having a second conductivity type opposite to the first conductivity type; a first doped region disposed in the first well; a second doped region disposed in the second well; a first gate structure and a second gate structure, wherein the first gate structure is disposed between the first doped region and the second doped region; a first insulating layer covering a portion of the first well and a portion of the first gate structure; as well as a first field plate structure disposed on the first insulating layer and at least partially overlapping with the first gate structure, wherein the first field plate structure is divided into a first partial field plate and a second partial field plate along a first direction, and the first gate structure and the second gate structure are arranged along a second direction perpendicular to the first direction, and the first partial field plate and the second partial field plate are separated from each other.

2. The semiconductor structure according to claim 1, wherein: The first partial field plate has a first length in the first direction, and the second partial field plate has a second length in the first direction. The first partial field plate is electrically connected to the first gate structure, and the second partial field plate is electrically connected to the second doped region.

3. The semiconductor structure according to claim 2, wherein: The first length is different from the second length.

4. The semiconductor structure according to claim 1, wherein: The first field plate structure is divided into the first partial field plate having a first length, the second partial field plate having a second length, and a third partial field plate having a third length along the first direction. The first partial field plate, the second partial field plate, and the third partial field plate are separated from each other.

5. The semiconductor structure according to claim 4, wherein: The first length and the third length are greater than the second length.

6. The semiconductor structure according to claim 5, wherein: The first partial field plate and the third partial field plate are electrically connected to the second doped region, and the second partial field plate is electrically connected to the first gate structure, or the first partial field plate and the third partial field plate are electrically connected to the first gate structure, and the second partial field plate is electrically connected to the second doped region, and the second doped region is a source.

7. The semiconductor structure according to claim 1, wherein: The first field plate structure is divided into a plurality of partial field plates along the first direction including the first partial field plate and the second partial field plate, wherein each of the plurality of partial field plates is electrically connected to the first gate structure or the second doped region.

8. The semiconductor structure according to claim 1, wherein: It also includes a third doping region, which is arranged in the second well, and is adjacent to and connected to the second doping region, wherein the second doping region has the first conductivity type, and the third doping region has the second conductivity type.

9. The semiconductor structure according to claim 1, wherein: Also includes: a third well disposed in the substrate and adjacent to the first well, and having the second conductivity type; a fourth doped region disposed in the third well; The second gate structure is disposed between the first doping region and the fourth doping region; a second insulating layer covering a portion of the first well and a portion of the second gate structure; and A second field plate structure is disposed on the second insulating layer and partially overlaps with the second gate structure, wherein the second field plate structure is divided into a fourth partial field plate and a fifth partial field plate along the first direction, and the fourth partial field plate and the fifth partial field plate are separated from each other.

10. The semiconductor structure according to claim 9, wherein: The second field plate structure is divided into a plurality of field plate portions along the first direction including the fourth partial field plate and the fifth partial field plate, wherein each of the plurality of field plate portions is electrically connected to the second gate structure or the fourth doped region.

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