An FPGA reconfiguration method based on dynamic perception life balance and related device

Abstract

The application discloses a FPGA reconfiguration method based on dynamic perception life balance and related devices. The method selects a configuration file from a preset configuration file set, obtains the write times of each physical block memory, solves the execution time weight of each configuration file according to the write times and the historical write times of the physical block memory, selects the configuration file according to the execution time weight to generate a configuration file sequence, sets a second threshold for the configuration file according to the execution time weight of each configuration file sequence, and sequentially runs each configuration file in the configuration file sequence until all the configuration files in the configuration file sequence are run. The logical block memory is remapped to other physical block memories, so that the life balance of the physical block memory is realized, and the life of the physical block memory is balanced according to the real write times through dynamic sensing.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of nonvolatile FPGA (Nonvolatile Filed Programmable Gate Array), and particularly relate to a FPGA reconfiguration method based on dynamic perception life balance and related devices. BACKGROUND

[0002] The life balance of the traditional memory is mainly based on a static analysis method. The static analysis method is to generate a series of random excitations in an offline stage to predict the logic block memory write frequency, and to estimate the physical wear of the mapped physical block memory according to the logic block memory write frequency.

[0003] In the offline stage, a plurality of configuration files are generated according to the predicted logic block memory write frequency, and in the running stage, the reconfiguration controller switches between them according to the sequence of the configuration files generated in the offline stage to remap the logic block memory to the physical block memory, so as to achieve the life balance between the physical block memories.

[0004] However, with the switching of the circuit working mode, the write frequency of the static analysis often deviates greatly from the actual write frequency. It is difficult for most circuit synthesis tools to obtain accurate excitation file sequences, and only random excitation can be used instead, which also makes the accuracy of the static analysis method far from the actual running process. SUMMARY

[0005] The present application provides a FPGA reconfiguration method based on dynamic perception life balance and related devices to achieve the life balance of the memory through dynamic perception write mode.

[0006] In a first aspect, embodiments of the present application provide a FPGA reconfiguration method based on dynamic perception life balance and related devices for the life balance of the memory, comprising:

[0007] selecting a configuration file from a preset configuration file set, the configuration file including a mapping relationship between a logic block memory and a physical block memory;

[0008] acquiring the write times of each physical block memory in the process of storing data in the physical block memory according to the configuration file;

[0009] when the write times are greater than a first threshold, solving the execution time weight of each configuration file according to the write times and the historical write times of the physical block memory;

[0010] generating a configuration file sequence according to the execution time weight selection configuration file, and setting a second threshold for each configuration file according to the execution time weight of each configuration file sequence;

[0011] sequentially running each configuration file in the configuration file sequence, and when running each configuration file, if the number of write times of the physical block memory is greater than the second threshold, running the next configuration file in the configuration file sequence, until all configuration files in the configuration file sequence are run.

[0012] Optionally, before selecting a configuration file from a preset configuration file set, the method further comprises:

[0013] when detecting a trigger generation configuration file event, loading a physical block memory usage dictionary, the physical block memory usage dictionary comprising the number of write times of each physical block memory and the number of remapping times of a logical block memory mapped to the same physical block memory;

[0014] determining a candidate physical block memory from all physical block memories;

[0015] randomly mapping each logical block memory to a candidate physical block memory to obtain an initial configuration file;

[0016] adjusting the mapping relationship between the logical memory and the candidate physical block memory in the initial configuration file based on the number of write times, the number of remapping times, and a simulated annealing algorithm to obtain a final configuration file.

[0017] Optionally, the determining a candidate physical block memory from all physical block memories comprises:

[0018] sorting the physical block memories according to the number of write times from large to small;

[0019] determining the first N physical block memories in the sorting as candidate physical block memories.

[0020] Optionally, the adjusting the mapping relationship between the logical memory and the candidate physical block memory in the initial configuration file based on the number of write times, the number of remapping times, and a simulated annealing algorithm to obtain a final configuration file comprises:

[0021] randomly selecting a logical block memory and remapping the logical block memory to another candidate physical block memory;

[0022] calculating a cost before remapping and a cost after remapping based on the number of write times and the number of remapping times;

[0023] when the difference between the cost before the remapping and the cost after the remapping is less than a preset value, accepting the logical block memory remapping to another candidate physical block memory;

[0024] when the difference between the cost before the remapping and the cost after the remapping is greater than a preset value, calculating an acceptance probability by using the difference and a preset parameter;

[0025] when the acceptance probability is greater than a preset probability, accepting the logical block memory remapping to another candidate physical block memory;

[0026] judging whether a termination iteration condition is met;

[0027] if yes, generating a configuration file according to the accepted mapping relationship;

[0028] if no, returning to the step of randomly selecting a logical block memory and remapping the logical block memory to another candidate physical block memory.

[0029] Optionally, the cost includes a first cost and a second cost, and the cost before the remapping is calculated based on the write times and the remapping times, including:

[0030] the first cost is calculated by the following formula:

[0031]

[0032] Use(BRAM i ) represents the write times of the physical block memory numbered i, and Max_Used(BRAMs) represents the write times of the most used physical block memory among all the physical block memories;

[0033] the second cost is calculated by the following formula:

[0034]

[0035] Reuse(BRAM i ,Log j ) represents the remapping times of the logical block memory numbered j being mapped to the physical block memory numbered i.

[0036] Optionally, when the write times are greater than a first threshold value, the execution time weight of each configuration file is solved according to the write times and the historical write times of the physical block memory, including:

[0037] for each physical block memory, the predicted write times are calculated by using the historical write times;

[0038] The write number matrix, the predicted write number matrix and the weight matrix are respectively constructed by using the write number of each physical block memory, the predicted write number and the execution time weight of each configuration file;

[0039] An optimization function is constructed by using the write number matrix, the predicted write number matrix and the weight matrix, and the optimization function takes the execution time weight in the weight matrix as a variable;

[0040] The weight matrix that makes the optimization function minimum is solved by using a quadratic programming algorithm, and the execution time weight of each configuration file is obtained.

[0041] Optionally, the second threshold value is set for the configuration file according to the execution time weight of each configuration file sequence, and the method comprises the following steps of:

[0042] For each configuration file, the product of the execution time weight of the configuration file and a preset reconstruction granularity constant is calculated;

[0043] For each physical block memory, the sum value of the product and the current write number of the physical block memory is calculated as the second threshold value of the physical block memory in the configuration file.

[0044] In a second aspect, an FPGA reconstruction device based on dynamic perception life balance is also provided, and the device comprises:

[0045] A configuration file selection module is configured to select a configuration file from a preset configuration file set, and the configuration file comprises a mapping relationship between a logic block memory and a physical block memory;

[0046] A write number acquisition module is configured to acquire the write number of each physical block memory in the process of storing data in the physical block memory according to the configuration file;

[0047] An execution time weight solving module is configured to solve the execution time weight of each configuration file according to the write number and the historical write number of the physical block memory when the write number is greater than a first threshold value;

[0048] A configuration file sequence generation module is configured to select a configuration file to generate a configuration file sequence according to the execution time weight, and set a second threshold value for the configuration file according to the execution time weight of each configuration file sequence;

[0049] A configuration file running module is configured to sequentially run each configuration file in the configuration file sequence, and run the next configuration file in the configuration file sequence when the write number of the physical block memory is greater than the second threshold value during the running of each configuration file, until all the configuration files in the configuration file sequence are run.

[0050] In a third aspect, an electronic device is provided, and the electronic device comprises:

[0051] at least one processor; and

[0052] a memory connected with the at least one processor in communication; wherein

[0053] the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the FPGA reconfiguration method based on dynamic perception life balance according to any one of the first aspect.

[0054] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores computer instructions for enabling a processor to implement the FPGA reconfiguration method based on dynamic perception life balance according to any one of the first aspect when executed by the processor.

[0055] The present application selects a configuration file from a preset configuration file set, obtains the write times of each physical block memory, solves the execution time weight of each configuration file according to the write times and the historical write times of the physical block memory, selects the configuration file according to the execution time weight to generate a configuration file sequence, sets a second threshold for the configuration file according to the execution time weight of each configuration file sequence, and sequentially runs each configuration file in the configuration file sequence until all configuration files in the configuration file sequence are run. The execution time weight of each configuration file is solved by dynamically perceiving the write times and the historical write times of the physical machine memory, and the second threshold of each configuration file is recalculated according to the execution time weight. When the configuration file in the configuration file sequence is executed and the write times reach the second threshold, the execution of the configuration file is ended to execute the next configuration file. The logical block memory is remapped to other physical block memory, thereby realizing the life balance of the physical block memory. Compared with the prior art of generating configuration files offline and executing the configuration files according to the configuration file generation sequence, the present embodiment dynamically perceives the write times and the historical write times of each physical block memory to switch the configuration file to reconstruct the mapping relationship of the logical block memory to the physical block memory, and the life of the physical block memory can be more balanced according to the real write times. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0057] Figure 1 is a flow chart of a FPGA reconfiguration method based on dynamic perception life balance in the embodiment one of the present application;

[0058] Figure 2 is a flow chart of a FPGA reconfiguration method based on dynamic perception life balance in the embodiment two of the present application;

[0059] Figure 3 is a structural schematic diagram of a FPGA reconfiguration device based on dynamic perception life balance in the embodiment three of the present application;

[0060] Figure 4 is a structural schematic diagram of an electronic device in the embodiment four of the present application. DETAILED DESCRIPTION

[0061] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0062] Embodiment one

[0063] Figure 1 is a flow chart of a FPGA reconfiguration method based on dynamic perception life balance provided in the embodiment one of the present application. The present embodiment can be applicable to the life balance of the memory. The method can be executed by a FPGA reconfiguration device based on dynamic perception life balance, which can be integrated in an electronic device, and specifically includes the following steps:

[0064] S101, selecting a configuration file from a preset configuration file set. The configuration file includes the mapping relationship between the logical block memory and the physical block memory.

[0065] The logical block memory can be the block memory logically needed by the user in the design, and the physical block memory can be the physical area of the stored data on the memory, i.e. the specific block memory on the memory, which is the physical resource of the memory.

[0066] The configuration file can be a file representing a mapping relationship between logical block storage and physical block storage, and application indicates data storage on the logical block storage on the design to the corresponding physical block storage. In actual application, a plurality of configuration files can be generated in advance, and the mapping relationship between the logical block storage and the physical block storage is different in each configuration file. The plurality of configuration files constitute a configuration file set.

[0067] For each memory, a configuration file can be randomly selected to run at each power-on, to indicate data storage of each logical block storage to the corresponding physical block storage.

[0068] S102, in the process of storing data in the physical block storage according to the configuration file, obtaining the write times of each physical block storage.

[0069] In the process of storing data in the memory according to the configuration file, the count data of the counter set on each physical block storage can be read, and the count data of the counter is taken as the write times.

[0070] S103, when the write times are greater than a first threshold, solving the execution time weight of each configuration file according to the write times and the historical write times of the physical block storage.

[0071] The execution time weight can be the weight of the time allocated to execute each configuration file within a period of time. The first threshold can be a fixed threshold, which can be determined according to the write life of the physical block storage. When the write times of a certain physical block storage are greater than the first threshold during the execution of the configuration file, the execution time weight of each configuration file is solved according to the write times of each physical block storage and the historical write times of the physical block storage. The execution time weight makes the write times of each physical block storage balanced, i.e. the life balanced, after executing each configuration file within a period of time in the future.

[0072] In one example, for each physical block storage, the historical write times can be used to calculate the predicted write times, the write times, the predicted write times and the execution time weight of each configuration file are used to construct a write times matrix, a predicted write times matrix and a weight matrix respectively, and the write times matrix, the predicted write times matrix and the weight matrix are used to construct an optimization function, and the optimization function takes the execution time weight in the weight matrix as a variable. The weight matrix that makes the optimization function minimum is solved by using a quadratic programming algorithm, and the execution time weight of each configuration file is obtained.

[0073] S104, selecting a configuration file according to the execution time weight to generate a configuration file sequence, and setting a second threshold for the configuration file according to the execution time weight of each configuration file sequence.

[0074] Since the execution time weight can be a weight of time allocated by each configuration file in a time period, the configuration file with the execution time weight not being 0 can be selected to obtain a configuration file sequence, for each configuration file, a product of the execution time weight of the configuration file and a preset reconstruction granularity constant is calculated, and for each physical block memory, a sum value of the product and a current write count of the physical block memory is calculated as a second threshold value of the physical block memory in the configuration file, and the second threshold value is also a second threshold value of the configuration file.

[0075] S105, each configuration file in the configuration file sequence is sequentially run, and when each configuration file is run, if the write count of the physical block memory is greater than the second threshold value, the next configuration file in the configuration file sequence is run, until all the configuration files in the configuration file sequence are run.

[0076] After the configuration file sequence is generated, each configuration file in the configuration file sequence can be sequentially executed, and when each configuration file is executed, the write count of each physical block memory is obtained through a counter on the physical block memory, when the write count of one physical block memory is greater than the second threshold value, the execution of the current configuration file is stopped, and then the next configuration file is executed, and so on, until all the configuration files are executed, and then S103 is returned to regenerate the configuration file sequence.

[0077] The present application selects one configuration file from a preset configuration file set, obtains the write count of each physical block memory, solves the execution time weight of each configuration file according to the write count and the historical write count of the physical block memory, generates a configuration file sequence according to the execution time weight, sets a second threshold value for the configuration file according to the execution time weight of each configuration file sequence, and sequentially runs each configuration file in the configuration file sequence until all the configuration files in the configuration file sequence are run. The execution time weight of each configuration file is solved by dynamically sensing the write count and the historical write count of the physical machine memory, the second threshold value of each configuration file is recalculated according to the execution time weight, when the configuration file in the configuration file sequence is executed and the write count reaches the second threshold value, the execution of the configuration file is ended to execute the next configuration file, the logical block memory is remapped to other physical block memory, the life balance of the physical block memory is realized, and compared with the prior art of generating configuration files offline and executing the configuration files according to the configuration file generation order, the present embodiment dynamically senses the write count and the historical write count of each physical block memory to switch the configuration file to reconstruct the mapping relationship of the logical block memory to the physical block memory, and the life of the physical block memory can be more balanced according to the real write count.

[0078] Embodiment two

[0079] Figure 2 A flowchart of a FPGA reconfiguration method based on dynamic perception life balance provided for the second embodiment of the present application, the embodiment is further optimized on the basis of the first embodiment, as shown in the figure, the FPGA reconfiguration method based on dynamic perception life balance of the embodiment of the present application specifically includes the following: Figure 2

[0080] S201, when detecting a trigger generation profile event, load the physical block memory usage dictionary, the physical block memory usage dictionary includes the write times of each physical block memory, and the remapping times of the logical block memory mapped to the same physical block memory.

[0081] The generation profile event can be memory power-off, that is, when the memory is powered off, the offline generation profile is triggered, of course, the generation profile event can also be a preset interval time, the embodiment does not limit the trigger generation profile event.

[0082] The physical block memory usage dictionary can be a file recording the historical delay record of each physical block memory, such as including the write times of each physical block memory, and the remapping times of the logical block memory mapped to the same physical block memory.

[0083] S202, determine the candidate physical block memory from all physical block memories.

[0084] Among them, the candidate physical block memory can be determined from all physical block memories, the physical block memories are sorted in descending order according to the write times, and the first N physical block memories are determined as the candidate physical block memories. Optionally, in the subsequent layout stage, the physical block memory is selected from the candidate physical block memory. Preferably, in order to ensure the legality of the layout position, the number of candidate physical block memories does not exceed the total number of physical block memories of the memory.

[0085] S203, randomly map each logical block memory to a candidate physical block memory to obtain an initial configuration file.

[0086] Among them, the initial configuration file can be that a candidate physical block memory is randomly selected from all candidate physical block memories for each logical block memory.

[0087] S204, adjust the mapping relationship between the logical memory and the candidate physical block memory in the initial configuration file based on the write times, the remapping times and the simulated annealing algorithm to obtain a final configuration file.

[0088] ​In an optional embodiment, by randomly selecting a logical block memory, remapping the logical block memory to another candidate physical block memory, calculating the cost before remapping based on the write times and the remapping times, and calculating the cost after remapping, when the difference between the cost before remapping and the cost after remapping is less than a preset value, accepting the remapping of the logical block memory to another candidate physical block memory, when the difference between the cost before remapping and the cost after remapping is greater than the preset value, calculating an acceptance probability using the difference and a preset parameter, when the acceptance probability is greater than a preset probability, accepting the remapping of the logical block memory to another candidate physical block memory, determining whether the iteration termination condition is met, if yes, generating a configuration file according to the accepted mapping relationship, otherwise, returning to the step of randomly selecting a logical block memory and remapping the logical block memory to another candidate physical block memory.

[0089] The simulated annealing algorithm can refer to the prior art, which will not be described in detail here. In the present embodiment, the cost before remapping and the cost after remapping are calculated each time the iteration is calculated. The cost includes a first cost and a second cost. The cost before remapping is calculated based on the write times and the remapping times, including:

[0090] The first cost is calculated by the following formula:

[0091]

[0092] Used(BRAM i ) represents the write times of the physical block memory numbered i, and Max_Used(BRAMs) represents the write times of the most used physical block memory among all physical block memories.

[0093] The second cost is calculated by the following formula:

[0094]

[0095] Reuse(BRAM i ,Log j ) represents the remapping times of the logical block memory numbered j mapped to the physical block memory numbered i.

[0096] The cost before remapping can be the sum of the first cost and the second cost before remapping. Similarly, the cost after remapping can be the sum of the first cost and the second cost before remapping. Of course, the sum of the first cost and the second cost can not be calculated, i.e. the cost before remapping includes the first cost and the second cost before remapping, and the cost after remapping includes the first cost and the second cost after remapping. If the cost is the sum of the first cost and the second cost, the difference between the sum is calculated, and the acceptance probability is calculated by the difference as follows:

[0097]

[0098] ΔCost is the cost difference, T is the annealing temperature, the annealing temperature T can be pre-set, and is lowered after each iteration.

[0099] If the cost includes the first cost and the second cost, a first difference value can be calculated by calculating the difference between the first cost before remapping and the first cost after remapping, and a second difference value can be calculated by calculating the difference between the second cost before remapping and the second cost after remapping, if both the first difference value and the second difference value are less than a preset value, the current remapping is directly received to obtain the configuration file, otherwise, the first difference value and the second difference value are respectively substituted into the above-mentioned acceptance probability formula to calculate the first acceptance probability and the second acceptance probability, and then the average value is taken as the final acceptance probability.

[0100] It can be known from the first cost calculation formula that the greater Used(BRAM i ) indicates that the number of times of writing of the physical block memory numbered i is greater, the greater the first cost Cost use , and the higher the cost of mapping the logical block memory to the physical block memory, so that the logical block memory can be avoided from being mapped to the physical block memory with a large number of times of writing, the logical block memory is mapped to the physical block memory with a small number of times of writing as much as possible, that is, when the configuration file is generated, the logical block memory is mapped to the physical block memory with a long service life as much as possible.

[0101] It can be known from the second cost calculation formula that the greater Reuse(BRAM i , Log j ) indicates that the number of times of mapping of the logical block memory numbered j to the physical block memory numbered i is greater, the greater the second cost Cost reuse , and the higher the cost of mapping the logical block memory to the physical block memory, so that the logical block memory can be avoided from being mapped to the physical block memory that has been mapped, the logical block memory is mapped to different physical block memories as much as possible, that is, when the plurality of configuration files are generated, the same logical block memory is mapped to different physical block memories.

[0102] The embodiment adjusts the mapping relationship between the logical memory and the candidate physical block memory in the initial configuration file through the write times of the physical block memory, the remapping times and the simulated annealing algorithm when detecting the trigger generation configuration file event, obtains the final configuration file, realizes the generation of the configuration file through the real write times and the remapping times of the physical block memory, solves the problem that the existing technology generates the configuration file through the random excitation, which leads to the inaccuracy of the random excitation and the real write times and remapping times, and causes the inaccuracy of the final configuration file, and can generate an accurate configuration file, when the configuration file is executed, the mapping relationship between the logical block memory and the physical block memory is reconstructed more accurately and efficiently, so that more effective life balance is realized.

[0103] S205, select a configuration file from a preset configuration file set, the configuration file including the mapping relationship between the logical block memory and the physical block memory.

[0104] S206, in the process that the physical block memory stores data according to the configuration file, obtain the write times of each physical block memory.

[0105] S207, for each physical block memory, calculate the predicted write times by using the historical write times.

[0106] In one example, the write frequency can be calculated according to the historical write times, the write times are calculated as the predicted write times by using the write frequency and the preset period, in another example, the mean value of the historical write times in each preset period can be calculated as the predicted write times, of course, the predicted write times can also be calculated by other methods such as curve trend analysis.

[0107] S208, respectively construct the write times matrix, the predicted write times matrix and the weight matrix by using the write times, the predicted write times of each physical block memory and the execution time weight of each configuration file.

[0108] S209, construct the optimization function by using the write times matrix, the predicted write times matrix and the weight matrix, and the execution time weight in the weight matrix is the variable of the optimization function.

[0109] Wherein, the optimization function can be:

[0110]

[0111] s.t 0≤w≤1 (3)

[0112] The matrix Cur represents the historical write times of the physical block memory, the matrix Con represents the predicted write times of the physical block memory after reconstruction, the matrix w is the weight of the execution time of each configuration file, and Con w represents the write times after the configuration file is executed for a period of time. The configuration file decision module sets different reconstruction triggering thresholds according to the weight w.

[0113] The target of wear leveling is to make the write times of each block memory close, that is, in a balanced state, therefore, the process needs to increase some constraints, limit the value of the weight sequence w to belong to the interval [0:1], then formula (3) can be converted into the expression of formula (4):

[0114]

[0115] s.t 0≤w≤1 (4)

[0116] S210, a quadratic programming algorithm is used to solve the weight matrix that makes the optimization function minimum, to obtain the execution time weight of each configuration file.

[0117] Wherein, the quadratic programming algorithm for solving the weight matrix that makes the optimization function minimum can be to write the matrix [-Con] in formula (4) as A, and the matrix [1-Cur] as b, and formula (4) can be converted into formula (5):

[0118]

[0119] s.t.0≤w≤1 (5)

[0120] And since the square root function is monotonic, and b is a constant term, formula (5) can be abstracted as formula (6) to find a w to minimize the weight matrix.

[0121]

[0122] s.t.0≤w≤1 (6)

[0123] In the case where A and b are known and determined, the w that makes formula (6) minimum can be solved by using existing quadratic programming algorithm, which will not be described here in detail.

[0124] S211, for each configuration file, the product of the execution time weight of the configuration file and the preset reconstruction granularity constant is calculated.

[0125] Wherein, the reconstruction granularity constant can be set to be any number less than the write life of the nonvolatile memory, the smaller the reconstruction granularity constant, the more the reconstruction times, but the better the leveling effect.

[0126] S212, for each physical block memory, calculate the sum value of the product and the current write times of the physical block memory as the second threshold value of the physical block memory in the configuration file.

[0127] The current write times can be the count data of the current counter.

[0128] S213, sequentially run each configuration file in the configuration file sequence, and when running each configuration file, if the write times of the physical block memory are greater than the second threshold value, run the next configuration file in the configuration file sequence until all configuration files in the configuration file sequence are run.

[0129] The application selects a configuration file from a preset configuration file set, obtains the write times of each physical block memory, solves the execution time weight of each configuration file according to the write times and the historical write times of the physical block memory, selects the configuration file according to the execution time weight to generate a configuration file sequence, sets the second threshold value for the configuration file according to the execution time weight of each configuration file sequence, and sequentially runs each configuration file in the configuration file sequence until all configuration files in the configuration file sequence are run. The execution time weight of each configuration file is solved by dynamically sensing the write times and the historical write times of the physical machine memory, the second threshold value of each configuration file is recalculated according to the execution time weight, when the configuration file in the configuration file sequence is executed and the write times reach the second threshold value, the execution of the configuration file is ended to execute the next configuration file, the logical block memory is remapped to other physical block memory, the life balance of the physical block memory is realized, and compared with the prior art, the configuration file is executed according to the configuration file generation sequence after the configuration file is generated offline. The mapping relationship of the logical block memory to the physical block memory is reconstructed by dynamically sensing the write times and the historical write times of each physical block memory to switch the configuration file, which can more evenly balance the life of the physical block memory according to the real write times.

[0130] Embodiment three

[0131] Figure 3 A structure schematic diagram of an FPGA reconstruction device based on dynamic perception life balance is provided for the third embodiment of the application. As shown in the figure, Figure 3 The memory life balance device includes:

[0132] The configuration file selection module 310 is configured to select a configuration file from a preset configuration file set, and the configuration file includes the mapping relationship between the logical block memory and the physical block memory.

[0133] The write times obtaining module 320 is configured to obtain the write times of each physical block memory during the process that the physical block memory stores data according to the configuration file.

[0134] The execution time weight solving module 330 is configured to solve the execution time weight of each configuration file according to the write times and the historical write times of the physical block memory when the write times are greater than a first threshold value.

[0135] The configuration file sequence generating module 340 is configured to generate a configuration file sequence according to the execution time weights of the configuration files, and set a second threshold value for each configuration file in the configuration file sequence according to the execution time weight of the configuration file.

[0136] The configuration file running module 350 is configured to run each configuration file in the configuration file sequence in sequence, and run the next configuration file in the configuration file sequence when the write times of the physical block memory are greater than the second threshold value during the running of each configuration file, until all the configuration files in the configuration file sequence are run.

[0137] Optionally, the FPGA reconstruction device based on dynamic perception life balance further comprises:

[0138] The physical block memory usage dictionary loading module is configured to load a physical block memory usage dictionary when a trigger generating configuration file event is detected before selecting a configuration file from a preset configuration file set, wherein the physical block memory usage dictionary comprises the write times of each physical block memory and the remapping times of the logical block memory mapped to the same physical block memory.

[0139] The candidate physical block memory selecting module is configured to determine candidate physical block memories from all the physical block memories.

[0140] The first mapping relationship establishing module is configured to randomly map each logical block memory to a candidate physical block memory to obtain an initial configuration file.

[0141] The mapping relationship adjusting module is configured to adjust the mapping relationship between the logical block memory and the candidate physical block memory in the initial configuration file based on the write times, the remapping times and the simulated annealing algorithm to obtain a final configuration file.

[0142] Optionally, the candidate physical block memory selecting module comprises:

[0143] The sorting module is configured to sort the physical block memories according to the write times from large to small.

[0144] The determining module is configured to determine the physical block memories ranked in the top N as candidate physical block memories.

[0145] Optionally, the mapping relationship adjusting module comprises:

[0146] The second mapping relationship establishing module is configured to randomly select a logical block memory and remap the logical block memory to another candidate physical block memory.

[0147] The cost calculating module is configured to calculate a cost before remapping based on the write times and the remapping times, and calculate a cost after remapping.

[0148] The first mapping relationship updating module is configured to accept the remapping of the logical block memory to another candidate physical block memory when a difference between the cost before remapping and the cost after remapping is less than a preset value.

[0149] The acceptance probability calculating module is configured to calculate an acceptance probability by using the difference and a preset parameter when the difference between the cost before remapping and the cost after remapping is greater than the preset value.

[0150] The second mapping relationship updating module is configured to accept the remapping of the logical block memory to another candidate physical block memory when the acceptance probability is greater than a preset probability.

[0151] The iteration terminating module is configured to determine whether a terminating iteration condition is met.

[0152] If yes, a configuration file is generated according to the accepted mapping relationship.

[0153] If no, the step of randomly selecting a logical block memory and remapping the logical block memory to another candidate physical block memory is returned.

[0154] Optionally, the cost comprises a first cost and a second cost, and the cost calculating module is specifically configured to:

[0155] The first cost is calculated by the following formula:

[0156]

[0157] Used(BRAM i ) represents the write times of the physical block memory numbered i, and Max_Used(BRAMs) represents the write times of the most frequently used physical block memory among all the physical block memories.

[0158] The second cost is calculated by the following formula:

[0159]

[0160] Reuse(BRAM i ,Log j ) represents the number of times that the logical block memory numbered j is mapped to the physical block memory numbered i.

[0161] Optionally, the execution time weight solving module is specifically configured to:

[0162] For each physical block memory, the historical write number is used to calculate a predicted write number.

[0163] The write number matrix, the predicted write number matrix and the weight matrix are respectively constructed by using the write number, the predicted write number of each physical block memory and the execution time weight of each configuration file.

[0164] The optimization function is constructed by using the write number matrix, the predicted write number matrix and the weight matrix, and the optimization function takes the execution time weight in the weight matrix as a variable.

[0165] The weight matrix that makes the optimization function minimum is solved by using a quadratic programming algorithm, and the execution time weight of each configuration file is obtained.

[0166] Optionally, the configuration file sequence generating module is specifically configured to:

[0167] For each configuration file, the product of the execution time weight of the configuration file and a preset reconstruction granularity constant is calculated.

[0168] For each physical block memory, the sum value of the product and the current write number of the physical block memory is calculated as the second threshold value of the physical block memory in the configuration file.

[0169] The FPGA reconstruction device based on dynamic perception life balance provided by the above-mentioned embodiment can execute the FPGA reconstruction method based on dynamic perception life balance provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method.

[0170] Embodiment four

[0171] Figure 4A structural diagram of an electronic device 40 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application described and / or claimed in this document.

[0172] As shown in Figure 4 The electronic device 40 includes at least one processor 41, and a memory, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., communicatively connected to the at least one processor 41, where the memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes according to the computer programs stored in the read-only memory (ROM) 42 or loaded into the random access memory (RAM) 43 from the storage unit 48. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0173] Various components in the electronic device 40 are connected to the I / O interface 45, including an input unit 46, such as a keyboard, a mouse, etc., an output unit 47, such as various types of displays, speakers, etc., a storage unit 48, such as a magnetic disk, an optical disk, etc., and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0174] The processor 41 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 performs various methods and processes described above, such as the FPGA reconfiguration method based on dynamic perception lifetime balancing.

[0175] In some embodiments, the dynamic perception lifetime balancing based FPGA reconfiguration method can be implemented as a computer program tangibly embodied in a computer readable storage medium, e.g., storage unit 48. In some embodiments, parts or all of the computer program can be loaded and / or installed onto electronic device 40 via, e.g., ROM 42 and / or communication unit 49. When the computer program is loaded onto RAM 43 and executed by processor 41, one or more steps of the dynamic perception lifetime balancing based FPGA reconfiguration method described above can be performed. Alternatively, in other embodiments, processor 41 can be configured to perform the dynamic perception lifetime balancing based FPGA reconfiguration method by way of other any suitable means (e.g., by way of firmware).

[0176] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0177] Computer programs used to implement the dynamic perception lifetime balancing based FPGA reconfiguration method of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program running on the processor implements the functions / operations specified in the flowcharts and / or the block diagrams. The computer program can be executed entirely on a machine, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0178] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0179] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0180] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), blockchain network, and the Internet.

[0181] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network.

[0182] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0183] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall fall within the protection scope of the present application.

[0184] Example Five

[0185] The embodiment provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the memory life balancing method according to any of the embodiments of the present application.

[0186] From the above description of the embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and necessary universal hardware, and of course, can also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a floppy disk, a read-only memory (ROM), a random access memory (RAM), a FLASH memory, a hard disk, or an optical disc, and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in various embodiments of the present application.

[0187] Note that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments, and substitutions can be made without departing from the protection scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A method for FPGA reconfiguration based on dynamic perception lifetime balancing, characterized in that, A method for life balance of memory, comprising: selecting a configuration file from a preset configuration file set, the configuration file comprising a mapping relationship between logical block memory and physical block memory; acquiring a write frequency of each of the physical block memory in a process of storing data in the physical block memory according to the configuration file; when the write frequency is greater than a first threshold, solving an execution time weight of each configuration file according to the write frequency and a historical write frequency of the physical block memory; wherein the execution time weight is a weight of an execution time allocated to each configuration file in a preset time; generating a configuration file sequence according to the execution time weight of each configuration file sequence, and setting a second threshold for each configuration file according to the execution time weight of each configuration file sequence; sequentially running each configuration file in the configuration file sequence, and when running each configuration file, if the write frequency of the physical block memory is greater than the second threshold, running a next configuration file in the configuration file sequence, until all configuration files in the configuration file sequence are run.

2. The FPGA reconfiguration method based on dynamic perception life balance according to claim 1, characterized in that, Before selecting a configuration file from a preset configuration file set, further comprising: when a configuration file generation event is detected, loading a physical block memory usage dictionary, the physical block memory usage dictionary comprising a write frequency of each of the physical block memory and a remapping frequency of logical block memory mapped to the same physical block memory; determining candidate physical block memory from all physical block memory; randomly mapping each logical block memory to a candidate physical block memory to obtain an initial configuration file; adjusting a mapping relationship between logical memory and candidate physical block memory in the initial configuration file based on the write frequency, the remapping frequency and a simulated annealing algorithm to obtain a final configuration file.

3. The FPGA reconfiguration method based on dynamic perception lifetime balancing according to claim 2, characterized in that, The determining candidate physical block memory from all physical block memory comprises: sorting the physical block memory in descending order of the write frequency; determining the first N physical block memory in the sorting as candidate physical block memory.

4. The FPGA reconfiguration method based on dynamic perception lifetime balancing according to claim 2, wherein, The adjusting a mapping relationship between logical memory and candidate physical block memory in the initial configuration file based on the write frequency, the remapping frequency and a simulated annealing algorithm to obtain a final configuration file comprises: randomly selecting a logical block memory and remapping the logical block memory to another candidate physical block memory; calculating a cost before remapping and a cost after remapping based on the write frequency and the remapping frequency; when a difference between the cost before remapping and the cost after remapping is less than a preset value, accepting the remapping of the logical block memory to another candidate physical block memory; when the difference between the cost before remapping and the cost after remapping is greater than a preset value, calculating an acceptance probability using the difference and a preset parameter; when the acceptance probability is greater than a preset probability, accepting the remapping of the logical block memory to another candidate physical block memory; judging whether a termination iteration condition is met; when yes, generating a configuration file according to the accepted mapping relationship; If not, return to randomly select a logical block memory, remap the logical block memory to another candidate physical block memory.

5. The FPGA reconfiguration method based on dynamic perception lifetime balancing according to claim 4, characterized in that, The cost includes a first cost and a second cost, and the cost before remapping is calculated based on the write number and the remapping number, including: The first cost is calculated by the following formula: ； a number of writes to a physical block memory numbered i, a number of writes to a physical block memory that is most used among all physical block memories; The second cost is calculated by the following formula: ； The number of remappings of a logical block memory denoted by the number j to a physical block memory denoted by the number i.

6. The FPGA reconfiguration method based on dynamic perception lifetime balancing according to any one of claims 1-5, characterized in that, When the write number is greater than a first threshold, the execution time weight of each configuration file is solved according to the write number and the historical write number of the physical block memory, including: For each physical block memory, the predicted write number is calculated using the historical write number; The write number matrix, the predicted write number matrix and the weight matrix are respectively constructed using the write number, the predicted write number of each physical block memory and the execution time weight of each configuration file; The optimization function is constructed using the write number matrix, the predicted write number matrix and the weight matrix, and the optimization function takes the execution time weight in the weight matrix as a variable; The weight matrix that makes the optimization function minimum is solved using a quadratic programming algorithm, and the execution time weight of each configuration file is obtained.

7. The FPGA reconfiguration method based on dynamic perception lifetime balancing according to any one of claims 1-5, characterized in that, The second threshold of each configuration file is set according to the execution time weight of each configuration file sequence, including: For each configuration file, the product of the execution time weight of the configuration file and a preset reconstruction granularity constant is calculated; For each physical block memory, the sum value of the product and the current write number of the physical block memory is calculated as the second threshold of the physical block memory in the configuration file.

8. An FPGA reconfiguration device based on dynamic perception lifetime balancing, comprising: Applied to chip wear leveling, including: A configuration file selection module is configured to select a configuration file from a preset configuration file set, the configuration file including a mapping relationship between a logical block memory and a physical block memory; A write number acquisition module is configured to acquire a write number of each physical block memory in a process of storing data in the physical block memory according to the configuration file; An execution time weight solving module is configured to solve an execution time weight of each configuration file according to the write number and a historical write number of the physical block memory when the write number is greater than a first threshold, the execution time weight being a weight of an execution time allocated by each configuration file within a preset time; A configuration file sequence generation module is configured to select a configuration file to generate a configuration file sequence according to the execution time weight, and set a second threshold of each configuration file according to an execution time weight of each configuration file sequence; A configuration file running module is configured to sequentially run each configuration file in the configuration file sequence, and run a next configuration file in the configuration file sequence when a write number of the physical block memory is greater than the second threshold during running each configuration file, until all configuration files in the configuration file sequence are run.

9. An electronic device, comprising: The electronic device includes: at least one processor; and a memory connected in communication with the at least one processor; wherein The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the FPGA reconfiguration method based on dynamic perception life balance according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to perform the FPGA reconfiguration method based on dynamic perception life balance of the memory according to any one of claims 1-7 when executed.

Images