Chip routing system and method based on generative deep learning

Abstract

A chip wiring system and method based on generative deep learning, comprising: a data preprocessing module, a basic condition generative adversarial network module, a multi-scale condition generative adversarial network module, a condition generative adversarial network parameter updating module, a post-processing module, a deep latent variable learning network module and a deep latent variable learning network parameter updating module, the application designs a new intelligent wiring solver through a condition generative adversarial model method, through a common data driving mechanism of artificial intelligence, in a pre-training and supervision training mode, the algorithm has the ability to generalize to a new netlist diagram; the algorithm can be used for wiring of a large-size chip by adopting a multi-scale model, so that more accurate results can be generated, a large-size chip and a net can be used, and the results of a chip wiring solving network of a smaller size can be directly migrated to a larger size chip, therefore, the application has stronger plasticity and expandability, and can be suitable for a large-size chip by spending less fine-tuning training.

Description

Technical Field

[0001] This invention relates to a technology in the field of integrated circuit chip design, specifically a chip routing system and method based on generative deep learning. Background Technology

[0002] Electronic design automation (EDA) is an upstream industry in the integrated circuit sector, aiming to provide automated solutions for complex circuit design. With the rapid expansion of chip scale, the algorithmic complexity for solving chip routing problems also increases rapidly with the increasing number of netlists, the size of individual netlists, the size of the routing mesh, and the time spent calculating remaining routing resources. Current algorithms for solving routing problems are typically based on traditional algorithms such as netlist decomposition, pattern routing, maze routing, and negotiation-based decomposition and rerouting. These algorithms have bottlenecks in terms of time efficiency and the design complexity of specific routing problems, and cannot effectively utilize the computing power of rapidly developing processors and the resulting innovations in AI technology. In recent years, with continuous breakthroughs in machine learning, more and more researchers have begun to try using machine learning techniques to solve scientific and industrial problems, including chip routing problems. Researchers use neural networks to extract and evaluate data path patterns from high-dimensional data such as netlist structure, initial placement instructions, and relative areas to predict routing results, thereby helping traditional placement algorithms obtain better solutions.

[0003] Conditional Generative Adversarial Networks (cGANs) are an improvement on Generative Adversarial Networks (GANs). They achieve conditional generation by adding extra conditional information to the generator G and discriminator D of the original GAN. This extra conditional information can be class labels or other auxiliary information. The goal of cGANs is to generate results that satisfy the true distribution of the data through the generator G based on known conditional information, and to make it impossible for the discriminator D to distinguish between the result generated by the generator G and the true result based on the given conditional information. Summary of the Invention

[0004] This invention addresses the limitations of existing learning-based methods in handling intelligent chip routing problems involving large-sized chips, massive netlists, and single netlists with multiple pins. It proposes a chip routing system and method based on generative deep learning. A novel intelligent routing solver is designed using a conditional generative adversarial model. Through data-driven mechanisms common in artificial intelligence, pre-training combined with supervised training enables the algorithm to generalize to new netlist graphs. Employing a multi-scale model allows the algorithm to route large-sized chips, generating more accurate results. It can be used with larger chips and nets and can directly transfer the routing solution results from smaller chips to larger chips. Therefore, this invention has greater flexibility and scalability, and can be applied to large-sized chips with relatively little fine-tuning.

[0005] This invention is achieved through the following technical solution:

[0006] This invention relates to a chip routing system based on generative deep learning, comprising: a data preprocessing module, a basic conditional generative adversarial network (GAN) module, a multi-scale conditional GAN ​​module, a conditional GAN ​​parameter update module, a post-processing module, a deep latent variable learning network (DLLM) module, and a DLLM parameter update module. The data preprocessing module reads and parses GR format files, converts layout information and routing resources into image data, and generates ground truth values ​​for the supervised training part. The basic conditional GAN ​​module performs generative routing processing based on the pin position information in each input net and the grid routing capacity information after chip partitioning, obtaining the result of generative routing for each net. The multi-scale conditional GAN ​​module performs generative routing processing based on the pin position information in each input net and the grid routing capacity information after chip partitioning, obtaining the result of generative routing for each net. The process involves several steps: First, the Generative Adversarial Network (GAN) parameter update module performs generative routing based on the pin positions in each input net and the grid routing capacity of the chip. Second, the post-processing module uses a greedy maze routing algorithm to obtain the final solution when the generated routing does not form a path, removing redundant points to achieve the optimized routing result. Third, the Deep Latent Variable Learning (DLL) network module performs reparameterized latent variable sampling and generative routing based on the pin positions in each previously unrouted net and the grid routing capacity of the chip, resulting in a routing result adjusted according to the latent variables. Finally, the LDL parameter update module performs error calculation and backpropagation training based on the evaluation metrics of the adjusted routing result, yielding the updated LDL parameters.

[0007] This invention relates to a chip wiring method based on generative deep learning of the above-described system, comprising:

[0008] Step 1) Receive the chip layout data file describing the to be routed through the data preprocessing module, and extract the routing resources and all the nets to be routed after preprocessing;

[0009] The preprocessing mentioned refers to the following: In the smart chip routing problem, the condition information is defined as the positions of all pins of the network to be routed and the current status of the chip routing resources. Specifically, the chip is divided into regions (Gcells) of uniform size according to a fixed length and width. Physically adjacent Gcells share a common edge, and the number of lines that can pass through each common edge is limited. Then, each Gcell is regarded as a grid point (vertex), and the common edge of adjacent grid points is regarded as an edge. The weight of this edge is defined as the number of lines that can still be accommodated. Thus, the entire chip is modeled as a weighted mesh.

[0010] Preferably, all grid points containing pins in a mesh are assigned a value of 1, grid points without pins are assigned a value of 0, and edges with weights greater than 0 are assigned a value of 1, while edges with weights equal to 0 are assigned a value of 0. The matrix composed of the values ​​of all pins is encoded as the R channel of the image, and the matrices composed of the weights of the horizontal and vertical edges are encoded as the G and B channels of the image, respectively.

[0011] Step 2) Construct a mesh to store the current wiring resources, select a mesh to be wired, convert it into a tensor (convert it into an image during training, and skip this process during solving), and then obtain the probability of each point belonging to the final solution by generating the network;

[0012] Step 3) Keep the points with a probability higher than 50% and solve whether the network is connected. If it is not connected, go to step 4; otherwise, go to step 5.

[0013] Step 4) After obtaining the connected routes by running the greedy maze wiring algorithm, proceed to step 5;

[0014] Step 5) Return to step 2 to read the new nets to be routed. Once all nets have been processed, the routing scheme for the current chip layout is obtained. Attached Figure Description

[0015] Figure 1 This is a flowchart of an example implementation. Detailed Implementation

[0016] This embodiment relates to a chip routing system based on generative deep learning, including: a data preprocessing module, a basic conditional generative adversarial network (GAN) module, a multi-scale conditional GAN ​​module, a conditional GAN ​​parameter update module, a post-processing module, a deep latent variable learning network (DLMU) module, and a DLMU parameter update module. Specifically: the data preprocessing module reads and parses GR format files, converts layout information and routing resources into image data, and generates ground truth values ​​for the supervised training part; the basic conditional GAN ​​module performs generative routing processing based on the pin position information in each input net and the grid routing capacity information after chip partitioning, obtaining the result of generative routing for each net; the multi-scale conditional GAN ​​module performs generative routing processing based on the pin position information in each input net and the grid routing capacity information after chip partitioning, obtaining the result of generative routing for each net. The process involves several steps: First, the Generative Adversarial Network (GAN) parameter update module performs generative routing based on the pin positions in each input net and the grid routing capacity of the chip. Second, the post-processing module uses a greedy maze routing algorithm to obtain the final solution when the generated routing does not form a path, removing redundant points to achieve the optimized routing result. Third, the Deep Latent Variable Learning (DLL) network module performs reparameterized latent variable sampling and generative routing based on the pin positions in each previously unrouted net and the grid routing capacity of the chip, resulting in a routing result adjusted according to the latent variables. Finally, the LDL parameter update module performs error calculation and backpropagation training based on the evaluation metrics of the adjusted routing result, yielding the updated LDL parameters.

[0017] The ground truth of the supervised training part is converted into image data based on layout information and routing resources as input, and the output result is obtained through, but not limited to, the NCTU-GR 2.0 chip router.

[0018] The NCTU-GR 2.0 chip router is described in Liu, Wen-Hao, et al. "NCTU-GR 2.0: Multithreaded collision-aware global routing with bounded-length mazerouting." IEEE Transactions on computer-aided design of integrated circuits and systems 32.5(2013):709-722.

[0019] Preferably, the data preprocessing module stores the parsed data for easy reuse to avoid the need to convert the format every time the algorithm is run.

[0020] The data preprocessing module includes: a data reading unit, a chip mesh initialization unit, a network information initialization unit, and a tensor conversion unit. Specifically: the data reading unit reads and processes the input chip mesh attributes and the information of the networks to be routed, obtaining a formatted input result; the chip mesh initialization unit performs chip mesh modeling processing based on the formatted chip mesh attribute information, obtaining a mathematical model result of the chip mesh; the network information initialization unit performs merging processing based on the formatted network information, obtaining a structured pin result for each network requiring routing; and the tensor conversion unit performs tensor generation processing based on the chip mesh mathematical model information and the pin information of the networks to be routed, obtaining a tensor result based on the current chip mesh information and the networks to be routed.

[0021] The basic conditional generative adversarial network module includes a generator and a discriminator. The discriminator consists of multiple sub-discriminators. Both the generator and the sub-discriminators are composed of convolutional neural networks. The generator first extracts the feature map of the chip-divided image through an augmentation and convolutional neural network. After passing through multiple residual network (ResNet) devices, a high-dimensional feature map is extracted. Then, after multi-layer deconvolution processing, the probability of each point belonging to the final line is obtained through an activation function as the generation result. The first sub-discriminator judges the connectivity, i.e., the correctness, of the generation result. The second sub-discriminator judges the line length of the generation result. The third sub-discriminator judges the overall integrity of the generation result.

[0022] The chip partitioned scale image refers to: obtaining the remaining wiring resources of the mesh at the current moment and the pin positions of the current mesh, where 1 indicates a position with pins or an edge that can still accommodate lines.

[0023] The multi-scale conditional generative adversarial network module includes: a pre-feature extraction unit, a downsampling feature extraction unit, and a wiring diagram generation unit. Specifically: the pre-feature extraction unit performs convolutional network feature extraction processing based on the input tensor information to obtain the basic multi-channel feature information result; the downsampling feature extraction unit performs downsampling and convolutional network feature extraction processing based on the input tensor information to obtain the multi-channel feature information result from a global perspective; and the wiring diagram generation unit performs bitwise addition and generative network processing based on the basic multi-channel feature information obtained from the above two units and the multi-channel feature information from a global perspective to obtain the generated wiring diagram result.

[0024] The multi-scale conditional generative adversarial network module extracts feature maps from the larger-scale chip mesh through expansion and convolutional neural networks, using them as part of the features. Simultaneously, it downsamples the original image to adapt its size to the basic conditional generative adversarial network, which then extracts global feature maps. The two extracted feature maps are added together to fuse the information. The fused features are then subjected to subsequent feature processing, and finally deconvolution is performed to obtain the generated result. The generator output and the ground truth are concatenated with the conditional information and then input into the discriminator to obtain the discrimination result.

[0025] The conditional generative adversarial network parameter update module includes a discriminator parameter update unit and a generator parameter update unit. The discriminator parameter update unit performs error calculation and backpropagation learning based on the discriminator's output discrimination result and the corresponding input truth information to obtain updated discriminator network parameter results. The generator parameter update unit performs error calculation and backpropagation learning based on the output wiring diagram and truth wiring diagram, as well as the error information transmitted by the discriminator between the output and truth values, to obtain updated generator network parameter results.

[0026] Since the routing results for each network are not unique, the generator parameter update unit adds a reconstruction loss based on the ground truth to the generator's original loss function during initial training. This ensures that the generated results from the initially trained network are closer to the ground truth, without considering the diversity of the network. Therefore, no latent variables are introduced at this stage. The reconstruction loss consists of a weighted sum of mean squared error and Focal error. This is to prevent the final generated result from being a blank line, because the points included in the routing line only occupy a very small portion of the entire grid. Even if the generated result does not include any grid points, the loss is still very small. The error calculation for this unit is as follows: The error calculation for the corresponding discriminator parameter update unit is as follows: Where: α is the weight of the mean squared error, β is the weight of the Focal Loss, θ represents the parameters of the generator network, and π represents the parameters of the discriminator network.

[0027] The greedy maze routing algorithm described herein employs, but is not limited to, the techniques described in Soukup, JIRI, "Fast mazerouter." Design Automation Conference. IEEE Computer Society, 1978.

[0028] The deep latent variable learning network module includes a parameter unit, a latent variable sampling unit, and a latent variable feature map mapping unit. Specifically: the parameter unit performs convolution and fully connected network mapping processing based on the input tensor information to obtain the mean and standard deviation of a Gaussian distribution; the latent variable sampling unit performs standard Gaussian distribution sampling processing based on random seed information to obtain the sampled latent variable results; and the latent variable feature map mapping unit performs latent variable reparameterization and latent variable-to-feature map mapping processing based on the parameter unit and the latent variable sampling information to obtain conditional latent variable feature map results.

[0029] like Figure 1 As shown, this embodiment uses a generative deep learning-based chip routing method based on the aforementioned system. By acquiring the remaining routing resources of the grid at the current moment and the pin positions of the current grid, the grid size, i.e., the image of the chip after partitioning, is obtained. The image is input into the network and processed to obtain scalar values, i.e., the standard deviation and mean of the latent variables. Basic features are sampled from a standard Gaussian distribution, multiplied by the standard deviation and added to the mean to obtain the required latent variables. The latent variables are deconvolved to obtain a feature map, which is then connected to the feature map output by the basic conditional generative adversarial network module. Finally, a deconvolution is performed to obtain the routing result.

[0030] The deep latent variable learning network parameter update module: The latent variable learning network uses the previously learned discriminator's discrimination result as an evaluation, and updates the network with the goal of optimizing this evaluation. The parameter update formula is as follows: Where λ represents the parameters of the deep latent variable network.

[0031] Through specific practical experiments, under the specific environment settings of ISPD98 benchmarks, and by starting / running the above device / method with the trained network parameters, the experimental data that can be obtained are:

[0032]

[0033]

[0034] Through specific practical experiments, under the specific environment settings of the test set of 200,000 samples obtained from the ISPD08 benchmarks, and running the above system with the trained network parameters, the accuracy rate was 79.5%, and the ratio of the line length to the ground truth was 1.007.

[0035] In practical implementation, the generator and discriminator in the basic conditional generative adversarial network module use residual networks composed of convolutional neural networks to generate wiring results and discriminate the results. The design of these two networks is not unique; for example, more complex, deeper residual networks or Transformer network structures can be used to replace the original network skeletons in the generator and discriminator. When using a wiring network based on a U-Net skeleton, an accuracy of 73.1% and a ground truth line length ratio of 1.022 can be achieved. The number of discriminators in the basic conditional generative adversarial network module can be adjusted for different constraints. When the number of discriminators is reduced to one, an accuracy of 62.3% and a ground truth line length ratio of 1.017 can be obtained. The number of downsampling and global feature extraction networks used in the multi-scale conditional generative adversarial network module can be adjusted, and its residual network skeleton can also be replaced with a more complex and deeper network, such as a Transformer network structure. Specifically, the number of downsampling networks can be increased to two. The algorithm for connecting disconnected lines in the post-processing module can be replaced with the A* routing algorithm or the Multi-source Multi-sink Maze routing algorithm. The network implementing latent variable learning in the deep latent variable learning network module can be replaced with networks such as Transformer.

[0036] Compared with existing deep learning-based routing methods, this system uses a conditional generative adversarial model to solve the chip routing problem. It uses multiple discriminators to make joint judgments and feeds back the judgment results to update the generative model. It also combines pre-training, supervised training and unsupervised training. The pre-training and supervised training significantly improve the routing efficiency. Experiments were conducted on actual chip benchmarks rather than on randomly generated simple routing problems, and the success rate and wire length of the final routing were significantly improved.

[0037] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A generative deep learning based chip routing system, characterized by, include: The system comprises a data preprocessing module, a basic conditional generative adversarial network (GAN) module, a multi-scale conditional GAN ​​module, a conditional GAN ​​parameter update module, a post-processing module, a deep latent variable learning (DLL) module, and a DDL parameter update module. Specifically: the data preprocessing module reads and parses GR format files, converts layout information and wiring resources into image data, and generates ground truth values ​​for the supervised training part; the basic conditional GAN ​​module performs generative routing based on the pin position information of each input net and the grid wiring capacity information after chip partitioning, obtaining the result of generative routing for each net; the multi-scale conditional GAN ​​module performs generative routing based on the pin position information of each input net and the grid wiring capacity information after chip partitioning, obtaining the result of generative routing for each net; and the conditional... The Generative Adversarial Network (GAN) parameter update module performs generative routing based on the pin position information of each input network and the grid routing capacity information after chip partitioning, obtaining the result of generative routing for each network. The post-processing module obtains the final solution using a greedy maze routing algorithm when the generated routing results do not form a path, and removes redundant points in the route to obtain the optimized routing result. The Deep Latent Variable Learning (DLVL) module performs reparameterized latent variable sampling and generative routing based on the pin position information of each previously unrouted network and the grid routing capacity information after chip partitioning, obtaining the routing result adjusted according to the latent variables. The DLVL parameter update module performs error calculation and backpropagation training based on the evaluation index information of the routing result adjusted by the latent variables, obtaining the updated latent variable learning network parameter results.

2. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The data preprocessing module includes: a data reading unit, a chip mesh initialization unit, a network information initialization unit, and a tensor conversion unit. Specifically: the data reading unit reads and processes the input chip mesh attributes and the information of the networks to be routed, obtaining a formatted input result; the chip mesh initialization unit performs chip mesh modeling processing based on the formatted chip mesh attribute information, obtaining a mathematical model result of the chip mesh; the network information initialization unit performs merging processing based on the formatted network information, obtaining a structured pin result for each network requiring routing; and the tensor conversion unit performs tensor generation processing based on the chip mesh mathematical model information and the pin information of the networks to be routed, obtaining a tensor result based on the current chip mesh information and the networks to be routed.

3. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The basic conditional generative adversarial network module includes a generator and a discriminator. The discriminator consists of multiple sub-discriminators. Both the generator and the sub-discriminators are composed of convolutional neural networks. The generator first extracts the feature map of the chip-divided image through an augmentation and convolutional neural network. After passing through multiple residual network (ResNet) devices, a high-dimensional feature map is extracted. Then, after multi-layer deconvolution processing, the probability of each point belonging to the final line is obtained through an activation function as the generation result. The first sub-discriminator judges the connectivity, i.e., the correctness, of the generation result. The second sub-discriminator judges the line length of the generation result. The third sub-discriminator judges the overall integrity of the generation result. The chip-divided scale image refers to: assigning a value of 1 to all grid points containing pins in a grid, assigning a value of 0 to grid points where no pins exist, and assigning a value of 1 to edges with a weight greater than 0, i.e., 1 indicates a pin location or an edge that can still accommodate a line; assigning a value of 0 to edges with a weight of 0; encoding the matrix composed of the values ​​of all pins as the R channel of the image, and encoding the matrices composed of the weights of the horizontal and vertical edges as the G and B channels of the image, respectively.

4. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The multi-scale conditional generative adversarial network module includes: a pre-feature extraction unit, a downsampling feature extraction unit, and a wiring diagram generation unit. Specifically: the pre-feature extraction unit performs convolutional network feature extraction processing based on the input tensor information to obtain the basic multi-channel feature information result; the downsampling feature extraction unit performs downsampling and convolutional network feature extraction processing based on the input tensor information to obtain the multi-channel feature information result from a global perspective; and the wiring diagram generation unit performs bitwise addition and generative network processing based on the basic multi-channel feature information obtained from the above two units and the multi-channel feature information from a global perspective to obtain the generated wiring diagram result.

5. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The multi-scale conditional generative adversarial network module extracts feature maps from the larger-scale chip mesh through expansion and convolutional neural networks, using them as part of the features. Simultaneously, it downsamples the original image to adapt its size to the basic conditional generative adversarial network, which then extracts global feature maps. The two extracted feature maps are added together to fuse the information. The fused features are then subjected to subsequent feature processing, and finally deconvolution is performed to obtain the generated result. The generator output and the ground truth are concatenated with the conditional information and then input into the discriminator to obtain the discrimination result.

6. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The conditional generative adversarial network parameter update module includes a discriminator parameter update unit and a generator parameter update unit. The discriminator parameter update unit performs error calculation and backpropagation learning based on the discriminator's output discrimination result and the corresponding input truth information to obtain updated discriminator network parameter results. The generator parameter update unit performs error calculation and backpropagation learning based on the output wiring diagram and truth wiring diagram, as well as the error information transmitted by the discriminator between the output and truth values, to obtain updated generator network parameter results.

7. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The generator parameter update unit, during initial training, adds a reconstruction loss of the generated result to the ground truth value based on the generator's original loss function. This makes the generated result of the initially trained network closer to the ground truth value, without considering its diversity. Therefore, no latent variables are introduced at this stage. The error calculation for this unit is as follows: The error calculation for the corresponding discriminator parameter update unit is as follows: Where: α is the weight of the mean squared error, β is the weight of the Focal Loss, θ represents the parameters of the generator network, and π represents the parameters of the discriminator network.

8. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The deep latent variable learning network module includes a parameter unit, a latent variable sampling unit, and a latent variable feature map mapping unit. Specifically: the parameter unit performs convolution and fully connected network mapping processing based on the input tensor information to obtain the mean and standard deviation of a Gaussian distribution; the latent variable sampling unit performs standard Gaussian distribution sampling processing based on random seed information to obtain the sampled latent variable results; and the latent variable feature map mapping unit performs latent variable reparameterization and latent variable-to-feature map mapping processing based on the parameter unit and the latent variable sampling information to obtain conditional latent variable feature map results.

9. The chip wiring system based on generative deep learning according to claim 1, characterized in that, The deep latent variable learning network parameter update module uses the previously learned discriminator's discrimination result as an evaluation, and updates the network with the goal of optimizing this evaluation. The parameter update formula is as follows: Where λ represents the parameters of the deep latent variable network.

10. A chip routing method based on generative deep learning according to the chip routing system based on generative deep learning as described in claims 1-9, characterized in that, include: Step 1) Receive the chip layout data file describing the to be routed through the data preprocessing module, and extract the routing resources and all the nets to be routed after preprocessing; Step 2) Construct a mesh to store the current wiring resources, select a mesh to be wired, convert it into a tensor, and obtain the probability of each point belonging to the final solution by generating the network; Step 3) Keep the points with a probability higher than 50% and solve whether the network is connected. If it is not connected, go to step 4; otherwise, go to step 5. Step 4) After obtaining the connected routes by running the greedy maze wiring algorithm, proceed to step 5; Step 5) Return to step 2 to read the new nets to be routed. Once all nets have been processed, the routing scheme for the current chip layout is obtained.

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