Fan-out packaging unit for PoP packaging and manufacturing method thereof

Abstract

The present invention provides a fan-out package unit for PoP packaging and a manufacturing method thereof. The manufacturing method includes: forming a first redistribution layer; forming a hybrid bonding structure between a first main surface of the first redistribution layer and a semiconductor chip to electrically couple the semiconductor chip to the first main surface of the first redistribution layer respectively; forming a molding layer on the first main surface of the first redistribution layer to form a package layer, the molding layer covering the semiconductor chip; forming a second redistribution layer on a second main surface of the first redistribution layer, the second redistribution layer including a second metal wiring layer exposed on a first main surface of the second redistribution layer, the second metal wiring layer being electrically connected to the second main surface of the first redistribution layer. The formed fan-out package unit uses a first redistribution layer made of all-inorganic materials to replace the TSV interposer, reducing the cost of package manufacturing and optimizing the package volume.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor packaging, and relates to a fan-out packaging unit and a manufacturing method thereof. Background Art

[0002] With the increasing requirements for packaging in mobile consumer electronic products such as mobile phones, personal digital assistants (PDAs), digital cameras, etc. for function integration, large storage space, miniaturization, and high reliability, how to integrate multiple different types of high-density chips together to form a powerful system or subsystem with small volume and low power consumption has become a major challenge in the field of advanced semiconductor chip packaging.

[0003] System In Package (SIP) technology, as an emerging heterogeneous integration technology, can integrate multiple active devices with different functions, passive devices, micro-electro-mechanical systems (MEMS) and / or other components such as optical elements into a single package body, thereby forming a system or subsystem that can provide multiple functions, and has become the packaging form of more and more chips. Currently, chips with different performances prepared by the front-end process (Front End of Line, FEOL) are usually respectively bonded to a TSV interposer, and the ultra-fine pins of the chips are led out and effectively interconnected through the TSV interposer to form a functional module or system. However, the cost of this technology is relatively high, which greatly limits its application scope.

[0004] In addition, with the increasing requirements for packaging components and functions, the existing system-level packaging structure will occupy an increasing area and thickness, which is not conducive to improving the integration level. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a fan-out packaging unit for PoP packaging and a manufacturing method thereof, which are used to solve the problems that the existing system-level packaging structure faces difficulties in reducing the occupied space of the package body, improving the I / O density, and having too high production costs in realizing high-density and miniaturized packaging.

[0006] To achieve the above object and other related objects, the present invention provides a manufacturing method of a fan-out packaging unit for PoP packaging, including the following steps:

[0007] Provide a support substrate, and form a first redistribution layer on the support substrate. The first redistribution layer has a first main surface and a second main surface arranged oppositely. The step of forming the first redistribution layer includes: forming a patterned first inorganic dielectric layer, and forming a first metal wiring layer;

[0008] A hybrid bonding structure is formed between the first main surface of the first redistribution layer and the semiconductor chip to electrically couple the semiconductor chip to the first main surface of the first redistribution layer respectively. The hybrid bonding structure includes a first bonding layer formed on the first main surface of the first redistribution layer;

[0009] A molding layer is formed on the first main surface of the first redistribution layer to form a package layer, and the molding layer covers the semiconductor chip;

[0010] A second redistribution layer is formed on the second main surface of the first redistribution layer. The second redistribution layer has a first main surface and a second main surface arranged oppositely. The second redistribution layer includes a second metal wiring layer exposed on the first main surface of the second redistribution layer, and the second metal wiring layer is electrically connected to the second main surface of the first redistribution layer.

[0011] Optionally, the following steps are further included: repeating the steps of forming the patterned first inorganic dielectric layer and forming the first metal wiring layer at least once.

[0012] Optionally, the step of removing the support substrate includes: thinning the support substrate by a mechanical grinding process, and then removing the remaining support substrate by a chemical mechanical polishing process, wherein the support substrate is a silicon-based substrate.

[0013] Optionally, the step of forming the first bonding layer on the first main surface of the first redistribution layer includes:

[0014] Forming a first passivation layer on the first main surface of the first redistribution layer;

[0015] Forming an opening in the first passivation layer by a photolithography process and an etching process, and plating a metal in the opening to form a first pad.

[0016] Optionally, the material of the first inorganic dielectric layer includes one of silicon nitride and silicon oxynitride, and the material of the first metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0017] Optionally, the step of forming the second redistribution layer further includes:

[0018] Forming an opening exposing the second metal wiring on the second main surface of the second redistribution layer;

[0019] Forming an under-bump metal layer on the opening;

[0020] Forming solder balls in the opening by ball placement and reflow.

[0021] The present invention also provides a fan-out package unit for PoP package, including:

[0022] A first redistribution layer having a first major surface and a second major surface disposed opposite to each other. A first bonding layer is disposed on the first major surface of the first redistribution layer. The first redistribution layer includes a first inorganic dielectric layer and a first metal wiring layer stacked in a vertical direction;

[0023] A hybrid bonding structure is located on the first major surface of the first redistribution layer and is configured to electrically couple a semiconductor chip to the first major surface of the first redistribution layer to achieve interconnection between the semiconductor chips through the first redistribution layer. The semiconductor chip is covered with a molding layer to form a package layer;

[0024] A second redistribution layer having a first major surface and a second major surface disposed opposite to each other. The second redistribution layer includes a second metal wiring layer exposed on the first major surface of the second redistribution layer. The second metal wiring layer is electrically connected to the second major surface of the first redistribution layer to electrically lead out the semiconductor chip and the first redistribution layer.

[0025] Optionally, the conductive interconnection includes a solder ball array disposed on the second major surface of the second redistribution layer. Each solder ball is disposed on the under-bump metal layer and is used to achieve conductive interconnection with an external chip or package unit.

[0026] Optionally, the hybrid bonding structure is configured to directly bond with a second bonding layer disposed on the surface of the semiconductor chip through the first bonding layer at the interface between the two. The formed bonding interface has an interconnection pitch of less than 10 microns.

[0027] Optionally, the semiconductor chip includes active devices and passive devices, and the active devices and the passive devices are arranged side by side.

[0028] The present invention provides a PoP package structure, including: the fan-out package unit according to the foregoing, and the fan-out package units are stacked on a package substrate.

[0029] As described above, the fan-out package unit for PoP package and its manufacturing method of the present invention have the following beneficial effects:

[0030] In the fan-out package unit for PoP package of the present invention, a hybrid bonding structure is used to perform solderless bonding between the first redistribution layer and the semiconductor chip, avoiding cracks of solder at the interface between the two, improving the reliability of the interconnection, realizing a high-performance system-level fan-out package unit, and also being beneficial to reducing the pitch between pins, thereby increasing the density of I / O ports and being beneficial to the miniaturization of the package structure;

[0031] In the fan-out package unit of the present invention, heterogeneous integration and interconnection of multiple chips can be achieved without using a TSV interposer, reducing the cost of package manufacturing. In addition, a second redistribution layer is used to replace the package substrate, and is electrically coupled to an external chip or package unit through conductive interconnections to implement an integrated solution for stacked packaging.

[0032] In the manufacturing method of the fan-out package unit of the present invention, by selecting an inorganic dielectric as the insulating material of the first redistribution layer, the line pitch in the first redistribution layer is reduced to less than 1 μm, and a hybrid bond is formed at the interface between the first redistribution layer and the semiconductor chip, avoiding the formation of an interface between organic and inorganic materials, improving the process integration of package manufacturing, and optimizing the package volume. Brief Description of the Drawings

[0033] Figure 1 It shows a process flow chart of the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0034] Figure 2 It shows a schematic diagram of forming a second inorganic dielectric layer on a support substrate in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0035] Figure 3 It shows a schematic diagram of forming contact pads on a support substrate in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0036] Figure 4 It shows a schematic diagram of forming a first redistribution layer in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0037] Figure 5A It shows a schematic diagram of forming a first bonding layer on the first main surface of the first redistribution layer in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0038] Figure 5B It shows a schematic diagram of forming a second bonding layer on the surface of a semiconductor chip in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0039] Figure 6 It shows a schematic diagram of forming a hybrid bonding structure between the first main surface of the first redistribution layer and a semiconductor chip in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0040] Figure 7 It shows a schematic diagram of forming a molding layer on the first main surface of the first redistribution layer in the manufacturing method of the fan-out package unit for PoP packaging of the present invention.

[0041] Figure 8 Schematic diagram showing thinning of the plastic encapsulation layer in the manufacturing method of the fan-out encapsulation unit for PoP packaging according to the present invention.

[0042] Figure 9 Schematic diagram showing removal of the support substrate in the manufacturing method of the fan-out encapsulation unit for PoP packaging according to the present invention.

[0043] Figure 10 Schematic diagram showing formation of the second redistribution layer on the second main surface of the first redistribution layer in the manufacturing method of the fan-out encapsulation unit for PoP packaging according to the present invention.

[0044] Figure 11 Schematic diagram showing formation of solder balls within the openings of the second redistribution layer in the manufacturing method of the fan-out encapsulation unit for PoP packaging according to the present invention.

[0045] Element reference numeral description:

[0046] Steps - S1 to S5; support substrate - 10; first redistribution layer - 20; first metal wiring layer - 201; patterned first inorganic dielectric layer - 202; vias - 204; second inorganic dielectric layer - 210; patterned second inorganic dielectric layer - 211; contact pads - 212; hybrid bonding structure - 30; first bonding layer - 310; first passivation layer - 311; first pads - 312; second bonding layer - 320; second passivation layer - 321; second pads - 322; encapsulation layer - 40; plastic encapsulation layer - 410; second redistribution layer - 50; second metal wiring layer - 501; organic dielectric layer - 502; openings - 503; under-bump metal layer - 504; solder balls - 505. Detailed implementation manners

[0047] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] Please refer to Figures 1 to 11 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The type, quantity, and ratio of each component during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] This embodiment provides a manufacturing method for a fan-out packaging unit for PoP packaging. Please refer to Figure 1 , which shows the process flow chart of this method, including the following steps:

[0050] S1: Provide a support substrate, and form a first redistribution layer on the support substrate, including: forming a patterned first inorganic dielectric layer, and forming a first metal wiring layer;

[0051] S2: Form a hybrid bonding structure between the first main surface of the first redistribution layer and the semiconductor chip to electrically couple the semiconductor chip to the first main surface of the first redistribution layer respectively;

[0052] S3: Form a molding layer on the first main surface of the first redistribution layer to form a packaging layer, and the molding layer covers the semiconductor chip;

[0053] S4: Remove the support substrate to expose the second main surface of the first redistribution layer;

[0054] S5: Form a second redistribution layer on the second main surface of the first redistribution layer, and the second redistribution layer includes a second metal wiring layer exposed on the first main surface of the second redistribution layer.

[0055] First, as Figures 1 to 2 shown, perform step S1 to provide a support substrate 10 and form a first redistribution layer 20 on the support substrate 10. Specifically, the support substrate 10 is used to prevent cracking, warping, fracture, etc. of the layer structure during the packaging process. The shape of the support substrate 10 can be wafer-shaped, panel-shaped, and any other required shape, including but not limited to any one of silicon-based, glass, metal, semiconductor substrate, polymer, and ceramic. In this embodiment, the support substrate 10 can be selected as a silicon substrate to reduce the cost of packaging manufacturing.

[0056] Refer to Figure 2 , step S1 includes: step S1-1, after forming a second inorganic dielectric layer 210 on the support substrate 10, form a plurality of spaced vias (not shown) in the second inorganic dielectric layer 210 by laser etching or a similar process to obtain a patterned second inorganic dielectric layer 211.

[0057] Please refer to Figure 3 , step S1 further includes: S1-2, form a first metal wiring layer 201 on the surface of the patterned second inorganic dielectric layer 211.

[0058] Specifically, at step S1-2, a contact pad 212 is formed in the via hole by sputtering, electroplating, electroless plating or other suitable processes, and a first metal material layer is formed on the patterned second inorganic dielectric layer 211; the first metal material layer is patterned by an etching process to obtain a first metal wiring layer 201 with the required wiring function, and the material of the first metal wiring layer 201 includes, but is not limited to, one or a combination of metals such as copper, aluminum, nickel, gold, silver, titanium, etc. Preferably, the first metal wiring layer 201 can be made of copper metal.

[0059] Please refer to Figure 4 , step S1 further includes: S1-3, forming a patterned first inorganic dielectric layer 202 on the first metal wiring layer 201.

[0060] Specifically, step S1-3 includes: forming a first inorganic dielectric layer on the surface of the first metal wiring layer 201 by chemical vapor deposition process, physical vapor deposition or other suitable processes, and etching the first inorganic dielectric layer to form a patterned first inorganic dielectric layer 202. The first inorganic dielectric layer can be made of a material with a hardness greater than that of the second inorganic dielectric layer, which includes, but is not limited to, one of silicon nitride and silicon oxynitride.

[0061] In this embodiment, the material of the first inorganic dielectric layer is selected as silicon nitride, and the material of the second inorganic dielectric layer is selected as silicon oxide, which reduces the damage caused by etching to the first inorganic dielectric material and reduces the manufacturing difficulty of the first rewiring layer.

[0062] Specifically, the steps of forming the first rewiring layer 20 further include: forming a first inorganic dielectric layer 202 on the first metal wiring layer 201 by including, but not limited to, a vapor deposition process, then forming a patterned area or via hole in the first inorganic dielectric layer 202 by a photolithography and etching process, and then forming a first metal material layer in the patterned area or via hole and on the surface of the first inorganic dielectric layer 202 by including, but not limited to, one or a combination of methods such as sputtering method, electroplating method, electroless plating method, etc. to form the first metal wiring layer 201; that is, repeating the steps of forming the patterned first inorganic dielectric layer 202 and forming the first metal wiring layer 201 at least once. According to the wiring requirements, the connection between the first metal wiring layers of each layer is realized by patterning the first inorganic dielectric layer of each layer or making vias. The first inorganic dielectric layer 202 and the first metal wiring layer 201 can both be single-layer or multi-layer structures to achieve different wiring functions, but it is necessary to ensure that the first metal wiring layers of different layers are electrically connected to each other. By configuring the first rewiring layer as an inorganic wiring layer, the line pitch in the first rewiring layer is reduced to less than 1 μm, and the interface between the organic material and the inorganic material is also avoided.

[0063] In this embodiment, it is shown that the first redistribution layer 20 includes two layers of first inorganic dielectric layers and two layers of first metal wiring layers. A via hole 204 exposing the first metal wiring layer is provided in the upper first inorganic dielectric layer 202.

[0064] Please refer to Figures 5A to 5B to Figure 6 , and perform step S2: Form a hybrid bonding structure 30 between the first main surface of the first redistribution layer and the semiconductor chip.

[0065] As an example, step S2 includes: S2-1, forming a first bonding layer 310 on the first main surface of the first redistribution layer 20; S2-2, directly bonding the first pads 312 to the second pads 322 on the semiconductor chip by alignment respectively.

[0066] Specifically, as Figures 5A to 5B shown, step S2-1 includes: forming a first passivation layer 311 on the first main surface of the first redistribution layer 20; forming an opening (not shown) in the first passivation layer 311 through photolithography and etching processes, and plating a second metal in the opening to form the first pad 312 embedded in the first passivation layer 311.

[0067] As an example, sputtering, electroplating, electroless plating or other suitable processes are used to fill the second metal on the surface of the patterned first passivation layer to form the embedded first pad 312. At the same time, the second metal enters the via hole 204 in the upper second inorganic dielectric layer to form a conductive plug, thereby realizing the electrical connection between the first bonding layer 310 and the first redistribution layer 20. As Figure 5A shown, a first passivation layer 312 is formed on the upper second inorganic dielectric layer; an opening corresponding to the first pad is formed in the first passivation layer 312 through photolithography and etching processes, and the via hole 204 in the upper second inorganic dielectric layer is exposed at the bottom of the opening; the second metal is filled on the surface of the patterned first passivation layer to form the embedded first pad 312. By defining the size and position of the first pad on the first passivation layer 311 through photolithography, the line pitch / pitch between pins can be adjusted to increase the density of I / O ports.

[0068] In one example, the first passivation layer 312 has the same material as the second inorganic dielectric layer, while in other examples, the first passivation layer 312 has a different material from the second inorganic dielectric layer. For example, the first passivation layer can be one of silicon oxide and silicon nitride. Correspondingly, as Figure 5B shown, a second bonding layer 320 is provided on the surface of the semiconductor chip, and the second bonding layer 320 includes a second passivation layer 321 and a second pad 322 embedded in the second passivation layer.

[0069] Specifically, step S2-2 includes: aligning and directly bonding the first pad 312 with the second pad 322 on the semiconductor chip. In this embodiment, hydrophilic bonding is utilized between the first passivation layer and the second passivation layer, and the first pad 312 is aligned and directly bonded with the second pad 322 disposed on the surface of the semiconductor chip. Since a hybrid bonding structure is formed between the semiconductor chip and the first redistribution layer through solderless bonding, cracks caused by solder at the interface between the two are avoided.

[0070] As an example, the second metal can be selected as the same metal material as the first metal material; preferably, the materials of the first pad 312 and the second pad 322 are selected as copper metal, and the formed Cu-Cu bonded interconnection line has better electrical conductivity and better electromigration resistance.

[0071] Please refer to Figure 6 , and perform step S3: form a molding compound layer 410 on the first major surface of the first redistribution layer 20 to form a package layer 40, and the molding compound layer 410 covers the semiconductor chip.

[0072] As an example, the semiconductor chip can be a functional chip, which includes active devices and passive devices, and can realize heterogeneous integration of the active devices and the passive devices, thereby forming a package body that realizes a specific function.

[0073] As an example, the method for forming the molding compound layer 410 includes but is not limited to any one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating method. The material of the molding compound layer can be a curable material, such as a polymer-based material, a resin-based material, an epoxy resin, a liquid thermosetting epoxy resin, a plastic compound, a polyamide, and any combination thereof. Among them, refer to Figure 8 , after forming the molding compound layer 410, it may further include the step of thinning the molding compound layer 410, such as using a chemical mechanical polishing (CMP) process, etc., acting on the surface of the molding compound layer 410 to provide a flat package layer 40 and further reduce the thickness of the subsequent formed system-level packaging unit.

[0074] Please refer to Figure 9 , and perform step S4: remove the support substrate 10 to expose the second major surface of the first redistribution layer 20.

[0075] Specifically, the step of removing the support substrate 10: a CMP process can be adopted to facilitate providing a flat surface, but it is not limited thereto, such as an etching method can also be adopted. Through thinning, the contact pads 212 and the patterned second inorganic dielectric layer 211 can be exposed, and the thickness of the subsequent formed system-level packaging structure can be further reduced by thinning, wherein the support substrate 10 is a silicon-based substrate.

[0076] Refer to Figures 10 to 11 , perform step S5 to form a second redistribution layer 50 on the second major surface of the first redistribution layer 20. The second redistribution layer 50 includes a second metal wiring layer 501 and an organic dielectric layer 502 covering the second metal wiring layer 501. The second metal wiring layer 501 is exposed on the first major surface of the second redistribution layer 50.

[0077] Specifically, the material of the organic dielectric layer can be one or a combination of two or more of epoxy resin, silicone, polyimide (PI), poly(p-phenylene benzobisoxazole) (PBO), and benzocyclobutene (BCB). In this embodiment, the material of the organic dielectric layer 502 can be selected as PI to further reduce the process difficulty and process cost.

[0078] As an example, the material of the second metal wiring layer can be selected to be the same as that of the first metal wiring layer; preferably, the material of the second metal wiring layer is selected as copper metal, so that the main structures of the packaging unit are all electrically connected through copper metal, having further optimized packaging electrical properties and better electromigration resistance.

[0079] As an example, step S4 further includes: after forming the organic dielectric layer, forming solder balls on the second major surface of the second redistribution layer to achieve the interconnection between the package body and an external chip or packaging unit. The specific steps include: forming an opening 503 exposing the second metal wiring on the second major surface of the second redistribution layer 50; forming an under bump metallization (UBM) 504 on the opening 503; forming solder balls 505 in the opening through ball placement and reflow. It should be noted that although the external interconnection of the package body is realized based on the solder ball method here, the present invention also covers other methods including metal bumps, solder bumps, and realizing external interconnection.

[0080] Embodiment 2

[0081] The present invention provides a fan-out package unit for PoP packaging, comprising: a first redistribution layer 20, a hybrid bonding structure 30, and a second redistribution layer 50, wherein the first redistribution layer 20 has a first main surface and a second main surface disposed opposite to each other, and the hybrid bonding structure 30 is located on the first main surface of the first redistribution layer 20 for electrically coupling a semiconductor chip to the first main surface of the first redistribution layer 20. Specifically, the first redistribution layer 20 includes a first inorganic dielectric layer 202 and a first metal wiring layer 201 stacked in the vertical direction, the semiconductor chip is covered with a molding compound layer 410 to form a package layer 40, the second redistribution layer 50 includes a second metal wiring layer 501 exposed on the first main surface of the second redistribution layer 50, and the second metal wiring layer 501 is electrically connected to the second main surface of the first redistribution layer 20 to realize electrical lead-out of the semiconductor chip and the first redistribution layer 20.

[0082] As an example, the first redistribution layer 20 includes at least one set of stacked first metal wiring layer 201 and first inorganic dielectric layer 202, the first inorganic dielectric layer 202 and the first metal wiring layer 201 are alternately arranged, and the first redistribution layer 20 is configured as a wiring layer based on inorganic materials using an inorganic dielectric material as an insulating material, and the line pitch of the first redistribution layer 20 can be reduced to less than 1 μm, optimizing the package volume, replacing the TSV interposer, and reducing the manufacturing cost at the same time.

[0083] As an example, the material of the first inorganic dielectric layer is different from the material of the second inorganic dielectric layer. For example, the first inorganic dielectric layer includes silicon oxide, and the second inorganic dielectric layer includes silicon nitride.

[0084] As an example, contact pads 212 are exposed on the second main surface 20 of the first redistribution layer, and the contact pads 212 are electrically connected to the second metal wiring layer 501 exposed on the first main surface of the second redistribution layer 50.

[0085] As an example, a first bonding layer 310 is disposed on the first main surface of the first redistribution layer 20, a second bonding layer 320 is disposed on the surface of the semiconductor chip, and the hybrid bonding structure 30 is configured to directly bond through the first bonding layer 310 and the second bonding layer 320 disposed on the surface of the semiconductor chip at the interface between the two, and the obtained bonding interface forms a solderless bonding surface and has an interconnect pitch of less than 10 microns.

[0086] As an example, the second rewiring layer 50 further includes an organic dielectric layer 502 covering the second metal wiring layer 501. The material of the first metal wiring layer may be selected to be the same as that of the second metal wiring layer. The first metal wiring layer includes one or more combinations of copper, aluminum, nickel, gold, silver, and titanium. The material of the organic dielectric layer 502 may be one or more combinations of epoxy resin, silicone, polyimide (PI), poly(phenylene benzobisoxazole) (PBO), and benzocyclobutene (BCB).

[0087] Specifically, the second major surface of the second rewiring layer 50 is electrically coupled to an external chip or packaging unit through conductive interconnections. The conductive interconnections include a solder ball array disposed on the second major surface of the second rewiring layer 50, and the solder balls 505 are respectively disposed on the under-bump metal layer 504.

[0088] As an example, the semiconductor chip may be a functional chip, which includes active devices, such as one or more of a logic device (logic IC), a high-bandwidth memory (HBM), a switch, a power management unit (PM), and a surface-mounted device (SMD) (each type of device may be single or multiple), and passive devices, such as resistors, inductors, capacitors, etc.

[0089] As Figure 11 As shown, the fan-out package unit for PoP packaging may be a system-in-package module (SIP Module), which can integrate a processor, a sensor, a data encryption chip, an actuator, a memory, a connectivity, a built-in security chip, etc. at the same time. The active devices and the passive devices are arranged side by side and are respectively electrically connected to the first rewiring layer 20 through the hybrid bonding structure 30. The hybrid bonding structure 30 is used to integrate two or more heterogeneous semiconductor components and passive devices into a standard package body that realizes a basically complete function, thereby forming a system-in-package (SiP). Thus, a packaging structure with required functions can be customized more flexibly.

[0090] This embodiment also provides a PoP packaging structure, which includes: the fan-out package unit as described above, and the fan-out package unit is stacked on a packaging substrate. Specifically, the fan-out package unit may be stacked with an external chip or packaging unit.

[0091] In summary, in the fan-out package unit for PoP packaging of the present invention, a first redistribution layer made of all-inorganic materials is adopted to replace the conventionally used TSV interposer, while reducing the cost of package manufacturing, achieving a high-performance system-level fan-out package unit. The first redistribution layer and the semiconductor chip are solderless bonded using a hybrid bonding structure, avoiding cracks at the interface between the two solders, improving the reliability of the interconnection, and also facilitating the reduction of the pitch between pins, thereby increasing the density of I / O ports and being conducive to the miniaturization of the package structure. In addition, a second redistribution layer is adopted to replace the package substrate and is electrically coupled to an external chip or package unit through conductive interconnections to implement an integrated solution for stacked packaging.

[0092] In the manufacturing method of the fan-out package unit of the present invention, by selecting an inorganic dielectric as the insulating material of the first redistribution layer, the line pitch in the first redistribution layer is reduced to less than 1 μm, and a hybrid bond is formed at the interface between the first redistribution layer and the semiconductor chip, avoiding the formation of an interface between organic and inorganic materials, improving the process integration of package manufacturing, and optimizing the package volume. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0093] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method for a fan-out package unit for PoP packaging, characterized in that, Including the following steps: Providing a support substrate, forming a first redistribution layer on the support substrate, the first redistribution layer having a first main surface and a second main surface disposed opposite to each other. The step of forming the first redistribution layer includes: forming a patterned second inorganic dielectric layer on the support substrate, forming an embedded first metal wiring layer in the patterned second inorganic dielectric layer, and forming a patterned first inorganic dielectric layer on the first metal wiring layer. And the material of the first inorganic dielectric layer includes one of silicon nitride and silicon oxynitride, and the material of the second inorganic dielectric layer includes silicon oxide; Forming a hybrid bonding structure between the first main surface of the first redistribution layer and the semiconductor chip to electrically couple the semiconductor chip to the first main surface of the first redistribution layer respectively. The hybrid bonding structure includes a first bonding layer formed on the first main surface of the first redistribution layer; Forming a molding layer on the first main surface of the first redistribution layer to form a package layer, the molding layer covering the semiconductor chip; Forming a second redistribution layer on the second main surface of the first redistribution layer, the second redistribution layer having a first main surface and a second main surface disposed opposite to each other. The second redistribution layer includes a second metal wiring layer exposed on the first main surface of the second redistribution layer and an organic dielectric layer covering the second metal wiring layer, and the second metal wiring layer is electrically connected to the second main surface of the first redistribution layer.

2. The manufacturing method for the fan-out package unit according to claim 1, characterized in that, It further includes the following steps: Repeating the steps of forming the patterned first inorganic dielectric layer and forming the first metal wiring layer at least once.

3. The manufacturing method for the fan-out package unit according to claim 1, characterized in that, It further includes the following steps: The step of removing the support substrate includes: thinning the support substrate by a mechanical grinding process, and then removing the remaining support substrate by a chemical mechanical polishing process, wherein the support substrate is a silicon-based substrate.

4. The manufacturing method for the fan-out package unit according to claim 1 or 2, characterized in that, The step of forming the first bonding layer on the first main surface of the first redistribution layer includes: Forming a first passivation layer on the first main surface of the first redistribution layer; Forming an opening in the first passivation layer by a photolithography process and an etching process, and plating a metal in the opening to form a first pad.

5. The manufacturing method for the fan-out package unit according to claim 1, characterized in that: The material of the first metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

6. The manufacturing method for the fan-out package unit according to claim 1, characterized in that, The step of forming the second redistribution layer further includes: Forming an opening exposing the second metal wiring on the second main surface of the second redistribution layer; Forming an under-bump metal layer on the opening; Forming solder balls in the opening by ball implantation and reflow.

7. A fan-out package unit for PoP packaging, characterized in that, Including: A first redistribution layer having a first main surface and a second main surface disposed opposite to each other. A first bonding layer is disposed on the first main surface of the first redistribution layer. The first redistribution layer includes a first inorganic dielectric layer, a first metal wiring layer, and a second inorganic dielectric layer stacked in the vertical direction. The first metal wiring layer is embedded in the patterned second inorganic dielectric layer. The material of the first inorganic dielectric layer includes one of silicon nitride and silicon oxynitride, and the material of the second inorganic dielectric layer includes silicon oxide; A hybrid bonding structure is located on the first main surface of the first redistribution layer and is configured to electrically couple a semiconductor chip to the first main surface of the first redistribution layer to achieve interconnection between the semiconductor chips through the first redistribution layer, and the semiconductor chip is covered with a molding compound layer to form a package layer; A second redistribution layer has a first main surface and a second main surface disposed opposite to each other. The second redistribution layer includes a second metal wiring layer exposed on the first main surface of the second redistribution layer and an organic dielectric layer covering the second metal wiring layer. The second metal wiring layer is electrically connected to the second main surface of the first redistribution layer to electrically lead out the semiconductor chip and the first redistribution layer.

8. The fan-out package unit according to claim 7, characterized in that: An opening exposing the second metal wiring is formed on the second main surface of the second redistribution layer, and a under-bump metal layer is formed on the opening. The conductive interconnection includes a solder ball array disposed on the second main surface of the second redistribution layer, and each solder ball is disposed on the under-bump metal layer for achieving conductive interconnection with an external chip or package unit.

9. The fan-out package unit according to claim 7, characterized in that: The hybrid bonding structure is configured to directly bond through a first bonding layer and a second bonding layer disposed on the surface of the semiconductor chip at the interface between the two, and the formed bonding interface has an interconnection pitch of less than 10 microns.

10. The fan-out package unit according to claim 7, characterized in that: The semiconductor chip includes active devices and passive devices, and the active devices and the passive devices are arranged side by side.

11. A PoP packaging structure, characterized in that, Comprising: The fan-out package unit according to any one of claims 7 to 10, and the fan-out package units are stacked on a package substrate.

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