Wafer abnormality early warning method

Abstract

This invention provides a wafer anomaly early warning method. When an anomaly occurs at a process station, multiple wafers from the same batch passing through the anomaly station will show repeated anomaly points at the same location. For each test station, this invention first obtains test images of several wafers from the same batch that need to be analyzed at the test station. Then, it obtains the ratio between the maximum number of wafer test images with repeated anomaly points at the same location and the total number of wafer test images. Based on the ratio, it determines whether a wafer anomaly early warning is needed. In this way, once an anomaly occurs at a process station, it can be detected in a timely and accurate manner, effectively warning of wafer anomalies and avoiding the generation of batch defective products.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for early warning of wafer anomalies. Background Technology

[0002] The manufacturing process of integrated circuit chips is extremely complex and has a long production cycle. Final shipment typically involves hundreds or even thousands of steps and hundreds of machines. Machines performing the same process step are usually grouped into a single process station, where wafers are processed sequentially. To ensure the final product's performance is up to standard, stable, reliable, and has a high yield, strict requirements are placed on all process steps. Therefore, inspection stations are set up at the end of each process station to detect wafer anomalies (such as defects), thereby monitoring each process step and providing early warnings of wafer anomalies. This facilitates timely detection of any abnormalities at the current process station, preventing the generation of batches of defective products.

[0003] However, since wafers pass through different process stations sequentially and perform corresponding process steps at each station, wafers with abnormalities detected at the current inspection station will be released directly if the number of defects does not reach a certain threshold. In reality, multiple wafers in the same batch with defects in the same location are also the focus of attention. Due to the error of the measurement equipment, multiple wafers cannot be directly overlaid. Therefore, how to detect such abnormalities at the current process station in a timely and accurate manner is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a wafer anomaly early warning method to solve the current problem of not being able to detect whether anomalies occur at process stations in a timely and accurate manner.

[0005] To achieve the above objectives, this invention provides a wafer anomaly early warning method, which performs the following steps for each test site:

[0006] Obtain test images of several wafers from the same batch that require anomaly analysis at the test site;

[0007] Obtain the ratio between the maximum number of wafer test patterns with duplicate anomalies at the same location and the total number of wafer test patterns; and,

[0008] The determination of whether a wafer anomaly warning is needed is based on the stated percentage.

[0009] Optionally, the wafer test pattern is a wafer defect test pattern, and the abnormal points in the wafer test pattern are the locations of defects; or, the wafer test pattern is a wafer electrical test pattern, and the abnormal points in the wafer test pattern are the locations of defective dies; or, the wafer test pattern is a wafer parameter test pattern, and the abnormal points in the wafer test pattern are the locations of parameter abnormalities.

[0010] Optionally, when the number of abnormal points in the wafer test pattern is less than a first threshold, it is determined that the wafer test pattern needs to be analyzed for abnormalities.

[0011] Optionally, the step of obtaining the maximum number of wafer test patterns with repeating anomalies at the same location includes:

[0012] In each of the aforementioned wafer test patterns, a circle is drawn with the center of each anomaly point as the center and half the preset tolerance as the radius, to obtain the corresponding first anomaly tolerance pattern; and,

[0013] All the first anomaly tolerance maps are superimposed, and the maximum number of overlapping circles is the maximum number of wafer test maps with repeated anomaly points at the same location.

[0014] Optionally, in the first anomaly tolerance map, the grayscale value of the area within the circle is 1, and the grayscale value of other areas is 0; and,

[0015] When all the first abnormal tolerance maps are superimposed, all the first abnormal tolerance maps are added together to obtain a first abnormal tolerance superimposed map. The maximum gray value in the first abnormal tolerance superimposed map is the maximum number of wafer test maps with abnormal points at the same position.

[0016] Optionally, after determining that a wafer anomaly warning is needed, the following may also be included:

[0017] Obtain the location of the repeated anomaly points.

[0018] Optionally, the step of obtaining the location of the repeated anomaly points includes:

[0019] In each of the wafer test patterns, a circle is drawn with the center of each anomaly point as the center and the preset tolerance as the radius to obtain the corresponding second anomaly tolerance pattern;

[0020] Overlay all the second anomaly tolerance maps; the area with the most overlapping circles is the repeating anomaly area; and,

[0021] The repeated abnormal region is superimposed on all the abnormal points in the wafer test pattern, and the abnormal points that overlap with the repeated abnormal region are the repeated abnormal points.

[0022] Optionally, in the second anomaly tolerance map, the gray value of the area within the circle is 1, and the gray value of other areas is 0;

[0023] When overlaying all the second abnormal tolerance maps, all the second abnormal tolerance maps are added together to obtain a second abnormal tolerance overlay map. The region with the largest gray value in the second abnormal tolerance overlay map is the repeated abnormal region; and,

[0024] The grayscale value of the abnormal point in the wafer test pattern is 1, and the grayscale value of other areas is 0. When the repeated abnormal area is superimposed with the abnormal points in all the wafer test patterns, the grayscale value of the repeated abnormal area in the second abnormal tolerance superimposed image is first set to 1, and the grayscale value of other areas is set to 0. Then, the second abnormal tolerance superimposed image is multiplied by the sum of all the wafer test patterns to obtain the repeated abnormal image. The position with a grayscale value of 1 in the repeated abnormal image is the repeated abnormal point.

[0025] Optionally, after determining that a wafer anomaly warning is needed, the following may also be included:

[0026] The source of the anomaly is obtained based on the location of the repeated anomaly.

[0027] Optionally, the step of obtaining the anomaly source of the repeated anomaly based on its location includes:

[0028] Obtain all machine structures in the process station corresponding to the test station that could cause wafer abnormalities;

[0029] Obtain an analysis diagram of the effect of each of the machine structure on the wafer. The analysis diagram has several effect regions, which are used to characterize the surface of the machine structure on the wafer.

[0030] Each of the action regions in each action analysis map is superimposed on the repeating anomalies one by one; the repeating anomalies that overlap with the action regions are suspected anomalies; and...

[0031] The machine structure that generates the repeated anomaly point is determined based on the suspected anomaly point corresponding to each of the machine structures.

[0032] Optionally, the machine structure includes a robotic arm, and the action analysis diagram includes a projection image of each clamping position of the robotic arm on the wafer; and / or, the machine structure includes a heating stage, and the action analysis diagram includes projection images of all heating areas of the heating stage on the wafer; and / or, the machine structure includes a vacuum adsorption stage, and the action analysis diagram includes projection images of all adsorption areas of the vacuum adsorption stage on the wafer.

[0033] Optionally, in the effect analysis diagram, the grayscale value of the effect area that needs to be superimposed on the repeated anomaly point is 1, and the grayscale value of other areas is 0; and,

[0034] When the effect region of the effect analysis map is superimposed with the repeated anomaly point, the effect analysis map is multiplied by the repeated anomaly map to obtain a suspected anomaly map, and the area with a gray value of 1 in the suspected anomaly map is the suspected anomaly point.

[0035] Optionally, the machine structure that is determined to have a maximum number of suspected anomalies greater than a second threshold is the machine structure that generates the repeated anomalies; or, the machine structure that is determined to have a ratio between the maximum number of suspected anomalies and the total number of anomalies in all the wafer test patterns greater than a third threshold is the machine structure that generates the repeated anomalies.

[0036] Optionally, when the percentage is greater than the fourth threshold, it is determined that a wafer anomaly warning needs to be issued.

[0037] In the wafer anomaly early warning method provided by this invention, when an anomaly occurs at a process station, multiple wafers of the same batch passing through the anomaly process station will have repeated anomaly points at the same location. For each test station, this invention first obtains several wafer test images of the same batch that need to be analyzed for anomalies at the test station, and then obtains the ratio between the maximum number of wafer test images with repeated anomaly points at the same location and the total number of wafer test images. Then, based on the ratio, it is determined whether a wafer anomaly early warning is needed. In this way, once an anomaly occurs at a process station, it can be detected in a timely and accurate manner, effectively warning of wafer anomalies and avoiding the generation of batch defective products. Attached Figure Description

[0038] Figure 1 A flowchart of a wafer anomaly early warning method provided in an embodiment of the present invention;

[0039] Figures 2a-2c A schematic diagram of three wafer test images that require anomaly analysis, provided for an embodiment of the present invention;

[0040] Figures 3a-3c A schematic diagram of three first anomaly tolerance diagrams provided in an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the first abnormal tolerance overlay provided in an embodiment of the present invention;

[0042] Figures 5a-5c A schematic diagram of three second anomaly tolerance diagrams provided in an embodiment of the present invention;

[0043] Figure 6This is a schematic diagram of the second abnormal tolerance overlay diagram provided in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the processed second abnormal tolerance overlay provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram showing the sum of all wafer test patterns provided in an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of superimposing the repeating abnormal region with the abnormal points in all wafer test patterns, provided by an embodiment of the present invention.

[0047] Figure 10 This is a schematic diagram showing the result of multiplying the processed second anomaly tolerance overlay pattern with the sum of all wafer test patterns, as provided in an embodiment of the present invention.

[0048] Figures 11a-11c These are schematic diagrams illustrating the function analysis of the robotic arm in three clamping orientations of 0°, 30°, and 90°, as provided in the embodiments of the present invention.

[0049] Figure 12 These are schematic diagrams illustrating the function of the vacuum adsorption stage provided in the embodiments of the present invention;

[0050] Figure 13 These are schematic diagrams illustrating the function of the heating stage provided in the embodiments of the present invention;

[0051] Figure 14 This is a schematic diagram of another repeating anomaly graph provided in an embodiment of the present invention;

[0052] Figures 15a-15c This is a schematic diagram provided by an embodiment of the present invention, showing the superposition of the action area in the action analysis diagram of the robotic arm with the repeated abnormal points;

[0053] Figures 16a-16c This is a schematic diagram provided by an embodiment of the present invention, showing the superposition of the functional areas in the analysis diagram of the function of the heating stage / vacuum adsorption stage with the repeated abnormal points;

[0054] Figures 17a-17c A schematic diagram of three suspected anomaly graphs provided in an embodiment of the present invention;

[0055] Figures 18a-18c Schematic diagrams of three other suspected anomaly diagrams provided in embodiments of the present invention;

[0056] The attached figures are labeled as follows:

[0057] A, B, C - Wafer test maps; a1, a2, a3, a4, b1, b2, b3, c1, c2, c3 - Anomaly points; A1, B1, C1 - First anomaly tolerance map; A2, B2, C2 - Second anomaly tolerance map; a11, a12, a13, a14, a21, a22, a23, a24, b11, b12, b13, b21, b22, b23, c11, c12, c13, c2 1, c22, c23 - Circles; D1 - First anomaly tolerance overlay; D2, D2' - Second anomaly tolerance overlay; q - Repeated anomaly area; E1 - Anomaly point overlay; E2, I - Repeated anomaly map; F1, F2, F3, G, H - Action analysis map; g1, g2, g3, h1, h2, h3 - Action area; i1, i2, i3 - Repeated anomaly points; J1, J2, J3, K1, K2, K3 - Suspected anomaly map. Detailed Implementation

[0058] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0059] Figure 1 This is a flowchart of the wafer anomaly early warning method provided in this embodiment. Figure 1 As shown, the wafer anomaly early warning method performs the following steps for each test site:

[0060] Step S100: Obtain test images of several wafers from the same batch that require anomaly analysis at the test site;

[0061] Step S200: Obtain the ratio between the maximum number of wafer test patterns with duplicate anomalies at the same location and the total number of wafer test patterns; and,

[0062] Step S300: Determine whether a wafer anomaly warning is needed based on the stated percentage.

[0063] In this embodiment, the wafer test pattern is a wafer defect test pattern, and the abnormal points in the wafer test pattern are the locations of defects. However, this should not be the limitation. The wafer test pattern can also be other wafer test patterns. For example, the wafer test pattern can also be a wafer electrical test pattern. In this case, the abnormal points in the wafer test pattern are the locations of defective dies. Alternatively, the wafer test pattern can also be a wafer parameter test pattern (thickness measurement pattern, size measurement pattern, alignment offset pattern, etc.). In this case, the abnormal points in the wafer test pattern are the locations of parameter abnormalities.

[0064] Specifically, in step S100, all wafer test images obtained by the test station from testing the same batch of wafers are acquired. These wafer test images may or may not contain anomalies (i.e., the locations of defects). The number of anomalies in each wafer test image is obtained and compared with a preset first threshold. If the number of anomalies in a wafer test image is less than the first threshold, it indicates that there are few anomalies, suggesting a possibility of misplacement, and the wafer test image is determined to require anomaly analysis. Conversely, if the number of anomalies in a wafer test image is greater than or equal to the first threshold, it indicates that there are many anomalies, potentially causing the system to be blocked, and the current wafer test image is determined not to require anomaly analysis.

[0065] It should be understood that this embodiment is not limited to determining whether the wafer test pattern needs to be analyzed based on the number of abnormal points in the wafer test pattern. Other methods can also be used, such as determining whether the wafer test pattern needs to be analyzed based on the sum of the areas of the abnormal points in the wafer test pattern or the size of the largest abnormal point. Examples will not be given here.

[0066] Furthermore, since all the wafer test patterns are obtained from the same test site, the wafer test patterns are obtained by the test site from testing different wafers of the same batch. For example, multiple wafers of the same batch pass through the test site one by one. When it is necessary to determine whether an anomaly has occurred at the test site, the wafer test patterns corresponding to these wafers are selected based on the first threshold to identify the wafer test patterns that require anomaly analysis.

[0067] Figures 2a-2c This is a schematic diagram of three wafer test images required for anomaly analysis, provided in this embodiment. (See diagram below.) Figure 2a As shown, in this embodiment, the wafer test pattern A has four abnormal points, namely abnormal points a1, a2, a3, and a4; Figure 2b As shown, wafer test pattern B has three outliers, namely outliers b1, b2, and b3; Figure 2c As shown, there are three abnormal points on the wafer test pattern C, namely abnormal points c1, c2, and c3.

[0068] In this embodiment, the wafer test pattern A, the wafer test pattern B, and the wafer test pattern C are obtained by testing them sequentially at the test station. That is, the three wafers are tested sequentially through the test station to obtain the wafer test pattern A, the wafer test pattern B, and the wafer test pattern C in sequence.

[0069] It should be noted that the test station may also test other wafers between the wafer corresponding to test pattern A and the wafer corresponding to test pattern B, and between the wafer corresponding to test pattern B and the wafer corresponding to test pattern C, thereby obtaining other wafer test patterns. This invention does not impose any limitations.

[0070] Further, step S200 is executed to obtain the maximum number of wafer test patterns with repeated anomalies at the same location. The repeated anomalies are anomalies present at the same location in at least two wafer test patterns. Since multiple wafers passing through the abnormal process station will have repeated anomalies at the same location when an anomaly occurs at the process station, and this embodiment provides wafer warnings for each test station, it can be assumed that the repeated anomalies are generated by the current process station.

[0071] Specifically, in the wafer test map, a circle is first drawn with the center of each abnormal point as the center and half of the preset tolerance as the radius to obtain the corresponding first abnormality tolerance map.

[0072] Optionally, the preset tolerance is an empirical value, and the specific value of the preset tolerance will not be illustrated here.

[0073] Figure 3a This is a schematic diagram of the first anomaly tolerance diagram A1 provided in this embodiment. Figure 3a As shown, the preset tolerance is γ. The first anomaly tolerance diagram A1 has four circles, namely circles a11, a12, a13, and a14. The center of circle a11 is the anomaly point a1, and the radius is γ / 2; the center of circle a12 is the anomaly point a2, and the radius is γ / 2; the center of circle a13 is the anomaly point a3, and the radius is γ / 2; and the center of circle a14 is the anomaly point a4, and the radius is γ / 2.

[0074] Figure 3b This is a schematic diagram of the first anomaly tolerance diagram B1 provided in this embodiment. (See diagram below.) Figure 3b As shown, the preset tolerance is γ. The first anomaly tolerance diagram B1 has three circles, namely circles b11, b12, and b13. The center of circle b11 is the anomaly point b1, and the radius is γ / 2; the center of circle b12 is the anomaly point b2, and the radius is γ / 2; the center of circle b13 is the anomaly point b3, and the radius is γ / 2.

[0075] Figure 3c This is a schematic diagram of the first anomaly tolerance diagram C1 provided in this embodiment. (See diagram below.) Figure 3cAs shown, the preset tolerance is γ. The first anomaly tolerance diagram C1 has three circles, namely circles c11, c12, and c13. The center of circle c11 is the anomaly point c1, and the radius is γ / 2; the center of circle c12 is the anomaly point c2, and the radius is γ / 2; the center of circle c13 is the anomaly point c3, and the radius is γ / 2.

[0076] Next, all the first abnormal tolerance maps are superimposed, and the maximum number of overlapping circles is the maximum number of wafer test maps with repeated abnormal points at the same location. Specifically, in this embodiment, in all the first abnormal tolerance maps, the gray value of the area inside the circle is 1, and the gray value of other areas (areas outside the circle) is 0. When superimposing all the first abnormal tolerance maps, all the first abnormal tolerance maps are added together to obtain a first abnormal tolerance superimposed map. The maximum gray value in the first abnormal tolerance superimposed map is the maximum number of wafer test maps with abnormal points at the same location.

[0077] It should be understood that adding all the first abnormal tolerance maps together means adding the gray values ​​of each pixel in all the first abnormal tolerance maps together to obtain the first grayscale map, which is the first abnormal tolerance overlay map.

[0078] For example, Figure 3a In the diagram, the grayscale value inside circles a11, a12, a13, and a14 (the gray area) is 1, while the grayscale value outside circles a11, a12, a13, and a14 (the white area) is 0. Figure 3b In the diagram, the grayscale value inside circles b11, b12, and b13 (the gray area) is 1, and the grayscale value outside circles b11, b12, and b13 (the white area) is 0. Figure 3c In the diagram, the grayscale value inside circles c11, c12, and c13 (the gray area) is 1, while the grayscale value outside circles c11, c12, and c13 (the white area) is 0.

[0079] Figure 4 This is a schematic diagram of the first abnormal tolerance overlay diagram D1 provided in this embodiment. (See diagram below.) Figure 4 As shown, the first abnormal tolerance map A1, the first abnormal tolerance map B1, and the first abnormal tolerance map C1 are added together to obtain the first abnormal tolerance overlay map D1. The maximum gray value in the first abnormal tolerance overlay map D1 is 3. Figure 4 As can be seen from the diagram, the maximum number of overlapping circles is 3, which means that the maximum number of wafer test patterns with anomalies at the same position is 3 (at most 3 wafer test patterns have anomalies at the same position).

[0080] Furthermore, after obtaining the maximum number of wafer test patterns with duplicate anomalies at the same location, it is also necessary to obtain the ratio between the maximum number of wafer test patterns with duplicate anomalies at the same location and the total number of wafer test patterns. Specifically, the ratio can be obtained by dividing the maximum number of wafer test patterns with duplicate anomalies at the same location by the total number of wafer test patterns.

[0081] For example, according to Figure 4 The maximum number of wafer test images with repeated anomalies at the same location is 3, and the total number of wafer test images is also 3. Therefore, the percentage can be calculated to be 1.

[0082] Step S300 is executed, determining whether a wafer anomaly warning is needed based on the percentage. In this embodiment, after obtaining the percentage, the percentage is compared with a preset fourth threshold. When the percentage is greater than the fourth threshold, it indicates that there are many wafers with repeated anomalies at the same location, and it is determined that a wafer anomaly warning is needed; conversely, when the percentage is less than or equal to the fourth threshold, it indicates that there are few wafers with repeated anomalies at the same location, and it is determined that a wafer anomaly warning is not needed.

[0083] For example, the fourth threshold is 0.6. When the percentage is 1, it can be determined that a wafer anomaly warning needs to be issued.

[0084] Furthermore, after determining that a wafer anomaly warning is needed, the location of the repeated anomaly point can be obtained, which facilitates subsequent anomaly analysis. It should be noted that although the repeated anomaly point is ideally considered to be an anomaly point at the same location on at least two wafers, due to the existence of positional deviations, the repeated anomaly point is often not necessarily at the same location on at least two wafers in practice, but rather has a certain offset within the error range.

[0085] Based on this, in this embodiment, firstly, in the wafer test map, a circle is drawn with the center of each abnormal point as the center and the preset tolerance as the radius to obtain the corresponding second abnormal tolerance map.

[0086] Figure 5a This is a schematic diagram of the second anomaly tolerance diagram A2 provided in this embodiment. (See diagram below.) Figure 5a As shown, the preset tolerance is γ. The second anomaly tolerance diagram A2 has four circles, namely circles a21, a22, a23, and a24. The center of circle a21 is the anomaly point a1, and the radius is γ; the center of circle a22 is the anomaly point a2, and the radius is γ; the center of circle a23 is the anomaly point a3, and the radius is γ; and the center of circle a24 is the anomaly point a4, and the radius is γ.

[0087] Figure 5b This is a schematic diagram of the second anomaly tolerance diagram B2 provided in this embodiment. (See diagram below.) Figure 5b As shown, the preset tolerance is γ. The second anomaly tolerance diagram B2 has three circles, namely circles b21, b22 and b23. The center of circle b21 is the anomaly point b1 and the radius is γ; the center of circle b22 is the anomaly point b2 and the radius is γ; the center of circle b23 is the anomaly point b3 and the radius is γ.

[0088] Figure 5c This is a schematic diagram of the second anomaly tolerance diagram C2 provided in this embodiment. Figure 5c As shown, the preset tolerance is γ. The second abnormal tolerance diagram C2 has three circles, namely circles c21, c22, and c23. The center of circle c21 is the abnormal point c1, and the radius is γ; the center of circle c22 is the abnormal point c2, and the radius is γ; the center of circle c23 is the abnormal point c3, and the radius is γ.

[0089] Next, all the second anomaly tolerance maps are superimposed. The region with the most overlapping circles is the repeating anomaly region, which is used to characterize the possible locations of the repeating anomaly points. Specifically, in this embodiment, in all the second anomaly tolerance maps, the grayscale value of the area inside the circle is 1, and the grayscale value of other areas (areas outside the circle) is 0. When superimposing all the second anomaly tolerance maps, all the second anomaly tolerance maps are added together to obtain the second anomaly tolerance overlay map. The region with the most overlapping circles in the second anomaly tolerance overlay map is the repeating anomaly region.

[0090] It should be understood that adding all the second abnormal tolerance maps together means adding the gray values ​​of each pixel in all the second abnormal tolerance maps together to obtain the second grayscale map, which is the second abnormal tolerance overlay map.

[0091] For example, Figure 5a In the diagram, the grayscale value inside circles a21, a22, a23, and a24 (the gray area) is 1, while the grayscale value outside circles a21, a22, a23, and a24 (the white area) is 0. Figure 5b In the diagram, the grayscale value inside circles b21, b22, and b23 (the gray area) is 1, while the grayscale value outside circles b21, b22, and b23 (the white area) is 0. Figure 5c In the diagram, the grayscale value inside circles c21, c22, and c23 (the gray area) is 1, while the grayscale value outside circles c21, c22, and c23 (the white area) is 0.

[0092] Figure 6 This is a schematic diagram of the second abnormal tolerance overlay diagram D2 provided in this embodiment. (See diagram below.) Figure 6 As shown, the second abnormal tolerance map A2, the second abnormal tolerance map B2 and the second abnormal tolerance map C2 are added together to obtain the second abnormal tolerance overlay map D2. The area with the largest gray value (the area with a gray value of 3) in the second abnormal tolerance overlay map D2 is the repeated abnormal area q.

[0093] Next, the repeated abnormal region is superimposed with all the abnormal points in the wafer test pattern. The abnormal points that overlap with the repeated abnormal region are the repeated abnormal points. Specifically, in this embodiment, the grayscale value of the abnormal points in the wafer test pattern is 1, and the grayscale value of other areas is 0. When superimposing the repeated abnormal region with all the abnormal points in the wafer test pattern, the second abnormal tolerance overlay is processed first. The grayscale value of the repeated abnormal region in the second abnormal tolerance overlay is set to 1, and the grayscale value of other areas is set to 0. Then, the processed second abnormal tolerance overlay is multiplied by the sum of all the wafer test patterns to obtain a repeated abnormal map. The position with a grayscale value of 1 in the repeated abnormal map is the repeated abnormal point.

[0094] It should be understood that multiplying the processed second anomaly tolerance overlay image with the sum of all the wafer test images involves first adding the grayscale values ​​of each pixel in all the wafer test images to obtain a third grayscale image, and then multiplying the processed second anomaly tolerance overlay image with the grayscale values ​​of each pixel in the third grayscale image to obtain the repeating anomaly image.

[0095] Figure 7 This is a schematic diagram of the processed second abnormal tolerance overlay diagram D2' provided in this embodiment. Figure 7 As shown, after setting the gray value of the repeated abnormal region q in the second abnormal tolerance overlay D2 to 1 and the gray value of other regions (regions outside the repeated abnormal region q) to 0, the processed second abnormal tolerance overlay D2' is obtained.

[0096] like Figures 2a-2c As shown, in wafer test image A, the grayscale value of abnormal points a1, a2, a3, and a4 is 1, and the grayscale value of other areas is 0; in wafer test image B, the grayscale value of abnormal points b1, b2, and b3 is 1, and the grayscale value of other areas is 0; in wafer test image C, the grayscale value of abnormal points c1, c2, and c3 is 1, and the grayscale value of other areas is 0. Figure 8 This is a schematic diagram showing the sum of all the wafer test patterns provided in this embodiment. (See diagram below.) Figure 8As shown, after adding the wafer test image A, the wafer test image B, and the wafer test image C, an anomaly overlay image E1 (i.e., the third grayscale image mentioned above) is obtained. The anomaly overlay image E1 contains all the anomalies in the wafer test images A, B, and C. In the anomaly overlay image E1, the grayscale value of anomalies a1, a2, a3, a4, b1, b2, b3, c1, c2, and c3 is 1, and the grayscale value of other areas is 0.

[0097] Figure 9 This is a schematic diagram provided in this embodiment, showing the superposition of the recurring abnormal region with all the abnormal points in the wafer test pattern. (See diagram below.) Figure 9 As shown, when the second abnormal tolerance overlay map D2' is superimposed with the abnormal point overlay map E1, it can be seen that there are three abnormal points that overlap with the repeated abnormal region q, namely abnormal points a1, b2, and c2. It can be seen that abnormal points a1, b2, and c2 are the repeated abnormal points.

[0098] Figure 10 This is a schematic diagram showing the result of multiplying the processed second anomaly tolerance overlay pattern by the sum of all the said wafer test patterns, as provided in this embodiment. Figure 10 As shown, the second anomaly tolerance overlay D2' is multiplied by the anomaly point overlay E1 to obtain the repeating anomaly map E2. The regions with a gray value of 1 in the repeating anomaly map E2 are anomaly points a1, b2, and c2, while the gray values ​​of other regions are all 0. It can be seen that anomaly points a1, b2, and c2 are the repeating anomaly points.

[0099] Understandably, compared to comparing all the wafer test images one by one and traversing all defects to find repeating anomalies, this embodiment uses image processing to find repeating anomalies, which is faster, more efficient, and more reliable. In particular, the advantages of this invention become more pronounced as the number of wafers in each test site increases.

[0100] Furthermore, after obtaining the location of the repeated anomaly, the source of the anomaly can be obtained based on the location of the repeated anomaly, that is, the machine structure that generates the repeated anomaly in the process station corresponding to the test station.

[0101] Specifically, the process first identifies all equipment structures at the manufacturing station that could cause wafer anomalies. For example, these equipment structures at the testing station include robotic arms, vacuum adsorption stages, or heating stages. When transferring wafers, the robotic arm may scratch them due to positional deviations, leading to anomalies. When adsorbing wafers, the vacuum adsorption stage may cause anomalies due to uneven adsorption forces in the adsorption area. When heating wafers, the heating stage may cause anomalies due to uneven heat distribution in the heating area. The presence of particulate matter on the contact surfaces between the robotic arm, adsorption stage, heating stage, or other equipment structures and the wafer can also cause anomalies. Therefore, the robotic arm, vacuum adsorption stage, and heating stage are all equipment structures at the manufacturing station that could cause wafer anomalies.

[0102] Furthermore, an analysis diagram of the effect of each of the machine structure on the wafer is obtained. The analysis diagram has several effect regions, which are used to characterize the surface on which the machine structure affects the wafer. The analysis diagram of the effect of the machine structure can be one or more. Correspondingly, each analysis diagram can have one effect region or more than one effect region.

[0103] For example, when the machine structure is a robotic arm, the action analysis diagram can be a projection image of each clamping position of the robotic arm on the wafer. Therefore, the action analysis diagram of the robotic arm is related to the number of clamping positions of the robotic arm. Furthermore, since the robotic arm is in overall contact with the wafer, the action analysis diagram of the robotic arm typically only has one action area. When the machine structure is a vacuum adsorption stage, the action analysis diagram can be a projection image of all adsorption areas of the vacuum adsorption stage on the wafer. The positions of all adsorption areas of the vacuum adsorption stage typically do not change, therefore, the action analysis diagram of the vacuum adsorption stage has only one image. Furthermore, since each adsorption area of ​​the vacuum adsorption stage is composed of multiple uniformly distributed nozzles, and each adsorption area contacts the wafer at different positions, the action analysis diagram of the vacuum adsorption stage typically has multiple action areas. The number and shape of the action areas are related to the number of adsorption areas on the vacuum adsorption stage and the distribution of the nozzles, respectively. When the machine structure is a heating stage, the action analysis diagram can be a projection image of all heating areas of the heating stage on the wafer. The positions of all heating areas of the heating stage usually do not change, so there is only one action analysis diagram of the heating stage. Furthermore, since the temperature distribution of each heating area of ​​the heating stage may be different, and each heating area may have different interactions with the wafer, the action analysis diagram of the heating stage usually has multiple action areas. The number and shape of the action areas are related to the number of heating areas on the heating stage and the distribution of heating elements.

[0104] Figures 11a-11c These are schematic diagrams F1, F2, and F3, respectively, illustrating the function analysis of the robotic arm in the three clamping orientations of 0°, 30°, and 90° provided in this embodiment. Figures 11a-11c As shown, since the robotic arm has three clamping orientations of 0°, 30° and 90°, there are also three function analysis diagrams of the robotic arm, namely function analysis diagrams F1, F2 and F3. Each of the function analysis diagrams F1, F2 and F3 has only one function area, that is, the projection image of the entire robotic arm on the wafer.

[0105] Figure 12 These are schematic diagrams of the function analysis diagram G of the vacuum adsorption stage provided in this embodiment. (See diagram G for example.) Figure 12 As shown, the adsorption areas on the vacuum adsorption stage are distributed in concentric rings. The analysis diagram G of the vacuum adsorption stage has three functional areas, namely functional areas g1, g2, and g3. The functional areas g1, g2, and g3 are the projection images of the three adsorption areas of the vacuum adsorption stage on the wafer.

[0106] Figure 13These are schematic diagrams of the function analysis diagram H of the heating stage provided in this embodiment. For example... Figure 13 As shown, the heating areas on the heating stage are distributed in concentric rings. The analysis diagram H of the heating stage has three functional areas, namely functional areas h1, h2, and h3. The functional areas h1, h2, and h3 are the projection images of the three heating areas of the heating stage on the wafer.

[0107] Of course, the above are just examples. The distribution of the functional areas of the vacuum adsorption stage and the heating stage in the analysis diagram is not limited to three concentric rings. There may be other numbers of rings. These will not be listed here.

[0108] Furthermore, each of the action regions in each action analysis diagram is superimposed on the repeated anomalies one by one, and the repeated anomalies that overlap with the action regions are the suspected anomalies.

[0109] Figure 14 This is a schematic diagram of the repeating anomaly diagram I provided in this embodiment. For example... Figure 14 As shown, the repeated anomaly diagram I has three repeated anomaly points, namely repeated anomaly points i1, i2, and i3.

[0110] Figures 15a-15c This embodiment provides a schematic diagram by superimposing the functional areas in the analysis diagrams F1, F2, and F3 of the robotic arm with the recurring anomaly points i1, i2, and i3, respectively. For example... Figure 15a As shown, after superimposing the area of ​​effect of the action analysis diagram F1 with the repeated anomalies i1, i2, and i3, it can be found that the area of ​​effect of the repeated anomalies i1, i2, and i3 overlaps with the area of ​​effect of the action analysis diagram F1, and it can be determined that the repeated anomalies i1, i2, and i3 are all suspected anomalies. Figure 15b As shown, after superimposing the area of ​​effect of the action analysis diagram F2 with the repeated anomalies i1, i2, and i3, it can be found that the area of ​​effect of the repeated anomaly i1 overlaps with that of the action analysis diagram F1, and it can be determined that the repeated anomaly i1 is the suspected anomaly. Figure 15c As shown, after superimposing the area of ​​action of the action analysis diagram F3 with the repeated anomalies i1, i2, and i3, it can be found that the repeated anomalies i1, i2, and i3 do not overlap with the area of ​​action of the action analysis diagram F3. Therefore, it can be determined that the repeated anomalies i1, i2, and i3 are not the suspected anomalies.

[0111] Figures 16a-16cThis is a schematic diagram provided in this embodiment, showing the superimposed functional regions h1 / g1, h2 / g2, and h3 / g3 in the functional analysis diagram H / G of the heating stage / vacuum adsorption stage with the recurring abnormal points i1, i2, and i3, respectively. (See diagram below.) Figure 16a As shown, after superimposing the action region h1 / g1 of the action analysis map H / G with the repeated anomaly points i1, i2, and i3, it can be found that the repeated anomaly points i1, i2, and i3 do not overlap with the action region h1 / g1 of the action analysis map H / G. Therefore, it can be determined that the repeated anomaly points i1, i2, and i3 are not the suspected anomaly points. Figure 16b As shown, when the effect area h2 / g2 of the effect analysis map H / G is superimposed with the repeated anomaly points i1, i2, and i3, it can be found that the repeated anomaly points i1, i2, and i3 all overlap with the effect area h2 / g2 of the effect analysis map H / G. Therefore, it can be determined that the repeated anomaly points i1, i2, and i3 are all suspected anomaly points. Figure 16c As shown, when the action region h3 / g3 of the action analysis diagram H / G is superimposed with the repeated anomaly points i1, i2, and i3, it can be found that the repeated anomaly points i1, i2, and i3 do not overlap with the action region h3 / g3 of the action analysis diagram H / G. Therefore, it can be determined that the repeated anomaly points i1, i2, and i3 are not the suspected anomaly points.

[0112] Specifically, in this embodiment, when each of the functional regions in the functional analysis map is superimposed on the repeated anomaly points one by one, the grayscale value of the functional region in the functional analysis map that needs to be superimposed on the repeated anomaly points is 1, and the grayscale value of other regions is 0. When superimposing the functional regions in the functional analysis map with the repeated anomaly points, the functional analysis map and the repeated anomaly map are multiplied to obtain a suspected anomaly map, and the region with a grayscale value of 1 in the suspected anomaly map is the suspected anomaly point.

[0113] It should be understood that multiplying the action analysis map with the repeating anomaly map involves multiplying the grayscale values ​​of each pixel in the action analysis map and the repeating anomaly map to obtain a fourth grayscale map, which is the suspected anomaly map.

[0114] It should be noted that in the action analysis diagram, only the grayscale value of the action area that needs to be superimposed with the repeated anomaly point is 1, and the grayscale value of other areas is 0. In the repeated anomaly diagram, the grayscale value of the repeated anomaly point is 1, and the grayscale value of other areas is 0. When the action analysis diagram and the repeated anomaly diagram are multiplied, only the grayscale value of the repeated anomaly point in the repeated anomaly diagram and the effective action area (the action area that needs to be superimposed) in the action analysis diagram is 1. Therefore, the area with a grayscale value of 1 in the suspected anomaly diagram is the suspected anomaly point.

[0115] Figures 17a-17c This is a schematic diagram of the suspected anomaly diagrams J1, J2, and J3 provided in this embodiment. For example... Figure 11a , Figure 14 and Figure 17a As shown, multiplying the repeating anomaly map I with the action analysis map F1 yields the suspected anomaly map J1. The regions with a grayscale value of 1 in the suspected anomaly map J1 represent the repeating anomaly points i1, i2, and i3; that is, the repeating anomaly points i1, i2, and i3 are the suspected anomaly points. For example... Figure 11b , Figure 14 and Figure 17b As shown, multiplying the repeating anomaly map I with the action analysis map F2 yields the suspected anomaly map J2. The region with a grayscale value of 1 in the suspected anomaly map J2 is the repeating anomaly point i1, meaning that the repeating anomaly point i1 is the suspected anomaly point. For example... Figure 11c , Figure 14 and Figure 17c As shown, the suspected anomaly map J3 is obtained by multiplying the repeated anomaly map I with the action analysis map F3. There is no region with a gray value of 1 in the suspected anomaly map J3, that is, the repeated anomaly points i1, i2 and i3 are not the suspected anomaly points.

[0116] Figures 18a-18c This is a schematic diagram of the suspected anomaly diagrams K1, K2, and K3 provided in this embodiment. For example... Figure 12 / Figure 13 , Figure 14 and Figure 18a As shown, multiplying the repeating anomaly map I with the action analysis map H / G (where the grayscale value of the action region h1 / g1 is 1, and the grayscale value of other regions is 0) yields the suspected anomaly map K1. No region with a grayscale value of 1 exists in the suspected anomaly map K1, meaning that the repeating anomaly points i1, i2, and i3 are not the suspected anomaly points. Figure 12 / Figure 13 , Figure 14 and Figure 18b As shown, the suspected anomaly map K2 is obtained by multiplying the repeating anomaly map I with the effect analysis map H / G (the grayscale value of the effect region h2 / g2 is 1, and the grayscale value of other regions is 0). The regions with a grayscale value of 1 in the suspected anomaly map K2 are the repeating anomaly points i1, i2, and i3, that is, the repeating anomaly points i1, i2, and i3 are the suspected anomaly points. Figure 12 / Figure 13 , Figure 14 and Figure 18cAs shown, the suspected anomaly map K3 is obtained by multiplying the repeated anomaly map I with the action analysis map H / G (the gray value of the action area h3 / g3 is 1, and the gray value of other areas is 0). There is no area with a gray value of 1 in the suspected anomaly map K3, that is, the repeated anomaly points i1, i2, and i3 are not the suspected anomaly points.

[0117] Next, based on the suspected anomalies corresponding to each machine structure, the machine structure that generates the repeated anomalies is determined. In this embodiment, the machine structure whose maximum number of suspected anomalies is greater than a second threshold is determined to be the machine structure that generates the repeated anomalies.

[0118] For example, if the second threshold is set to 2, the maximum number of suspected abnormal points corresponding to the robotic arm in the 0° clamping position is 3, and the maximum number of suspected abnormal points corresponding to the central heating / adsorption areas of the heating platform and the vacuum adsorption platform is also 3, it can be determined that the robotic arm, the heating platform, and the vacuum adsorption platform may all be machine structures that generate the repeated abnormal points. Furthermore, the robotic arm may have an abnormality in the 0° clamping position, and the central heating / adsorption areas of the heating platform and the vacuum adsorption platform may have an abnormality.

[0119] It should be understood that this embodiment is not limited to determining the machine structure that generates the repeated anomalies based on the maximum number of repeated anomalies. Other methods can also be used, such as determining the machine structure that generates the repeated anomalies based on the ratio between the maximum number of suspected anomalies and the total number of anomalies in all the wafer test patterns. Specifically, the machine structure that generates the repeated anomalies can be determined as the machine structure that generates the repeated anomalies if the ratio between the maximum number of suspected anomalies and the total number of anomalies in all the wafer test patterns is greater than a third threshold. In addition, the machine structure that generates the repeated anomalies can also be determined based on the sum of the areas of the suspected anomalies or the size of the largest suspected anomaly. Examples will not be given here.

[0120] After determining the machine structure that generates the recurring anomalies, a wafer warning message can be issued to remind the user that an anomaly has occurred at the process station, and specifically which machine structure at the process station is the source of the anomaly. This allows for timely and accurate detection of whether an anomaly has occurred at the process station, effectively providing early warning of wafer anomalies. Based on the wafer warning message, the user can repair or correct the corresponding machine structure to avoid the generation of batch defective products.

[0121] In summary, in the wafer anomaly early warning method provided by the embodiments of the present invention, when an anomaly occurs at a process station, multiple wafers of the same batch passing through the abnormal process station will have repeated anomaly points at the same location. For each test station, the present invention first obtains several wafer test images of the same batch that need to be analyzed for anomalies at the test station, and then obtains the ratio between the maximum number of wafer test images with repeated anomaly points at the same location and the total number of wafer test images. Then, based on the ratio, it is determined whether a wafer anomaly early warning is needed. In this way, once an anomaly occurs at a process station, it can be detected in a timely and accurate manner, effectively warning of wafer anomalies and avoiding the generation of batch defective products.

[0122] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0123] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0124] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0125] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A wafer abnormality early warning method, characterized by, For each test site, perform the following steps: Obtain test images of several wafers from the same batch that require anomaly analysis at the test site; The method for obtaining the ratio between the maximum number of wafer test images with duplicate anomalies at the same location and the total number of wafer test images includes: in each wafer test image, drawing a circle with the center of each anomaly as the center and half the radius of a preset tolerance as the radius, to obtain a corresponding first anomaly tolerance image; and superimposing all the first anomaly tolerance images, with the maximum number of overlapping circles being the maximum number of wafer test images with duplicate anomalies at the same location; in the first anomaly tolerance image, the grayscale value of the area within the circle is 1, and the grayscale value of other areas is 0; and when superimposing all the first anomaly tolerance images, all the first anomaly tolerance images are added together to obtain a first anomaly tolerance overlay image, the maximum grayscale value in the first anomaly tolerance overlay image being the maximum number of wafer test images with anomalies at the same location; and... Based on the aforementioned percentage, determine whether a wafer anomaly warning is needed; After determining that a wafer anomaly warning is needed, the method further includes: obtaining the location of the repeating anomaly points. The step of obtaining the location of the repeating anomaly points includes: in each wafer test image, drawing a circle with the center of each anomaly point as the center and a preset tolerance as the radius to obtain a corresponding second anomaly tolerance image; superimposing all the second anomaly tolerance images, with the area having the most overlapping circles being the repeating anomaly area; and superimposing the repeating anomaly area with all the anomaly points in the wafer test images, with the anomaly points overlapping the repeating anomaly area being the repeating anomaly points; in the second anomaly tolerance image, the grayscale value of the area within the circle is 1, and the grayscale value of other areas is 0; superimposing all the second anomaly... When overlaying constant tolerance maps, all second abnormal tolerance maps are added together to obtain a second abnormal tolerance overlay map. The region with the largest gray value in the second abnormal tolerance overlay map is the repeating abnormal region. Furthermore, the gray value of the abnormal point in the wafer test map is 1, and the gray value of other regions is 0. When overlaying the repeating abnormal region with all abnormal points in the wafer test maps, first set the gray value of the repeating abnormal region in the second abnormal tolerance overlay map to 1, and set the gray value of other regions to 0. Then multiply the second abnormal tolerance overlay map by the sum of all the wafer test maps to obtain a repeating abnormal map. The position with a gray value of 1 in the repeating abnormal map is the repeating abnormal point.

2. The wafer abnormality early warning method according to claim 1, wherein The wafer test pattern is a wafer defect test pattern, and the abnormal points in the wafer test pattern are the locations of defects; or, the wafer test pattern is a wafer electrical test pattern, and the abnormal points in the wafer test pattern are the locations of defective dies; or, the wafer test pattern is a wafer parameter test pattern, and the abnormal points in the wafer test pattern are the locations of parameter abnormalities.

3. The wafer anomaly early warning method as described in claim 1, characterized in that, When the number of abnormal points in the wafer test pattern is less than a first threshold, it is determined that the wafer test pattern needs to be analyzed for abnormalities.

4. The wafer anomaly early warning method as described in claim 1, characterized in that, After obtaining the location of the repeated anomaly points, the method further includes: The source of the anomaly is obtained based on the location of the repeated anomaly.

5. The wafer anomaly early warning method as described in claim 4, characterized in that, The steps for obtaining the anomaly source of the repeated anomaly point based on its location include: Obtain all machine structures in the process station corresponding to the test station that could cause wafer abnormalities; Obtain an analysis diagram of the effect of each of the machine structure on the wafer. The analysis diagram has several effect regions, which are used to characterize the surface of the machine structure on the wafer. Each of the action regions in each action analysis map is superimposed on the repeating anomalies one by one; the repeating anomalies that overlap with the action regions are suspected anomalies; and... The machine structure that generates the repeated anomaly point is determined based on the suspected anomaly point corresponding to each of the machine structures.

6. The wafer anomaly early warning method as described in claim 5, characterized in that, The machine tool structure includes a robotic arm, and the action analysis diagram includes a projection image of each clamping position of the robotic arm on the wafer; and / or, the machine tool structure includes a heating stage, and the action analysis diagram includes a projection image of all heating areas of the heating stage on the wafer; and / or, the machine tool structure includes a vacuum adsorption stage, and the action analysis diagram includes a projection image of all adsorption areas of the vacuum adsorption stage on the wafer.

7. The wafer anomaly early warning method as described in claim 5, characterized in that, In the effect analysis diagram, the grayscale value of the effect area that needs to be superimposed on the repeated anomaly point is 1, and the grayscale value of other areas is 0; and, When the effect region of the effect analysis map is superimposed with the repeated anomaly point, the effect analysis map is multiplied by the repeated anomaly map to obtain a suspected anomaly map, and the area with a gray value of 1 in the suspected anomaly map is the suspected anomaly point.

8. The wafer anomaly early warning method according to any one of claims 5 to 7, characterized in that, The machine structure that is determined to generate the repeated anomalies is determined to be the machine structure that generates the repeated anomalies if the maximum number of suspected anomalies is greater than the second threshold; or, the machine structure that is determined to generate the repeated anomalies is the machine structure that generates the repeated anomalies if the ratio between the maximum number of suspected anomalies and the total number of anomalies in all the wafer test patterns is greater than the third threshold.

9. The wafer anomaly early warning method as described in claim 1, characterized in that, When the percentage exceeds the fourth threshold, it is determined that a wafer anomaly warning is required.

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