Semiconductor package structure

Abstract

Semiconductor package structures are provided that allow for greater flexibility in the design of the semiconductor package structures. In one embodiment, a semiconductor package structure can include a base substrate having a wiring structure, a redistribution layer disposed on the base substrate, a first semiconductor chip disposed on the redistribution layer, and a first capacitor disposed in the base substrate and electrically coupled to the first semiconductor chip, wherein the first capacitor includes a first capacitor substrate having a first top surface and a first bottom surface, at least one first capacitor cell disposed in the first capacitor substrate, and a first via disposed in the first capacitor substrate, the first via electrically coupling the at least one first capacitor cell to the wiring structure of the base substrate located on the first top surface and the first bottom surface of the first capacitor substrate.

Description

Technical Field

[0001] This invention relates to semiconductor packaging technology, and in particular to a semiconductor packaging structure including a capacitor. Background Technology

[0002] The power supply provides the voltage required for the operation of electronic circuits. During operation, the power supply voltage may provide transient currents of relatively high intensity, causing the electronic circuits to malfunction. To provide a more stable power supply, one or more decoupling capacitors are connected between the power supply voltage and ground to provide a bypass path for transient currents. In other words, the decoupling capacitors act as temporary charge storage devices.

[0003] Furthermore, decoupling capacitors can reduce the impact of electromagnetic interference (EMI) and improve signal performance by stabilizing current flow. As semiconductor packaging structures become increasingly miniaturized, EMI problems are escalating, making decoupling capacitors even more crucial.

[0004] While existing semiconductor packaging structures generally meet the requirements, they are not entirely satisfactory in every aspect. For example, the bump structure of the land-side capacitor (LSC) is removed. This reduces current density and heat dissipation paths. Heat is generated during the operation of a semiconductor die. If this heat is not adequately dissipated, the elevated temperature can damage one or more semiconductor components. Therefore, further improvements to semiconductor packaging structures are needed. Summary of the Invention

[0005] This invention provides a semiconductor packaging structure that allows for greater flexibility in semiconductor packaging design.

[0006] In one embodiment, a semiconductor package structure may include: a base substrate having a wiring structure; a redistribution layer disposed on the base substrate; a first semiconductor chip disposed on the redistribution layer; and a first capacitor disposed in the base substrate and electrically coupled to the first semiconductor chip, wherein the first capacitor includes: a first capacitor substrate having a first top surface and a first bottom surface; at least one first capacitor cell disposed in the first capacitor substrate; and a first via disposed in the first capacitor substrate, the first via electrically coupling the at least one first capacitor cell to the wiring structure of the base substrate located on the first top surface and the first bottom surface of the first capacitor substrate.

[0007] In another embodiment, a semiconductor package structure may include: a base substrate having a wiring structure; a redistribution layer disposed on the base substrate; a first semiconductor chip and a second semiconductor chip disposed on the redistribution layer; and a first multi-capacitor structure disposed between the redistribution layer and the base substrate and electrically coupled to the first semiconductor chip and the second semiconductor chip, wherein the first multi-capacitor structure includes: a capacitor substrate; a plurality of capacitor units disposed in the capacitor substrate; and a first via disposed in the capacitor substrate and electrically coupled to the wiring structure of the redistribution layer and the base substrate.

[0008] As described above, the semiconductor package structure of this embodiment includes a capacitor with a through-hole, which allows the capacitor to be electrically coupled to other components on both surfaces of the capacitor. This provides greater flexibility in the design of the semiconductor package structure. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of a capacitor 100 according to some embodiments of the present invention.

[0010] Figure 2 This is a cross-sectional view of a semiconductor package structure 200 according to some embodiments of the present invention.

[0011] Figure 3 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention.

[0012] Figure 4 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention.

[0013] Figure 5 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention.

[0014] Figure 6 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention.

[0015] Figure 7 This is a cross-sectional view of a capacitor 700 according to some embodiments of the present invention.

[0016] Figure 8 This is a cross-sectional view of a capacitor 800 according to some embodiments of the present invention.

[0017] Figure 9 This is a cross-sectional view of a semiconductor package structure 900 according to some embodiments of the present invention. Detailed Implementation

[0018] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.

[0019] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto and is defined only by the claims. The described drawings are illustrative only and are not restrictive. In the drawings, the dimensions of some components may be exaggerated for illustrative purposes and are not drawn to scale. These dimensions and relative dimensions do not correspond to actual dimensions in the practice of the invention.

[0020] The present invention can add additional components to the following embodiments. For example, the description of "forming a first component on a second component" can include embodiments in which the first component and the second component are in direct contact, or embodiments in which an additional component is disposed between the first component and the second component so that the first component and the second component are not in direct contact. Furthermore, the spatial relative relationship between the first component and the second component can change as the device is operated or used in different directions.

[0021] In the following description, the phrase "first component extending through second component" can include embodiments in which the first component is disposed within the second component and extends from one side of the second component to the opposite side of the second component, wherein the surface of the first component may be flush with the surface of the second component, or the surface of the first component may be outside the surface of the second component. Furthermore, the same reference numerals and / or letter designations may be repeated in various embodiments of the invention. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments discussed.

[0022] According to some embodiments of the present invention, a semiconductor package structure including a capacitor is described. The capacitor of the present invention includes a through-via penetrating the capacitor substrate, which allows the capacitor to be electrically coupled to other components on both surfaces of the capacitor. This provides greater flexibility in design.

[0023] Figure 1 This is a cross-sectional view of a capacitor 100 according to some embodiments of the present invention. For the sake of simplicity, Figure 1 Only a portion of capacitor 100 is shown. Additional features can be added to capacitor 100. Furthermore, some features described below can be replaced or eliminated for different embodiments.

[0024] like Figure 1As shown, according to some embodiments, capacitor 100 includes capacitor substrate 102. Capacitor substrate 102 may be a semiconductor substrate. Capacitor substrate 102 may include bulk semiconductor, compound semiconductor, alloy semiconductor, or the like, or combinations thereof. Capacitor substrate 102 may be formed of any suitable semiconductor material, such as silicon. Capacitor substrate 102 may be doped (e.g., using p-type or n-type dopants) or undoped. Capacitor substrate 102 has a first surface 102a and a second surface 102b opposite thereto.

[0025] like Figure 1 As shown, according to some embodiments, capacitor 100 includes a multi-capacitor structure to reduce the space occupied by the capacitor. For example, capacitor 100 has a plurality of capacitor cells 104 embedded in capacitor substrate 102. (In a specific implementation, each capacitor cell 104 may include at least a first electrode, a second electrode, and a dielectric layer for isolating the two electrodes; for example, each capacitor cell 104 may be...) Figure 7 or Figure 8 The illustrated metal-insulator-metal (MIM) structure 708. Some capacitor cells 104 may be adjacent to the first surface 102a of the capacitor substrate 102, while other capacitor cells 104 may be adjacent to the second surface 102b of the capacitor substrate 102. It should be noted that the configuration and number of capacitor cells 104 in the multi-capacitor structure shown in the figure are merely exemplary and are not intended to limit the invention.

[0026] like Figure 1 As shown, capacitor 100 may have one or more power lines 106 and one or more ground lines 108, which may be electrically coupled to capacitor cell 104. The power lines 106 and ground lines 108 may be formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof. Each capacitor cell 104 may be electrically coupled to the power line 106 and ground line 108 located on opposite sides of the capacitor cell 104.

[0027] like Figure 1 As shown, according to some embodiments, capacitor 100 has one or more through-holes 110 disposed in capacitor substrate 102 and electrically coupled to power line 106 and ground line 108. The through-holes 110 may be formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof.

[0028] like Figure 1 As shown, according to some embodiments, the via 110 extends from a first surface 102a of the capacitor substrate 102 to a second surface 102b. As a result, the capacitor 100 can be electrically coupled to other components on both the first surface 102a and the second surface 102b. Compared to embodiments where the capacitor is electrically coupled to components on a single surface, the capacitor 100 of the present invention offers greater flexibility in the design of semiconductor package structures. Furthermore, current density can be increased, and heat dissipation efficiency can be improved.

[0029] like Figure 1 As shown, according to some embodiments, capacitor 100 has one or more power terminals 112 and ground terminals 116 on a first surface 102a of capacitor substrate 102, and one or more power terminals 114 and ground terminals 118 on a second surface 102b of capacitor substrate 102. The power terminals 112, 114 and the ground terminals 116, 118 can be electrically coupled to capacitor cell 104 via power line 106, ground line 108, and through-hole 110. The power terminals 112, 114 and the ground terminals 116, 118 can be formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof.

[0030] The dimensions (e.g., width) of power terminals 112, 114 and ground terminals 116, 118 may depend on the components they are electrically coupled to. For example, as Figure 1 As shown, in some embodiments where there are more components electrically coupled to capacitor 100 on the second surface 102b than on the first surface 102a, the dimensions (e.g., width) of power terminal 114 and ground terminal 118 may be larger than the dimensions (e.g., width) of power terminal 112 and ground terminal 116.

[0031] Figure 2 This is a cross-sectional view of a semiconductor package structure 200 according to some embodiments of the present invention. For simplicity, only a portion of the semiconductor package structure 200 is shown. Additional features may be added to the semiconductor package structure 200. For different embodiments, some features described below may be replaced or eliminated. In the following embodiments, the semiconductor package structure 200 includes one or more capacitors having one or more through-holes.

[0032] like Figure 2As shown, according to some embodiments, the semiconductor package structure 200 includes a substrate 202. The substrate 202 can be a coreless substrate or a cored substrate to prevent warping. The substrate 202 may have a wiring structure 204. In some embodiments, the wiring structure 204 includes a conductive pad, a conductive via, a conductive line, a conductive pillar, or the like, or a combination thereof. The wiring structure 204 may be formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof.

[0033] The wiring structure 204 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer can be formed of organic materials (e.g., polymer substrates), inorganic materials (including silicon nitride, silicon oxide, silicon oxynitride), or the like, or combinations thereof.

[0034] It should be noted that the configuration of substrate 202 shown in the figure is merely exemplary and is not intended to limit the invention. Any desired semiconductor component can be formed in and on substrate 202. However, for the sake of simplicity, only a flat substrate 202 is shown.

[0035] like Figure 2 As shown, according to some embodiments, the semiconductor package structure 200 includes a redistribution layer 210 disposed on a substrate 202. The redistribution layer 210 may include one or more conductive layers 212 disposed within one or more passivation layers. The conductive layers 212 may be formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof. In some embodiments, the passivation layer includes a polymer layer, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, or the like, or combinations thereof. Alternatively, the passivation layer may include a dielectric layer, including silicon oxide, silicon nitride, silicon oxynitride, or the like, or combinations thereof.

[0036] like Figure 2As shown, according to some embodiments, the semiconductor package structure 200 includes a plurality of bump structures 208 disposed between the redistribution layer 210 and the substrate 202 and electrically coupling the redistribution layer 210 to the substrate 202. The bump structures 208 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or the like, or combinations thereof. The bump structures 208 may be formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof.

[0037] like Figure 2 As shown, according to some embodiments, the semiconductor package structure 200 includes one or more semiconductor chips 218 disposed on the redistribution layer 210. In some embodiments, the semiconductor chip 218 includes a system-on-a-chip (SoC) chip, a logic device, a memory device, a radio frequency (RF) device, or the like, or any combination thereof. For example, the semiconductor chip 218 may include a microcontroller unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a global positioning system (GPS) device, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (I / O) chip, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), etc., or any combination thereof.

[0038] Semiconductor chip 218 may include a single semiconductor chip or two or more semiconductor chips stacked vertically. In some embodiments, semiconductor package structure 200 may also include one or more passive components (not shown) adjacent to semiconductor chip 218, such as resistors, capacitors, inductors, or the like, or combinations thereof.

[0039] like Figure 2 As shown, according to some embodiments, the semiconductor package structure 200 includes a plurality of bump structures 216 disposed between a semiconductor chip 218 and a redistribution layer 210 and electrically coupling the semiconductor chip 218 to the redistribution layer 210. The bump structures 216 may include microbumps, controlled-collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or the like, or combinations thereof. The bump structures 216 may be formed of conductive materials, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof.

[0040] like Figure 2 As shown, according to some embodiments, the semiconductor package structure 200 includes one or more capacitors electrically coupled to the semiconductor chip 218. In one embodiment, the semiconductor package structure 200 includes a capacitor 220 embedded in a substrate 202. The capacitor 220 can be electrically coupled to the semiconductor chip 218 via wiring structure 204, bump structure 208, conductive layer 212 of redistribution layer 210, and bump structure 216 of substrate 202. (Refer to...) Figure 3 This embodiment is described.

[0041] Figure 3 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention. Figure 3 Some of the components shown can be similar to Figure 2 Some components of the semiconductor package structure 200 shown are illustrated. For simplicity, these components will not be discussed in detail.

[0042] like Figure 3 As shown, the wiring structure 204 of the substrate 202 may have a power supply component 204a and a ground component 204b, each of which may include a conductive pad, a conductive via, a conductive wire, a conductive post, or the like, or a combination thereof. Figure 3 As shown, according to some embodiments, conductive vias of the power supply assembly 204a and the grounding assembly 204b are disposed on two surfaces of the capacitor 220 and electrically coupled to the capacitor cell through the vias of the capacitor 220. Figure 3 As shown, capacitor 220 can be Figure 1 The capacitor 100 shown includes a multi-capacitor structure. However, this is not a limitation of the invention. In other embodiments, the capacitor 220 may also be other capacitors without a multi-capacitor structure. For example, the capacitor 220 may include only one capacitor unit 104, or the capacitor 220 may be... Figure 7 and Figure 8The capacitor shown includes a through-hole that extends through the capacitor substrate, allowing the capacitor to be electrically coupled to other components on both surfaces of the capacitor. All capacitors are within the protection scope of the capacitor 220 of this invention.

[0043] In some embodiments, the conductive vias of the power supply component 204a and the grounding component 204b can contact the two surfaces of the capacitor 220 and electrically couple the capacitor 220 to the conductive lines of the power supply component 204a and the grounding component 204b. Alternatively, in another embodiment, the conductive lines of the power supply component 204a and the grounding component 204b can contact the two surfaces of the capacitor 220.

[0044] like Figure 3 As shown, the semiconductor package structure 200 may also include a capacitor 232 disposed beneath the substrate 202 and electrically coupled to the wiring structure 204. The capacitor 232 may be an integrated passive device (IPD) to enhance electrical properties.

[0045] Refer again Figure 2 In one embodiment, the semiconductor package structure 200 includes a capacitor 222 and a plurality of bump structures 224 located between the redistribution layer 210 and the substrate 202. The bump structures 224 may be disposed on two surfaces of the capacitor 222. The capacitor 222 can be electrically coupled to the semiconductor chip 218 via the bump structures 224, the conductive layer 212 of the redistribution layer 210, and the bump structures 216. (Refer to...) Figure 4 This embodiment is described.

[0046] Figure 4 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention. Figure 4 Some of the components shown can be similar to Figure 2 Some components of the semiconductor package structure 200 shown are illustrated. For simplicity, these components will not be discussed in detail.

[0047] like Figure 4 As shown, according to some embodiments of the present invention, capacitor 222 is electrically coupled to bump structure 224, wherein a first surface of capacitor 222 is electrically coupled to a first bump structure 224a, and a second surface of capacitor 222 is electrically coupled to a second bump structure 224b. The first bump structure 224a can electrically couple capacitor 222 to redistribution layer 210, while the second bump structure 224b can electrically couple capacitor 222 to substrate 202. Figure 4 As shown, capacitor 222 can be Figure 1The capacitor 100 shown includes a multi-capacitor structure. However, this is not a limitation of the invention. In other embodiments, capacitor 222 may also be other capacitors without a multi-capacitor structure. For example, capacitor 222 may include only one capacitor unit 104, or capacitor 222 may be... Figure 7 and Figure 8 The capacitor shown includes a through-hole that penetrates the capacitor substrate, allowing the capacitor to be electrically coupled to other components on both surfaces of the capacitor. All capacitors are within the protection scope of capacitor 222 of this invention.

[0048] Since capacitor 222 can be connected on both surfaces, bump structures 224 can be maintained on both surfaces of capacitor 222. Therefore, heat dissipation paths can be increased, and heat dissipation efficiency can be improved. Furthermore, a semiconductor package structure with high current density can be achieved. Additionally, the pinout can be freely assigned.

[0049] Since the first bump structure 224a and the second bump structure 224b can be electrically coupled to different components, the dimensions (e.g., width) of the first bump structure 224a and the second bump structure 224b can be different. For example, as Figure 4 As shown, the size (e.g., width) of the second bump structure 224b can be larger than the size (e.g., width) of the first bump structure 224a.

[0050] like Figure 4 As shown, the total thickness of a first bump structure 224a, a second bump structure 224b, and a capacitor 222 can be substantially equal to the thickness of a bump structure 208.

[0051] Although not shown, an underfill material may be formed between the redistribution layer 210 and the substrate 202, and the underfill material may fill the gap between the capacitor 222 and the bump structures 208 and 224 to provide structural support. The underfill material may surround the capacitor 222 and each of the bump structures 208 and 224. In some embodiments, the underfill material is formed of a polymer such as epoxy resin. The underfill material may be distributed by capillary force and then cured by any suitable curing process.

[0052] Refer again Figure 2 In one embodiment, the semiconductor package structure 200 includes a capacitor 226 embedded in the redistribution layer 210. The capacitor 226 can be electrically coupled to the semiconductor chip 218 via the conductive layer 212 and bump structure 216 of the redistribution layer 210. (Refer to...) Figure 5 This embodiment is described.

[0053] Figure 5 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention. Figure 5 Some of the components shown can be similar to Figure 2 Some components of the semiconductor package structure 200 shown are illustrated. For simplicity, these components will not be discussed in detail.

[0054] like Figure 5 As shown, the conductive layer 212 of the redistribution layer 210 may have a power supply component 212a and a grounding component 212b, which may include conductive pads, conductive vias, conductive wires, conductive posts, or the like, or combinations thereof. Figure 5 As shown, according to some embodiments, conductive vias of the power supply assembly 212a and the grounding assembly 212b are disposed on two surfaces of the capacitor 226 and electrically coupled to the capacitor cell through the vias of the capacitor 226. Figure 5 As shown, capacitor 226 can be Figure 1 The capacitor 100 shown includes a multi-capacitor structure. However, this is not a limitation of the invention. In other embodiments, capacitor 226 may also be other capacitors without a multi-capacitor structure. For example, capacitor 226 may include only one capacitor unit 104, or capacitor 226 may be... Figure 7 and Figure 8 The capacitor shown includes a through-hole that extends through the capacitor substrate, allowing the capacitor to be electrically coupled to other components on both surfaces of the capacitor. All capacitors are within the protection scope of capacitor 226 of this invention.

[0055] In some embodiments, the conductive vias of the power supply assembly 212a and the grounding assembly 212b may contact the two surfaces of the capacitor 226 and electrically couple the capacitor 226 to the conductive lines of the power supply assembly 212a and the grounding assembly 212b. Alternatively, in another embodiment, the conductive lines of the power supply assembly 212a and the grounding assembly 212b may contact the two surfaces of the capacitor 226.

[0056] Refer again Figure 2 In one embodiment, the semiconductor package structure 200 includes a capacitor 228 and a plurality of bump structures 230 located between a semiconductor chip 218 and a redistribution layer 210. The bump structures 230 may be disposed on two surfaces of the capacitor 228. The capacitor 228 can be electrically coupled to the semiconductor chip 218 through the bump structures 230. (Refer to...) Figure 6 This embodiment is described.

[0057] Figure 6 This is a cross-sectional view of a portion of a semiconductor package structure according to some embodiments of the present invention. Figure 6 Some of the components shown can be similar to Figure 2 Some components of the semiconductor package structure 200 shown are illustrated. For simplicity, these components will not be discussed in detail.

[0058] like Figure 6 As shown, according to some embodiments of the present invention, capacitor 228 is electrically coupled to bump structure 230, wherein a first surface of capacitor 228 is electrically coupled to first bump structure 230a, and a second surface of capacitor 228 is electrically coupled to second bump structure 230b. First bump structure 230a can electrically couple capacitor 228 to semiconductor chip 218, and second bump structure 224b can electrically couple capacitor 228 to redistribution layer 210. Figure 6 As shown, capacitor 228 can be Figure 1 The capacitor 100 shown includes a multi-capacitor structure. However, this is not a limitation of the invention. In other embodiments, capacitor 228 may also be other capacitors without a multi-capacitor structure. For example, capacitor 228 may include only one capacitor unit 104, or capacitor 228 may be... Figure 7 and Figure 8 The capacitor shown includes a through-hole that extends through the capacitor substrate, allowing the capacitor to be electrically coupled to other components on both surfaces of the capacitor. All capacitors are within the protection scope of capacitor 228 of this invention.

[0059] As described above, since the first bump structure 230a and the second bump structure 230b can be electrically coupled to different components, the dimensions (e.g., width) of the first bump structure 230a and the second bump structure 230b can be different. For example, as Figure 6 As shown, the size (e.g., width) of the second bump structure 230b can be larger than the size (e.g., width) of the first bump structure 230a.

[0060] like Figure 6 As shown, the total thickness of a first bump structure 230a, a second bump structure 230b, and a capacitor 228 can be substantially equal to the thickness of a bump structure 216.

[0061] Although not shown, an underfill material may be formed between the semiconductor chip 218 and the redistribution layer 210, and the underfill material may fill the gap between the capacitor 228 and the bump structures 216 and 230 to provide structural support. The underfill material may surround the capacitor 228 and each of the bump structures 216 and 230. In some embodiments, the underfill material is formed of a polymer such as epoxy resin. The underfill material may be distributed by capillary force and then cured by any suitable curing process.

[0062] Refer again Figure 2Although capacitors 220, 222, 226, and 228 are described separately, the semiconductor package structure 200 may include more than one capacitor 220, 222, 226, and 228, each of which may be electrically coupled to each semiconductor chip 218. For example, in one embodiment, the semiconductor package structure 200 may include capacitors 220 and 222, wherein capacitor 220 is electrically coupled to one semiconductor chip 218, and capacitor 222 is electrically coupled to another semiconductor chip 218. Alternatively, in one embodiment, the semiconductor package structure 200 may include two capacitors 228, wherein one capacitor 228 may be disposed below and electrically coupled to one semiconductor chip 218, and the other capacitor 228 may be disposed below and electrically coupled to another semiconductor chip 218.

[0063] Figure 7 This is a cross-sectional view of a capacitor 700 according to some embodiments of the present invention. For simplicity, only a portion of the capacitor 700 is shown. Additional features may be added to the capacitor 700. For different embodiments, some features described below may be replaced or eliminated. In the following embodiments, a capacitor 700 with a through-hole will be described.

[0064] like Figure 7 As shown, according to some embodiments, capacitor 700 includes capacitor substrate 702. Capacitor substrate 702 can be similar to... Figure 1 The capacitor substrate 102 shown is not described in detail here.

[0065] like Figure 7 As shown, according to some embodiments, capacitor 700 includes an insulating layer 704 covering the sidewalls of an opening. The insulating layer 704 can extend from a first surface of capacitor substrate 702 to a second surface through the sidewalls of the opening. In some embodiments, the insulating layer 704 is formed of an insulating material, including silicon oxide, silicon nitride, silicon oxynitride, or the like, or combinations thereof.

[0066] like Figure 7 As shown, according to some embodiments, capacitor 700 includes one or more through-holes 706 embedded in capacitor substrate 702. The through-holes 706 may be disposed in an opening and extend through capacitor substrate 702. Each through-hole 706 may be surrounded by an insulating layer 704. In some embodiments, the through-holes 706 are formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof.

[0067] like Figure 7As shown, according to some embodiments, capacitor 700 includes a metal-insulator-metal (MIM) structure 708 embedded in capacitor substrate 702. The MIM structure 708 may be disposed in trenches and may include a first electrode 710, an interlayer dielectric layer 712, and a second electrode 714. In some embodiments, the first electrode 710 and the second electrode 714 are each independently formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof. The first electrode 710 and the second electrode 714 may be made of the same material or different materials. According to some embodiments, the interlayer dielectric layer 712 is formed of a high-k dielectric material such as aluminum oxide.

[0068] Capacitor 700 can be used as such Figure 2 The semiconductor package structure 200 shown includes one or more of capacitors 220, 222, 226, and 228. Specifically, as described above, capacitor 700 may be embedded in the substrate, disposed between the substrate and the redistribution layer, embedded in the redistribution layer, disposed between the redistribution layer and the semiconductor chip, or multiple capacitors 700 may be simultaneously disposed in the aforementioned different locations. These details will not be described again in detail.

[0069] Figure 8 This is a cross-sectional view of a capacitor 800 according to some embodiments of the present invention. For simplicity, only a portion of the capacitor 800 is shown. Additional features may be added to the capacitor 800. For different embodiments, some features described below may be replaced or eliminated. In the following embodiments, a capacitor 800 having a through-hole and a metal-insulator-metal (MIM) structure surrounding the through-hole will be described.

[0070] like Figure 8 As shown, according to some embodiments, capacitor 800 includes capacitor substrate 802, insulating layer 804, and one or more through holes 806. The capacitor substrate 802, insulating layer 804, and through holes 806 may each be similar to... Figure 7 The capacitor substrate 702, insulating layer 704, and through-hole 706 shown are not described in detail here.

[0071] like Figure 8As shown, according to some embodiments, capacitor 800 includes a metal-insulator-metal (MIM) structure 808 embedded in capacitor substrate 802 and disposed between insulating layer 804 and via 806. MIM structure 808 may include a first electrode 810, an interlayer dielectric layer 812, and a second electrode 814. In some embodiments, the first electrode 810 and the second electrode 814 are each independently formed of a conductive material, including copper, aluminum, tungsten, or the like, or alloys thereof, or combinations thereof. The first electrode 810 and the second electrode 814 may be made of the same material or different materials. In some embodiments, the interlayer dielectric layer 812 is formed of a high-k dielectric material such as alumina.

[0072] like Figure 8 As shown, according to some embodiments, capacitor 800 includes a barrier layer 816 embedded in capacitor substrate 802 and disposed between insulating layer 804 and via 806. Barrier layer 816 may surround each of via 806 and serve as a diffusion barrier layer. Barrier layer 816 may include titanium nitride or any suitable material.

[0073] Capacitor 800 can be used as such Figure 2 The semiconductor package structure 200 shown includes one or more of capacitors 220, 222, 226, and 228. Specifically, as described above, capacitor 800 may be embedded in the substrate, disposed between the substrate and the redistribution layer, embedded in the redistribution layer, disposed between the redistribution layer and the semiconductor chip, or multiple capacitors 800 may be simultaneously disposed in the aforementioned different locations. These details will not be described again in detail.

[0074] Figure 9 This is a cross-sectional view of a semiconductor package structure 900 according to some embodiments of the present invention. For simplicity, only a portion of the semiconductor package structure 900 is shown. Additional features may be added to the semiconductor package structure 900. For different embodiments, some features described below may be replaced or eliminated. In the following embodiments, the semiconductor package structure 900 includes a capacitor having one or more through-holes, wherein the capacitor includes a multi-capacitor structure to reduce the space occupied by the capacitor.

[0075] like Figure 9 As shown, according to some embodiments, the semiconductor package structure 900 includes a substrate 902. The substrate 902 may be similar to... Figure 2 The substrate 202 shown is not described in detail here.

[0076] like Figure 9As shown, according to some embodiments, the semiconductor package structure 900 includes a redistribution layer 906, which may include multiple conductive layers RDL1, RDL2, RDL3, and RDL4. The four conductive layers RDL1, RDL2, RDL3, and RDL4 are shown for illustrative purposes only, and there may be more or fewer than four conductive layers. The redistribution layer 906 can be similar to... Figure 2 The redistribution layer 210 is shown. Conductive layers RDL1, RDL2, RDL3, and RDL4 can each be similar to... Figure 2 The conductive layer 212 shown is not described in detail here.

[0077] like Figure 9 As shown, according to some embodiments, the semiconductor package structure 900 includes a plurality of bump structures 904 disposed between a redistribution layer 906 and a substrate 902, electrically coupling the redistribution layer 906 to the substrate 902. The bump structures 904 may be similar to... Figure 2 The bump structure 208 shown will not be described in detail.

[0078] like Figure 9 As shown, according to some embodiments, the semiconductor package structure 900 includes a first semiconductor chip 908 and a second semiconductor chip 910 vertically stacked on a redistribution layer 906. The first semiconductor chip 908 and the second semiconductor chip 910 may each be similar to... Figure 2 The semiconductor chip 218 shown is not described in detail here.

[0079] It should be noted that the two semiconductor chips 908 and 910 are shown for illustrative purposes only, and the semiconductor package structure 900 may include more than two semiconductor chips. Furthermore, according to some embodiments, the semiconductor package structure 900 includes one or more passive components (not shown) adjacent to the semiconductor chips 908 and 910, such as resistors, capacitors, inductors, or the like, or combinations thereof.

[0080] like Figure 9 As shown, the first semiconductor chip 908 may have a first XPU (a general term for various processors such as CPU, GPU, DPU) core 908a, and the second semiconductor chip 910 may have a second XPU core 910a. The first XPU core 908a may be electrically coupled to the redistribution layer 906, and the second XPU core 910a may be electrically coupled to the redistribution layer 906 through multiple vias in the first semiconductor chip 908.

[0081] like Figure 9 As shown, according to some embodiments, the semiconductor package structure 900 includes a multi-capacitor structure 912 and a plurality of bump structures 914 between a redistribution layer 906 and a substrate 902. The multi-capacitor structure 912 may be similar to Figure 1 The capacitor shown is 100, so it will not be described in detail again.

[0082] like Figure 9 As shown, the bump structure 914 can be disposed on both surfaces of the multi-capacitor structure 912. The multi-capacitor structure 912 can be electrically coupled to the first semiconductor chip 908 and the second semiconductor chip 910 through the bump structure 914 and the redistribution layer 906. As described above, the semiconductor package structure 900 can include more than two semiconductor chips, therefore the multi-capacitor structure 912 can be electrically coupled to more than two semiconductor chips.

[0083] As described above, since the bump structures 914 on different surfaces of the multi-capacitor structure 912 can be electrically coupled to different components, the dimensions (e.g., width) of the bump structures 914 on different surfaces of the multi-capacitor structure 912 can be different. For example, the dimensions (e.g., width) of the bump structure 914 connecting the multi-capacitor structure 912 to the substrate 902 can be larger than the dimensions (e.g., width) of the bump structure 914 connecting the multi-capacitor structure 912 to the redistribution layer 906.

[0084] Although not shown, an underfill material may be formed between the redistribution layer 906 and the substrate 902, and the underfill material may fill the gaps between the multi-capacitor structure 912 and the bump structures 904 and 914 to provide structural support. The underfill material may surround each of the multi-capacitor structure 912 and the bump structures 904 and 914. In some embodiments, the underfill material is formed of a polymer such as epoxy resin. The underfill material may be distributed by capillary force and then cured by any suitable curing process.

[0085] It should be noted that the multi-capacitor structure 912 disposed between the redistribution layer 906 and the substrate 902 is shown for illustrative purposes only, and the multi-capacitor structure 912 can be configured as follows: Figure 2 The semiconductor package structure 200 shown includes capacitors 220, 222, 226, or 228. That is, as described above, the multi-capacitor structure 912 can be embedded in the substrate 902, disposed between the substrate 902 and the redistribution layer 906, embedded in the redistribution layer 906, disposed between the redistribution layer 906 and the semiconductor chips 908 and 910, or multiple multi-capacitor structures 912 can be simultaneously disposed in the aforementioned different locations. These details will not be described in detail again.

[0086] Furthermore, the semiconductor package structure 900 may include more than one multi-capacitor structure and more than two semiconductor chips. It should be understood that in embodiments where the semiconductor package structure 900 has more than one capacitor, not all capacitors are necessarily multi-capacitor structures. Some capacitors may be multi-capacitor structures electrically coupled to two or more semiconductor chips, and some capacitors may be electrically coupled to a single semiconductor chip.

[0087] Compared to embodiments where semiconductor package structures include separate capacitors for different semiconductor chips, semiconductor package structure 900 uses a multi-capacitor structure 912 electrically coupled to at least two semiconductor chips, which can reduce the space occupied by capacitors. Furthermore, it allows for greater flexibility in design.

[0088] In summary, in some embodiments, the semiconductor package structure according to the present invention includes a capacitor with through-holes for electrically coupling to other components on both surfaces of the capacitor. Therefore, the capacitor can serve as a heat dissipation path, ultimately improving heat dissipation efficiency. Furthermore, high current density semiconductor package structures can be achieved. Additionally, the pinout can be freely assigned, thus providing greater flexibility in the design of the semiconductor package structure.

[0089] Additionally, in some embodiments, the semiconductor package structure according to the invention includes a multi-capacitor structure that can be electrically coupled to two or more semiconductor chips. As a result, multiple capacitors can be integrated, reducing the space occupied by the capacitors and providing greater flexibility in design.

[0090] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (which will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor packaging structure, characterized in that, include: A base substrate with wiring structure; A redistribution layer disposed on the base substrate; The first semiconductor chip disposed on the redistribution layer; and A first capacitor disposed in the base substrate and electrically coupled to the first semiconductor chip, wherein the first capacitor comprises: A first capacitor substrate having a first top surface and a first bottom surface; At least one first capacitor cell disposed in the first capacitor substrate; and A first through-hole is disposed in the first capacitor substrate, the first through-hole electrically couples at least one first capacitor cell to the wiring structure of the base substrate located on the first top surface and the first bottom surface of the first capacitor substrate; The semiconductor packaging structure also includes: A plurality of first bump structures are disposed between the redistribution layer and the base substrate, the first bump structures electrically connecting the redistribution layer to the base substrate; A second capacitor is located adjacent to the plurality of first bump structures and is electrically connected to the first semiconductor chip; Multiple second bump structures and multiple third bump structures are respectively disposed on two surfaces of the second capacitor, wherein the multiple second bump structures electrically couple the second capacitor to the redistribution layer, and the multiple third bump structures electrically couple the second capacitor to the base substrate, and the size of the multiple third bump structures is larger than the size of the multiple second bump structures.

2. The semiconductor packaging structure as described in claim 1, characterized in that, The second capacitor includes: Second capacitor substrate; At least one second capacitor cell disposed in the second capacitor substrate; and A second via is disposed in the second capacitor substrate, the second via electrically coupling at least one second capacitor cell to the redistribution layer and the base substrate.

3. The semiconductor packaging structure as described in claim 1, characterized in that, Also includes: A third capacitor is embedded in the redistribution layer and electrically coupled to the first semiconductor chip.

4. The semiconductor packaging structure as described in claim 3, characterized in that, The third capacitor includes: A third capacitor substrate having a third top surface and a third bottom surface; At least one third capacitor cell disposed in the third capacitor substrate; and A third via is disposed in the third capacitor substrate, the third via electrically coupling at least one third capacitor cell to the conductive layer of the redistribution layer located on the third top surface and the third bottom surface.

5. The semiconductor packaging structure as described in claim 4, characterized in that, Also includes: A fourth capacitor and a plurality of fourth bump structures are disposed between the first semiconductor chip and the redistribution layer; The fourth capacitor is electrically coupled to the first semiconductor chip through the plurality of fourth bump structures, wherein the plurality of fourth bump structures are disposed on two surfaces of the fourth capacitor.

6. The semiconductor packaging structure as described in claim 1, characterized in that, Also includes: Multiple fifth bump structures are disposed between the first semiconductor chip and the redistribution layer.

7. The semiconductor packaging structure as described in claim 5, characterized in that, The fourth capacitor includes: Fourth capacitor substrate; At least one fourth capacitor cell disposed in the fourth capacitor substrate; and A fourth via is disposed in the fourth capacitor substrate, which electrically couples at least one fourth capacitor cell to the plurality of fourth bump structures.

8. The semiconductor packaging structure as described in claim 7, characterized in that, It also includes a bottom filling material surrounding the plurality of fourth bump structures and the fourth capacitor.

9. The semiconductor packaging structure as described in claim 1, characterized in that, The first capacitor includes a multi-capacitor structure, which includes: First capacitor substrate; A plurality of first capacitor cells disposed in the first capacitor substrate; and Through-holes disposed in the first capacitor substrate electrically couple the plurality of first capacitor units to the redistribution layer and the wiring structure of the base substrate.

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