Display substrate and display device

Abstract

The present disclosure provides a display substrate, comprising: a base substrate; a driving function layer, comprising: a plurality of pixel driving circuits and a plurality of signal lines for providing electrical signals to the pixel driving circuits, wherein a node to be detected is configured on at least one pixel driving circuit and / or at least one signal line; a plurality of light-emitting elements, located on a side of the driving function layer away from the base substrate, the light-emitting elements comprising a first electrode, an electroluminescent layer, and a second electrode sequentially arranged in a direction away from the base substrate, the first electrodes of the light-emitting elements being connected to the corresponding pixel driving circuits; and at least one conductive lead terminal, the conductive lead terminal being located on a side of the driving function layer away from the base substrate, the conductive lead terminal corresponding one-to-one to the node to be detected, the conductive lead terminal being electrically connected to the corresponding node to be detected, and the orthographic projection of the conductive lead terminal on the base substrate and the orthographic projection of the electroluminescent layer on the base substrate not overlapping.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a display substrate and a display device. Background Art

[0002] With technological advancements, display technology is developing rapidly. Organic Light Emitting Diode (AMOLED) displays are becoming a trend in the future, offering multiple advantages such as low power consumption, self-luminescence, and flexibility. However, low product yield has been a major obstacle to OLED development. Currently, OLED manufacturers prioritize yield improvement and cost reduction for mass production.

[0003] The pixel unit is the basic light-emitting unit in the display device. The pixel unit includes a pixel driving circuit and a light-emitting element. The pixel driving circuit is used to output a driving current to drive the light-emitting element to emit light. Therefore, the electrical characteristics of certain electrical devices (such as transistors) in the pixel driving circuit and the electrical characteristics of the signal routing that provides electrical signals to the pixel driving circuit are key factors that directly affect the yield of the display device. However, the current testing technology can only estimate the overall performance of the display device through the TEG test component in the display device, and cannot effectively analyze the actual situation of the defective area in the display device. In other words, the existing testing scheme cannot perform refined testing on pixel units and signal routing. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] substrate;

[0007] The driving function layer includes: a plurality of pixel driving circuits and a plurality of signal lines for providing electrical signals to the pixel driving circuits, and a node to be detected is configured on at least one pixel driving circuit and / or at least one of the signal lines;

[0008] a plurality of light-emitting elements, located on a side of the driving function layer away from the base substrate, the light-emitting elements comprising a first electrode, an electroluminescent layer, and a second electrode sequentially arranged in a direction away from the base substrate, the first electrodes of the light-emitting elements being connected to corresponding pixel driving circuits;

[0009] At least one conductive lead-out terminal, the conductive lead-out terminal is located on a side of the driving function layer away from the base substrate, the conductive lead-out terminal corresponds one-to-one to the node to be detected, the conductive lead-out terminal is electrically connected to the corresponding node to be detected, and the orthographic projection of the conductive lead-out terminal on the base substrate does not overlap with the orthographic projection of the electroluminescent layer on the base substrate.

[0010] In some embodiments, the conductive lead terminal is provided in the same layer as the first electrode.

[0011] In some embodiments, the display substrate further comprises:

[0012] a pixel defining layer, located on a side of the driving function layer away from the base substrate, comprising: pixel openings, each corresponding to each of the light-emitting elements, each of which is located within the corresponding pixel opening;

[0013] The pixel defining layer further includes: a terminal opening, wherein the terminal opening corresponds to the conductive lead terminal on a one-to-one basis and is connected to the corresponding conductive lead terminal.

[0014] In some embodiments, the second electrode is a planar electrode, and an insulating isolation layer is provided in the terminal opening and between the conductive lead terminal and the second electrode.

[0015] In some embodiments, at least one non-luminescent functional layer is further provided between the first electrode and the second electrode, and the non-luminescent functional layer includes at least one of an electron blocking layer, a hole transport layer, an electron transport layer, and a hole blocking layer;

[0016] The insulating isolation layer includes at least one non-luminescent functional layer.

[0017] In some embodiments, the pixel driving circuit includes:

[0018] a driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the second node, and a second electrode of the driving transistor is connected to the third node, and the driving transistor is configured to output a corresponding driving current according to signals at the first node and the second node;

[0019] The reset circuit is connected to the corresponding reset control signal line, the reset voltage transmission line, the first node, and the first electrode corresponding to the light-emitting element, and is configured to write the reset voltage provided by the reset voltage transmission line to the first node and the first electrode corresponding to the light-emitting element in response to the control of the effective level signal provided by the reset control signal line;

[0020] a writing and compensation circuit connected to a corresponding gate line, a corresponding data line, a first node, a second node, and a third node, and configured to write a data voltage Vdata provided by the data line to the second node in response to control by an effective level signal provided by the gate line, and to write a light-emitting control voltage Vdata' obtained after threshold compensation to the first node, where Vdata'=Vdata+Vth, where Vth is the threshold voltage of the driving transistor;

[0021] a light-emitting control circuit connected to the light-emitting control signal line, the operating voltage transmission line, the third node, and the first electrode corresponding to the light-emitting element, and configured to write the operating voltage provided by the operating voltage transmission line to the second node and write the signal at the third node to the first electrode corresponding to the light-emitting element in response to the control of the effective level signal provided by the light-emitting control signal line;

[0022] At least one of the first node, the second node, and the third node is a node to be detected configured by the pixel driving circuit.

[0023] In some embodiments, the base substrate includes: a display area and a peripheral area located around the display area;

[0024] The plurality of signal traces include: a plurality of first signal traces extending along a first direction and a plurality of second signal traces extending along a second direction, wherein the first direction intersects the second direction;

[0025] The plurality of first signal lines include: the gate line, the reset control signal line, the light emitting control signal line and the reset voltage transmission line;

[0026] The plurality of second signal lines include: the data line and the operating voltage transmission line;

[0027] At least one of the first signal lines and / or at least one of the second signal lines is configured with the node to be detected located in the peripheral area.

[0028] In some embodiments, a plurality of first transfer traces corresponding one-to-one to the first signal traces are provided in the peripheral area, the first transfer traces are located on a side of the corresponding first signal trace away from the substrate, and the first transfer traces are connected to the corresponding first signal traces through first vias;

[0029] At least one of the first signal lines is configured with the node to be detected located in the peripheral area, the node to be detected configured for the first signal line is located on a first transfer line corresponding to the first signal line and on a side of the first via away from the display area, and the node to be detected configured for the first signal line is in contact with the corresponding conductive lead-out terminal;

[0030] In some embodiments, a plurality of second transfer traces corresponding one-to-one to the second signal traces are provided in the peripheral area, the second transfer traces are located on a side of the corresponding second signal trace close to the substrate, and the second transfer traces are connected to the corresponding second signal traces through second vias;

[0031] At least one of the second signal lines is configured with the node to be detected located in the peripheral area, the node to be detected configured by the second signal line is located on the second signal line and on the side of the second via close to the display area, and the node to be detected configured by the second signal line is in contact with the corresponding conductive lead-out terminal.

[0032] In some embodiments, the writing and compensation circuit includes: a data writing transistor and a threshold compensation transistor, the reset circuit includes: a first reset transistor and a second reset transistor, and the light emission control circuit includes: a first light emission control transistor and a second light emission control transistor;

[0033] The control electrode of the data writing transistor is connected to the corresponding gate line, the first electrode of the data writing transistor is connected to the corresponding data line, and the second electrode of the data writing transistor is connected to the second node;

[0034] The control electrode of the threshold compensation transistor is connected to the corresponding gate line, the first electrode of the threshold compensation transistor is connected to the first node, and the second electrode of the threshold compensation transistor is connected to the third node;

[0035] The control electrode of the first reset transistor is connected to the corresponding reset control signal line, the first electrode of the first reset transistor is connected to the first node, and the second electrode of the first reset transistor is connected to the reset voltage transmission line;

[0036] The control electrode of the second reset transistor is connected to the corresponding reset control signal line, the first electrode of the second reset transistor is connected to the reset voltage transmission line, and the second electrode of the second reset transistor is connected to the first electrode of the corresponding light-emitting element;

[0037] The control electrode of the first light-emitting control transistor is connected to the light-emitting control signal line, the first electrode of the first light-emitting control transistor is connected to the working voltage transmission line, and the second electrode of the first light-emitting control transistor is connected to the second node;

[0038] The control electrode of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode of the second light emitting control transistor is connected to the third node, and the second electrode of the second light emitting control transistor is connected to the first electrode of the corresponding light emitting element.

[0039] In some embodiments, the driving function layer includes: an active semiconductor layer, a gate insulating layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer sequentially arranged in a direction away from the substrate;

[0040] The active semiconductor layer includes active layer patterns and source / drain doped region patterns of each transistor in the pixel driving circuit; the first conductive layer includes control electrodes of each transistor in the pixel driving circuit, the gate line, the reset control signal line, and the light emitting control signal line; the second conductive layer includes the reset voltage transmission line; and the third conductive layer includes the data line and the operating voltage transmission line.

[0041] The node to be detected configured by the pixel driving circuit includes the first node, and the third conductive layer further includes: a first connecting portion, the first connecting portion configured to connect the second electrode of the threshold compensation transistor and the control electrode of the driving transistor, the first node is located on the first connecting portion, and the conductive lead terminal corresponding to the first node is in contact with the first node;

[0042] And / or, the node to be detected configured by the pixel driving circuit includes the second node, the second node is located on the source-drain doped region pattern in the active semiconductor layer that is connected to the active layer pattern of the driving transistor, the active layer pattern of the data writing transistor, and the active layer pattern of the first light-emitting control transistor, and the third conductive layer also includes: a second connecting portion, the second connecting portion is in contact with the second node, and the conductive lead terminal corresponding to the second node is in contact with the second connecting portion.

[0043] And / or, the node to be detected configured by the pixel driving circuit includes the third node, and the third node is located on the source-drain doped region pattern in the active semiconductor layer that is connected to the active layer pattern of the driving transistor, the active layer pattern of the threshold compensation transistor, and the active layer pattern of the second light-emitting control transistor, and the third conductive layer also includes: a third connecting portion, the third connecting portion is in contact with the third node, and the conductive lead terminal corresponding to the third node is in contact with the third connecting portion.

[0044] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: a display substrate as provided in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic top view of a display substrate provided by an embodiment of the present disclosure;

[0046] Figure 2 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present disclosure;

[0047] Figure 3 A schematic cross-sectional view of an embodiment of the present disclosure after the encapsulation layer located above the light-emitting element is removed;

[0048] Figure 4 Schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of the present disclosure;

[0049] Figure 5 A schematic diagram of a layout of a pixel driving circuit in an embodiment of the present disclosure;

[0050] Figure 6 A schematic diagram of a layout of a portion of the upper area of ​​the active semiconductor layer in an embodiment of the present disclosure;

[0051] Figure 7 A schematic diagram of a layout of a portion of the upper area of ​​the first conductive layer in an embodiment of the present disclosure;

[0052] Figure 8 A schematic diagram of a layout of a portion of the upper area of ​​the second conductive layer in the embodiment of the present disclosure;

[0053] Figure 9 A schematic diagram of a layout of a portion of the upper area of ​​the third conductive layer in an embodiment of the present disclosure;

[0054] Figure 10 for Figure 5 A schematic cross-sectional view in the A-A' direction;

[0055] Figure 11 for Figure 1 An enlarged top view of the area surrounding the middle portion;

[0056] Figure 12 for Figure 11 A schematic cross-sectional view in the B-B' direction;

[0057] Figure 13 for Figure 1 An enlarged top view of the middle portion and surrounding area;

[0058] Figure 14 for Figure 13 A schematic cross-sectional view along the C-C' direction. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the technical solution of the present invention, a display substrate and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0060] Figure 1 A schematic top view of a display substrate provided by an embodiment of the present disclosure, Figure 2 A schematic cross-sectional view of a portion of a display substrate provided in an embodiment of the present disclosure is provided. Figure 3 FIG. 1 is a cross-sectional schematic diagram of an embodiment of the present disclosure after the encapsulation layer located above the light-emitting element is removed, as shown in FIG. Figures 1 to 3 As shown, the display substrate includes: a base substrate 1, a driving function layer 10, a plurality of light emitting elements EL and at least one conductive lead terminal 21a, 21b.

[0061] The base substrate 1 includes a display area 1a and a peripheral area 1b located around the display area 1a. The base substrate 1 can be a hard substrate (e.g., a glass substrate) or a flexible substrate (e.g., a plastic substrate). The display area 1a is used to form pixel units PIX.

[0062] The driving function layer 10 includes: multiple pixel driving circuits and multiple signal lines 20 for providing electrical signals to the pixel driving circuits. Detection nodes 30a and 30b are configured on at least one pixel driving circuit and / or at least one signal line 20. The pixel driving circuit includes at least a transistor TFT and a conductive structure (not shown) for connecting the transistor TFT. Of course, the pixel driving circuit may also include a capacitor (not shown).

[0063] The light emitting element EL is located on the side of the driving function layer 10 away from the base substrate 1. The light emitting element EL includes a first electrode 16, an electroluminescent layer 18 and a second electrode 17 sequentially arranged in a direction away from the base substrate. The first electrode of the light emitting element EL is connected to the corresponding pixel driving circuit.

[0064] The conductive lead terminals 21a and 21b are located on the side of the driving function layer away from the base substrate 10. The conductive lead terminals 21a and 21b correspond one-to-one to the nodes 30a and 30b to be detected. The conductive lead terminals 21a and 21b are electrically connected to the corresponding nodes 30a and 30b to be detected. The orthographic projections of the conductive lead terminals 21a and 21b on the base substrate 1 do not overlap with the orthographic projections of the electroluminescent layer 18 on the base substrate 1.

[0065] It should be noted that the pixel driving circuit and its corresponding light-emitting element EL constitute a pixel unit. The pixel driving circuit can be used to provide a driving current to the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light. The light-emitting element EL is a current-driven light-emitting element, such as an LED or OLED.

[0066] In the embodiment of the present disclosure, part of the positions on the pixel driving circuit and / or the signal routing can be used as nodes to be detected according to actual test needs. After the preparation of the driving function layer is completed, conductive lead-out terminals corresponding to these nodes to be detected can be prepared for these nodes to be detected. The conductive lead-out terminals are electrically connected to the corresponding nodes to be detected. When it is necessary to test one or more nodes to be detected on the display substrate in the future, it is only necessary to contact the conductive lead-out terminals corresponding to the nodes to be detected through the test probe.

[0067] At the same time, in order to prevent the conductive lead terminal from affecting the light emission of the light emitting element, the orthographic projection of the conductive lead terminal on the base substrate does not overlap with the orthographic projection of the electroluminescent layer on the base substrate.

[0068] It should be noted that the attached Figure 2 The illustrations in the accompanying drawings illustrate only the case where the pixel driving circuit is configured with a node to be detected 30b corresponding to the conductive lead terminal 21b, and the signal trace 20 is configured with a node to be detected 30a corresponding to the conductive lead terminal 21a. This is merely an example and does not limit the technical solutions of the present disclosure. Furthermore, the accompanying drawings also illustrate the case where the conductive lead terminal 21b is electrically connected to the node to be detected 30b via other conductive structures, and the case where the conductive lead terminal 21a is electrically connected to the node to be detected 30a via direct contact. In other words, in the present disclosure, any method where a conductive lead terminal is directly or indirectly connected to a corresponding node to be detected to achieve electrical connection between the two is within the scope of protection of the present disclosure.

[0069] In some embodiments, the conductive lead terminals 21a and 21b are disposed in the same layer as the first electrode 16. In the embodiments of the present disclosure, "two or more structures disposed in the same layer" means that the two or more structures are formed from the same thin film material; that is, the two or more structures disposed in the same layer can be produced using the same patterning process. It should be noted that the distances between the two or more structures disposed in the same layer and the substrate can be equal or unequal.

[0070] The patterning process in the embodiments of the present disclosure refers to a process that may include steps such as photoresist coating, exposure, development, thin film etching, and photoresist stripping.

[0071] In the embodiment of the present disclosure, the conductive lead terminals 21a and 21b are arranged in the same layer as the first electrode 16, that is, the existing process for preparing the first electrode 16 can be used to simultaneously prepare the conductive lead terminals 21a and 21b, so there is no need to add additional process steps for the preparation of the conductive lead terminals 21a and 21b, which is conducive to shortening the production cycle and reducing production costs.

[0072] In some embodiments, the display substrate further includes a pixel defining layer 22, which is located on a side of the driving function layer 10 away from the base substrate. The pixel defining layer 22 is provided with pixel openings 22a and terminal openings 22b. The pixel openings 22a correspond one-to-one with the light-emitting elements EL, which are located within the corresponding pixel openings 22a. The terminal openings 22b correspond one-to-one with the conductive lead terminals 21a and 21b, and the terminal openings 22b are connected to the corresponding conductive lead terminals 21a and 21b. When testing one or more nodes 30a and 30b to be tested on the display substrate, a test probe need only be inserted into the terminal openings 22b corresponding to the corresponding conductive lead terminals 21a and 21b, ensuring that the bottom of the test probe contacts the corresponding conductive lead terminals 21a and 21b.

[0073] In some embodiments, a planarization layer 24 is disposed between the pixel definition layer 22 and the driving function layer 10 , and the first electrode 16 is connected to the corresponding pixel driving circuit in the driving function layer through a via hole in the planarization layer 24 .

[0074] In some embodiments, the second electrode 17 is a planar electrode, and an insulating isolation layer 24 is provided within the terminal opening 22b and between the conductive lead terminals 21a, 21b and the second electrode 17. The provision of the insulating isolation layer 24 can insulate the second electrode 17 from the conductive lead terminals 21a, 21b to ensure normal display of the display substrate.

[0075] In some embodiments, at least one non-luminescent functional layer 19a, 19b is further disposed between first electrode 16 and second electrode 17. The non-luminescent functional layer includes at least one of an electron blocking layer, a hole transport layer, an electron transport layer, and a hole blocking layer. Insulating isolation layer 24 includes at least one non-luminescent functional layer 19a, 19b. In other words, at least one of the electron blocking layer, hole transport layer, electron transport layer, and hole blocking layer functions as an insulating isolation layer. This eliminates the need for additional steps to prepare the insulating isolation layer, shortening production cycles and reducing production costs.

[0076] It should be noted that the accompanying drawings only exemplify a situation in which a non-luminescent functional layer 19b (specifically, a hole transport layer or an electron blocking layer) is provided between the first electrode 16 and the electroluminescent layer 18, a luminescent functional layer 19a (specifically, an electron transport layer or a hole blocking layer) is provided between the second electrode 17 and the electroluminescent layer 18, and the insulating isolation layer 24 includes both the non-luminescent functional layer 19a and the non-luminescent functional layer 19b. This situation only serves as an example and does not limit the technical solution disclosed herein.

[0077] See also Figure 2 and Figure 3 As shown, in order to protect the light-emitting element EL, generally after the preparation of the light-emitting element is completed, an encapsulation layer structure 23 is set on the side of the light-emitting element EL facing away from the substrate. The encapsulation layer structure 23 is generally a stacked structure formed by alternating organic encapsulation layers and inorganic encapsulation layers. When it is necessary to test the node to be detected on the display substrate, the encapsulation layer structure can be torn off. In the process of tearing off the encapsulation layer structure, the second electrode 17, the non-luminescent functional layer 19a and the electroluminescent layer 18 located in the pixel opening 22a, and the insulating isolation layer 24 located in the terminal opening 22b will all be removed together. At this time, the first electrode 16 is exposed in the pixel opening 22a, and the conductive lead terminals 21a and 21b are exposed in the terminal opening 22b. Thereafter, corresponding tests can be performed based on the exposed conductive lead terminals 21a, 21b and / or the first electrode 16. The test content will be described in detail later with reference to specific examples.

[0078] Figure 4 FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of the present disclosure. Figure 4 As shown, in some embodiments, the pixel driving circuit includes: a driving transistor T1 , a reset circuit 101 , a writing and compensation circuit 103 and a light emitting control circuit 102 .

[0079] Among them, the control electrode of the driving transistor T1 is connected to the first node N1, the first electrode of the driving transistor T1 is connected to the second node N2, the second electrode of the driving transistor T1 is connected to the third node N3, and the driving transistor TFT is configured to output corresponding driving current according to the signals at the first node N1 and the second node N2.

[0080] The reset circuit 101 is connected to the corresponding reset control signal line Rst, the reset voltage transmission line (providing the reset voltage VINIT), the first node N1 and the first electrode of the corresponding light-emitting element EL. The reset circuit 101 is configured to write the reset voltage VINIT provided by the reset voltage transmission line Rst to the first node N1 and the first electrode 16 of the corresponding light-emitting element EL in response to the control of the effective level signal provided by the reset control signal line Rst.

[0081] The writing and compensation circuit 103 is connected to the corresponding gate line Gate, the corresponding data line Data, the first node N1, the second node N2, and the third node N3. The writing and compensation circuit 103 is configured to respond to the control of the effective level signal provided by the gate line Gate, write the data voltage Vdata provided by the data line Data to the second node, and write the light-emitting control voltage Vdata' obtained after threshold compensation to the first node, Vdata'=Vdata+Vth, Vth is the threshold voltage of the driving transistor.

[0082] The light-emitting control circuit 102 is connected to the light-emitting control signal line EM, the working voltage transmission line (providing the working voltage VDD), the third node N3 and the first electrode 16 of the corresponding light-emitting element EL. The light-emitting control circuit 102 is configured to write the working voltage VDD provided by the working voltage transmission line to the second node N2 and write the signal at the third node N3 to the first electrode 16 of the corresponding light-emitting element EL in response to the control of the effective level signal provided by the light-emitting control signal line EM.

[0083] In some embodiments, at least one of the first node N1 , the second node N2 , and the third node N3 is a node to be detected configured by the pixel driving circuit.

[0084] Continue to see Figure 4 As shown, in some embodiments, the writing and compensation circuit 103 includes: a data writing transistor T2 and a threshold compensation transistor T3, the reset circuit 101 includes: a first reset transistor T6 and a second reset transistor T7, and the light emitting control circuit 102 includes a first light emitting control transistor T4 and a second light emitting control transistor T5.

[0085] A control electrode of the data writing transistor T2 is connected to the corresponding gate line Gate, a first electrode of the data writing transistor T2 is connected to the corresponding data line Data, and a second electrode of the data writing transistor T2 is connected to the second node N2.

[0086] A control electrode of the threshold compensation transistor T3 is connected to the corresponding gate line Gate, a first electrode of the threshold compensation transistor T3 is connected to the first node N1, and a second electrode of the threshold compensation transistor T3 is connected to the third node N3.

[0087] A control electrode of the first reset transistor T6 is connected to the corresponding reset control signal line Rst, a first electrode of the first reset transistor T6 is connected to the first node N1, and a second electrode of the first reset transistor T6 is connected to the reset voltage transmission line.

[0088] The control electrode of the second reset transistor T2 is connected to the corresponding reset control signal line Rst, the first electrode of the second reset transistor T2 is connected to the reset voltage transmission line, and the second electrode of the second reset transistor T2 is connected to the first electrode of the corresponding light emitting element EL.

[0089] The control electrode of the first light emitting control transistor T4 is connected to the light emitting control signal line EM, the first electrode of the first light emitting control transistor T4 is connected to the working voltage transmission line, and the second electrode of the first light emitting control transistor T4 is connected to the second node N2.

[0090] The control electrode of the second light emitting control transistor T5 is connected to the light emitting control signal line EM, the first electrode of the second light emitting control transistor T5 is connected to the third node N3, and the second electrode of the second light emitting control transistor T5 is connected to the first electrode of the corresponding light emitting element EL.

[0091] In some embodiments, the pixel driving circuit further includes a storage capacitor C, a first end plate of the storage capacitor C is electrically connected to the corresponding working voltage transmission line, and a second end plate of the storage capacitor C is electrically connected to the control electrode of the driving transistor T1.

[0092] Figure 5 is a schematic diagram of a layout of a pixel driving circuit in an embodiment of the present disclosure, Figure 6 Schematic diagram of a layout of a portion of the upper area of ​​the active semiconductor layer in an embodiment of the present disclosure. Figure 7 This is a schematic diagram of a partial area on the first conductive layer in an embodiment of the present disclosure. Figure 8 This is a schematic diagram of a layout of a portion of the upper area of ​​the second conductive layer in the embodiment of the present disclosure. Figure 9 Schematic diagram of a layout of a portion of the upper area of ​​the third conductive layer in an embodiment of the present disclosure. Figure 10 for Figure 5 A cross-sectional diagram in the A-A' direction, as shown in Figures 5 to 10As shown, in some embodiments, an active semiconductor layer, a gate insulating layer 11 , a first conductive layer, a first insulating layer 12 , a second conductive layer, a second insulating layer 13 and a third conductive layer are sequentially arranged in a direction away from the substrate 1 .

[0093] See also Figure 6 As shown, the active semiconductor layer includes: the active layer pattern (channel region a) and the source-drain doping region pattern (including the source region s and the drain region d) of each transistor in the pixel driving circuit. Figure 6 In the figure, the portion of the active semiconductor layer within the dashed rectangular box indicated by Tna represents the active layer pattern of transistor Tn, Tns represents the source region of transistor Tn, and Tnd represents the drain region of transistor Tn, where 1≤n≤7 and n is a positive integer. For example, the portion of the active semiconductor layer within the dashed rectangular box indicated by T1a represents the active layer pattern of drive transistor T1, T1s represents the source region of drive transistor T1, and T1d represents the drain region T1d of drive transistor T1. The portion of the active semiconductor layer within the dashed rectangular box indicated by T7a represents the active layer pattern of second reset transistor T7, T7s represents the source region of second reset transistor T7, and T7d represents the drain region T7d of second reset transistor T7. The active layer pattern and source / drain doped region pattern of each transistor in the same pixel driving circuit are integrated.

[0094] It should be noted that the active semiconductor layer may include an integrally formed low-temperature polysilicon layer, wherein the source and drain regions of each transistor may be made conductive through doping, etc., to achieve electrical connection between the various structures. In other words, the active layer pattern and source and drain doping region pattern of each transistor in each pixel driving circuit are an integral pattern formed of p-silicon, and the active layer patterns of different transistors may be separated by doping structures.

[0095] For example, the active semiconductor layer may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. The source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0096] See also Figure 7 As shown, the first conductive layer includes: control electrodes of each transistor in the pixel driving circuit, a reset control signal line Rst, a gate line Gate, a second end plate C_2 of the storage capacitor C, and a light emitting control signal line EM.

[0097] The control electrode of the data write transistor T2 can be the portion where the gate line Gate overlaps with the active semiconductor layer; the control electrode of the first light-emitting control transistor T4 can be the first portion where the light-emitting control signal line EM overlaps with the active semiconductor layer, and the control electrode of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line EM overlaps with the active semiconductor layer; the control electrode of the first reset transistor T6 can be the first portion where the reset control signal line Rst overlaps with the active semiconductor layer, and the control electrode of the second reset transistor T7 can be the second portion where the reset control signal line Rst overlaps with the active semiconductor layer; the threshold compensation transistor T3 can be a thin film transistor with a dual-gate structure, the first control electrode of the threshold compensation transistor T3 can be the portion where the gate line Gate overlaps with the active semiconductor layer, the second control electrode of the threshold compensation transistor T3 can be the portion where the protrusion P protruding from the gate line Gate overlaps with the active semiconductor layer, and the control electrode of the drive transistor T1 can be the second end plate C_2 of the storage capacitor C. It should be noted that Figure 6 The dashed rectangular boxes in FIG. 1 also show the portions where the first conductive layer overlaps the active semiconductor layer.

[0098] In some embodiments, the control electrode of the data writing transistor T2, the control electrode of the threshold compensation transistor T3, the control electrode of the first reset transistor T6, and the control electrode of the second reset transistor T7 are all located on the first side of the control electrode of the driving transistor T1, and the control electrode of the first light emitting control transistor T4 and the control electrode of the second light emitting control transistor T5 are all located on the second side of the control electrode of the driving transistor T1, and the first side and the second side are opposite sides in the second direction Y; for example, the first side is attached Figures 5 to 9 The upper side and the second side are attached Figures 5 to 9 The control electrode of the data writing transistor T2 and the control electrode of the first light emitting control transistor T4 are both located on the third side of the control electrode of the driving transistor T1, the first control electrode of the threshold compensation transistor T3, the control electrode of the second light emitting control transistor T5 and the control electrode of the second reset transistor T7 are all located on the fourth side of the control electrode of the driving transistor T1, and the third side and the fourth side are opposite sides in the first direction X; for example, the third side is attached Figures 5 to 9 The left side and the second side are attached Figures 5 to 9 on the right side of the .

[0099] The reset control signal line Rst, the gate line Gate, and the light-emission control signal line EM all extend along the first direction X. Within the same pixel driving circuit, the reset control signal line Rst configured in the pixel driving circuit is located on a first side of the configured gate line Gate, the gate line Gate configured in the pixel driving circuit is located on a first side of the second end plate C_2 of the storage capacitor C, and the light-emission control signal line EM configured in the pixel driving circuit is located on a second side of the second end plate C_2 of the storage capacitor C. In other words, within the same pixel driving circuit, the reset control signal line Rst, the configured gate line Gate, the second end plate C_2 of the storage capacitor C, and the light-emission control signal line EM configured in the pixel driving circuit are arranged sequentially from top to bottom.

[0100] See also Figure 8 As shown, the second conductive layer includes: a reset voltage transmission line Init and a first end plate C_1 of a storage capacitor C. The reset voltage transmission line Init extends along a first direction X; the overlapping portion of the first end plate C_1 of the storage capacitor C and the second end plate C_2 of the storage capacitor C can form a capacitor.

[0101] See also Figure 9 As shown, the third conductive layer includes: a data line Data and a first operating voltage transmission line 5, both of which extend along the second direction Y. For any pixel unit PIX, the data line Data configured for the pixel unit PIX is located on a third side of the first operating voltage transmission line 5 configured for the same pixel unit PIX. For example, the data line Data configured for the pixel unit PIX is located on the left side of the first operating voltage transmission line 5 configured for the same pixel unit PIX.

[0102] In some embodiments, the node to be detected configured by the pixel driving circuit includes a first node N1, and the third conductive layer also includes: a first connection portion Q1, the first connection portion Q1 extends along the second direction, and the first connection portion Q1 is configured to connect the second electrode of the threshold compensation transistor T3 and the control electrode of the driving transistor T1. The first node N1 is located on the first connection portion, and the conductive lead-out terminal 21 corresponding to the first node N1 is in contact with the first node N1.

[0103] The node to be detected configured by the pixel driving circuit includes a second node N2, which is located on a source-drain doped region pattern in the active semiconductor layer that is connected to the active layer pattern of the driving transistor T1, the active layer pattern of the data writing transistor T2, and the active layer pattern of the first light-emitting control transistor T4. The third conductive layer also includes: a second connecting portion Q2, the second connecting portion Q2 is in contact with the second node N2, and the conductive lead terminal 21 corresponding to the second node N2 is in contact with the second connecting portion Q2.

[0104] The nodes to be detected configured by the pixel driving circuit include a third node N3. The third node N3 is located on a source-drain doped region pattern in the active semiconductor layer that is connected to the active layer pattern of the driving transistor T1, the active layer pattern of the threshold compensation transistor T3, and the active layer pattern of the second light-emitting control transistor T5. The third conductive layer also includes: a third connecting portion Q3, the third connecting portion Q3 is in contact with the third node N3, and the conductive lead terminal 21 corresponding to the third node N3 is in contact with the third connecting portion Q3.

[0105] See also Figure 9 As shown, in some embodiments, the third conductive layer further includes a fourth connection portion Q4 and a fifth connection portion 15. The fourth connection portion Q4 is configured to connect the reset voltage transmission line Init and the first electrode of the second reset transistor T7, and the fifth connection portion 15 is configured to connect the first electrode 16 of the light-emitting element EL and the second electrode of the second light-emitting control transistor T5.

[0106] In some embodiments, the multiple signal lines include: multiple first signal lines extending along a first direction and multiple second signal lines extending along a second direction, the first direction intersects the second direction; the multiple first signal lines include: a gate line Gate, a reset control signal line Rst, a light emitting control signal line EM and a reset voltage transmission line Init; the multiple second signal lines include: a data line Data and an operating voltage transmission line 5; at least one first signal line and / or at least one second signal line is configured with a node to be detected located in the peripheral area.

[0107] Figure 11 for Figure 1 A top-down enlarged schematic diagram of the area surrounding the middle part, Figure 12 for Figure 11 A cross-sectional diagram in the B-B' direction, such as Figure 11 and Figure 12 As shown, in some embodiments, a plurality of first transfer traces 40a corresponding one-to-one to the first signal traces 20a are provided in the peripheral area 1b. The first transfer traces 40b are located on a side of the corresponding first signal trace 20a away from the substrate 1 in a direction perpendicular to the substrate 1. The first transfer traces 40a are connected to the corresponding first signal traces 20a through first vias 41.

[0108] At least one first signal trace 20a is configured with a node 30 to be detected located in the peripheral area 1b. The node 30 to be detected configured on the first signal trace 20a is located on the first transfer trace 40a corresponding to the first signal trace 20a and is located on the side of the first via 41 away from the display area 1a. The node 30 to be detected configured on the first signal trace 20a is in contact with the corresponding conductive lead-out terminal 21.

[0109] In some embodiments, the first transfer trace 40 a is located in the third conductive layer.

[0110] Figure 13 for Figure 1 A top-down enlarged schematic diagram of the surrounding area in the middle part, Figure 14 for Figure 13 A cross-sectional diagram in the C-C' direction, such as Figure 13 and Figure 14 As shown, in some embodiments, a plurality of second transfer traces 20b corresponding one-to-one to the second signal traces 40b are provided in the peripheral area 1b. In the direction perpendicular to the base substrate 1, the second transfer traces 20b are located on the side of the corresponding second signal trace 40b close to the base substrate 1, and the second transfer traces 20b are connected to the corresponding second signal trace 40b through a second via 42; at least one second signal trace 40b is configured with a node to be detected 30 located in the peripheral area 1b, and the node to be detected configured by the second signal trace 40b is located on the second signal trace 40b and on the side of the second via 42 close to the display area 1a, and the node to be detected configured by the second signal trace 40b is in contact with the corresponding conductive lead-out terminal 21.

[0111] In some embodiments, the second transfer trace 20 b is located in the first conductive layer.

[0112] As a specific application scheme, the first node N1, the second node N2, and the third node N3 are all used as nodes to be detected and are configured with corresponding conductive lead-out terminals, and the gate line Gate, the reset control signal line Rst, the light control signal line EM, the reset voltage transmission line Init, the data line Data, and the working voltage transmission line 5 are all configured with corresponding nodes to be detected and corresponding conductive lead-out terminals in the peripheral area 1b.

[0113] Before testing, the encapsulation layer on the display substrate surface is removed 30 . The material within the pixel openings 22a and terminal openings 22b on the pixel defining layer 22 is removed. Each pixel opening 22a exposes the corresponding first electrode 16, and each terminal opening 22b exposes the corresponding conductive lead terminal 21. The display substrate is then tested as follows:

[0114] When it is necessary to test the electrical characteristics of the driving transistor T1, the three test probes of the testing equipment can be respectively contacted with the conductive lead-out terminal 21 corresponding to the first node N1, the conductive lead-out terminal 21 corresponding to the second node N2, and the conductive lead-out terminal 21 corresponding to the third node N3, and the electrical characteristics of the driving transistor T1 can be tested.

[0115] When it is necessary to test the electrical characteristics of the data writing transistor T2, the three test probes of the testing equipment can be respectively contacted with the conductive lead-out terminal 21 corresponding to the second node N2, the conductive lead-out terminal 21 corresponding to the gate line Gate connected to the data writing transistor T2, and the conductive lead-out terminal 21 corresponding to the data line Data connected to the data writing transistor T2, and the electrical characteristics of the data writing transistor T2 can be tested.

[0116] When it is necessary to test the electrical characteristics of the threshold compensation transistor T3, the three test probes of the testing equipment can be respectively contacted with the conductive lead-out terminal 21 corresponding to the first node N1, the conductive lead-out terminal 21 corresponding to the third node N3, and the conductive lead-out terminal 21 corresponding to the gate line Gate connected to the threshold compensation transistor T3, and the electrical characteristics of the threshold compensation transistor T3 can be tested.

[0117] When it is necessary to test the electrical characteristics of the first light-emitting control transistor T4, the three test probes of the testing equipment can be respectively contacted with the conductive lead-out terminal 21 corresponding to the second node N2, the conductive lead-out terminal 21 corresponding to the working voltage transmission line 5 connected to the first light-emitting control transistor T4, and the conductive lead-out terminal 21 of the light-emitting control signal line EM connected to the first light-emitting control transistor T4, and the electrical characteristics of the first light-emitting control transistor T4 can be tested.

[0118] When it is necessary to test the electrical characteristics of the second light-emitting control transistor T5, the three test probes of the testing equipment can be respectively contacted with the conductive lead-out terminal 21 corresponding to the third node N3, the conductive lead-out terminal 21 corresponding to the working voltage transmission line 5 connected to the second light-emitting control transistor T5, and the first electrode 16 connected to the second light-emitting control transistor T5, and the electrical characteristics of the second light-emitting control transistor T5 can be tested.

[0119] When it is necessary to test the electrical characteristics of the first reset transistor T6, the three test probes of the test equipment can be respectively contacted with the conductive lead-out terminal 21 corresponding to the first node N1, the conductive lead-out terminal 21 corresponding to the reset voltage transmission line Init connected to the first reset transistor T6, and the conductive lead-out terminal 21 corresponding to the reset control signal line Rst connected to the first reset transistor T6, and the electrical characteristics of the first reset transistor T6 can be tested.

[0120] When it is necessary to test the electrical characteristics of the second reset transistor T7, the three test probes of the test equipment can be respectively contacted with the first electrode 16 connected to the first reset transistor T6, the conductive lead-out terminal 21 corresponding to the reset voltage transmission line VINIT connected to the first reset transistor T6, and the conductive lead-out terminal 21 corresponding to the reset control signal line Rst connected to the first reset transistor T6, and the electrical characteristics of the second reset transistor T7 can be tested.

[0121] When testing the signal loaded on any signal line among the gate line Gate, reset control signal line Rst, light control signal line EM, reset voltage transmission line Init, data line Data and working voltage transmission line 5, a test probe of the test equipment can be brought into contact with the conductive lead-out terminal 21 corresponding to the signal line to be tested, and based on the detected signal waveform, it can be judged whether the signal line has a short circuit, open circuit or other defects.

[0122] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display substrate. The display substrate adopts the display substrate provided by the previous embodiment. For the specific description of the display substrate, please refer to the content of the previous embodiment and will not be repeated here.

[0123] The display device provided in this embodiment can be any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present invention.

[0124] Furthermore, the display device may also include various types of display devices, such as an electroluminescent display device; specifically, the display device is an OLED display device, a QLED display device, or a QD-OLED display device, which is not limited here.

[0125] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Persons skilled in the art will readily appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: include: substrate; The driving function layer includes: a plurality of pixel driving circuits and a plurality of signal lines for providing electrical signals to the pixel driving circuits, and a node to be detected is configured on at least one pixel driving circuit and at least one of the signal lines; a plurality of light-emitting elements, located on a side of the driving function layer away from the base substrate, the light-emitting elements comprising a first electrode, an electroluminescent layer, and a second electrode sequentially arranged in a direction away from the base substrate, the first electrodes of the light-emitting elements being connected to corresponding pixel driving circuits; At least one conductive lead terminal, the conductive lead terminal being located on a side of the driving function layer away from the base substrate, the conductive lead terminal corresponding to the node to be detected one-to-one, the conductive lead terminal being electrically connected to the corresponding node to be detected, and an orthographic projection of the conductive lead terminal on the base substrate and an orthographic projection of the electroluminescent layer on the base substrate not overlapping; The conductive lead terminal is provided on the same layer as the first electrode; The display substrate further includes: a pixel defining layer, located on a side of the driving function layer away from the base substrate, comprising: pixel openings, each corresponding to each of the light-emitting elements, each of which is located within the corresponding pixel opening; The pixel defining layer further includes: a terminal opening, wherein the terminal opening corresponds to the conductive lead terminal on a one-to-one basis and is connected to the corresponding conductive lead terminal.

2. The display substrate according to claim 1, wherein: The second electrode is a planar electrode, and an insulating isolation layer is provided in the terminal opening and between the conductive lead terminal and the second electrode.

3. The display substrate according to claim 2, wherein: At least one non-luminescent functional layer is further provided between the first electrode and the second electrode, wherein the non-luminescent functional layer comprises at least one of an electron blocking layer, a hole transport layer, an electron transport layer and a hole blocking layer; The insulating isolation layer includes at least one non-luminescent functional layer.

4. The display substrate according to claim 1, wherein The pixel driving circuit includes: a driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the second node, and a second electrode of the driving transistor is connected to the third node, and the driving transistor is configured to output a corresponding driving current according to signals at the first node and the second node; a reset circuit connected to the corresponding reset control signal line, the reset voltage transmission line, the first node, and the first electrode corresponding to the light-emitting element, and configured to write the reset voltage provided by the reset voltage transmission line to the first node and the first electrode corresponding to the light-emitting element in response to the control of the effective level signal provided by the reset control signal line; A writing and compensation circuit is connected to the corresponding gate line, the corresponding data line, the first node, the second node, and the third node, and is configured to write the data voltage Vdata provided by the data line to the second node in response to the control of the effective level signal provided by the gate line, and write the light-emitting control voltage Vdata' obtained after threshold compensation to the first node, where Vdata'=Vdata+Vth, where Vth is the threshold voltage of the driving transistor; a light-emitting control circuit connected to the light-emitting control signal line, the operating voltage transmission line, the third node, and the first electrode corresponding to the light-emitting element, and configured to write the operating voltage provided by the operating voltage transmission line to the second node and write the signal at the third node to the first electrode corresponding to the light-emitting element in response to the control of the effective level signal provided by the light-emitting control signal line; At least one of the first node, the second node, and the third node is a node to be detected configured by the pixel driving circuit.

5. The display substrate according to claim 4, wherein: The base substrate includes: a display area and a peripheral area located around the display area; The plurality of signal traces include: a plurality of first signal traces extending along a first direction and a plurality of second signal traces extending along a second direction, wherein the first direction intersects the second direction; The plurality of first signal lines include: the gate line, the reset control signal line, the light emitting control signal line and the reset voltage transmission line; The plurality of second signal lines include: the data line and the operating voltage transmission line; At least one of the first signal lines and / or at least one of the second signal lines is configured with the node to be detected located in the peripheral area.

6. The display substrate according to claim 5, wherein: A plurality of first transfer traces corresponding one-to-one to the first signal traces are provided in the peripheral area, the first transfer traces are located on a side of the corresponding first signal trace away from the substrate, and the first transfer traces are connected to the corresponding first signal traces through first vias; At least one of the first signal lines is configured with the node to be detected located in the peripheral area, the node to be detected configured by the first signal line is located on the first transfer line corresponding to the first signal line and is located on the side of the first via away from the display area, and the node to be detected configured by the first signal line is in contact with the corresponding conductive lead-out terminal.

7. The display substrate according to claim 6, wherein: A plurality of second transfer traces corresponding one-to-one to the second signal traces are provided in the peripheral area, the second transfer traces are located on a side of the corresponding second signal trace close to the base substrate, and the second transfer traces are connected to the corresponding second signal traces through second vias; At least one of the second signal lines is configured with the node to be detected located in the peripheral area, the node to be detected configured on the second signal line is located on the second signal line and on the side of the second via close to the display area, and the node to be detected configured on the second signal line is in contact with the corresponding conductive lead-out terminal.

8. The display substrate according to claim 7, wherein: The writing and compensation circuit includes: a data writing transistor and a threshold compensation transistor; the reset circuit includes: a first reset transistor and a second reset transistor; the light emitting control circuit includes: a first light emitting control transistor and a second light emitting control transistor; The control electrode of the data writing transistor is connected to the corresponding gate line, the first electrode of the data writing transistor is connected to the corresponding data line, and the second electrode of the data writing transistor is connected to the second node; The control electrode of the threshold compensation transistor is connected to the corresponding gate line, the first electrode of the threshold compensation transistor is connected to the first node, and the second electrode of the threshold compensation transistor is connected to the third node; The control electrode of the first reset transistor is connected to the corresponding reset control signal line, the first electrode of the first reset transistor is connected to the first node, and the second electrode of the first reset transistor is connected to the reset voltage transmission line; The control electrode of the second reset transistor is connected to the corresponding reset control signal line, the first electrode of the second reset transistor is connected to the reset voltage transmission line, and the second electrode of the second reset transistor is connected to the first electrode of the corresponding light-emitting element; The control electrode of the first light-emitting control transistor is connected to the light-emitting control signal line, the first electrode of the first light-emitting control transistor is connected to the working voltage transmission line, and the second electrode of the first light-emitting control transistor is connected to the second node; The control electrode of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode of the second light emitting control transistor is connected to the third node, and the second electrode of the second light emitting control transistor is connected to the first electrode of the corresponding light emitting element.

9. The display substrate according to claim 8, wherein: The driving function layer includes: an active semiconductor layer, a gate insulating layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer arranged in sequence in a direction away from the substrate; The active semiconductor layer includes active layer patterns and source / drain doped region patterns of each transistor in the pixel driving circuit; the first conductive layer includes control electrodes of each transistor in the pixel driving circuit, the gate line, the reset control signal line, and the light emitting control signal line; the second conductive layer includes the reset voltage transmission line; and the third conductive layer includes the data line and the operating voltage transmission line. The node to be detected configured by the pixel driving circuit includes the first node, and the third conductive layer further includes: a first connecting portion, the first connecting portion configured to connect the second electrode of the threshold compensation transistor and the control electrode of the driving transistor, the first node is located on the first connecting portion, and the conductive lead terminal corresponding to the first node is in contact with the first node; And / or, the node to be detected configured by the pixel driving circuit includes the second node, the second node is located on a source-drain doped region pattern in the active semiconductor layer that is connected to the active layer pattern of the driving transistor, the active layer pattern of the data writing transistor, and the active layer pattern of the first light-emitting control transistor, and the third conductive layer further includes: a second connecting portion, the second connecting portion is in contact with the second node, and a conductive lead terminal corresponding to the second node is in contact with the second connecting portion; And / or, the node to be detected configured by the pixel driving circuit includes the third node, and the third node is located on the source-drain doped region pattern in the active semiconductor layer that is connected to the active layer pattern of the driving transistor, the active layer pattern of the threshold compensation transistor, and the active layer pattern of the second light-emitting control transistor, and the third conductive layer also includes: a third connecting portion, the third connecting portion is in contact with the third node, and the conductive lead terminal corresponding to the third node is in contact with the third connecting portion.

10. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 9.

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