Automatic harmonic tracking circuit based on oscillator and third harmonic frequency multiplier

Abstract

The present invention discloses an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier, comprising a class F oscillator, a third harmonic extraction frequency multiplier, a negative peak detection circuit, a low-pass filter, a sample-and-hold circuit, a comparator, and a logic circuit. The class F oscillator obtains a periodic pseudo-square wave AC differential signal; the third harmonic extraction frequency multiplier obtains a third harmonic differential signal after fundamental frequency suppression; the negative peak detection circuit extracts the amplitude signal of the third harmonic differential signal; the low-pass filter filters the amplitude signal to a DC level; the comparator compares the amplitude signals of different frequency bands and outputs the comparison result; and the logic circuit controls the switched capacitor array in the third harmonic extraction frequency multiplier to adaptively switch the frequency band to the desired frequency band. The present invention can achieve automatic tracking of the third harmonic, solving the problems that the third harmonic frequency multiplier can only achieve excellent phase noise within a narrow frequency band and requires manual adjustment of the frequency band, which takes too much time.

Description

Technical Field

[0001] The invention belongs to the technical field of digital-analog hybrid integrated circuits, and in particular relates to an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier. Background Art

[0002] Phase noise is one of the most important performance metrics for evaluating voltage-controlled oscillators (VCOs). In charge pump phase-locked loops (CPPLs), high-frequency phase noise is determined by the VCO and directly affects the timing jitter of the output signal. For high-frequency millimeter-wave applications, the oscillator's sensitivity to parasitic capacitance and inductance, coupled with the deterioration of the capacitor's quality factor, significantly degrades the oscillator's Figure of Merit (FOM). Consequently, the application of common fundamental oscillators in frequency bands above millimeter-wave is limited.

[0003] To achieve better phase noise at the same power consumption, oscillators usually need to use frequency multipliers to generate millimeter-wave clock signals. In pursuit of superior FOM values, more and more frequency multipliers have been proposed. Millimeter-wave clock circuits based on a two-stage phase-locked loop cascade have high power consumption, area, and design complexity. The frequency multiplication structure based on a low-frequency oscillator driving a nonlinear device and then selecting the output through a filter achieves wideband performance. However, due to the weak nonlinearity, the signal amplitude is small, and a buffer with large power consumption and area is required to drive it. In order to reduce power consumption and achieve higher FOM values, injection-locked frequency multipliers and harmonic extraction frequency multipliers based on Class F oscillators are more common. However, they can only achieve superior noise performance in a small range near the oscillator's harmonic frequency. There are problems with achieving wideband and the need to manually adjust the frequency band, which causes a long locking time. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier, comprising a class F oscillator, a third harmonic extraction frequency multiplier, a negative peak detection circuit, a low-pass filter, a sample-and-hold circuit, a comparator, and a logic circuit, wherein:

[0006] The class F oscillator is used to convert the DC voltage of the power supply into a periodic pseudo-square wave AC differential signal with a constant frequency and containing the third harmonic;

[0007] The third harmonic extraction frequency multiplier is connected to the class F oscillator, and is used to suppress the fundamental frequency signal in the periodic pseudo square wave AC differential signal, and extract and amplify the third harmonic in the periodic pseudo square wave AC differential signal to obtain a third harmonic differential signal after fundamental frequency suppression;

[0008] The negative peak detection circuit is connected to the third harmonic extraction frequency multiplier, and is used to detect the amplitude of the third harmonic differential signal and extract the amplitude signal of the third harmonic differential signal;

[0009] The low-pass filter is connected to the negative peak detection circuit and is used to filter the amplitude signal of the extracted third harmonic into a DC level;

[0010] The sample-and-hold circuit is connected to the low-pass filter and is used to sample and hold amplitude signals of different frequency bands;

[0011] The comparator is connected to the sample-and-hold circuit, and is used to compare amplitude signals of different frequency bands and output a comparison result;

[0012] The logic circuit is connected between the comparator and the third harmonic extraction frequency multiplier, and is used to generate a digital control signal according to the comparison result to control the switching capacitor array in the third harmonic extraction frequency multiplier to adaptively switch the frequency band of the third harmonic extraction frequency multiplier to a required frequency band.

[0013] In one embodiment of the present invention, the class F oscillator includes a first MOS transistor M1, a second MOS transistor M2, a capacitor group C D , capacitor group C G , switched capacitor array C S , switched capacitor array C P , variable capacitor C VAR 、Inductor L D and inductor L G ,in,

[0014] The capacitor group C D , the switch capacitor array C P and the inductor L D The inductor L is connected in parallel between the drain of the first MOS tube M1 and the drain of the second MOS tube M2. D The tap is connected to the first power supply terminal VD;

[0015] The inductor L G , the capacitor group C G , the switch capacitor array C S and the variable capacitance tube C VAR The inductor L is connected in parallel between the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2.G The tap is connected to the second power supply terminal VG, the inductor L G and the inductor L D Forming transformer T0, the variable capacitor C VAR An external control voltage Vcont is connected to control the variable capacitance tube C VAR The size of the capacitor can adjust the fundamental frequency of the Class F oscillator;

[0016] The source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both connected to the ground terminal GND; the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 serve as the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator respectively.

[0017] In one embodiment of the present invention, the capacitor group C D and the capacitor group C G Both include two capacitors connected in series.

[0018] In one embodiment of the present invention, the third harmonic extraction frequency multiplier includes a third harmonic extraction module and a third harmonic amplification module, wherein:

[0019] The third harmonic extraction module is connected to the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator, and is used to suppress the fundamental frequency signal in the differential signal between the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator, and extract the third harmonic component;

[0020] The third harmonic amplification module is used to perform power amplification on the extracted third harmonic component and realize the tripling of the fundamental frequency of the periodic pseudo square wave AC differential signal of the class F oscillator.

[0021] In one embodiment of the present invention, the third harmonic extraction module includes a third MOS tube M3, a fourth MOS tube M4, an inductor L1, a capacitor group C fix , switched capacitor array C0, switched capacitor array C1, capacitor C n1 , capacitor C n2 , capacitor C ac1 , capacitor C ac2 , resistor R ac1 , resistor R ac2 and the inductor L s ,in,

[0022] The capacitor C ac1 The capacitor C is connected between the first differential output terminal VDP of the class F oscillator and the gate of the third MOS transistor M3. ac2The capacitor C is connected between the second differential output terminal VDN of the class F oscillator and the gate of the fourth MOS transistor M4. n1 connected between the gate of the third MOS tube M3 and the drain of the fourth MOS tube M4, the capacitor C n2 connected between the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4;

[0023] The capacitor group C fix , the switched capacitor array C0 and the inductor L s The inductor L is connected in parallel between the source of the third MOS tube M3 and the source of the fourth MOS tube M4. s The tap is connected to the ground terminal GND;

[0024] The inductor L1 and the switched capacitor array C1 are connected in parallel between the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4, and a tap of the inductor L1 is connected to an external power supply VPA1;

[0025] The resistor R ac1 Connected between the gate of the third MOS tube M3 and the external bias voltage VPB1, the resistor R ac2 connected between the gate of the fourth MOS transistor M4 and the external bias VPB1;

[0026] The switch capacitor array C0 and the switch capacitor array C1 are respectively connected to the output end of the logic circuit.

[0027] In one embodiment of the present invention, the third harmonic amplification module includes a fifth MOS transistor M5, a sixth MOS transistor M6, an inductor L2, a switch capacitor array C2, a capacitor C n3 , capacitor C n4 , inductor L3, inductor L4 and external load resistor R load , wherein the drain of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are both connected to the ground terminal GND, the inductor L2 is connected between the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6, the inductor L2 and the inductor L1 form a transformer T1, and the tap of the inductor L2 is connected to the voltage VPB2;

[0028] The capacitor C n3 Connected between the gate of the fifth MOS tube M5 and the drain of the sixth MOS tube M6, the capacitor C n4 connected between the drain of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6;

[0029] The inductor L3 and the switch capacitor array C2 are connected in parallel between the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6. The tap of the inductor L3 is connected to the external power supply VPA2. The inductor L3 and the inductor L4 form a transformer T2. The inductor L4 and the external load resistor R load connected in series between two ground terminals; the switch capacitor array C2 is connected to the output terminal of the logic circuit;

[0030] The drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 serve as the first differential output terminal VDP2 and the second differential output terminal VDN2 of the third harmonic amplifying module, respectively.

[0031] In one embodiment of the present invention, the negative peak detection circuit includes a seventh MOS transistor M7, an eighth MOS transistor M8 and a charging capacitor C AD ,in,

[0032] The drain of the seventh MOS transistor M7 is connected to the second differential output terminal VDN2 of the third harmonic amplification module and the gate of the eighth MOS transistor M8, and the drain of the eighth MOS transistor M8 is connected to the second differential output terminal VDP2 of the third harmonic amplification module and the gate of the seventh MOS transistor M7;

[0033] The source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are both connected to the charging capacitor C AD The first end of the charging capacitor C AD The second end is connected to the ground terminal GND;

[0034] The source of the eighth MOS transistor M8 serves as the output end of the negative peak detection circuit.

[0035] In one embodiment of the present invention, the low-pass filter includes a resistor R1 and a capacitor C4, wherein:

[0036] The first end of the resistor R1 is connected to the output end of the negative peak detection circuit, and the second end serves as the output end VSAMP of the low-pass filter; the capacitor C4 is connected between the output end VSAMP of the low-pass filter and the ground end GND, and the node between the resistor R1 and the capacitor C4 serves as the output end VSAMP of the low-pass filter and is connected to the sample-and-hold circuit.

[0037] In one embodiment of the present invention, the sample-and-hold circuit includes a first sampling switch K1, a second sampling switch K2, a first sampling capacitor C samp1 and the second sampling capacitor C samp2 ,in,

[0038] The first sampling switch K1 is connected between the output terminal VSAMP of the low-pass filter and the first input terminal VINP of the comparator, and the second sampling switch K2 is connected between the output terminal VSAMP of the low-pass filter and the second input terminal VINN of the comparator;

[0039] The first sampling capacitor C samp1 connected between the first input terminal VINP of the comparator and the ground terminal, the second sampling capacitor C samp2 The first input terminal VINN is connected between the second input terminal VINN of the comparator and the ground terminal.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] 1. The fast automatic harmonic tracking circuit based on the third harmonic extraction frequency multiplier of the present invention realizes wide-band application through a switched capacitor array, uses a negative peak detection circuit and a sample-and-hold circuit to detect the output amplitude of the third harmonic extraction frequency multiplier, compares the amplitudes of different frequency bands through a comparator, and uses a logic circuit to realize automatic tracking of the third harmonic. This solves the problem of such frequency multipliers requiring manual frequency band adjustment, which takes too much time, and accurately locks on the third harmonic, thereby achieving superior noise performance, lower power consumption and greater output power.

[0042] 2. The present invention accurately extracts the amplitude of the third harmonic through a negative peak detection circuit, calibrates the harmonic frequency of the harmonic multiplier and the injection-locked multiplier according to the harmonic amplitude, and provides a new way to automatically obtain the operating point of the optimal phase noise and maximum output power.

[0043] 3. The present invention first uses a negative peak detector to detect the amplitude of the third harmonic output, then compares the amplitudes of different frequency bands through a sampler and a comparator, and finally accurately realizes the third harmonic extraction based on a logic circuit and a search algorithm. The ratio of the frequency multiplier to the fundamental output frequency of the oscillator is 3:1, and more superior phase noise, power consumption and output power performance can be achieved in a wider frequency band.

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 1 is a schematic structural diagram of an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier provided by an embodiment of the present invention;

[0046] Figure 2 is a circuit diagram of a Class F oscillator provided by an embodiment of the present invention;

[0047] Figure 3This is a circuit diagram of a third harmonic extraction frequency multiplier provided by an embodiment of the present invention;

[0048] Figure 4 1 is another structural diagram of an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier provided by an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of a logic search algorithm for a logic circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier proposed in accordance with the present invention, in conjunction with the accompanying drawings and specific implementation methods.

[0051] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0052] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0053] See Figure 1 , Figure 11 is a structural diagram of an automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier provided by an embodiment of the present invention. The fast automatic harmonic tracking circuit includes a class F oscillator 101, a third harmonic extraction frequency multiplier 102, a negative peak detection circuit 103, a low-pass filter 104, a sampling and holding circuit 105, a comparator 106 and a logic circuit 107, wherein the class F oscillator 101 is used to convert the DC voltage of the power supply into a periodic pseudo-square wave AC differential signal with a constant frequency and containing a third harmonic; the third harmonic extraction frequency multiplier 102 is connected to the class F oscillator 101, and is used to suppress the fundamental frequency signal in the periodic pseudo-square wave AC differential signal, and extract and amplify the third harmonic in the periodic pseudo-square wave AC differential signal to obtain the third harmonic differential signal after the fundamental frequency is suppressed; the negative peak detection circuit 103 is connected to the third harmonic extraction frequency multiplier 102, and is used to detect the third harmonic. The amplitude of the third harmonic differential signal is detected and the amplitude signal of the third harmonic differential signal is extracted; the low-pass filter 104 is connected to the negative peak detection circuit 103, and is used to filter the amplitude signal of the extracted third harmonic into a DC level; the sampling and holding circuit 105 is connected to the low-pass filter 104, and is used to sample and hold the amplitude signals of different frequency bands; the comparator 106 is connected to the sampling and holding circuit 105, and is used to compare the amplitude signals of different frequency bands and output the comparison result; the logic circuit 107 is connected between the comparator 106 and the third harmonic extraction multiplier 102, and is used to generate a digital control signal according to the comparison result, and control the switch capacitor array in the third harmonic extraction multiplier 102 to adaptively switch the frequency band of the third harmonic extraction multiplier 102 to the required frequency band.

[0054] Further, see Figure 2 , Figure 2 The circuit diagram of a class F oscillator provided by an embodiment of the present invention is shown in FIG. The class F oscillator 101 of this embodiment includes a first MOS transistor M1, a second MOS transistor M2, a capacitor group C D , capacitor group C G , switched capacitor array C S , switched capacitor array C P , variable capacitor C VAR 、Inductor L D and inductor L G , where the capacitor group C D , switched capacitor array C P and inductor L D The inductor L is connected in parallel between the drain of the first MOS tube M1 and the drain of the second MOS tube M2. D The tap is connected to the first power supply terminal VD; the inductor L G , capacitor group C G , switched capacitor array C S and variable capacitance tube C VARConnected in parallel between the gate of the first MOS tube M1 and the gate of the second MOS tube M2, the inductor L G The tap is connected to the second power supply terminal VG, the inductor L G and inductor L D Forming transformer T0, variable capacitor C VAR An external control voltage Vcont is used to control the variable capacitor C VAR The capacitance value is adjusted to adjust the fundamental frequency of the class F oscillator; the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both connected to the ground terminal GND; the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 serve as the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator 101 respectively.

[0055] Specifically, the class F oscillator 101 includes a group of cross-coupled MOS transistors M1 and M2, the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are both connected to the inductor L G , capacitor group C G and the switched capacitor array C S The inductor and capacitor resonant network is used to obtain the required fundamental wave signals VGP and VGN, and the variable capacitor tube C VAR Applied in phase-locked loop circuits. In the Class F oscillator 101, multiple switched capacitor arrays (switched capacitor arrays C S and the switched capacitor array C P ) expands the frequency band of the fundamental signal. Connect the drain terminals of the first MOS tube M1 and the second MOS tube M2 to the inductor L D , switched capacitor array C P and capacitor group C D Another set of inductor and capacitor resonant networks is formed, and the drain voltage is mainly based on the fundamental signal, which contains the required third harmonic component. G and L D There is a certain coupling coefficient km between them, forming a transformer-like structure.

[0056] When the transformer primary and secondary L in the class F oscillator 101 D , L GAfter all capacitors are connected to form a resonant network, the impedance of the resonant network has a high-resistance peak. If the frequency of the two peaks is designed to be 1:3, the drain voltage of the Class F oscillator 101 becomes a square wave-like shape, which is mainly composed of the fundamental wave and contains a certain third harmonic. It is a type of harmonic tuning oscillator with a high figure of merit FOM, which can achieve low power consumption and low noise. The proportion of the third harmonic is changed by adjusting the coupling coefficient km. For applications that require third harmonic extraction and frequency multiplication, the coupling coefficient km is usually designed to be 0.6 to obtain a larger third harmonic component. The switch capacitor array C at the drain and gate ends of the MOS tube P , C S Used to expand the operating frequency range of the oscillator. VAR To achieve fine-tuning of the frequency so as to adapt to the application of the phase-locked loop, the output terminals VGP and VGN are respectively connected to the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2, which can be used as the output of the fundamental oscillator in a common phase-locked loop and connected to the subsequent frequency divider. The first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator 101 contain a large third harmonic component, which can be tripled by the subsequent third harmonic extraction multiplier 102 to obtain a pure high-frequency millimeter-wave clock signal. In this embodiment, the capacitor group C D and capacitor group C G Both include two capacitors connected in series.

[0057] Further, see Figure 3 , Figure 3 This is a circuit diagram of a third harmonic extraction frequency multiplier provided by an embodiment of the present invention. The third harmonic extraction frequency multiplier 102 includes a third harmonic extraction module 1021 and a third harmonic amplification module 1022. The third harmonic extraction module 1021 is connected to the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator 101, and is used to suppress the fundamental frequency signal in the differential signal of the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator 101 and extract the third harmonic component. The third harmonic amplification module 1022 is used to power amplify the extracted third harmonic component and achieve triple frequency of the fundamental frequency of the periodic pseudo-square wave AC differential signal of the class F oscillator 101.

[0058] The third harmonic extraction multiplier 102 can suppress the unnecessary fundamental component at the drain end of the class F oscillator 101 and extract and amplify the required third harmonic component, thereby realizing a high-frequency millimeter-wave clock signal with excellent phase noise performance.

[0059] The third harmonic extraction module 1021 of this embodiment includes a third MOS transistor M3, a fourth MOS transistor M4, an inductor L1, a capacitor group C fix, switched capacitor array C0, switched capacitor array C1, capacitor C n1 , capacitor C n2 , capacitor C ac1 , capacitor C ac2 , resistor R ac1 , resistor R ac2 and the inductor L s , where the capacitor C ac1 The capacitor C is connected between the first differential output terminal VDP of the class F oscillator 101 and the gate of the third MOS transistor M3. ac2 The capacitor C is connected between the second differential output terminal VDN of the class F oscillator 101 and the gate of the fourth MOS transistor M4. n1 Connected between the gate of the third MOS tube M3 and the drain of the fourth MOS tube M4, the capacitor C n2 Connected between the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4.

[0060] Capacitor group C fix , switched capacitor array C0 and inductor L s In parallel, the inductor L is connected between the source of the third MOS tube M3 and the source of the fourth MOS tube M4. s The tap of the inductor L1 is connected to the ground terminal GND; the inductor L1 and the switch capacitor array C1 are connected in parallel between the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4, and the tap of the inductor L1 is connected to the external power supply VPA1; the resistor R ac1 Connected between the gate of the third MOS tube M3 and the external bias voltage VPB1, the resistor R ac2 It is connected between the gate of the fourth MOS transistor M4 and the external bias VPB1; the switch capacitor array C0 and the switch capacitor array C1 are respectively connected to the output end of the logic circuit 107.

[0061] The third harmonic amplifying module 1022 of this embodiment includes a fifth MOS transistor M5, a sixth MOS transistor M6, an inductor L2, a switched capacitor array C2, a capacitor C n3 , capacitor C n4 , inductor L3, inductor L4 and external load resistor R load , wherein the drain of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are both connected to the ground terminal GND, the inductor L2 is connected between the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6, the inductor L2 and the inductor L1 form a transformer T1, and the tap of the inductor L2 is connected to the voltage VPB2; the capacitor C n3 Connected between the gate of the fifth MOS tube M5 and the drain of the sixth MOS tube M6, the capacitor C n4 Connected between the drain of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6.

[0062] The inductor L3 and the switch capacitor array C2 are connected in parallel between the drain of the fifth MOS tube M5 and the drain of the sixth MOS tube M6. The tap of the inductor L3 is connected to the external power supply VPA2. The inductor L3 and the inductor L4 form a transformer T2. The inductor L4 and the external load resistor R load connected in series between the two ground terminals; the switched capacitor array C2 is connected to the output terminal of the logic circuit 107; the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 serve as the first differential output terminal VDP2 and the second differential output terminal VDN2 of the third harmonic amplification module 1022 respectively.

[0063] Specifically, the capacitor C ac1 and capacitor C ac2 It is a DC blocking capacitor used to isolate DC voltage; the resistor R ac1 and resistor R ac2 The bias resistor is used to transfer the DC bias voltage VPB1 to the gate of the MOS tube. The MOS tubes M3 and M4 of the third harmonic extraction module provide the required gain to extract the third harmonic component. The resonant network at the source end of the MOS tubes M3 and M4 (including the inductor L s , capacitor group C fix The fundamental signal of the drain voltage of Class F oscillator 101 is suppressed by a resonant network (including transformer T1 and switched capacitor array C1) at the drain terminals of MOS transistors M3 and M4, which extracts the third harmonic. MOS transistors M5 and M6 in third harmonic amplification module 1022 also provide a large gain to amplify the extracted third harmonic. The resonant network at the drain terminals of MOS transistors M5 and M6 (including transformer T2 and switched capacitor array C2) enables gating of the third harmonic. By compromising the coupling coefficients km1 and km2 of the two sets of transformers T1 and T2, wideband or high output power operation can be achieved.

[0064] In the third harmonic extraction module 1021 and the third harmonic amplification module 1022, the capacitor C n1 , capacitor C n2 , capacitor C n3 and capacitor C n4 They are all connected as neutralizing capacitors in a cross-connected manner between the gate terminal of one MOS tube and the drain terminal of another MOS tube to ensure the common-mode stability of the third harmonic extraction module 1021 and the third harmonic amplification module 1022. The gate terminals of the MOS tubes M3 and M4 of the third harmonic extraction module 1021 are respectively connected to the DC blocking capacitors C ac1 , capacitor C ac2Isolated DC voltage. Bias voltage VPB2 provides a DC bias voltage for MOS transistors M5 and M6. Voltages VPA1 and VPA2 provide power supply voltages for third harmonic extraction module 1021 and third harmonic amplification module 1022, respectively. The coupling coefficients of transformers T1 and T2 are km1 and km2, respectively. VDP1 and VDN1 are the differential outputs of the third harmonic extraction module, and VDP2 and VDN2 are the differential outputs of the third harmonic amplification module 1021.

[0065] Further, see Figure 4 , Figure 4 This is another structural diagram of a fast automatic harmonic tracking circuit based on a third harmonic extraction frequency multiplier provided by an embodiment of the present invention. The negative peak detection circuit 103 of this embodiment has the seventh MOS transistor M7, the eighth MOS transistor M8 and the charging capacitor C AD The drain of the seventh MOS transistor M7 is connected to the second differential output terminal VDN2 of the third harmonic amplification module 1021 and the gate of the eighth MOS transistor M8, and the drain of the eighth MOS transistor M8 is connected to the second differential output terminal VDP2 of the third harmonic amplification module 1021 and the gate of the seventh MOS transistor M7; the source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are both connected to the charging capacitor C AD The first end of the charging capacitor C AD The second end of is connected to the ground end GND; the source of the eighth MOS transistor M8 serves as the output end of the negative peak detection circuit 103.

[0066] The cross-coupled MOS transistors M7, M8 and the charging capacitor C in the negative peak detection circuit 103 AD The amplitudes of the output signals VDP2 and VDN2 of the third harmonic extraction multiplier 102 are detected and the amplitude signal of the third harmonic difference signal is extracted.

[0067] The low-pass filter 104 of this embodiment includes a resistor R1 and a capacitor C4, wherein a first end of the resistor R1 is connected to the output end of the negative peak detection circuit 103, and a second end serves as the output end VSAMP of the low-pass filter 104; the capacitor C4 is connected between the output end VSAMP of the low-pass filter 104 and the ground end GND, and the node between the resistor R1 and the capacitor C4 serves as the output end VSAMP of the low-pass filter 104 and is connected to the sample-and-hold circuit 105.

[0068] The sample-and-hold circuit 105 of this embodiment includes a first sampling switch K1, a second sampling switch K2, a first sampling capacitor C samp1 and the second sampling capacitor C samp2, wherein the first sampling switch K1 is connected between the output terminal VSAMP of the low-pass filter 104 and the first input terminal VINP of the comparator 106, and the second sampling switch K2 is connected between the output terminal VSAMP of the low-pass filter 104 and the second input terminal VINN of the comparator 106; the first sampling capacitor C samp1 The second sampling capacitor C is connected between the first input terminal VINP of the comparator 106 and the ground terminal. samp2 Connected between the second input terminal VINN of the comparator 106 and the ground terminal. The sampling capacitor C in the sample and hold circuit 105 samp1 and C samp2 The first output terminal and the second output terminal of the sample and hold circuit 105 are used to output the amplitude signals VINP and VINN of different frequency bands respectively.

[0069] Furthermore, comparator 106 is configured to compare amplitude signals V INP and V INN of different frequency bands and output comparison results V COMP and V COMN , which are then input to logic circuit 107 . The output of logic circuit 107 is connected to the three switched capacitor arrays C0<3:0>, C1<3:0>, and C2<3:0> in third-harmonic extraction multiplier 102 , achieving accurate third-harmonic tracking within a very short microsecond timeframe and enabling wide-band applications.

[0070] In this embodiment, the logic circuit 107 presets the frequency band to 1000, samples the amplitude at the frequency band of 1000 in the first cycle, and then directly converts the frequency band to 1100 through the logic circuit 107. In the second cycle, the amplitude is sampled at the frequency band of 1100. The comparator 106 then compares the amplitudes at the frequency bands of 1000 and 1100.

[0071] Subsequently, logic circuit 107 generates digital signals C0<3:0>, C1<3:0>, and C2<3:0> using a logic search algorithm to control the switched capacitor arrays C0, C1, and C2 in third-harmonic extraction multiplier 102, accurately obtaining a third-harmonic resonant network. After harmonic tracking is complete (after third-frequency band comparison), the third harmonic is locked, and the automatic harmonic tracking circuit is deactivated via the logic circuit.

[0072] Specifically, see Figure 5 , Figure 5This is a schematic diagram of a logic search algorithm for a logic circuit provided by an embodiment of the present invention. The logic circuit uses a logic algorithm to output a 4-bit binary digital code consisting of 0s and 1s to control the conduction and shutdown of the capacitor switches in the corresponding bits of the switched capacitor array to achieve frequency band switching. Specifically, at the beginning of the logic search algorithm, the output of logic circuit 107 is reset to 1000. The first two steps of the algorithm are performed using a binary search method, similar to traditional switching algorithms. When VCOMP and VCOMN are 1 and 0, respectively, the frequency band increases (the binary digital code decreases); when VCOMP and VCOMN are 0 and 1, respectively, the frequency band decreases (the binary digital code increases). The third step uses an adaptive frequency band search to correct the final frequency band and make a final determination within two adjacent frequency bands. During the final comparison, if VCOMP and VCOMN are 1 and 0, respectively, the frequency band remains unchanged; when VCOMP and VCOMN are 0 and 1, respectively, the frequency band decreases. The last two bits of the binary digital code have the same weight, i.e., 4:2:1:1.

[0073] The fast automatic harmonic tracking circuit based on the third harmonic extraction multiplier of the embodiment of the present invention realizes wide-band application through a switched capacitor array, uses a negative peak detection circuit and a sample-and-hold circuit to detect the output amplitude of the third harmonic extraction multiplier, compares the amplitudes of different frequency bands through a comparator, and uses a logic circuit to realize automatic tracking of the third harmonic, thereby solving the problem that such multipliers require manual adjustment of the frequency band, which takes too much time, and accurately locks on the third harmonic, thereby achieving superior noise performance, lower power consumption and greater output power. In addition, the embodiment of the present invention accurately extracts the amplitude of the third harmonic through a negative peak detection circuit, calibrates the harmonic frequency of the harmonic multiplier and the injection-locked multiplier according to the harmonic amplitude, and provides a new method for automatically obtaining the operating point of the optimal phase noise and maximum output power.

[0074] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier, characterized in that: The invention comprises a class F oscillator (101), a third harmonic extraction frequency multiplier (102), a negative peak detection circuit (103), a low-pass filter (104), a sample-and-hold circuit (105), a comparator (106) and a logic circuit (107), wherein: The class F oscillator (101) is used to convert the DC voltage of the power supply into a periodic pseudo-square wave AC differential signal with a constant frequency and containing a third harmonic; The third harmonic extraction frequency multiplier (102) is connected to the Class F oscillator (101) and is used to suppress the fundamental frequency signal in the periodic pseudo square wave AC differential signal, and extract and amplify the third harmonic in the periodic pseudo square wave AC differential signal to obtain a third harmonic differential signal after fundamental frequency suppression; The negative peak detection circuit (103) is connected to the third harmonic extraction frequency multiplier (102) and is used to detect the amplitude of the third harmonic differential signal and extract the amplitude signal of the third harmonic differential signal; The low-pass filter (104) is connected to the negative peak detection circuit (103) and is used to filter the extracted third harmonic amplitude signal into a DC level; The sampling and holding circuit (105) is connected to the low-pass filter (104) and is used to sample and hold amplitude signals of different frequency bands; The comparator (106) is connected to the sample-and-hold circuit (105) and is used to compare amplitude signals of different frequency bands and output a comparison result; The logic circuit (107) is connected between the comparator (106) and the third harmonic extraction frequency multiplier (102), and is used to generate a digital control signal according to the comparison result, and control the switch capacitor array in the third harmonic extraction frequency multiplier (102) to adaptively switch the frequency band of the third harmonic extraction frequency multiplier (102) to a required frequency band.

2. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 1, characterized in that: The class F oscillator (101) comprises a first MOS transistor M1, a second MOS transistor M2, a capacitor group C D , capacitor group C G , switched capacitor array C S , switched capacitor array C P , variable capacitor C VAR 、Inductor L D and inductor L G ,in, The capacitor group C D , the switch capacitor array C P and the inductor L D The inductor L is connected in parallel between the drain of the first MOS tube M1 and the drain of the second MOS tube M2. D The tap is connected to the first power supply terminal VD; The inductor L G , the capacitor group C G , the switch capacitor array C S and the variable capacitance tube C VAR The inductor L is connected in parallel between the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2. G The tap is connected to the second power supply terminal VG, the inductor L G and the inductor L D Forming transformer T0, the variable capacitor C VAR An external control voltage Vcont is connected to control the variable capacitance tube C VAR The capacitance of the capacitor is adjusted to adjust the fundamental frequency of the Class F oscillator; The source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both connected to the ground terminal GND; the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 serve as the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator (101), respectively.

3. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 2, characterized in that: The capacitor group C D and the capacitor group C G Both include two capacitors connected in series.

4. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 2, characterized in that: The third harmonic extraction frequency multiplier (102) comprises a third harmonic extraction module (1021) and a third harmonic amplification module (1022), wherein: The third harmonic extraction module (1021) is connected to the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator (101), and is used to suppress the fundamental frequency signal in the differential signal between the first differential output terminal VDP and the second differential output terminal VDN of the class F oscillator (101), and to extract the third harmonic component; The third harmonic amplification module (1022) is used to perform power amplification on the extracted third harmonic component and realize the tripling of the fundamental frequency of the periodic pseudo square wave AC differential signal of the Class F oscillator (101).

5. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 4, characterized in that: The third harmonic extraction module (1021) includes a third MOS transistor M3, a fourth MOS transistor M4, an inductor L1, a capacitor group C fix , switched capacitor array C0, switched capacitor array C1, capacitor C n1 , capacitor C n2 , capacitor C ac1 , capacitor C ac2 , resistor R ac1 , resistor R ac2 and the inductor L s ,in, The capacitor C ac1 The capacitor C is connected between the first differential output terminal VDP of the class F oscillator (101) and the gate of the third MOS transistor M3. ac2 The capacitor C is connected between the second differential output terminal VDN of the class F oscillator (101) and the gate of the fourth MOS transistor M4. n1 connected between the gate of the third MOS tube M3 and the drain of the fourth MOS tube M4, the capacitor C n2 connected between the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4; The capacitor group C fix , the switched capacitor array C0 and the inductor L s The inductor L is connected in parallel between the source of the third MOS tube M3 and the source of the fourth MOS tube M4. s The tap is connected to the ground terminal GND; The inductor L1 and the switched capacitor array C1 are connected in parallel between the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4, and a tap of the inductor L1 is connected to an external power supply VPA1; The resistor R ac1 Connected between the gate of the third MOS tube M3 and the external bias voltage VPB1, the resistor R ac2 connected between the gate of the fourth MOS transistor M4 and the external bias VPB1; The switch capacitor array C0 and the switch capacitor array C1 are respectively connected to the output end of the logic circuit (107).

6. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 5, characterized in that: The third harmonic amplification module (1022) includes a fifth MOS transistor M5, a sixth MOS transistor M6, an inductor L2, a switch capacitor array C2, a capacitor C n3 , capacitor C n4 , inductor L3, inductor L4 and external load resistor R load , wherein the drain of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are both connected to the ground terminal GND, the inductor L2 is connected between the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6, the inductor L2 and the inductor L1 form a transformer T1, and the tap of the inductor L2 is connected to the voltage VPB2; The capacitor C n3 Connected between the gate of the fifth MOS tube M5 and the drain of the sixth MOS tube M6, the capacitor C n4 connected between the drain of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6; The inductor L3 and the switch capacitor array C2 are connected in parallel between the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6. The tap of the inductor L3 is connected to the external power supply VPA2. The inductor L3 and the inductor L4 form a transformer T2. The inductor L4 and the external load resistor R load connected in series between two ground terminals; the switch capacitor array C2 is connected to the output terminal of the logic circuit (107); The drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 serve as the first differential output terminal VDP2 and the second differential output terminal VDN2 of the third harmonic amplification module (1022), respectively.

7. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 6, characterized in that: The negative peak detection circuit (103) includes a seventh MOS transistor M7, an eighth MOS transistor M8 and a charging capacitor C AD ,in, The drain of the seventh MOS transistor M7 is connected to the second differential output terminal VDN2 of the third harmonic amplification module (1021) and the gate of the eighth MOS transistor M8, and the drain of the eighth MOS transistor M8 is connected to the second differential output terminal VDP2 of the third harmonic amplification module (1021) and the gate of the seventh MOS transistor M7; The source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are both connected to the charging capacitor C AD The first end of the charging capacitor C AD The second end is connected to the ground terminal GND; The source of the eighth MOS transistor M8 serves as the output end of the negative peak detection circuit (103).

8. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to claim 1, characterized in that: The low-pass filter (104) includes a resistor R1 and a capacitor C4, wherein: The first end of the resistor R1 is connected to the output end of the negative peak detection circuit (103), and the second end serves as the output end VSAMP of the low-pass filter (104); the capacitor C4 is connected between the output end VSAMP of the low-pass filter (104) and the ground end GND, and the node between the resistor R1 and the capacitor C4 serves as the output end VSAMP of the low-pass filter (104) and is connected to the sample-and-hold circuit (105).

9. The automatic harmonic tracking circuit based on an oscillator and a third harmonic frequency multiplier according to any one of claims 1 to 8, characterized in that: The sampling and holding circuit (105) includes a first sampling switch K1, a second sampling switch K2, a first sampling capacitor C samp1 and the second sampling capacitor C samp2 ,in, The first sampling switch K1 is connected between the output terminal VSAMP of the low-pass filter (104) and the first input terminal VINP of the comparator (106), and the second sampling switch K2 is connected between the output terminal VSAMP of the low-pass filter (104) and the second input terminal VINN of the comparator (106); The first sampling capacitor C samp1 The second sampling capacitor C is connected between the first input terminal VINP of the comparator (106) and the ground terminal. samp2 Connected between the second input terminal VINN of the comparator (106) and the ground terminal.

Images