On-chip Real-time FPN Correction Method

Abstract

The present invention relates to the field of image processing technology, and particularly relates to an on-chip real-time FPN correction method, which includes the steps of: S1. performing an addition calculation on the reset voltage and the signal voltage of image pixels in the image signal reading stage; S2. in the offset value extraction stage, performing two subtraction calculations on the reset voltage; S3. the counting processes in both stages are carried out on the same counter, and the final counting result is equivalent to subtracting the reset voltage from the signal voltage of the pixels, thereby obtaining an image information. The on-chip real-time FPN correction method of the present invention can correct FPN in real time, directly obtain the corrected result after the ADC quantization period, has low power consumption, high robustness, is insensitive to process, voltage and temperature changes, and is relatively easy to implement in architecture.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and particularly to an on-chip real-time FPN correction method. Background Art

[0002] Images, as carriers for information recording, play an increasingly important role in people's lives. The camera systems used for image acquisition have higher and higher requirements for imaging. The core component of the imaging system is the image sensor for photosensitive imaging, and its performance indicators directly determine the quality of the images. The imaging process of the image sensor is as follows. First, the optical signal is captured by the photosensitive elements (pixels) on the image sensor through an optical lens to form an electrical signal. The electrical signal is then subjected to analog and digital conversion through a readout circuit into a digital signal, and after data processing, the corresponding digital signal is output outside the chip to synthesize an image.

[0003] As Figure 1 shown, during the signal transmission process, there will be noise from various parts interfering with the signal. Among them, FPN (Fix Pattern Noise) is one of the main noises, which will cause spots and vertical stripes on the image. The generation of FPN seriously affects the imaging quality of the CMOS image sensor and becomes one of the main bottlenecks restricting the performance of the CMOS image sensor.

[0004] The CMOS image sensor will eliminate a part of the FPN, that is, the fixed noise between pixel columns, through CDS (Correlated Double Sampling) or CMS (Correlated Multiple Sampling). The required architecture and timing of CDS are as Figure 2 and Figure 3 shown. The ADC (Analog-to-Digital Converter) quantifies the RST voltage (reset voltage) and SIG voltage (signal voltage) of the pixels respectively, and stores the quantified digital quantities into the SRAM (Static Random-Access Memory), and performs subtraction in the subsequent data processing module to eliminate the FPN between pixel columns and a part of other noises. However, this method cannot eliminate the FPN between the columns of the readout circuit and can only perform algorithm optimization outside the chip. Summary of the Invention

[0005] In order to solve the above problems, the present invention provides an on-chip real-time FPN correction method, which can perform FPN correction inside the chip, improve the imaging quality of the CMOS image sensor, and reduce the additional workload after the chip is manufactured.

[0006] The present invention provides an on-chip real-time FPN correction method. The timing in the on-chip real-time FPN correction method includes an image signal reading stage and an offset value extraction stage. The on-chip real-time FPN correction method comprises the steps:

[0007] S1. In the image signal reading stage, perform an addition calculation on the reset voltage and the signal voltage of the image pixels;

[0008] S2. In the offset value extraction stage, perform two subtraction calculations on the reset voltage;

[0009] S3. The counting processes in both stages are carried out on the same counter. The final counting result is equivalent to subtracting the reset voltage from the signal voltage of the pixels, obtaining an image information.

[0010] Preferably, the time of the image signal reading stage is the same as the time of the offset value extraction stage.

[0011] Preferably, the timing in the on-chip real-time FPN correction method is implemented by an ADC circuit structure.

[0012] Preferably, the ADC circuit structure includes a comparator, an ADC logic controller, and an adder-subtractor counter.

[0013] Preferably, both the addition calculation and the subtraction calculation are implemented by the adder-subtractor counter in the ADC circuit structure.

[0014] Preferably, the adder-subtractor counter includes a signal for controlling addition and subtraction counting, a clock signal, a stop counting signal, a combinational logic control signal, and the output of the counter.

[0015] Preferably, when the signal for controlling addition and subtraction counting is at a high level, the adder-subtractor counter performs addition counting; when the signal for controlling addition and subtraction counting is at a low level, the adder-subtractor counter performs subtraction counting.

[0016] The on-chip real-time FPN correction method of the present invention can correct FPN in real time, directly obtain the corrected result after the ADC quantization period, has low power consumption, high robustness, is insensitive to process, voltage, and temperature changes, and is relatively easy to implement in architecture. Moreover, the area of the ADC circuit structure is relatively small. By using an adder-subtractor counter for real-time FPN correction, it avoids using too many storage modules to separately store the digital quantities after quantization of each signal voltage and reset voltage, and thus does not require a digital processing module for data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the noise classification commonly existing in a CMOS image sensor.

[0018] Figure 2It is a schematic diagram of the structure of a single-slope ADC circuit commonly used in CMOS image sensors.

[0019] Figure 3 It is a schematic diagram of the timing of a single-slope ADC in a CMOS image sensor through CDS sampling.

[0020] Figure 4 It is a schematic diagram of the connection method between the pixel bus and the comparator in a classic 4T pixel structure.

[0021] Figure 5 It is a schematic diagram of the timing in the on-chip real-time FPN correction method in a specific embodiment of the present invention.

[0022] Figure 6 It is a schematic diagram of the circuit structure in the on-chip real-time FPN correction method in a specific embodiment of the present invention.

[0023] Figure 7 It is a schematic diagram of the timing of the correction process in the on-chip real-time FPN correction method in a specific embodiment of the present invention.

[0024] Figure 8 It is a schematic diagram of the structure of an up / down counter in the on-chip real-time FPN correction method in a specific embodiment of the present invention. Specific Embodiments

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation to the present invention.

[0026] The explanations of the various professional terms mentioned in the present invention are as follows:

[0027] FPN: Fix Pattern Noise, the mainstream processing structure of the current CMOS image sensor system is to use a column-shared processing circuit, that is, each column of pixels shares a set of signal processing circuits. Due to various factors such as manufacturing process and layout, the mismatch between column processing circuits will bring performance deviation. In this way, even if the illumination on each pixel is the same, the output signal sizes of the corresponding column circuits are different, that is, the fixed noise unique to the array circuit is generated. For a given single pixel, FPN is fixed, and for different pixels it is different, so this kind of noise is called fixed pattern noise.

[0028] CDS: Correlated Double Sampling. That is, sampling is performed twice. One is the reset signal Vrst generated by the pixel, and the other is the signal voltage Vsig after pixel integration. Then, these two signals are subtracted to cancel out a part of the noise. CDS can mainly suppress noises such as 1 / f and KTC in MOS circuits.

[0029] CMS: Correlated Multiple Sampling. Similar to CDS, since some noises vary within a certain range over time, the noises sampled twice by CDS may not be the same, and such noises cannot be eliminated after subtraction. CMS is to sample Vrst and Vsig multiple times and then calculate the mean value. In this way, the amount of noise carried by these two voltages is more likely to be consistent. After performing subtraction operation on them, the homologous or related noises and errors are effectively reduced in the end.

[0030] As Figure 4 shown, it is a schematic diagram of the connection method between the pixel bus and the comparator in a classic 4T pixel structure. It can be seen from the figure that the column bus Column bus is connected to the ramp ADC. The working process of the pixel is as follows. First, the reset transistor RST is turned on to clear the FD dot charge, making the floating node voltage Vfd at this point equal to the pixel power supply voltage VDDPIX. PD is a photosensitive device, specifically a photosensitive diode, which converts the received optical signal into an electrical signal. As the electrons accumulate at its top, its voltage gradually decreases. After the exposure ends, the TX transistor is turned on, and the charge accumulated at the top of the photosensitive diode PD is introduced into the floating node FD, resulting in a decrease in the floating node voltage Vfd. SEL is a gating switch that controls whether the pixels in a row are connected to the column bus. When the SEL transistor is turned on, the floating node voltage Vfd is amplified by SF and used as the input Vpix of the ramp ADC. Usually, the pixel outputs two voltage signals, one is the reset voltage Vrst, and the other is the signal voltage Vsig. Subtracting the two voltages can remove the reset noise in the pixel and errors such as the compensation offset of the comparator, that is, CDS. Similar to CDS, since some noises vary within a certain range over time, subtracting only once the reset voltage Vrst and the signal voltage Vsig may not be able to subtract these noises. Therefore, after sampling the reset voltage Vrst and the signal voltage Vsig multiple times, calculating the mean value and then subtracting, the noises included in Vrst and Vsig are more likely to be equal, and the error after subtraction is smaller. Therefore, although CDS and CMS greatly improve the image quality, they still cannot eliminate the FPN between columns.

[0031] In a specific embodiment of the present invention, a method for on-chip real-time FPN correction is provided. The timing in the on-chip real-time FPN correction method includes an image signal reading stage and an offset value extraction stage. The on-chip real-time FPN correction method includes the steps:

[0032] S1. During the image signal reading stage, perform an addition calculation on the reset voltage and the signal voltage of the image pixels.

[0033] S2. During the offset value extraction stage, perform two subtraction calculations on the reset voltage.

[0034] S3. The counting processes in both stages are carried out on the same counter. The final counting result is equivalent to the signal voltage of the pixel minus the reset voltage, obtaining an image information.

[0035] The timing in the on-chip real-time FPN correction method provided by the specific embodiment of the present invention is specifically as Figure 5 shown, including an image signal reading stage (video signal reading phase) Ⅰ and an offset value extraction stage (offset extraction phase) Ⅱ. During the image signal reading stage, the reset voltage Vrst and the signal voltage Vsig of the pixel are quantized, and both are addition calculations. During the offset value extraction stage, Vrst is quantized twice, and both are subtraction calculations. Here, the counter of the ADC needs to have two counting capabilities of up and down, that is, in the specific embodiment of the present invention, the ADC circuit structure includes an up / down counter, so that the final result can be directly obtained after quantization, realizing the on-chip real-time correction of FPN, rather than storing each result in a memory and then performing data processing, which can save a large part of the layout area.

[0036] In the specific embodiment, under the timing of correcting FPN as Figure 5 shown, during the image signal reading stage, the reset voltage RST1 and the optical signal voltage SIG1 are obtained, and their sum is stored in the counter, that is, RST1 + SIG1. During the offset value extraction stage, the reset voltage RST2 and the optical signal SIG2 in the dark field are obtained, and both of these signals are subtracted and stored in the counter. At this time, in the counter is RST1 + SIG1 - RST2 - SIG2. Since the values of RST1, RST2, and SIG2 are approximately the same, and the difference is the KTC noise of the RST transistor, so the result in the counter at this time is SIG1 - RST1 plus the KTC noise of the RST transistor. Since this article is aimed at FPN noise, the KTC noise here will not be calculated further. Thus, the FPN is eliminated, and the specific process is as Figure 7 shown; Figure 7It is a timing diagram of the calibration process in the on-chip real-time FPN calibration method in a specific embodiment of the present invention. If the best calibration effect is desired, the time in the image signal reading stage and the offset value extraction stage needs to be the same to obtain an equal amount of FPN and then perform subtraction to eliminate it. However, this will increase the quantization time of the ADC by one time. Figure 5 is only an example of one of the timings. In other embodiments, according to the CMOS image sensor architecture, the two stages of the image signal reading stage and the offset value extraction stage can be interchanged and adjusted. Specifically, the two stages of the image signal reading stage and the offset value extraction stage can be adjusted with each other by adjusting the timing, that is, it is equivalent to first performing the offset value extraction stage and then performing the image signal reading stage.

[0037] Figure 6 It is a schematic diagram of the circuit structure in the on-chip real-time FPN calibration method in a specific embodiment of the present invention. Specifically, it is an ADC circuit structure. The ADC circuit structure includes a comparator, an ADC logic controller, and an up / down counter; Figure 5 The timing in the on-chip real-time FPN calibration method adopted in Figure 6 can be implemented by the circuit structure of Figure 5 The waveform of the ramp voltage Vramp in Figure 4 is input to the non-inverting input terminal of the comparator comp. Vramp is generated by a ramp generation circuit. The inverting input terminal of the comparator comp is connected to the pixel output signal, and its connection method is as shown in Figure 5 . The pixel output signal controls the pixel to output Vrst, Vsig, Vrst, Vrst in sequence through the selection SEL, reset RST, and transmit TX control timings in Figure 7 . These signals cause the output terminal of the comparator to flip through comparison with Vramp and generate a Conter_EN signal together with the timing control signal, as shown in Figure 8 . The Counter_EN signal is the signal that controls whether the counter counts. It generates the signal required for the counter to count after being ANDed with the clock signal CLK. The up / down counter controls whether the counter counts up or down through the Up / down control terminal. When it is at a high level, the counter counts up, and when it is at a low level, the counter counts down. After the counting is completed, the final value of the counter is stored in the SRAM through the Read signal. The up / down counter can be implemented by the structure of

[0038] In a specific embodiment, the up / down counter includes a signal for controlling up / down counting, a counting clock, a signal for stopping counting, a combinational logic control signal, and an output of the counter; as shown in Figure 8As shown in the figure, Up / down control is the signal for controlling up and down counting. When this signal is at a high level, all counters perform up counting; when the signal is at a low level, all counters perform down counting. CLK is the counting clock, that is, the clock signal. At each rising edge of the clock signal, the counter increments or decrements by one bit. Whether it increments or decrements by one bit is determined specifically according to whether Up / down control is at a high level or a low level. LOCK is the signal for stopping counting. When Up / down control is at a low level, counting stops and the output is locked. CLR and SET are combinational logic control signals. When CLR = 1, all counting is cleared; when SET = 1, all counting is set to 1. BIT<0:N - 1> is the output of the N-bit counter. Among them, BIT<0> is the least significant bit.

[0039] The on-chip real-time FPN correction method of the present invention can correct FPN in real time, directly obtain the corrected result after the ADC quantization period, has low power consumption, high robustness, is insensitive to process, voltage and temperature changes, and is relatively easy to implement in architecture. Moreover, the area of the ADC circuit structure is relatively small. By using an up / down counter for real-time FPN correction, it is avoided to use too many storage modules to store the digital quantities after quantizing each signal voltage and reset voltage respectively, and thus there is no need for a digital processing module to process data.

[0040] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0041] The above specific embodiments of the present invention do not constitute a limitation to the protection scope of the present invention. Any other corresponding changes and deformations made according to the technical concept of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A real-time on-chip FPN correction method, characterized in that The timing in the on-chip real-time FPN correction method includes an image signal reading stage and an offset value extraction stage; the on-chip real-time FPN correction method includes the steps: S1. During the image signal reading stage, perform an addition calculation on the reset voltage and the signal voltage of the image pixels; S2. During the offset value extraction stage, perform two subtraction calculations on the reset voltage; S3. The counting processes in both stages are carried out on the same counter. The final counting result is equivalent to subtracting the reset voltage from the signal voltage of the pixel, obtaining an image information.

2. The on-chip real-time FPN correction method according to claim 1, characterized in that The time of the image signal reading stage is the same as the time of the offset value extraction stage.

3. The on-chip real-time FPN correction method according to claim 1, characterized in that The timing in the on-chip real-time FPN correction method is implemented by an ADC circuit structure.

4. The on-chip real-time FPN correction method according to claim 3, wherein, The ADC circuit structure includes a comparator, an ADC logic controller, and an adder-subtractor counter.

5. The on-chip real-time FPN correction method according to claim 1, characterized in that Both the addition calculation and the subtraction calculation are implemented by the adder-subtractor counter in the ADC circuit structure.

6. The on-chip real-time FPN correction method according to claim 4, wherein When the signal controlling the addition and subtraction counting is at a high level, the adder-subtractor counter performs addition counting; when the signal controlling the addition and subtraction counting is at a low level, the adder-subtractor counter performs subtraction counting.

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