Physical memory compression

Abstract

A memory management system includes physical memory (108) associated with a computing device and a memory manager (102). The memory manager is configured to manage a shared memory cache (106) as part of compressing the physical memory using a cache compression algorithm, wherein the size of the compressed block used for compression is the size of a single cache line. The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses memory descriptors defined by STT entries having cache line maps and multiple sector pointers to load the cache from the physical memory into a Level 3 cache. The cache line maps contain cache line metadata, which includes the size of each cache line, the position of the cache line in one of the sectors pointed to by the STT entries, and multiple flags.

Description

Background Technology

[0001] Computer processor technology is rapidly evolving, leading to continuous improvements in processor performance, which in part depends on the available memory within a system (e.g., the memory available to the central processing unit (CPU) in a server). The performance of such processors can be adversely affected by other bottlenecks in the computer. For example, the speed at which data is transferred from the hard drive to random access memory (RAM) is a bottleneck for computer performance. One way to reduce the impact of bottlenecks in computers (such as servers) is to store more data in RAM. However, RAM remains so expensive that using very large amounts of RAM in computers (such as those required in server applications) is often prohibitively costly and impractical.

[0002] For example, currently about half of the capital expenditure (CAPEX) cost of servers is dynamic RAM (DRAM). Therefore, a significant increase in the amount of DRAM in a server will lead to a significant increase in the server's CAPEX cost. Consequently, currently available DRAM scaling techniques, especially in server applications, significantly increase the overall system cost. That is, as memory demand increases, the demand for physical memory (such as DRAM) also increases, and the only practical way to maintain system performance using traditional techniques is to add more memory. Memory compression techniques are also known, but these techniques generally have an adverse impact on system performance.

[0003] Therefore, current memory management technologies include: (i) compression techniques that involve compressing storage devices (e.g., storage disks), which can adversely affect system performance (including system speed), or (ii) increasing the amount of physical memory (such as DRAM), which increases the overall system cost. As a result, current technologies cannot be effectively scaled without sacrificing system performance or increasing system cost. Summary of the Invention

[0004] This summary is provided to introduce the selection of concepts in a simplified form, which will be further described in the detailed embodiments below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0005] A computerized method for tracking compressed memory includes: accessing a sector translation table (STT) defined by descriptors, wherein the descriptors include cache line mappings and multiple sector pointers to the sector memory. The computerized method also includes retrieving cache line metadata associated with the cache line from the cache line mappings, wherein the cache line metadata includes one or more flags, sector numbers, cache segment lengths, and cache line lengths. The computerized method further includes: loading the cache line from physical memory into the last level cache (LLC) based on the cache line metadata, wherein the size of the compressed block is the same as the size of a single cache line. The computerized method also includes using multiple cache lines to track the compressed physical memory.

[0006] Many of the accompanying features will be easier to understand as they become clearer through reference to the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0007] This description will be better understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram illustrating a memory management architecture based on an example.

[0009] Figure 2 This is a block diagram illustrating a memory management architecture based on another example;

[0010] Figure 3 This is a block diagram illustrating a memory management architecture based on another example;

[0011] Figure 4 It is a graph illustrating the compression ratio of different compression algorithms;

[0012] Figure 5 This is a block diagram illustrating physical memory management;

[0013] Figure 6 This is a block diagram illustrating a memory descriptor based on an example;

[0014] Figure 7 It is a block diagram based on an example free sector heap;

[0015] Figure 8 The diagram illustrates a flowchart of a method for tracking compressed physical memory, based on an example; and

[0016] Figure 9 This is a block diagram of an example computing environment suitable for implementing some of the various examples disclosed in this paper.

[0017] The corresponding reference numerals in the accompanying drawings indicate the relevant parts. In the drawings, the system is illustrated schematically. The drawings may not be drawn to scale. Detailed Implementation

[0018] In some examples, the computing devices and methods described herein are configured to perform inline physical memory compression using a combination of physical memory compression and cache memory compression techniques. Inline physical memory compression achieves real-time and transparent memory compression within the memory controller. Therefore, it is possible to use reduced physical memory, such as in a server, while performing the same amount of processing (e.g., reducing physical memory by an average of half to perform the same level of processing).

[0019] In various examples, the memory management architecture and / or system performs memory compression at cache line sizes. That is, the memory management techniques disclosed herein provide inline memory compression at cache line boundaries. In a particular example, a cache compression algorithm is used to compress DRAM, thereby extending cache compression techniques to physical memory with memory management. In some examples, cache line mapping is implemented to track memory compression at cache line sizes. That is, the compressed block size used in this disclosure is a single cache line size rather than multiple cache lines. Therefore, there is no difference between the CPU cache line size and the compressed block size, so there is no need to add a compression cache, which would increase performance and bandwidth overhead. Therefore, the compression algorithm of this disclosure is "lightweight" and power efficient (e.g., not "heavy" or expensive in terms of surface area, power, and latency). In this way, when the processor is programmed to perform the operations described herein, the processor is used in an unconventional manner and allows for improved memory performance without increasing physical memory or degrading processor performance, thereby improving the user experience.

[0020] In some examples, memory management techniques perform higher levels of compression throughout the compression hierarchy. That is, cache lines are stored in a compressed manner in the last-level cache (LLC), thereby increasing the LLC and improving performance. Using the cache compression algorithms disclosed herein and described herein, physical memory compression is performed using memory management techniques that contribute very little (e.g., 3%) overhead to managing the compressed physical memory.

[0021] More specifically, various examples perform physical memory compression, which includes compression of user data as well as compression of memory blocks that are not used in other ways. For example, most applications tend to have zero blocks in memory, which can account for up to 21% of the total physical memory blocks in a server workload. These blocks are rarely accessed by the CPU and tend to be very "cold". The inline physical memory compression disclosed in this paper effectively compresses these blocks, thereby freeing up most of these memory blocks (e.g., pages) for use elsewhere.

[0022] In one example, total physical memory compression is implemented, which reduces system cost (by decreasing the demand for physical memory) and improves overall system performance (by reducing I / O and paging operations). This document discloses two configurations for implementing physical memory compression: CPU-based and external memory management controller (MMC) / bridge-based. However, it should be understood that this disclosure is not limited to these configurations, which are described for illustrative purposes only. Various systems implemented with different architectures will now be described.

[0023] Figure 1 This is a block diagram illustrating a memory management architecture 100 according to an example. In this embodiment, the memory management architecture 100 is shown as a CPU-based memory compression configuration. That is, the memory management architecture 100 is a CPU-based cache management configuration in which compression is integrated into the CPU memory hierarchy, and compression / decompression is seamlessly performed as part of the load / store operation semantics. There are two different arrangements of the CPU-based memory compression configuration. Figure 1 In the first arrangement shown, compression / decompression occurs at the physical memory level. That is, the compressor and decompressor 104 are located (connected) between LLC 106 (shown as a Level 3 shared cache (shared cache L3)) and physical memory 108 (shown as DRAM). The compressor and decompressor 104 are used (called) as a result of LLC cache write-back or LLC read miss. It should be understood that in this configuration, LLC 106 contains the decompressed data, while physical memory 108 is compressed. Alternatively, the compressor and decompressor 104 can be any type of compression and decompression device that performs data compression and decompression using one or more different signal processing techniques.

[0024] exist Figure 2In the second arrangement shown, the memory management architecture 200 is configured with compression / decompression, i.e., a compressor and decompressor 204 located "on top" of LLC 106 between LLC 106 and other caches 110. That is, compression and decompression operations occur after the LLC is read or written by the compressor and decompressor 204 connected between LLC 106 and other caches 110. In this arrangement, both LLC 106 and physical memory 108 are compressed. Therefore, in Figure 2 In the memory management architecture, MMC-based memory compression is configured with a compressed L3 cache. It should be noted that in various examples, the same numbers represent the same parts.

[0025] like Figure 1 and Figure 2 As shown, in both arrangements, MMC 102 and physical memory 108 operate at the physical address level, while LLC 106 operates at the real address level and communicates with other caches 110, which are shown as L1 and L2 caches (Cache L1 and Cache L2). Furthermore, core 112 (e.g., the CPU processing core) operates at the virtual address level.

[0026] In operation, the MMC 102 controls memory management to provide physical memory compression as described in more detail herein. This control includes managing memory compression using a sector translation look-ahead buffer (STLB) 114 and a free sector cache (FSC) 116.

[0027] Figure 3 This is a block diagram illustrating a memory management architecture 300 according to another example. In this embodiment, the memory management architecture 300 is shown as a bridge-based memory compression configuration, i.e., an external MMC / bridge-based configuration. In this configuration, the compressor / decompressor 304 is located "external" to the CPU (and integrated MMC 102 or 202) in the external memory interface, which is shown as a compute fast link (CXL) CPU-to-device interconnect configured to also couple to an external cache 306 of the CXL MMC 302. The compressor / decompressor 304 is an external device, thus forming part of an external memory controller or bridge. It should be understood that this configuration works well in systems with extended memory systems via CXL, GenZ, OpenCAPI, or other similar mechanisms. In various examples, compression using the memory management architecture 300 helps reduce memory requirements and bandwidth requirements for memory interconnects.

[0028] Using the architecture described herein, this disclosure implements one or more compression algorithms. In some examples, cache compression algorithms are used to compress physical memory. Various compression algorithms and implementation considerations will now be discussed. Specifically, in some examples, the compression algorithms are lossless, ensuring no information loss during compression. In other words, decompressing a compressed block always generates the original uncompressed block 100% of the time. Second, the various compression algorithm examples exhibit low latency for compression and decompression. In other words, decompression and compression do not increase memory load latency. Third, the compression algorithms provide good compression efficiency for cache line-sized memory blocks (32 bytes or 64 bytes in various examples). It should be understood that the complexity of the compression algorithm does not necessarily lead to a better compression ratio. Fourth, the compression algorithms have low power requirements, ensuring no increase in the overall thermal design power (TDP) of the CPU. Fifth, the compression algorithms have low die area requirements.

[0029] This disclosure recognizes the observation behind Basic Increment Immediate (BDI) compression that, for many cache lines, the data values ​​stored within that line have a low dynamic range (i.e., the relative differences between values ​​are small). In this case, cache lines can be represented in a compact form using a common base value plus a set of relative differences (“increments”), the combined size of which is much smaller than the original cache line.

[0030] Firewall Policy Compression (FPC) is a lossless, single-channel, linear-time compression algorithm designed for double-precision floating-point data streams with unknown internal structures, such as data viewed by storage devices in network, scientific, or high-performance computing systems. FPC provides good average compression ratios for difficult-to-compress digital data.

[0031] C-Pack+Z achieves compression in two ways: (1) using statically determined compact encoding for frequently occurring data words; and (2) using a dynamically updated dictionary to accommodate other frequently occurring words. This dictionary supports both partial and full-word matching. Unlike BDI and FPC, the dictionary used, though small, improves compression ratios without adding extra complexity.

[0032] like Figure 4 As shown in Chart 400, C-Pack+Z achieves the highest compression ratio for a block size of 64 bytes. GZIP is added for comparison with the "gold standard" of offline data compression. However, GZIP requires a larger block size to achieve optimal efficiency. For a block size of 64 bytes, C-Pack+Z demonstrates superior performance and is used in various examples.

[0033] An example of memory management for compressed memory will now be discussed. It should be understood that memory management can be implemented using any architecture described in this article or other architectures.

[0034] More specifically, and also referring to Figures 1 to 3 During operation, utilizing methods such as Figure 5 The physical memory management 500 shown uses one or more processing cores to execute instructions using virtual addresses. All virtual addresses are then translated to physical addresses using a CPU TLB table (e.g., STLB 114). These physical addresses are used to access cache lines in L1 cache 110, L2 cache 110, and L3 cache 106, respectively. In the event of an L3 cache miss, the physical address is translated to a physical address before a load or store operation is issued to the DIMM by the MMC 102, 202, or 302. The MMC 102, 202, or 302 uses STLB 114 internally to perform this translation. In one example, as... Figure 5 As shown, STLB 114 is a cache of entries from sector translation table (STT) 502. This disclosure implements the physical memory organization described below.

[0035] The physical memory is divided into two main regions: the STT 502 region and the sector memory region 504. The STT 502 is an array of 64-byte descriptors 506. Each descriptor 506 contains metadata and location information corresponding to 32 physical memory cache lines, equivalent to 2KB of physical memory. In the example shown, the 64-byte descriptor 506 includes a 32-byte cache line map 508, a 16-byte segment allocator 510, and four sector pointers 512 totaling 16 bytes (i.e., each of the four sector pointers 512 has 4 bytes). In this configuration, the STT 502 is used by MMC 102, 202, or 302 to manage and track the metadata of the actual compressed physical memory.

[0036] The second part is sector memory region 504. This sector memory region 504 is divided into blocks 514 of 512 bytes and is the actual memory (physical memory or real memory) that stores the operating system and application data and content. In one example, each STT entry can point to a maximum of four blocks 514, with a maximum size of 2KB. If all 2KB of real memory is empty, the corresponding STT entry points to zero blocks. In the case of a 2KB compression ratio of 1 (incompressible), the STT entry points to four blocks within block 514.

[0037] In various examples, the memory descriptor 600, shown as an STT entry, is implemented as follows: Figure 6As shown. Each entry is divided into two main regions: cache line mapping 602 and four sector pointers 604. The four sector pointers 604 are four 40-bit fields. Each field is a pointer to a 512-byte memory sector used as storage for the compressed contents of the cache line. Depending on the compression ratio of the cache line, zero to four sector pointers 604 can be used. Because this disclosure uses optimization techniques to store zero cache lines, all pointers 604 are empty when all 32 cache lines associated with the STT entry are zero. On the other hand, if all cache lines are incompressible or have a very low compression ratio, all four pointers 604 point to physical memory sectors.

[0038] In one example, the first 48 bytes of an STT entry are cache line mapping 602, which contains cache line metadata such as the size of each cache line, the location of the cache line in one of the sectors pointed to by the STT entry, and other flags. Figure 6 In the example shown, the 48-byte map is divided into 32 12-bit fields 606. The first three bits 608 are flags associated with cache lines. Bit 0 describes whether the cache line is allocated a 1 or not allocated a 0. Bit 2 is 0 if the cache line is zero, otherwise it is 1. Bit 3 is 0 if the cache line is not compressed, and 1 if it is compressed. The next two bits 610 (bits 3 and 4) specify the sectors (from four possible sectors) that store the cache line. Each memory sector is logically divided into 16-byte segments. Compacted cache lines use zero to four segments to store the cache line. The next two bits 612 (bits 5 to 9) are used to store the address of the compressed line within the sector (16-byte aligned). The last bit 614 (bits 10 and 11) is used to store the length of the cache line in 16-byte units. It is important to note that the sector number (sector #), segment offset (cache segment #), and length are three (or triplets) that uniquely identify a compressed cache line.

[0039] During operation, and also referring to Figures 1 to 3MMCs 102, 202, and 302 are configured as memory managers that receive the physical address and zero out the least significant 11 bits to obtain an STT entry containing all metadata corresponding to the 32 cache lines associated with that entry. MMCs 102, 202, and 302 load the entry into STLB 114. In one example, bits 6 through 11 of the physical address include the cache line number to be loaded. MMCs 102, 202, and 302 locate the metadata flags, sector #, cache segment #, and length. The metadata contains all the information used by MMCs 102, 202, and 302 to load the cache lines from physical memory into L3 cache 106. In one example, each physical memory access uses two memory reads. One read is used to read the STT entry, and the second read is used for the actual cache line. In some examples, to optimize physical memory access, an STLB cache is added to MMCs 102, 202, and 302 to help reduce STT entry reads.

[0040] In one example, such as Figure 7 As shown, all free memory sectors are organized into a heap 700 (i.e., a free sector heap), and it uses free sectors for storage. Heap 700 is accessed by the free list header 706. In this example, each sector can store up to 63 pointers 702a to free sectors. The last 8 bytes of a sector are pointers 704 to the next sector containing the free sector pointer 702b. In some examples, MMCs 102, 202, and 302 include a free sector register (shown as the free list header) pointing to the first sector of heap 700. To optimize free sector allocation, in one example, MMCs 102, 202, and 302 cache several sectors (e.g., three or four sectors) from the free memory sectors into FSC 116. As free memory sectors are consumed, the sectors used by the free sector heap are freed and added to heap 700. Therefore, heap 700 does not consume any physical memory.

[0041] This disclosure also uses other mechanisms. In some examples, the MMC 102, 202, 302 includes a set of registers that track data compression ratios, the ratio of free physical memory sectors to used physical memory sectors, etc. Furthermore, in some examples, the MMC 102, 202, 302 includes a set of programmable interrupts used to generate events when a specific counter is reached.

[0042] Figure 8The document illustrates a method 800 for tracking and compressing physical memory to allow for the use of cache compression algorithms. For example, by implementing method 800, a cache compression algorithm can be used to compress DRAM to the cache line size. In some examples, physical memory compression and cache compression are used to compress inline physical memory. The operations illustrated in the flowcharts described herein may be performed in a different order than those shown, may include additional or fewer steps, and may be modified as desired or required. Furthermore, one or more operations may be performed simultaneously, in parallel, or sequentially.

[0043] More specifically, and also referring to Figures 1 to 7 and Figure 9 Method 800 includes accessing the STT defined by the descriptor at 802. In some examples, the descriptor includes a cache line map and sector pointers to sector memory. For example, as described herein, memory descriptor 600 includes a cache line map 602 and sector pointers 604. It should be understood that memory descriptor 600 may have different configurations that allow compression at the cache line size.

[0044] Method 800 retrieves cache line metadata from the cache line map in 804. The cache line metadata includes one or more flags, sector number, cache segment length, and cache line length. Figure 6 The diagram illustrates an example of metadata configuration. It should be understood that the order and size of each part of the metadata can be changed as desired or required. In some examples, each descriptor contains metadata and location information about 32 physical memory cache lines, which is equivalent to 2KB of physical memory.

[0045] Method 800 loads cache lines from physical memory into the LLC based on cache line metadata in 806, where the compressed block size is a single cache line. That is, loading cache lines allows memory management at cache line boundaries to perform cache compression techniques to compress physical memory without using compressed memory caches. The compressed physical memory is tracked using the metadata of this disclosure to allow the use of cache compression techniques. For example, in 808, multiple cache lines are used to track physical memory. That is, this method allows memory management of physical memory. In one example, MMC 102, 202, or 302 uses STT defined by metadata to manage and track the actual compressed physical memory.

[0046] It should be understood that this disclosure and the examples described herein can be implemented in different environments. For example, the memory management and compression techniques described herein can be implemented in a cloud computing environment. However, this disclosure can be implemented in conjunction with any type of computing device or system, such as Figure 9The computing device 900 is shown in the diagram.

[0047] Example operating environment

[0048] Figure 9 This is a block diagram of an example computing device 900 used to implement the aspects disclosed herein, and is generally designated as computing device 900. Computing device 900 is merely an example of a suitable computing environment and is not intended to impose any limitation on the scope or functionality of the examples disclosed herein. Computing device 900 should also not be construed as having any dependencies or requirements associated with any one or combination of the shown components / modules. The examples disclosed herein can be described in the general context of computer code or machine-usable instructions, including computer-executable instructions (such as program components) executed by a computer or other machine (such as a personal data assistant or other handheld device). Generally, a program component, including routines, programs, objects, parts, data structures, etc., refers to code that performs a specific task or implements a specific abstract data type. The disclosed examples can be implemented in a variety of system configurations, including servers, personal computers, laptops, smartphones, mobile tablets, handheld devices, consumer electronics, professional computing devices, etc. The disclosed examples can also be implemented in distributed computing environments when the task is performed by a remote processing device linked via a communication network.

[0049] Computing device 900 includes a bus 910 that directly or indirectly couples to the following devices: computer storage memory 912 (which includes physical memory such as DRAM), one or more processors 914, one or more presentation units 916, input / output (I / O) ports 918, I / O units 920, power supply 922, and network units 824. Although computer device 900 is depicted as a single device, multiple computing devices 900 can work together and share the depicted device resources. For example, computer storage memory 912 can be distributed across multiple devices, processors 914 can be provided and housed on different devices, etc.

[0050] Bus 910 indicates that it can be one or more buses (such as an address bus, a data bus, or a combination thereof). Although for clarity... Figure 9 The various blocks are represented by lines; in reality, depicting each component is not so clear, and metaphorically, the lines would be more accurately described as gray and blurry. For example, the presentation components of a display device can be considered as I / O components. Furthermore, the processor has memory. This is the essence of the art, and to reiterate... Figure 9 The diagrams only illustrate exemplary computing devices that can be used in conjunction with one or more of the publicly disclosed examples. There is no distinction between categories such as "workstation," "server," "laptop," and "handheld device," as all of these categories are... Figure 9 Within the scope of this document's reference to "computing device," computer storage memory 912 may take the form of a computer storage medium referenced below and operatively provide storage for computer-readable instructions, data structures, program modules, and other data to computing device 900. For example, computer storage memory 912 may store an operating system, a general-purpose application platform, or other program modules and program data. Computer storage memory 912 can be used to store and access instructions configured to perform the various operations disclosed herein.

[0051] As described below, computer storage memory 912 may include volatile and / or non-volatile memory, removable or non-removable memory, a data disk in a virtual environment, or a combination thereof as computer storage media. Furthermore, computer storage memory 912 may include any number of memories associated with or accessible by computing device 900. Memory 912 may be internal to computing device 900 (e.g., Figure 9 The memory 912 may be located outside the computing device 900 (not shown), or both inside and outside the computing device 900 (not shown). Examples of memory 912 include, but are not limited to, random access memory (RAM); read-only memory (ROM); electrically erasable programmable read-only memory (EEPROM); flash memory or other storage technologies; CD-ROM, digital versatile optical disc (DVD) or other optical or holographic media; magnetic tape, magnetic tape, disk storage or other magnetic storage devices; memory connected to an analog computing device; or any other medium used by the computing device 900 to encode and access desired information. Additionally or alternatively, the computer storage memory 912 may be distributed across multiple computing devices 900, for example, in a virtualized environment where instruction processing is executed on multiple devices 900. For the purposes of this disclosure, “computer storage medium,” “computer storage memory,” “memory,” and “storage device” are synonyms for computer storage memory 912, and none of these terms include a carrier wave or propagating signal.

[0052] The (multiple) processors 914 may include any number of processing units that read data from various entities such as memory 912 or I / O components 920. Specifically, the (multiple) processors 914 are programmed to execute computer-executable instructions to implement aspects of this disclosure. The instructions may be executed by a processor, multiple processors within computing device 900, or a processor external to client computing device 900. In some examples, the (multiple) processors 914 are programmed to execute instructions. Furthermore, in some examples, the (multiple) processors 914 represent an implementation of analog technology to perform the operations described herein. For example, the operations may be performed by analog client computing device 900 and / or digital client computing device 900. The (multiple) presentation components 916 present data indications to a user or other device. Exemplary presentation components include display devices, speakers, printing components, vibrating components, etc. Those skilled in the art will understand and recognize that computer data can be presented in a variety of ways, such as visually in a graphical user interface (GUI), audibly through a speaker, wirelessly between computing devices 900, via a wired connection, or otherwise. Port 918 allows computing device 900 to be logically coupled to other devices, including I / O components 920, some of which may be built-in. Example I / O components 920 include, for example, but not limited to, microphones, joysticks, game controllers, satellite antennas, scanners, printers, wireless devices, etc.

[0053] Computing device 900 can operate in a network environment via network component 924 using a logical connection to one or more remote computers. In some examples, network component 924 includes a network interface card and / or computer-executable instructions (e.g., a driver) for operating the network interface card. Communication between computing device 900 and other devices can occur over any wired or wireless connection using any protocol or mechanism. In some examples, network component 924 is operable to use a transmission protocol with short-range communication technologies (e.g., Near Field Communication (NFC), Bluetooth). TM Wirelessly transmitting data or a combination thereof between devices (such as brand communication devices) over public, private, or hybrid (public and private) networks. For example, network component 924 communicates with network 828 via communication link 926.

[0054] Although described in conjunction with example computing device 900, the examples of this disclosure can be implemented with many other general-purpose or special-purpose computing system environments, configurations, or devices. Examples of well-known computing systems, environments, and / or configurations applicable to aspects of this disclosure include, but are not limited to, smartphones, mobile tablets, mobile computing devices, personal computers, server computers, handheld or laptop devices, multiprocessor systems, game consoles, microprocessor-based systems, set-top boxes, programmable consumer electronics, mobile phones, mobile computing and / or wearable or accessory-type communication devices (e.g., watches, glasses, headsets, or headphones), network PCs, minicomputers, mainframes, distributed computing environments including any of the above systems or devices, VR devices, holographic devices, etc. Such systems or devices can accept input from users in any manner, including from input devices such as keyboards or pointing devices, gesture input, proximity input (such as by hovering), and / or voice input.

[0055] Examples of this disclosure can be described in the general context of computer-executable instructions, such as program modules, that are executed by one or more computers or other devices as software, firmware, hardware, or a combination thereof. Computer-executable instructions can be organized into one or more computer-executable parts or modules. Typically, program modules include, but are not limited to, routines, programs, objects, components, and data structures that perform a particular task or implement a particular abstract data type. Aspects of this disclosure can be implemented with any number and organization of such parts or modules. For example, aspects of this disclosure are not limited to specific computer-executable instructions or specific parts or modules shown in the figures and described herein. Other examples of this disclosure may include different computer-executable instructions or parts having more or fewer functions than those described herein. In examples involving general-purpose computers, aspects of this disclosure transform a general-purpose computer into a special-purpose computing device when configured to execute the instructions described herein.

[0056] By way of example and not limitation, computer-readable media include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable memory implemented in any manner or technology for storing information such as computer-readable instructions, data structures, program modules, etc. Computer storage media are tangible and mutually exclusive with communication media. Computer storage media are implemented in hardware and do not include carrier waves and propagating signals. Computer storage media used for the purposes of this disclosure are not signals themselves. Exemplary computer storage media include hard disks, flash drives, solid-state memory, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies, optical disc read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other non-transfer medium that can be used to store information for access by a computing device. In contrast, communication media typically embody computer-readable instructions, data structures, program modules, and any information transmission within modulated data signals such as carrier waves or other transmission mechanisms.

[0057] In examples involving general-purpose computers, when configured to execute the instructions described herein, aspects of this disclosure transform a general-purpose computer into a dedicated computing device.

[0058] A memory management system includes physical memory associated with a computing device; and a memory manager configured to manage a shared memory cache as a portion of the physical memory to be compressed using a cache compression algorithm, wherein the size of the compressed block is a single cache line size.

[0059] A computerized method for tracking compressed memory includes: accessing a sector translation table (STT) defined by a descriptor, the descriptor including cache line mappings and multiple sector pointers to the sector memory; obtaining cache line metadata associated with the cache lines from the cache line mappings, the cache line metadata including one or more flags, sector number, cache segment length, and cache line length; loading the cache lines from physical memory into the last level cache (LLC) based on the cache line metadata, wherein the size of the compressed block is the same as the size of a single cache line; and using multiple cache lines to track the compressed physical memory.

[0060] One or more computer storage media have computer-executable instructions to perform memory management, which, when executed by a processor, cause the processor to at least: access a sector translation table (STT) defined by a descriptor, the descriptor including cache line mappings and multiple sector pointers to sector memory; obtain cache line metadata associated with the cache line from the cache line mappings, the cache line metadata including one or more flags, sector number, cache segment length, and cache line length; load the cache line from physical memory into the last level cache (LLC) based on the cache line metadata, wherein the size of the compacted block is the same as the size of a single cache line; and use multiple cache lines to track the compacted physical memory.

[0061] Alternatively, or in addition to the other examples described herein, examples include any combination of the following:

[0062] The physical memory includes dynamic random access memory (DRAM), and the memory manager includes a sector translation look-ahead buffer (STLB) with entries from a sector translation table, wherein the memory manager is configured to use the STLB to translate real memory addresses into physical memory addresses.

[0063] The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses memory descriptors defined by STT entries, which have cache line mappings and multiple sector pointers.

[0064] The multiple sector pointers include four sector pointers, each of which is a 40-bit field. Each 40-bit field is a pointer to a 512-byte memory sector, which is used to store the compressed contents of the cache line.

[0065] The first 48 bytes of the STT entry are a cache line mapping containing cache line metadata, which includes the size of each cache line, the location of the cache line in one of the sectors pointed to by the STT entry, and several flags.

[0066] The first 48 bytes are configured to be mapped into 32 12-bit fields, with the first three bits being flags associated with cache lines;

[0067] It also includes a Level 3 cache (L3 cache), in which the memory manager is configured to locate one or more metadata flags and cache line metadata, and use one or more metadata flags and cache line metadata to load cache lines from physical memory into the L3 cache;

[0068] The sector number, segment offset, and length uniquely identify the compressed cache line;

[0069] It also includes a free sector cache, which is configured to store free memory sectors;

[0070] The physical memory has a block size of 64 bytes, and the cache compression algorithm is C-Pack+Z compression algorithm;

[0071] The memory manager includes multiple compressors and decompressors;

[0072] The sector memory is configured into a physical memory block storing at least one of operating system data and application data, and also includes receiving a real address and setting multiple least significant bits of the real address to zero to obtain an STT entry containing cache line mapping and multiple sector pointers.

[0073] This also includes organizing free memory sectors into a free sector heap, which is stored using free memory sectors, wherein the sector memory includes sectors that store pointers to free memory sectors; and

[0074] It also includes multiple sectors of the cache free storage sector;

[0075] As will be apparent to those skilled in the art, any range or device value given herein may be extended or altered without losing the desired effect.

[0076] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

[0077] It should be understood that the above benefits and advantages may relate to one embodiment or several embodiments. The embodiments are not limited to embodiments that solve any or all of the described problems or that have any or all of the described benefits and advantages. It will be further understood that reference to "one" item means one or more of those items.

[0078] The embodiments illustrated and described herein, as well as embodiments not specifically described herein but within the scope of the claims, constitute exemplary apparatus for memory compression. One or more processors 914 illustrated, together with computer program code stored in memory 912, constitute exemplary processing apparatus for managing memory compression as described herein.

[0079] The term "comprising" is used in this specification to mean including the features or actions that follow, but does not exclude the presence of one or more additional features or actions.

[0080] In some examples, the operations illustrated in the figures can be implemented as software instructions encoded on a computer-readable medium, in hardware programmed or designed to perform the operations, or both. For example, aspects of this disclosure can be implemented as a system-on-a-chip or other circuitry comprising multiple interconnected conductive elements.

[0081] Unless otherwise stated, the order of execution or the execution of operations in the examples of this disclosure illustrated and described herein is not required. That is, unless otherwise stated, operations may be executed in any order, and the examples of this disclosure may include more or fewer operations than those disclosed herein. For example, specific operations are expected to be performed before, simultaneously with, or after another operation, or to be performed within the scope of aspects of this disclosure.

[0082] When introducing elements or examples of aspects of this disclosure, the articles “a,” “an,” “the,” and “the” are intended to indicate the presence of one or more elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and indicate that other elements may exist in addition to the listed elements. The term “exemplary” is intended to mean “an example of…”. The phrase “one or more of the following: A, B, and C” means “at least one of A and / or at least one of B and / or at least one of C.”

[0083] Various aspects of this disclosure have been described in detail, and modifications and changes may be made without departing from the scope of the aspects of this disclosure as defined in the appended claims. Because various changes can be made to the above structures, products, and methods without departing from the scope of the aspects of this disclosure, everything contained in the above description and shown in the accompanying drawings should be interpreted as illustrative rather than restrictive.

Claims

1. A memory management system, comprising: Physical storage, associated with computing devices; as well as A memory manager is configured to manage a shared memory cache, the management including compressing the physical memory using a cache compression algorithm, wherein the size of the compressed block used for the compression is the size of a single cache line, the memory manager using a memory descriptor having a cache line mapping and multiple sector pointers, the cache line mapping containing cache line metadata including the size of each cache line, the position of the cache line in a sector, and multiple flags.

2. The memory management system of claim 1, wherein the physical memory includes dynamic random access memory (DRAM), and the memory manager includes a sector translation look-ahead buffer (STLB) with entries from a sector translation table (STT), wherein the memory manager is configured to use the STLB to translate real memory addresses into physical memory addresses of the physical memory.

3. The memory management system according to claim 1, wherein the physical memory includes a sector translation table (STT) area and a sector memory area, wherein the memory descriptor is defined by an STT entry.

4. The memory management system of claim 3, wherein the cache line mapping is the first 48 bytes of the STT entry.

5. The memory management system of claim 4, wherein the first 48-byte region is configured to be mapped into 32 12-bit fields, the first three of which are flags associated with the cache line.

6. The memory management system according to claim 1, wherein the plurality of sector pointers includes four sector pointers, each sector pointer being a 4-byte field, wherein each 4-byte field is a pointer to a 512-byte memory sector, the 512-byte memory sector being used for storing the compressed content of the cache line.

7. The memory management system of claim 1 further includes a Level 3 cache (L3 cache), wherein the memory manager is configured to locate one or more metadata flags and the cache line metadata, and use the one or more metadata flags and the cache line metadata to load the cache line from the physical memory into the L3 cache.

8. The memory management system of claim 1, wherein the sector number, segment offset, and length uniquely identify the compressed cache line of the shared memory cache.

9. The memory management system of claim 1 further includes a free sector cache configured to store free memory sectors.

10. The memory management system according to claim 1, wherein the physical memory has a block size of 64 bytes, and the cache compression algorithm is the C-Pack+Z compression algorithm.

11. The memory management system of claim 1, wherein the memory manager includes a plurality of compressors and decompressors.

12. A computerized method for tracking compressed memory, the computerized method comprising: Access the sector translation table (STT) defined by a descriptor, which includes cache line mappings and multiple sector pointers to sector memory; The cache line metadata associated with the cache line is obtained from the cache line mapping. The cache line metadata includes one or more flags, sector number, cache segment length, and the length of the cache line. Based on the cache line metadata, the cache line is loaded from physical memory into the last-level cache (LLC), wherein the size of the compressed block is the same as the size of a single cache line; and Multiple cache lines are used to track the compressed physical memory.

13. The computerized method of claim 12, wherein the sector memory is configured into a physical memory block storing at least one of operating system data and application data, and the method further comprises: Receive the real address and set multiple least significant bits of the real address to zero to obtain an STT entry containing the cache line mapping and the multiple sector pointers.

14. The computerized method of claim 13, wherein the plurality of sector pointers comprises four sector pointers, each sector pointer being a 4-byte field, wherein each 4-byte field is a pointer to a 512-byte memory sector used for storing compressed content of the cache line, and wherein the first 48 bytes of the STT entry is a cache line mapping.

15. The computerized method according to claim 12, further comprising: Free memory sectors are organized into free sector heaps, which are stored using the free memory sectors, wherein the sector memory includes sectors that store pointers to the free memory sectors.

16. The computerized method according to claim 15, further comprising: The cache contains multiple sectors of the free memory sector.

17. The computerized method according to claim 12, further comprising: The cache line metadata is used to load the cache line from physical memory into the level 3 LLC.

18. The computerized method of claim 12, wherein the physical memory has a block size of 64 bytes and is compressed using a cache compression algorithm.

19. One or more computer storage media having computer-executable instructions for performing memory management, wherein the computer-executable instructions, when executed by a processor, cause the processor to at least: Access the sector translation table (STT) defined by a descriptor, which includes cache line mappings and multiple sector pointers to sector memory; The cache line metadata associated with the cache line is obtained from the cache line mapping. The cache line metadata includes one or more flags, sector number, cache segment length, and the length of the cache line. Based on the cache line metadata, the cache line is loaded from physical memory into the last-level cache (LLC), wherein the size of the compressed block is the same as the size of a single cache line; and Multiple cache lines are used to track the compressed physical memory.

20. One or more computer storage media of claim 19, wherein the computer-executable instructions, when executed by a processor, cause the processor to further organize free memory sectors into a free sector stack, the free sector stack being stored using the free memory sectors, wherein the sector memory includes sectors storing pointers to the free memory sectors.

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