Method for manufacturing a gate

Abstract

A method of fabricating a semiconductor-superconductor nanowire, comprising: forming a first amorphous mask having a first opening above a trench of a substrate (11); forming a single-crystalline conductive material (13) in the first opening by selective area growth, thereby forming a gate of a nanowire (15, 16) in the trench of the substrate; forming a second mask above the substrate (11) and the gate (13), the second mask also being amorphous and having a pattern of second openings; forming an insulating crystal buffer layer (15) in the second openings; forming a crystal semiconductor material (16) on the buffer layer in the second openings (15) by selective area growth to form a core of the nanowire, wherein the gate (13) intersects the core (16) in the plane of the substrate (11); and forming a superconducting material coating over at least a portion of each core.

Description

Background Art

[0001] Topological quantum computing is based on the phenomenon that non-Abelian anyons in the form of "Majorana zero modes" (MZMs) can be formed in regions where a semiconductor is coupled to a superconductor. Non-Abelian anyons are quasiparticles, meaning not particles themselves but excitations in an electron liquid that behave at least partly like particles. An MZM is a specific bound state of such quasiparticles. Under specific conditions, these states can form near the semiconductor-superconductor interface in a nanowire, which is formed by a segment of semiconductor coated with a superconductor. When an MZM is induced in the nanowire, it is said to be in a "topological state". To cause this, a magnetic field, usually applied externally, is required, and the nanowire also needs to be cooled to a temperature that causes superconducting behavior in the superconducting material. It may also involve controlling a part of the nanowire with an electrostatic potential.

[0002] By forming a network of such nanowires and introducing topological structures in certain parts of the network, qubits can be created, which can be operated on for the purposes of quantum computing. A qubit or quantum bit is an element on which a measurement with two possible outcomes can be performed, but which can actually be in a quantum superposition of two states corresponding to the different outcomes at any given time (when not measured).

[0003] To induce an MZM, the device is cooled to a temperature at which the superconductor (e.g., aluminum, Al) exhibits superconducting behavior. The superconductor causes a proximity effect in the adjacent semiconductor, whereby the semiconductor region near the interface with the superconductor also exhibits superconducting properties. That is, topological phase behavior is induced in the adjacent semiconductor as well as the superconductor. It is in this region of the semiconductor that the MZM is formed.

[0004] Another condition for inducing the topological phase that forms the MZM is to apply a magnetic field to lift the spin degeneracy in the semiconductor. Degeneracy in a quantum system refers to the situation where different quantum states have the same energy level. Removing degeneracy means making these states adopt different energy levels. Spin degeneracy refers to the situation where different spin states have the same energy level. Spin degeneracy can be lifted by a magnetic field, resulting in an energy level spillover between electrons with different spin polarizations. This is called the Zeeman effect. Usually, the magnetic field is applied by an external electromagnet. However, a ferromagnetic insulator layer set between the superconductor and the semiconductor can also be used to apply a magnetic field internally to lift the spin degeneracy without the need for an external magnet.

[0005] Inducing an MZM also involves gating the nanowire with an electrostatic potential to control the carrier density in the nanowire. The terminal to which this potential is applied is called a gate.

[0006] The structure of a semiconductor core, such as a nanowire network, can be formed on a substrate by a process called selective area growth (SAG), which refers to selective epitaxial growth through an amorphous mask. Epitaxy is a known deposition technique that involves growing one crystalline material on top of another crystalline material. The first material acts as a seed for the second material that grows on top of the first material. The growth is selectively performed by forming a patterned mask above the first material layer (e.g., a crystalline substrate) and growing a deposited material (e.g., the semiconductor of the nanowire) in the areas left exposed by the mask. Since the mask is amorphous, the deposited material does not grow on the mask but only in the openings of the underlying crystalline substrate that are exposed. Example techniques for epitaxial deposition itself include, for example, electron beam physical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition, as well as molecular beam epitaxy.

[0007] The gates can be formed as top gates or bottom gates. In the case of top gates, they are formed by a patterned metal layer formed above the semiconductor of the nanowire. In such an arrangement, the semiconductor core of the nanowire can be grown "planar" (i.e., horizontally on the substrate of the device itself) by selective area growth (SAG). However, a disadvantage of top gates is that after the semiconductor is formed, an additional chemical processing step must be applied on top of the semiconductor of the nanowire in order to pattern the gate material to form individual gates. Such processing steps can damage the nanowires. For example. The processing steps can involve depositing and removing a resist, which can damage the surface of the underlying semiconductor when removed or may leave residues of the resist. This damage can affect the ability to induce MZMs in the nanowires.

[0008] Furthermore, for top gates, the superconducting metal coating of the nanowire protects the semiconductor from the gates to some extent, reducing their effectiveness.

[0009] Bottom gates avoid these problems. In existing methods for manufacturing devices with bottom gates, the metal gates are formed in the substrate of the device being fabricated. The nanowires must be grown individually in the vertical direction and then "lowered" and transferred onto the device so as to lie flat above the gates in the substrate plane. These are referred to as "out-of-plane" nanowires because they grow away from the substrate plane of the device being fabricated, as opposed to in-plane nanowires that grow at an appropriate position above the substrate plane. Summary of the Invention

[0010] In existing methods of fabricating devices with bottom gates, since the metal commonly used to form the gates is typically deposited by evaporation or sputtering and is polycrystalline when deposited in this manner, the semiconductor of the nanowires cannot be grown above the substrate itself. If in-plane nanowires are grown on such a surface, this will result in defects in the wires. Therefore, the nanowires must be grown separately and then transferred to the substrate. However, this out-of-plane method has a problem because this method of forming nanowires cannot be scaled up to large or complex nanowire networks. To solve this or other problems, it is desirable to provide an alternative method of forming devices with bottom gates.

[0011] According to one aspect disclosed herein, a method of fabricating a device including a plurality of semiconductor-superconductor nanowires is provided, each semiconductor-superconductor nanowire including a respective semiconductor core and a superconducting material coating over the respective core. The method includes: forming a first mask over a substrate, the substrate defining a plane, wherein the first mask is formed of an amorphous material and has a pattern of first openings formed over trenches in the substrate, and the substrate includes crystalline material at least at the surface of the trenches; and forming single-crystalline conductive material in the first openings by selective area growth, thereby forming gates of the nanowires in the trenches of the substrate. The method further includes: forming a second mask over the substrate and the gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer layer in the second openings; and forming crystalline semiconductor material over the buffer layer in the second openings by selective area growth to form the cores of the nanowires, wherein the gates intersect the cores in the plane of the substrate; and forming a superconducting material coating over at least a portion of each core.

[0012] By embedding the gates in the substrate and forming them as single-crystalline materials by selective area growth, this enables in-plane nanowires to be grown above the bottom gates.

[0013] The present invention content is provided to introduce a selection of concepts in a simplified form that will be further described in the detailed description below. The present invention content is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is not limited to embodiments that solve any or all of the disadvantages mentioned herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To assist in understanding the embodiments of the present disclosure and to illustrate how such embodiments may be implemented, reference is made, by way of example only, to the accompanying drawings, in which:

[0015] Figure 1 is a flow chart showing a method of fabricating a device according to an exemplary embodiment disclosed herein,

[0016] Figures 2A - 2B is given inFigure 1 Schematic side views of devices at different stages of a manufacturing method,

[0017] Figure 3 schematically showing the layers of a device formed according to Figure 1 and Figures 2A - 2B the method of

[0018] Figure 4 is a schematic side view illustrating the formation of a superconducting coating on a device. DETAILED DESCRIPTION

[0019] The present disclosure provides an arrangement of selectively area-grown bottom gates (e.g., "finger" gates) for gating an in-plane nanowire network.

[0020] As previously mentioned, two existing gate types can be distinguished: top gates and bottom gates. In the case of in-plane wires, the common approach is to fabricate the gate on top of the nanowire, i.e., a top gate. This type of gate has at least two drawbacks. First, it adds an additional processing step after the nanowire growth, which may contaminate and potentially damage the nanowire surface, thereby creating scattering sites. This is particularly problematic for quantum applications as these scattering sites can have a negative impact on the carrier mobility and the coherence length of the device.

[0021] Furthermore, material platforms for topological quantum computing work with semiconductor-superconductor hybrid heterostructures. In the case of in-plane growth, the superconductor is deposited on top of the nanowire. This shields the effect of the top gate and reduces their efficiency.

[0022] If the gate is fabricated before the nanowire epitaxy, these problems can be avoided. Such a gate is also referred to as a bottom gate. Bottom gates are typically only used in the case of out-of-plane nanowires, where the wires are grown individually and then transferred to a pre-patterned substrate containing a bottom "finger" gate structure. However, the out-of-plane approach cannot be scaled to large or complex nanowire networks. Additionally, growing large structures is very difficult, and the probability of successfully producing a given structure decreases exponentially with the number of wires.

[0023] Given that the gate metal and the dielectric are typically amorphous, it is not possible to grow in-plane wires on top of an existing substrate containing a bottom gate. This severely limits the quality of any subsequent growth.

[0024] Note that the gate material must be patterned to form individual gates to selectively control each nanowire in the network, or even individual segments of a given nanowire. That is, a patterned gate structure is needed to allow one to choose where to gate and where not to gate (where to apply the desired electrostatic potential). A global back gate (i.e., a large uniform back gate) would only allow non-local adjustment of the overall chemical potential, rather than gating individual nanowires as required for nanowire operation in a quantum computing device.

[0025] It is desirable to be able to fabricate in-plane semiconductor nanowires by selective area epitaxy. This scalable approach would allow the growth of complex networks while maintaining the advantages of the nanowire geometry, i.e., quasi-one-dimensional. Gate electrodes are traditionally used to control the carrier density in these nanowires during transport measurements, e.g., to induce tunneling barriers or manipulate the chemical potential of the wire. As previously mentioned, these gate structures are typically fabricated after nanowire epitaxy and require chemical processing. This leaves residues or damages the nanowire surface and results in a degradation of the material quality.

[0026] The presently disclosed method enables the structure of a local bottom gate (e.g., "finger" gate) by selective area epitaxy. This preserves the crystal structure of the substrate in the gate and the semi-insulating material, thus allowing subsequent growth of a nanowire network on top of the gate.

[0027] As previously mentioned, since gate metals and dielectrics are typically amorphous, it is not possible to grow in-plane wires on top of a conventional substrate containing a bottom gate. Thus, according to the present invention, the gate material and the substrate (e.g., the dielectric) are crystalline. Selective area growth is used to form a network of patterned bottom gates (e.g., finger gates) on which nanowires can then be formed. This combines the flexibility of selective area growth and the precision of local gating.

[0028] Furthermore, many more advanced applications require a large number of gates, in which case it is necessary to choose to gate from below the network. Thus, selective area growth of finger gates is a good choice for maintaining high material quality in controlling the carrier density of in-plane nanowires using finger gates. Enabling effective gating of nanowires below a superconductor is important for tunability towards topological phases.

[0029] One material choice for the gate is degenerate doped InGaAs, which is lattice-matched to InP, a common substrate material for in-plane InSb and InAs growth. There are multiple choices for the crystalline semi-insulating layer, and the preferred choice depends on the crystal structure of the subsequent nanowire material. Two viable choices are InP or InAlSb.

[0030] Figure 1 is a flow chart of a method according to an exemplary embodiment of the present disclosure.Figure 2A A side view of a device fabricated during various stages of the method is shown, with the x-direction shown as left to right (horizontal in the plane of the page) and the y-direction shown into the page (perpendicular to the page). Figure 2B A side view of a device fabricated during other stages of the method is shown, with the y-direction shown left to right in the plane of the page and the x-direction shown into the page. Figure 3 Shows Figure 2A and Figure 2B corresponding isometric views of the respective layers shown in. The x and y axes are in the plane of the substrate 11.

[0031] The device to be fabricated will include: a substrate 11, a gate 13, a buffer layer 15, a semiconductor core 16 of a nanowire, and a superconducting coating 17 on some or all of each semiconductor core 16. It should be understood that the x-y axes relative to the plane of the substrate 11 may depend on the design. In addition, the straight-line designs shown herein are given only as examples. The gate 13 or the nanowires 16 / 17 do not have to form a straight line, and the gate 13 does not have to be perpendicular to the nanowires 16 / 17.

[0032] In terms of terminology, "above" in this document may mean directly formed on or indirectly formed above (with any one or more intermediate layers therebetween). "On" in this document means directly on, i.e., in contact without any intermediate layer. Also note that the terms "on" or "above" etc. used herein do not necessarily imply a specific direction relative to gravity (in some growth chambers, the device may be fabricated upside down compared to the direction shown in the figures). Instead, they refer to the position relative to the side of the substrate 11 being processed, i.e., the positive z-direction outward from the side of the substrate 11 being processed. Terms such as "under" or "beneath" etc. should be interpreted contrarily.

[0033] Step S1 includes providing the substrate 11. The substrate 11 may include one or more constituent layers. It is preferably a dielectric or other insulator, or at least has a much larger bandgap (i.e., more insulating) than the semiconductor material 16 to be used for the nanowire core. The substrate 11 includes a crystalline material (at least where the gate 13 is to be formed), e.g., InP (indium phosphide). InP is a semiconductor, but its bandgap is much larger than that of InSb, so it can act as an insulating material in this case. More generally, such a substrate material can be any insulator, such as GaAs, GaSb, or Si. In an embodiment, the substrate material 11 is single-crystalline. In an embodiment, the crystal structure of the substrate material is a zinc blende structure (named after the lattice structure found in the mineral sphalerite, although this does not mean using the mineral sphalerite itself or the presence of zinc).

[0034] In step S2, the method includes adding a first mask material layer 12, for example, silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or boron nitride. The mask material is amorphous (i.e., non-crystalline) as it will provide a mask for subsequent selective area growth (SAG) steps.

[0035] In step S3, the method includes patterning the first mask material layer 12. In an embodiment, this can include etching away portions of the mask to leave openings. In a particularly effective implementation, the etching is allowed to penetrate down through the mask material 12 and partially into the substrate 11, so that in one etching step, trenches are also formed in the substrate 11 that coincide with the openings in the first mask 12 in the plane of the substrate 11. It is in these openings and trenches that the gates 13 will be formed. The etching can be performed, for example, using lithography techniques such as electron beam lithography or a template mask.

[0036] However, in an alternative embodiment, it is not necessary to form the trenches and the openings in the same etching step. For example, the trenches can be formed in a first etching step, then the first mask material 12 can be subsequently applied and then patterned, for example, by lithography.

[0037] In either case, the openings in the first mask 12 coincide with the trenches in the substrate 11 in the plane of the substrate. The substrate 11 is formed of a crystalline material, or at least the upper surface of the bottom of the trenches is crystalline.

[0038] In step S4, gate material 13 is formed in the trench through the opening in the first mask 12. This is performed using selective area growth (SAG), where the surface at the bottom of the trench in the substrate 11 serves as a seed for the epitaxial growth of the gate material 13. Thus, the gate material 13 is also selected to be crystalline. Additionally, the gate material 13 is single-crystalline to support the epitaxial growth of the nanowire above it. Conventionally, the gate is formed of a metal that is polycrystalline during sputtering or evaporation. Additionally, the dielectric required for an electrically insulating bottom gate is typically amorphous. However, to form an in-plane nanowire above the bottom gate, a single-crystalline layer needs to be grown on it to minimize defects in the in-plane wire. Thus, the presently disclosed technique forms a single-crystalline material through selective area growth. In an embodiment, the gate material 13 has a zinc blende crystal structure to provide a good crystal match with the substrate material 11 on which it grows. However, other suitably matched crystal combinations are possible. The gate material 13 is conductive. The gate material 13 can be a non-metal. For example, in an embodiment, the gate material 13 is a doped semiconductor, such as doped InGaAs (indium gallium arsenide) or doped InP (indium phosphide), doped to a sufficient degree to act as a conductor for gating purposes. By doping, depending on the dopant that makes the material conductive, the Fermi level is shifted to the conduction / valence band. Preferably, the substrate 11 (or at least its upper surface) is a dielectric or other insulator and also has a larger bandgap than the semiconductor 16 of the nanowire in an embodiment. Thus, the substrate and the gate are isolated from each other.

[0039] In an embodiment, the gate 13 is formed flush with the upper surface of the substrate 11 to provide a flat surface to be processed in subsequent steps. However, this is not absolutely necessary. In an embodiment, the width of the opening in the first mask 12 and the trench in the substrate 11 and thus the width of the gate 13 is between 20 nm and 100 nm. They are as long as the length of the gate 13 in the design of the application under discussion. There is no strict limit on the width of the gate 13, although after about 100 nm, the quality of the growth can start to be affected. The depth of the gate 13 can be between about 10 nm and 100 nm. In principle, the gate can be of any depth, but increasing the width makes it more difficult to align the gate height with the substrate.

[0040] In step S5, the method includes removing the first mask 12. This can be performed using any suitable known chemical processing step. Note that no nanowire that could be damaged by the chemical processing has been formed at this stage.

[0041] In step S6, the method includes forming a second mask material layer 14. This can be formed of any of the possible materials discussed with respect to the first mask 12, for example. In step S7, the method includes patterning the second mask 14 to form openings through the second mask. These openings may not coincide with the first openings or the gates 13, but they do overlap partially. The openings in the second mask define where the semiconductor 16 cores of the nanowires will be formed. For example, these openings can again be formed by any suitable known lithography method.

[0042] In step S8, the method includes forming a buffer layer 15 in the openings of the second mask 14. In an embodiment, this is performed by SAG. However, other deposition techniques are not excluded for this step. The buffer layer 15 is both insulating and crystalline, preferably single-crystalline. It is insulating in order to electrically isolate the gate 13 from the nanowires 16 / 17 (so it has a larger bandgap than the semiconductor 16). The electrostatic field can penetrate from the gate 13 to the nanowire core 16, but there is no electrical contact. In an embodiment, the buffer layer 15 is a dielectric. It also includes a crystalline material to serve as a seed substrate for the semiconductor 16 of the nanowires to be formed in the next step. In an embodiment, the buffer layer 15 is formed of a single buffer material that is both insulating and crystalline, but a double-layer buffer layer with a lower insulating layer and an upper crystalline layer is not excluded. In an embodiment, the crystalline buffer material 15 has a zinc blende crystal structure to provide a good crystal match with the zinc blende gate material 13 grown thereon and with the semiconductor 16 (which may also have a zinc blende structure) that will be grown on the buffer layer 15. Examples of suitable single materials for use as the buffer layer 15 include InAlSb (indium aluminum antimonide) or InP. However, other suitable crystal matches are possible.

[0043] In step S9, the method includes growing the semiconductor 16 of the nanowires on the buffer layer 15, within the openings of the second mask 14, thereby forming a network of nanowire cores. This is again performed by SAG. Based on this method, almost any nanowire network structure desired by the designer can be lithographically defined, which is not possible with out-of-plane nanowire methods. The pattern of the nanowires is also arranged to at least partially intersect the underlying gate 13 in the substrate plane (but without making electrical contact in the z direction). This enables the device to be used to specifically select where to gate the nanowire network and where not to gate it. For example, in the example shown, the gate 13 is formed as an elongated line (a so-called "finger gate") and the nanowires 16 / 17 are formed perpendicular to the finger gate 13.

[0044] In an embodiment, the width of the openings in the second mask 14 and thus the width of the nanowire core 16 are between 20 nm and 100 nm. They can be of the lengths required for the application design under discussion. There is no strict limit on the width, but after about 100 nm, the influence of the 1D confinement on forming the MZM starts to weaken.

[0045] The semiconductor material 16 of the nanowire is crystalline, preferably single-crystalline.

[0046] In an embodiment, the semiconductor 16 of the nanowire is a III-V semiconductor, for example, InSb, InAs, InP, or GaAs. In another example, it can be silicon (Si). In an embodiment, the semiconductor 16 for the nanowire has a zinc blende crystal structure in order to provide a good crystal match with the buffer layer 15 grown thereon. However, other suitably matched crystal structures are also possible. The semiconductor 16 of the nanowire also has a smaller bandgap than any insulator or dielectric having such properties elsewhere in the device, such as the substrate 11 or the buffer layer 15.

[0047] In step S10, a superconducting coating 17 is formed over at least a portion of each nanowire core 16. This is also schematically shown in Figure 4 and shown in the Figure 4 same orientation (x into the page) as Figure 2B . As Figure 4 shown, the superconductor 17 can be formed all around the upper perimeter of the semiconductor core 16 (all faces are exposed in step S9); or it can be formed only in part (for example, when formed by inclined deposition, if only one or two facets can be covered). It can be formed all along the length of the nanowire (into the page) or only in part. Any superconducting material can be used, for example, aluminum, lead, tin, or niobium.

[0048] It should be understood that the above embodiments are described by way of example only.

[0049] More generally, according to one aspect disclosed herein, a method of fabricating a device is provided, the device comprising a plurality of semiconductor-superconductor nanowires, each semiconductor-superconductor nanowire comprising a respective semiconductor core and a superconducting material coating over the respective core; the method comprising: forming a first mask over a substrate, the substrate defining a plane, wherein the first mask is formed of an amorphous material and has a pattern of first openings formed over trenches in the substrate, and the substrate comprises crystalline material at least at the surface of the trenches; forming a single-crystalline conductive material in the first openings by selective area growth, thereby forming gates of the nanowires in the trenches of the substrate; forming a second mask over the substrate and the gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer layer in the second openings; forming a crystalline semiconductor material on the buffer layer in the second openings by selective area growth to form the cores of the nanowires, wherein the gates intersect the cores in the plane of the substrate; and forming a superconducting material coating over at least a portion of each core.

[0050] In an embodiment, the formation of the first mask can be performed by: forming a mask material layer over the substrate, and etching the first openings and the trenches in the same etching step.

[0051] In an embodiment, the semiconductor material can have a zinc blende crystal structure.

[0052] In an embodiment, the semiconductor material can be a III-V semiconductor.

[0053] In an embodiment, the semiconductor material can be one of InSb, InAs, InP, GaAs, or silicon.

[0054] In an embodiment, the conductive material of the gate can have a zinc blende crystal structure.

[0055] In an embodiment, the conductive material of the gate can comprise a doped semiconductor.

[0056] In an embodiment, the conductive material of the gate can be doped InGaAs or doped InP.

[0057] In an embodiment, the substrate can be a dielectric or other insulator.

[0058] In an embodiment, the substrate has a zinc blende crystal structure at least at the location where the gates are formed.

[0059] In an embodiment, the substrate comprises at least an upper layer of the crystalline material forming the trenches.

[0060] In an embodiment, the crystalline material of the substrate can have a zinc blende crystal structure.

[0061] In an embodiment, the substrate may be formed of InP, GaAs, GaSb, or Si.

[0062] In an embodiment, the buffer layer may also be formed by selective area growth through a second opening in the second mask.

[0063] In an embodiment, the buffer layer may have a zinc blende crystal structure.

[0064] In an embodiment, the buffer layer may be InAlSb or InP.

[0065] In an embodiment, the superconductor may be Al, Pb, Sn, or Nb.

[0066] In an embodiment, the first mask and / or the second mask may be a dielectric or other insulator.

[0067] In an embodiment, the first mask and / or the second mask may be formed of any one of the following: silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or boron nitride.

[0068] According to another aspect of the present disclosure, a device manufactured by the method of the embodiments disclosed herein is provided.

[0069] According to another aspect, a method of operating the device is provided, the method comprising: cooling the device to a temperature at which the superconductor becomes superconducting, applying a magnetic field from an internal or external source, and applying an electrostatic potential to the gate so as to induce Majorana zero modes in at least some of the nanowires.

[0070] Once the present disclosure is given, other variations or use cases of the disclosed technology may become apparent to those skilled in the art. The scope of the present disclosure is not limited by the described embodiments, but only by the appended claims.

Claims

1. A method of manufacturing a device including a plurality of semiconductor-superconductor nanowires, each semiconductor-superconductor nanowire including a respective semiconductor core and a superconducting material coating over the respective core; the method comprising: forming a first mask over a substrate, the substrate defining a plane, wherein the first mask is formed of an amorphous material and has a pattern of first openings formed over trenches in the substrate, and the substrate includes crystalline material at least at surfaces of the trenches; forming a single-crystalline conductive material in the first openings by selective area growth so as to thereby form gates of the nanowires in the trenches of the substrate; forming a second mask over the substrate and the gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer layer in the second openings; forming a crystalline semiconductor material on the buffer layer in the second openings by selective area growth so as to form the cores of the nanowires, wherein the gates intersect the cores in the plane of the substrate; and forming the superconducting material coating over at least a portion of each of the cores.

2. The method according to claim 1, wherein the formation of the first mask is performed by: forming a mask material layer over the substrate and etching the first openings and trenches in the same etching step.

3. The method according to any one of the preceding claims, wherein the semiconductor material has a zinc blende crystal structure.

4. The method according to claim 1 or 2, wherein the semiconductor material is a III-V semiconductor.

5. The method according to claim 1 or 2, wherein the semiconductor material is one of InSb, InAs, InP, GaAs, or silicon.

6. The method according to claim 1 or 2, wherein the conductive material of the gate has a zinc blende crystal structure.

7. The method according to claim 1 or 2, wherein the conductive material of the gate includes a doped semiconductor.

8. The method according to claim 7, wherein the conductive material of the gate is doped InGaAs or doped InP.

9. The method according to any one of claims 1, 2, and 8, wherein the substrate is a dielectric or other insulator.

10. The method according to any one of claims 1, 2, and 8, wherein the buffer layer is also formed by selective area growth through the second openings in the second mask.

11. The method according to any one of the preceding claims, wherein the first mask and / or the second mask is a dielectric or other insulator.

12. The method according to any one of claims 1, 2, and 8, wherein the buffer layer has a zinc blende crystal structure.

13. The method according to any one of claims 1, 2, and 8, wherein the buffer layer is InAlSb or InP.

14. The method according to any one of claims 1, 2, and 8, wherein the substrate includes at least an upper layer of the crystalline material in which the trenches are formed.

15. The method according to claim 14, wherein the material of the substrate has a zinc blende crystal structure.

16. The method according to any one of claims 1, 2, and 8, wherein the substrate is formed of InP, GaAs, GaSb, or Si.

17. The method according to any one of claims 1, 2, and 8, wherein the superconductor is Al, Pb, Sn, or Nb.

18. The method according to any one of claims 1, 2, and 8, wherein the first mask and / or the second mask is formed of any one of the following: silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or boron nitride.

19. A device manufactured by the method according to any one of the preceding claims.

20. A method of operating the device according to claim 19, comprising: cooling the device to a temperature at which the superconductor becomes superconducting, applying a magnetic field from an internal or external source, and applying an electrostatic potential to the gate to induce Majorana zero modes in at least some of the nanowires in the nanowire.

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