Test structure of integrated circuits
By designing a test structure in the integrated circuit and adjusting the first and second distances to form a parasitic PNP transistor, current changes can be monitored, solving the latch-up effect problem caused by electrostatic discharge and improving the reliability of the integrated circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-05-19
- Publication Date
- 2026-05-26
AI Technical Summary
Electrostatic discharge (ESD) can damage integrated circuits by causing latch-up effects, affecting their stability and potentially harming the circuit. Current technology lacks effective testing methods to assess and avoid such effects.
Design an integrated circuit test structure, including multiple electrical connections, by adjusting a first distance and a second distance, and by adjusting the first distance and/or the second distance, to form a parasitic PNP transistor, and evaluate the trigger voltage and current of latch-up effect by monitoring current changes.
Effective assessment and avoidance of latch-up effects during integrated circuit operation improve the reliability and stability of integrated circuits.
Smart Images
Figure CN115372785B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more particularly to a test structure for integrated circuits. Background Technology
[0002] The hazards of electrostatic discharge (ESD) to electronic devices, especially integrated circuits (ICs), are increasingly attracting attention. During ESD, a significant voltage is applied to the IC, triggering a latch-up effect and resulting in a sudden and violent voltage snapback. This voltage snapback often affects the stability of the IC and can even damage it.
[0003] To ensure the reliability of integrated circuits, it is necessary to test the electrical parameters of integrated circuits when latch-up occurs, in order to design integrated circuits. Summary of the Invention
[0004] In view of the above problems, embodiments of the present invention provide a test structure for integrated circuits, used to test the electrical parameters of integrated circuits when latch-up occurs.
[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:
[0006] In a first aspect, embodiments of the present invention provide a test structure for an integrated circuit, comprising: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region; wherein the first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are all located within an N-well, and the N-well is located on a P-type substrate; a first distance is provided between the first P-type heavily doped region and the second P-type heavily doped region, and a second distance is provided between the second P-type heavily doped region and the N-type heavily doped region; by adjusting the first distance and / or the second distance, the electrical parameters of the integrated circuit are obtained.
[0007] In the test structure of the integrated circuit described above, the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-type heavily doped region, the N-well, and the second P-type heavily doped region form a parasitic PNP transistor.
[0008] In the test structure of the integrated circuit described above, the N-well has a parasitic resistance, the first end of which is connected to the heavily doped N-type region, and the second end of which is connected to the base of the parasitic PNP transistor.
[0009] Secondly, embodiments of the present invention provide a test structure for an integrated circuit, comprising: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region; wherein the first P-type heavily doped region is located on a P-type substrate, the second P-type heavily doped region and the N-type heavily doped region are both located within an N-well, and the N-well is located on the P-type substrate; a first distance is provided between the first P-type heavily doped region and the second P-type heavily doped region, and a second distance is provided between the second P-type heavily doped region and the N-type heavily doped region; by adjusting the first distance and / or the second distance, the electrical parameters of the integrated circuit are obtained.
[0010] In the test structure of the integrated circuit described above, the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-type heavily doped region, the N-well, and the second P-type heavily doped region form a parasitic PNP transistor.
[0011] In the test structure of the integrated circuit described above, the N-well has a parasitic resistance, the first end of which is connected to the heavily doped N-type region, and the second end of which is connected to the base of the parasitic PNP transistor.
[0012] Thirdly, embodiments of the present invention provide a test structure for an integrated circuit, comprising: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region; wherein the first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are all located within a deep N-well, and the deep N-well is located on a P-type substrate; the first P-type heavily doped region is located within a first P-well, and the first P-well is located within the deep N-well; and / or, the second P-type heavily doped region is located within a second P-well, and the second P-well is located within the deep N-well; a first distance exists between the first P-type heavily doped region and the second P-type heavily doped region, and a second distance exists between the second P-type heavily doped region and the N-type heavily doped region; by adjusting the first distance and / or the second distance, the electrical parameters of the integrated circuit are obtained.
[0013] In the test structure of the integrated circuit described above, the second P-type heavily doped region is located in the deep N-well, and the first P-type heavily doped region is located in the first P-well; the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-well, the deep N-well, and the second P-type heavily doped region form a parasitic PNP transistor.
[0014] In the integrated circuit test structure described above, the deep N-well has a parasitic resistance. The first end of the parasitic resistance is connected to the heavily doped N-type region, and the second end of the parasitic resistance is connected to the base of the parasitic PNP transistor.
[0015] In the test structure of the integrated circuit described above, the first P-type heavily doped region is located within the deep N-well, and the second P-type heavily doped region is located within the second P-well; the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-type heavily doped region, the deep N-well, and the second P-well form a parasitic PNP transistor.
[0016] In the integrated circuit test structure described above, the deep N-well has a parasitic resistance. The first end of the parasitic resistance is connected to the heavily doped N-type region, and the second end of the parasitic resistance is connected to the base of the parasitic PNP transistor.
[0017] In the test structure of the integrated circuit described above, the first P-type heavily doped region is located within the first P-well, and the second P-type heavily doped region is located within the second P-well; the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-well, the deep N-well, and the second P-well form a parasitic PNP transistor.
[0018] In the integrated circuit test structure described above, the deep N-well has a parasitic resistance. The first end of the parasitic resistance is connected to the heavily doped N-type region, and the second end of the parasitic resistance is connected to the base of the parasitic PNP transistor.
[0019] Fourthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region; wherein the first P-type heavily doped region is located on a P-type substrate, the second P-type heavily doped region is located within a P-well, and the P-well is located within a deep N-well, and the N-type heavily doped region is located within the deep N-well, and the deep N-well is located on the P-type substrate; a first distance is provided between the first P-type heavily doped region and the second P-type heavily doped region, and a second distance is provided between the second P-type heavily doped region and the N-type heavily doped region; by adjusting the first distance and / or the second distance, the electrical parameters of the integrated circuit are obtained.
[0020] In the test structure of the integrated circuit described above, the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-type heavily doped region, the deep N-well and the P-well form a parasitic PNP transistor.
[0021] In the test structure of the integrated circuit described above, the deep N-well has a parasitic resistance, the first end of which is connected to the heavily doped N-type region, and the second end of which is connected to the base of the parasitic PNP transistor.
[0022] Fifthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region; wherein the first P-type heavily doped region is located on a P-type substrate, the second P-type heavily doped region and the N-type heavily doped region are both located within a deep N-well, and the deep N-well is located on the P-type substrate; a first distance is provided between the first P-type heavily doped region and the second P-type heavily doped region, and a second distance is provided between the second P-type heavily doped region and the N-type heavily doped region; by adjusting the first distance and / or the second distance, the electrical parameters of the integrated circuit are obtained.
[0023] In the test structure of the integrated circuit described above, the second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; the first P-type heavily doped region, the deep N-well, and the second P-type heavily doped region form a parasitic PNP transistor.
[0024] In the test structure of the integrated circuit described above, the deep N-well has a parasitic resistance, the first end of which is connected to the heavily doped N-type region, and the second end of which is connected to the base of the parasitic PNP transistor. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram illustrating an application scenario of the integrated circuit test structure in an embodiment of the present invention;
[0027] Figure 2 This is a top view of the test structure of the first integrated circuit in an embodiment of the present invention;
[0028] Figure 3 This is a cross-sectional view of the test structure of the first integrated circuit in an embodiment of the present invention;
[0029] Figure 4 This is a top view of the test structure of the second integrated circuit in this embodiment of the invention;
[0030] Figure 5 This is a cross-sectional view of the test structure of the second integrated circuit in an embodiment of the present invention;
[0031] Figure 6 This is a top view of the test structure of the third integrated circuit in this embodiment of the invention;
[0032] Figure 7 This is a cross-sectional view of the test structure of the third integrated circuit in this embodiment of the invention;
[0033] Figure 8 This is a top view of the test structure of the fourth integrated circuit in this embodiment of the invention;
[0034] Figure 9 This is a cross-sectional view of the test structure of the fourth integrated circuit in this embodiment of the invention;
[0035] Figure 10 This is a top view of the test structure of the fifth integrated circuit in this embodiment of the invention;
[0036] Figure 11 This is a cross-sectional view of the test structure of the fifth integrated circuit in this embodiment of the invention;
[0037] Figure 12 This is a top view of the test structure of the sixth integrated circuit in this embodiment of the invention;
[0038] Figure 13 This is a cross-sectional view of the test structure of the sixth integrated circuit in this embodiment of the invention;
[0039] Figure 14 This is a top view of the test structure of the seventh integrated circuit in this embodiment of the invention;
[0040] Figure 15 This is a cross-sectional view of the test structure of the seventh integrated circuit in this embodiment of the invention.
[0041] Explanation of reference numerals in the attached figures:
[0042] 100 - Wafer; 110 - Bare die;
[0043] 120 - Digging track; 210 - First heavily p-type doped region;
[0044] 220 - Second P-type heavily doped region; 230 - N-type heavily doped region;
[0045] 240-P type substrate; 250-N well;
[0046] 260 - Deep N-well; 270 - First P-well;
[0047] 280 - Second P-well; 290 - Shallow trench isolation structure;
[0048] 300-P trap. Detailed Implementation
[0049] To improve the reliability of integrated circuits (ICs), during the development phase, it is necessary to design the IC based on the electrical parameters when latch-up occurs. This invention provides a test structure for an IC, comprising a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region. A first distance exists between the first and second P-type heavily doped regions, and a second distance exists between the second P-type heavily doped region and the N-type heavily doped region. The first and second distances differ in different test structures. By adjusting the first and / or second distances in each test structure, the electrical parameters of the IC corresponding to that test structure can be obtained, thereby providing a basis for IC design and improving IC reliability.
[0050] To make the above-mentioned objectives, features, and advantages of the embodiments of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0051] Figure 1 This is a schematic diagram illustrating an application scenario of the integrated circuit test structure provided in an embodiment of the present invention. For example... Figure 1 As shown, this test structure is used in a scenario involving wafer 100, which is diced to form multiple dies 120 and scribe lines 110. Integrated circuits (ICs) are disposed within the dies 120, and the test structure for the ICs is disposed within either the scribe line 110 or the die 120. The equivalent circuits of the ICs and the test structure are identical. The test structure is used to test the electrical parameters of the ICs when latch-up occurs.
[0052] Electrical parameters include the trigger voltage, holding voltage, trigger current, and holding current, all of which contribute to the latch-up effect. The trigger voltage is the voltage at which the latch-up effect occurs; the holding voltage is the voltage at which the latch-up effect is maintained; the trigger current is the current that triggers the latch-up effect; and the holding current is the current that maintains the latch-up effect. The trigger voltage is typically greater than the holding voltage. As the trigger voltage or holding voltage increases, the likelihood of a latch-up effect occurring decreases, meaning it becomes less likely to occur.
[0053] The aforementioned electrical parameters are related to the specific structure of the integrated circuit. By measuring the electrical parameters of the integrated circuit through its test structure, and designing the integrated circuit in die 110 based on the test results, latch-up effects can be avoided during operation, thereby improving the reliability of the integrated circuit. Specifically, the test structure of the integrated circuit can be tested using a transmission line pulse generator (TLP). Based on the test results, corresponding design rules for the integrated circuit can be designed, thus ensuring the reliability of the integrated circuit.
[0054] The test structure of the integrated circuit provided in the embodiments of the present invention will be described in detail below. Figures 2 to 15 Seven integrated circuit test structures are provided. In the following embodiments, a heavily doped region refers to a region with a high amount of impurities, i.e., a high doping concentration. A P-type heavily doped region is abbreviated as P+, and an N-type heavily doped region is abbreviated as N+. A P-type substrate refers to a P-type semiconductor (hole-type semiconductor) substrate; the depth of an N-well is less than that of a deep N-well. The depth of an N-well is typically 0.3–0.5 μm, while the depth of a deep N-well is typically 0.5 μm–1 μm.
[0055] Example 1
[0056] Reference Figure 2 and Figure 3 , Figure 2 This is a top view of the test structure of the first integrated circuit in an embodiment of the present invention; Figure 3 This is a cross-sectional view of the test structure of the first integrated circuit in an embodiment of the present invention.
[0057] like Figure 2 and Figure 3 As shown, the test structure of the integrated circuit includes a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. A shallow trench isolation structure (STI) 290 can be provided between the first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230. The shallow trench isolation structure 290 is filled with insulating material to isolate the doped regions. The depth of the shallow trench isolation structure 290 can be 0.3 μm. The depth of the shallow trench isolation structure 290 refers to... Figure 3 The vertical direction is shown.
[0058] The first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230 are all located within the N-well 250, and the N-well 250 is located on the P-type substrate 240. For example... Figure 2 and Figure 3As shown, the second P-type heavily doped region 220 is located between the first P-type heavily doped region 210 and the N-type heavily doped region 230.
[0059] like Figure 2 As shown, a first distance L1 exists between the first heavily doped P-type region 210 and the second heavily doped P-type region 220, and a second distance L2 exists between the second heavily doped P-type region 220 and the heavily doped N-type region 230. The test structure of the integrated circuit obtains its electrical parameters by adjusting at least one of the first distance L1 and the second distance L2.
[0060] The first heavily P-type doped region 210, the N-well 250, and the second heavily P-type doped region 220 form a parasitic PNP transistor. The N-well 250 has a parasitic resistance R1, such as... Figure 3 As shown, the first end of the parasitic resistor R1 is connected to the N-type heavily doped region 230, and the second end of the parasitic resistor R1 is connected to the base of the parasitic PNP transistor.
[0061] Before testing the integrated circuit test structure in the embodiments of the present invention, the test structure needs to be electrically connected. For example... Figure 3 As shown, the first P-type heavily doped region 210 is connected to the ground terminal VSS, and the second P-type heavily doped region 220 and the N-type heavily doped region 230 are connected to the power supply terminal VDD.
[0062] During testing, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 5V, and the current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred.
[0063] By adjusting at least one of the first distance L1 and the second distance L2, multiple sets of correspondences between the first distance L1, the second distance L2, and the trigger voltage, sustaining voltage, trigger current, and sustaining current of the latch-up effect are obtained. This yields correspondences between different first distances L1 and second distances L2 and the electrical parameters of the integrated circuit. Based on these correspondences, the integrated circuit is designed to avoid latch-up during operation, thereby improving chip reliability.
[0064] In the aforementioned integrated circuit test structure, the base of the parasitic PNP transistor is an N-well 250, and the gain from the base to the collector can reach tens of times. Figure 3In the equivalent circuit formed by the parasitic PNP transistor and parasitic resistor R1 shown, the parasitic PNP transistor exists in both a cutoff and a conduction state. When there is no external interference and it is not triggered, the parasitic PNP transistor is in the cutoff state, the collector current is the reverse leakage current of CB, the current gain is very small, and the latch-up effect does not occur. When the parasitic PNP transistor is subjected to external interference, and its collector current or voltage suddenly increases to a preset value, the parasitic PNP transistor turns on. At this time, the parasitic PNP transistor forms a low-resistivity path between the power supply terminal VDD and the ground terminal VSS. Only a very small current is needed to continuously drive the amplification state of the parasitic PNP transistor, that is, latch-up occurs.
[0065] This invention provides a test structure for an integrated circuit, comprising a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. The first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230 are all located within an N-well 250, which is situated on a P-type substrate 240. A first distance L1 exists between the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a second distance L2 exists between the second P-type heavily doped region 220 and the N-type heavily doped region 230. By adjusting the first distance L1 and / or the second distance L2, the electrical parameters of the integrated circuit are obtained. Based on the relationship between the first distance L1 and / or the second distance L2 and the electrical parameters, the integrated circuit is designed to avoid latch-up effects and improve its reliability.
[0066] Example 2
[0067] Reference Figure 4 and Figure 5 , Figure 4 This is a top view of the test structure of the second integrated circuit in this embodiment of the invention; Figure 5 This is a cross-sectional view of the test structure of the second integrated circuit in an embodiment of the present invention.
[0068] like Figure 4 and Figure 5 As shown, the test structure of the integrated circuit includes a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. A shallow trench isolation structure 290 is also provided between the first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230. The shallow trench isolation structure 290 is filled with insulating material to isolate each doped region. The depth of the shallow trench isolation structure 290 can be 0.3 μm.
[0069] The first heavily p-type doped region 210 is located on the p-type substrate 240, and the second heavily p-type doped region 220 and the N-type heavily doped region 230 are both located within the N-well 250, which is located on the p-type substrate 240. Figure 4 and Figure 5 As shown, the second P-type heavily doped region 220 is located between the first P-type heavily doped region 210 and the N-type heavily doped region 230.
[0070] like Figure 4 As shown, a first distance L1 exists between the first heavily doped P-type region 210 and the second heavily doped P-type region 220, and a second distance L2 exists between the second heavily doped P-type region 220 and the heavily doped N-type region 230. The test structure of the integrated circuit obtains the electrical parameters of the integrated circuit by adjusting the first distance L1 and / or the second distance L2.
[0071] The first heavily P-type doped region 210, the N-well 250, and the second heavily P-type doped region 220 form a parasitic PNP transistor. The N-well 250 has a parasitic resistance R1, such as... Figure 4 As shown, the first end of the parasitic resistor R1 is connected to the N-type heavily doped region 230, and the second end of the parasitic resistor R1 is connected to the base of the parasitic PNP transistor.
[0072] Before testing the integrated circuit test structure in the embodiments of the present invention, the test structure needs to be electrically connected. For example... Figure 5 As shown, the first P-type heavily doped region 210 is connected to the ground terminal VSS, and the second P-type heavily doped region 220 and the N-type heavily doped region 230 are connected to the power supply terminal VDD.
[0073] During testing, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 5V, and the current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred.
[0074] By adjusting at least one of the first distance L1 and the second distance L2, multiple sets of correspondences between the first distance L1, the second distance L2, and the trigger voltage, sustaining voltage, trigger current, and sustaining current of the latch-up effect are obtained. This yields correspondences between different first distances L1 and second distances L2 and the electrical parameters of the integrated circuit. Based on these correspondences, the integrated circuit is designed to avoid latch-up during operation, thereby improving chip reliability.
[0075] In the aforementioned integrated circuit test structure, the base of the parasitic PNP transistor is an N-well 250, and the gain from the base to the collector can reach tens of times. Figure 5In the equivalent circuit formed by the parasitic PNP transistor and parasitic resistor R1, the parasitic PNP transistor exists in both a cutoff and a conduction state. When there is no external interference and it is not triggered, the parasitic PNP transistor is in the cutoff state, the collector current is the reverse leakage current of CB, the current gain is very small, and the latch-up effect does not occur. When the parasitic PNP transistor is subjected to external interference, and its collector current or voltage suddenly increases to a preset value, the parasitic PNP transistor turns on. At this time, the parasitic PNP transistor forms a low-resistivity path between the power supply terminal VDD and the ground terminal VSS. Only a very small current is needed to continuously drive the amplification state of the parasitic PNP transistor, that is, latch-up occurs.
[0076] This invention provides a test structure for an integrated circuit, comprising a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. The first P-type heavily doped region 210 is located on a P-type substrate 240, and both the second P-type heavily doped region 220 and the N-type heavily doped region 230 are located within an N-well 250, which is also located on the P-type substrate 240. A first distance exists between the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a second distance exists between the second P-type heavily doped region 220 and the N-type heavily doped region 230. Electrical parameters of the integrated circuit are obtained by adjusting the first and / or second distances. The distances within the integrated circuit are set according to the relationship between the first and / or second distances and the electrical parameters to avoid latch-up effects and improve the reliability of the integrated circuit.
[0077] Example 3
[0078] Reference Figures 6 to 11 , Figure 6 This is a top view of the test structure of the third integrated circuit in this embodiment of the invention; Figure 7 This is a cross-sectional view of the test structure of the third integrated circuit in this embodiment of the invention; Figure 8 This is a top view of the test structure of the fourth integrated circuit in this embodiment of the invention; Figure 9 This is a cross-sectional view of the test structure of the fourth integrated circuit in this embodiment of the invention; Figure 10 This is a top view of the test structure of the fifth integrated circuit in this embodiment of the invention; Figure 11 This is a cross-sectional view of the test structure of the fifth integrated circuit in this embodiment of the invention.
[0079] The test structure of the integrated circuit includes a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. A shallow trench isolation structure 290 is also provided between the first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230. The shallow trench isolation structure 290 is filled with insulating material to isolate each doped region. The depth of the shallow trench isolation structure 290 can be 0.3 μm.
[0080] The first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230 are all located within a deep N-well 260, and the deep N-well 260 is located on a P-type substrate 240. The first P-type heavily doped region 210 is located within a first P-well 270, and the first P-well 270 is located within a deep N-well 260; and / or, the second P-type heavily doped region 220 is located within a second P-well 280, and the second P-well 280 is located within a deep N-well 260.
[0081] like Figures 6 to 11 As shown, the second P-type heavily doped region 220 can be located between the first P-type heavily doped region 210 and the N-type heavily doped region 230. A first distance L1 exists between the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a second distance L2 exists between the second P-type heavily doped region 220 and the N-type heavily doped region 230. The test structure of the integrated circuit obtains the electrical parameters of the integrated circuit by adjusting the first distance L1 and / or the second distance L2.
[0082] In the first possible example, such as Figure 6 and Figure 7 As shown, the second P-type heavily doped region 220 is located within the deep N-well 260, and the first P-type heavily doped region 210 is located within the first P-well 270. That is, both the N-type heavily doped region 230 and the second P-type heavily doped region 220 are located within the deep N-well 260, and the deep N-well 260 is located on the P-type substrate 240. The first P-type heavily doped region 210 is located within the first P-well 270, and the first P-well 270 is located within the deep N-well 260.
[0083] like Figure 7 As shown, the first P-well 270, the deep N-well 260, and the second P-type heavily doped region 220 form a parasitic PNP transistor. The deep N-well 260 has a parasitic resistance R1. The first end of the parasitic resistance R1 is connected to the N-type heavily doped region 230, and the second end of the parasitic resistance R1 is connected to the base of the parasitic PNP transistor.
[0084] In the second possible example, such as Figure 8 and Figure 9As shown, the first heavily doped P-type region 210 is located within the deep N-well 260, and the second heavily doped P-type region 220 is located within the second P-well 280. That is, both the heavily doped N-type region 230 and the first heavily doped P-type region 210 are located within the deep N-well 260, and the deep N-well 260 is located on the P-type substrate 240. The second heavily doped P-type region 220 is located within the second P-well 280, and the second P-well 280 is located within the deep N-well 260.
[0085] like Figure 9 As shown, the first heavily P-type doped region 210, the deep N-well 260, and the second P-well 280 form a parasitic PNP transistor. The deep N-well 260 has a parasitic resistance R1. The first end of the parasitic resistance R1 is connected to the heavily N-type doped region 230, and the second end of the parasitic resistance R1 is connected to the base of the parasitic PNP transistor.
[0086] In the third possible example, such as Figure 10 and Figure 11 As shown, the first heavily doped P-type region 210 is located within the first P-well 270, and the second heavily doped P-type region is located within the second P-well 280. That is, the heavily doped N-type region 230 is located within the deep N-well 260, and the deep N-well 260 is located on the P-type substrate 240. The first heavily doped P-type region 210 is located within the first P-well 270, the second heavily doped P-type region is located within the second P-well 280, and the first P-well 270 and the second P-well 280 are located within the deep N-well 260.
[0087] like Figure 11 As shown, the first P-well 270, the deep N-well 260, and the second P-well 280 form a parasitic PNP transistor. The deep N-well 260 has a parasitic resistance R1, the first end of which is connected to the heavily doped N-type region 230, and the second end of which is connected to the base of the parasitic PNP transistor.
[0088] Before testing the integrated circuit test structures in the three examples above, the test structures must be electrically connected. Specifically, for example... Figure 7 , Figure 9 and Figure 11 As shown, the first P-type heavily doped region 210 is connected to the ground terminal VSS, and the second P-type heavily doped region 220 and the N-type heavily doped region 230 are connected to the power supply terminal VDD.
[0089] During testing, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 5V, and the current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred.
[0090] By adjusting at least one of the first distance L1 and the second distance L2, multiple sets of correspondences between the first distance L1, the second distance L2, and the trigger voltage, sustaining voltage, trigger current, and sustaining current of the latch-up effect are obtained. This yields correspondences between different first distances L1 and second distances L2 and the electrical parameters of the integrated circuit. Based on these correspondences, the integrated circuit is designed to avoid latch-up during operation, thereby improving chip reliability.
[0091] In the test structure of the aforementioned integrated circuit, the base of the parasitic PNP transistor is a deep N-well 260, and the gain from the base to the collector can reach tens of times. Figure 7 , Figure 9 and Figure 11 In the equivalent circuit formed by the parasitic PNP transistor and parasitic resistor R1, the parasitic PNP transistor exists in both a cutoff and a conduction state. When there is no external interference and it is not triggered, the parasitic PNP transistor is in the cutoff state, the collector current is the reverse leakage current of CB, the current gain is very small, and the latch-up effect does not occur. When the parasitic PNP transistor is subjected to external interference, and its collector current or voltage suddenly increases to a preset value, the parasitic PNP transistor turns on. At this time, the parasitic PNP transistor forms a low-resistivity path between the power supply terminal VDD and the ground terminal VSS. Only a very small current is needed to continuously drive the amplification state of the parasitic PNP transistor, that is, latch-up occurs.
[0092] This invention provides a test structure for an integrated circuit, comprising a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230, all located within a deep N-well 260, which is situated on a P-type substrate 240. The first P-type heavily doped region 210 is located within a first P-well 270, which is also located within the deep N-well 260; and / or, the second P-type heavily doped region 220 is located within a second P-well 280, which is also located within the deep N-well 260. A first distance L1 exists between the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a second distance L2 exists between the second P-type heavily doped region 220 and the N-type heavily doped region 230. By adjusting the first distance L1 and / or the second distance L2, the electrical parameters of the integrated circuit are obtained. Based on the relationship between the first distance L1 and / or the second distance L2 and the electrical parameters, the distances within the integrated circuit are set to avoid latch-up effects and improve the reliability of the integrated circuit.
[0093] Example 4
[0094] Reference Figure 12 and Figure 13 , Figure 12 This is a top view of the test structure of the sixth integrated circuit in this embodiment of the invention; Figure 13This is a cross-sectional view of the test structure of the sixth integrated circuit in this embodiment of the invention.
[0095] like Figure 12 and Figure 13 As shown, the test structure of the integrated circuit includes a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. A shallow trench isolation structure 290 is also provided between the first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230. The shallow trench isolation structure 290 is filled with insulating material to isolate each doped region. The depth of the shallow trench isolation structure 290 can be 0.3 μm.
[0096] The first heavily p-type doped region 210 is located on the p-type substrate 240, the second heavily p-type doped region 220 is located within the p-well 300, and the p-well 300 is located within the deep n-well 260. The heavily n-type doped region 230 is located within the deep n-well 260, and the deep n-well 260 is located on the p-type substrate 240. Figure 12 and Figure 13 As shown, the second P-type heavily doped region 220 is located between the first P-type heavily doped region 210 and the N-type heavily doped region 230.
[0097] like Figure 12 As shown, a first distance L1 exists between the first heavily doped P-type region 210 and the second heavily doped P-type region 220, and a second distance L2 exists between the second heavily doped P-type region 220 and the heavily doped N-type region 230. The test structure of the integrated circuit obtains the electrical parameters of the integrated circuit by adjusting the first distance L1 and / or the second distance L2.
[0098] The first P-type heavily doped region 210, the deep N-well 260, and the P-well 300 form a parasitic PNP transistor. The deep N-well 260 has a parasitic resistance R1, the first end of which is connected to the N-type heavily doped region 230, and the second end of which is connected to the base of the parasitic PNP transistor.
[0099] Before testing the integrated circuit test structure in the embodiments of the present invention, the test structure needs to be electrically connected. For example... Figure 13 As shown, the first P-type heavily doped region 210 is connected to the ground terminal VSS, and the second P-type heavily doped region 220 and the N-type heavily doped region 230 are connected to the power supply terminal VDD.
[0100] During testing, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 5V, and the current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred.
[0101] By adjusting at least one of the first distance L1 and the second distance L2, multiple sets of correspondences between the first distance L1, the second distance L2, and the trigger voltage, sustaining voltage, trigger current, and sustaining current of the latch-up effect are obtained. This yields correspondences between different first distances L1 and second distances L2 and the electrical parameters of the integrated circuit. Based on these correspondences, the integrated circuit is designed to avoid latch-up during operation, thereby improving chip reliability.
[0102] In the test structure of the aforementioned integrated circuit, the base of the parasitic PNP transistor is a deep N-well 260, and the gain from the base to the collector can reach tens of times. Figure 13 In the equivalent circuit formed by the parasitic PNP transistor and parasitic resistor R1, the parasitic PNP transistor exists in both a cutoff and a conduction state. When there is no external interference and it is not triggered, the parasitic PNP transistor is in the cutoff state, the collector current is the reverse leakage current of CB, the current gain is very small, and the latch-up effect does not occur. When the parasitic PNP transistor is subjected to external interference, and its collector current or voltage suddenly increases to a preset value, the parasitic PNP transistor turns on. At this time, the parasitic PNP transistor forms a low-resistivity path between the power supply terminal VDD and the ground terminal VSS. Only a very small current is needed to continuously drive the amplification state of the parasitic PNP transistor, that is, latch-up occurs.
[0103] This invention provides a test structure for an integrated circuit, comprising a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. The first P-type heavily doped region 210 is located on a P-type substrate 240, the second P-type heavily doped region 220 is located within a P-well 300, which is located within a deep N-well 260, and the N-type heavily doped region 230 is located within the deep N-well 260, which is located on the P-type substrate 240. A first distance L1 exists between the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a second distance L2 exists between the second P-type heavily doped region 220 and the N-type heavily doped region 230. By adjusting the first distance L1 and / or the second distance L2, the electrical parameters of the integrated circuit are obtained. Based on the relationship between the first distance L1 and / or the second distance L2 and the electrical parameters, the distances within the integrated circuit are set to avoid latch-up effects and improve the reliability of the integrated circuit.
[0104] Example 5
[0105] Reference Figure 14 and Figure 15 , Figure 14 This is a top view of the test structure of the seventh integrated circuit in this embodiment of the invention; Figure 15 This is a cross-sectional view of the test structure of the seventh integrated circuit in this embodiment of the invention.
[0106] like Figure 14 and Figure 15 As shown, the test structure includes a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. A shallow trench isolation structure 290 can also be provided between the first P-type heavily doped region 210, the second P-type heavily doped region 220, and the N-type heavily doped region 230. The shallow trench isolation structure 290 is filled with insulating material to isolate each doped region. The depth of the shallow trench isolation structure 290 can be 0.3 μm.
[0107] The first P-type heavily doped region 210 is located on the P-type substrate 240, and the N-type heavily doped region 230 and the second P-type heavily doped region 220 are both located within a deep N-well 260, which is also located on the P-type substrate 240. For example, the second P-type heavily doped region 220 is located between the first P-type heavily doped region 210 and the N-type heavily doped region 230.
[0108] like Figure 14 As shown, a first distance L1 exists between the first heavily doped P-type region 210 and the second heavily doped P-type region 220, and a second distance L2 exists between the second heavily doped P-type region 220 and the heavily doped N-type region 230. The test structure of the integrated circuit obtains the electrical parameters of the integrated circuit by adjusting the first distance L1 and / or the second distance L2.
[0109] The first heavily P-type doped region 210, the deep N-well 260, and the second heavily P-type doped region 220 form a parasitic PNP transistor. The N-well 250 has a parasitic resistance R1, such as... Figure 15 As shown, the first end of the parasitic resistor R1 is connected to the N-type heavily doped region 230, and the second end of the parasitic resistor R1 is connected to the base of the parasitic PNP transistor.
[0110] Before testing the integrated circuit test structure in the embodiments of the present invention, the test structure needs to be electrically connected. For example... Figure 15 As shown, the first P-type heavily doped region 210 is connected to the ground terminal VSS, and the second P-type heavily doped region 220 and the N-type heavily doped region 230 are connected to the power supply terminal VDD.
[0111] During testing, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 5V, and the current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred.
[0112] By adjusting at least one of the first distance L1 and the second distance L2, multiple sets of correspondences between the first distance L1, the second distance L2, and the trigger voltage, sustaining voltage, trigger current, and sustaining current of the latch-up effect are obtained. This yields correspondences between different first distances L1 and second distances L2 and the electrical parameters of the integrated circuit. Based on these correspondences, the integrated circuit is designed to avoid latch-up during operation, thereby improving chip reliability.
[0113] In the test structure of the aforementioned integrated circuit, the base of the parasitic PNP transistor is a deep N-well 260, and the gain from the base to the collector can reach tens of times. Figure 15 In the equivalent circuit formed by the parasitic PNP transistor and parasitic resistor R1, the parasitic PNP transistor exists in both a cutoff and a conduction state. When there is no external interference and it is not triggered, the parasitic PNP transistor is in the cutoff state, the collector current is the reverse leakage current of CB, the current gain is very small, and the latch-up effect does not occur. When the parasitic PNP transistor is subjected to external interference, and its collector current or voltage suddenly increases to a preset value, the parasitic PNP transistor turns on. At this time, the parasitic PNP transistor forms a low-resistivity path between the power supply terminal VDD and the ground terminal VSS. Only a very small current is needed to continuously drive the amplification state of the parasitic PNP transistor, that is, latch-up occurs.
[0114] This invention provides a test structure for an integrated circuit, comprising a first P-type heavily doped region 210, a second P-type heavily doped region 220, and an N-type heavily doped region 230. The first P-type heavily doped region 210 is located on a P-type substrate 240, while the N-type heavily doped region 230 and the second P-type heavily doped region 220 are both located within a deep N-well 260, which is also located on the P-type substrate 240. A first distance L1 exists between the first P-type heavily doped region 210 and the second P-type heavily doped region 220, and a second distance L2 exists between the second P-type heavily doped region 220 and the N-type heavily doped region 230. By adjusting the first distance L1 and / or the second distance L2, the electrical parameters of the integrated circuit are obtained. Based on the relationship between the first distance L1 and / or the second distance L2 and the electrical parameters, the distances within the integrated circuit are set to avoid latch-up effects and improve the reliability of the integrated circuit.
[0115] This invention provides a test structure for an integrated circuit, which includes setting the distance in the integrated circuit according to the relationship between a first distance and / or a second distance and electrical parameters, so as to avoid latch-up effect in the integrated circuit and improve the reliability of the integrated circuit.
[0116] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0117] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A test structure for an integrated circuit, characterized in that, include: The first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are arranged in sequence at intervals. The first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are all located in the N-well, and the N-well is located on the P-type substrate. There is a first distance between the first P-type heavily doped region and the second P-type heavily doped region, and there is a second distance between the second P-type heavily doped region and the N-type heavily doped region. The electrical parameters of the integrated circuit are obtained by adjusting the first distance and / or the second distance.
2. The integrated circuit test structure according to claim 1, characterized in that, The second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; The first P-type heavily doped region, the N-well, and the second P-type heavily doped region form a parasitic PNP transistor.
3. The integrated circuit test structure according to claim 2, characterized in that, The N-well has a parasitic resistance, the first end of which is connected to the heavily doped N-type region, and the second end of which is connected to the base of the parasitic PNP transistor.
4. A test structure for an integrated circuit, characterized in that, include: The first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are arranged in sequence at intervals. The first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are all located in a deep N-well, and the deep N-well is located on a P-type substrate. The first P-type heavily doped region is located within the first P-well, and the first P-well is located within the deep N-well; and / or, the second P-type heavily doped region is located within the second P-well, and the second P-well is located within the deep N-well; There is a first distance between the first P-type heavily doped region and the second P-type heavily doped region, and there is a second distance between the second P-type heavily doped region and the N-type heavily doped region. The electrical parameters of the integrated circuit are obtained by adjusting the first distance and / or the second distance.
5. The integrated circuit test structure according to claim 4, characterized in that, The second P-type heavily doped region is located in the deep N-well, and the first P-type heavily doped region is located in the first P-well; The second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; The first P-well, the deep N-well, and the second P-type heavily doped region form a parasitic PNP transistor.
6. The integrated circuit test structure according to claim 5, characterized in that, The deep N-well has a parasitic resistance. The first end of the parasitic resistance is connected to the heavily doped N-type region, and the second end of the parasitic resistance is connected to the base of the parasitic PNP transistor.
7. The integrated circuit test structure according to claim 4, characterized in that, The first P-type heavily doped region is located within the deep N-well, and the second P-type heavily doped region is located within the second P-well; The second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; The first P-type heavily doped region, the deep N-well, and the second P-well form a parasitic PNP transistor.
8. The test structure for an integrated circuit according to claim 7, characterized in that, The deep N-well has a parasitic resistance. The first end of the parasitic resistance is connected to the heavily doped N-type region, and the second end of the parasitic resistance is connected to the base of the parasitic PNP transistor.
9. The integrated circuit test structure according to claim 4, characterized in that, The first heavily doped P-type region is located within the first P-well, and the second heavily doped P-type region is located within the second P-well; The second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; The first P-well, the deep N-well, and the second P-well form a parasitic PNP transistor.
10. The test structure for an integrated circuit according to claim 9, characterized in that, The deep N-well has a parasitic resistance. The first end of the parasitic resistance is connected to the heavily doped N-type region, and the second end of the parasitic resistance is connected to the base of the parasitic PNP transistor.
11. A test structure for an integrated circuit, characterized in that, include: The first P-type heavily doped region, the second P-type heavily doped region, and the N-type heavily doped region are arranged in sequence at intervals. Wherein, the first P-type heavily doped region is located on a P-type substrate, the second P-type heavily doped region is located in a P-well, and the P-well is located in a deep N-well, the N-type heavily doped region is located in the deep N-well, and the deep N-well is located on the P-type substrate; There is a first distance between the first P-type heavily doped region and the second P-type heavily doped region, and there is a second distance between the second P-type heavily doped region and the N-type heavily doped region. The electrical parameters of the integrated circuit are obtained by adjusting the first distance and / or the second distance.
12. The test structure for an integrated circuit according to claim 11, characterized in that, The second P-type heavily doped region is located between the first P-type heavily doped region and the N-type heavily doped region; The first P-type heavily doped region, the deep N-well and the P-well form a parasitic PNP transistor.
13. The test structure for an integrated circuit according to claim 12, characterized in that, The deep N-well has a parasitic resistance, the first end of which is connected to the heavily doped N-type region, and the second end of which is connected to the base of the parasitic PNP transistor.