Configurable refresh operation speed

Abstract

This application relates to a configurable refresh operation speed. Before performing a refresh operation at a first portion of a cache containing a Single Level Cell (SLC), the memory system may transmit parameters associated with data stored in the first portion of the cache to the host system. The host system may then identify another portion of the cache (e.g., containing an SLC or a Multi Level Cell (MLC)) for the refresh operation based on the parameters and the speed of refresh operations associated with other portions of the cache. The host system may indicate the identified portion of the cache to the memory system, and the memory system may perform a refresh operation at the first portion of the cache. For example, the memory system may write a subset of the data stored in the first portion of the cache to a second portion of the cache.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 240,832, filed April 26, 2021, entitled "Configurable Flush Operation Speed," which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves configurable refresh operation speed. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus includes: a cache including a first portion having a plurality of single-level units and one or more additional portions having a plurality of single-level units or a plurality of multi-level units; and a controller coupled to the cache. The controller is configured to cause the apparatus to: transmit to a host system one or more parameters associated with data stored in the first portion of the cache; receive from the host system, at least in part based on the transmission of the one or more parameters, an instruction for a refresh operation of a portion of the cache in the one or more additional portions; and write a subset of the data stored in the first portion of the cache into a second portion of the cache in the one or more additional portions, at least in part based on performing the refresh operation and at least in part based on receiving the instruction of the portion of the cache.

[0007] Describe the device. The device includes a controller coupled to a memory system, wherein the controller is configured to cause the device to: receive from the memory system one or more parameters associated with data stored in a first portion of a cache of the memory system, the cache including the first portion having a plurality of single-level units and one or more additional portions having a plurality of single-level units or a plurality of multi-level units; identify, at least in part, a portion of the cache in the one or more additional portions for a refresh operation to be performed at the memory system based on the one or more parameters; and indicate to the memory system the identified portion of the cache for the refresh operation.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium stores code at a memory system and includes instructions executable by a processor to: transmit to a host system one or more parameters associated with data stored in a first portion of a cache in the memory system, the cache including the first portion having multiple single-level units and one or more additional portions having multiple single-level units or multiple multi-level units; receive from the host system, at least in part based on the transmission of the one or more parameters, an instruction for a refresh operation of a portion of the cache from the one or more additional portions; and write, at least in part based on performing the refresh operation and at least in part based on receiving the instruction of the portion of the cache, a subset of the data stored in the first portion of the cache into a second portion of the cache in the one or more additional portions of the cache. Attached Figure Description

[0009] Figure 1 Examples of systems that support configurable refresh operation speeds, based on the examples disclosed herein, are shown.

[0010] Figure 2 Examples of systems that support configurable refresh operation speeds, based on the examples disclosed herein, are shown.

[0011] Figure 3 An example of a process flow that supports configurable refresh operation speed is shown based on the examples disclosed herein.

[0012] Figure 4 A block diagram is shown that supports a memory system with configurable refresh operation speed according to the examples disclosed herein.

[0013] Figure 5 A block diagram is shown illustrating a host system that supports configurable refresh operation speeds based on the examples disclosed herein.

[0014] Figure 6 and 7 The flowcharts shown below, based on examples disclosed herein, illustrate one or more methods that support configurable refresh operation speeds. Detailed Implementation

[0015] Some memory systems may include caches, which contain multiple blocks of memory cells (e.g., multiple subsets) (e.g., multiple sections). For example, a multi-level cache may contain one or more single-level cell (SLC) sections and one or more multi-level cell (MLC) sections (e.g., two-level cell, three-level cell (TLC), four-level cell (QLC), or five-level cell (PLC) sections). In some instances, one of these sections may be used as a buffer (e.g., a write booster buffer). For example, an SLC section may be used as a buffer. In this instance, the memory system may receive data (e.g., from a host system) to store at a memory device within the memory system. The memory system may then buffer the data (e.g., received from the host system) in the SLC section of the cache instead of other sections of the cache. In some cases (e.g., in response to the SLC section of the cache reaching a threshold level, such as being full or nearly full), data written to the SLC section may be flushed (e.g., moved) to another section of the cache using a flush operation. In one instance, a refresh operation may involve writing data to one or more SLC portions of the cache. Alternatively, a refresh operation may involve writing data to one or more MLC portions of the cache. Different refresh operations (e.g., flushing data to an SLC portion of the cache, flushing data to an MLC portion of the cache) may be associated with different characteristics. For example, flushing data from one SLC portion to another SLC portion may be faster than flushing data from one SLC portion to another SLC portion. Additionally, flushing data from one SLC portion to an MLC portion may be more efficient (e.g., freeing up more space in the SLC portion) than flushing data from one SLC portion to another SLC portion. In some cases, one refresh operation may be better than another, depending on the desired speed of completion or the efficiency of the refresh operation.

[0016] As described herein, a memory system may utilize methods to determine the refresh operation to be performed based on or in response to the speed or efficiency associated with different options for performing the refresh operation. For example, the memory system may determine to perform a refresh operation on the SLC portion of the cache based on or in response to receiving an instruction from the host system for a cache portion used for the refresh operation. For example, the host system may evaluate one or more parameters associated with the memory system to determine whether a first refresh operation (e.g., whose completion will precede the execution of a second refresh operation of a different type, thus making it a faster refresh operation) or a second refresh operation (e.g., whose completion will follow the execution of a first refresh operation of a different type, thus making it a more efficient refresh operation) should be performed. After determining whether to perform the first or second refresh operation, as an example, the host system may instruct the memory system on the cache portion used for the refresh operation. For example, the host system may instruct the memory system on one or more SLC portions of the cache that should be used for the first (e.g., faster) refresh operation. Alternatively, the host system may instruct the memory system on one or more MLC portions of the cache for the second (e.g., more efficient) refresh operation. Based on or in response to an instruction received from the host system of one or more cache portions, the memory system may perform a refresh operation. For example, the memory system may write data from the SLC portion of the cache (e.g., acting as a buffer) to another portion. Therefore, the host system or the memory system (or both) may evaluate one or more parameters associated with the memory system to determine the type of refresh operation to be performed (e.g., fast refresh operation, efficient refresh operation).

[0017] The features of this disclosure are initially described in reference to Figures 1 to 2 The system described herein is described in the context of the system described. Features of this disclosure are described in reference to... Figure 3 The process flow described herein is described in the context of the process flow. These and other features of this disclosure are further illustrated by reference. Figure 4-7 The device diagrams and flowcharts describing the configurable refresh operation speed are shown and referenced in their description.

[0018] Figure 1 An example of a system 100 supporting configurable refresh operation speeds is shown, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130—and other such operations—collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0028] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions described herein as belonging to memory system controller 115. Generally, one or more functions described herein as belonging to memory system controller 115 may actually be performed in some cases by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 that is at least partially managed by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as SLC. Alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each; if configured to store two bits of information each, it may be referred to as MLC; if configured to store three bits of information each, it may be referred to as TLC; if configured to store four bits of information each, it may be referred to as QLC, or more generally, multilevel memory cells. Multilevel memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in the supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0036] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. For example, in some cases, such copying and remapping may be performed to account for latency or attrition, rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0037] In some cases, the L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data due to a more recent or updated version of the data being stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has never been written to or has been erased.

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, making more blocks 170 available for storing subsequent data (e.g., data subsequently received from host system 105).

[0039] In some instances, memory system 110 may include a cache. For example, local memory 120 may be an instance of a cache or may include a cache. In another instance, one of memory devices 130 may be or may include a cache. In either instance, the cache may be divided into multiple blocks 170 or portions (e.g., as shown in reference memory device 130-a). In some cases (e.g., for a multi-level cache design), the individual blocks of the cache may correspond to different cell types (e.g., architecture). For example, the first block 170 may be an instance of an SLC portion, and the second block 170 may be an instance of an MLC portion. Furthermore, in some instances, one or more blocks 170 of the cache may be used as buffers (e.g., write booster buffers). In some instances, memory system 110 may utilize buffers for intermediate data storage between host system 105 and memory system 110. That is, memory system 110 may write data to the buffer before storing the data at memory device 130.

[0040] The memory system 110 can perform a refresh operation to move valid data from a first block 170 of the cache to a second block 170 of the cache. In some cases, the refresh operation may clean up the first block 170 of the cache (e.g., corresponding to a buffer) and cause the memory system 110 to store additional data in the first block 170 of the cache (e.g., after the refresh operation). In some cases, the refresh operation may be characterized based on the type of cell architecture associated with the second block 170 of the cache. For example, a refresh operation associated with garbage collection of valid data to a block 170 containing SLCs may be relatively faster than a refresh operation associated with garbage collection of valid data to a block 170 containing MLCs (e.g., dual-level cells, TLCs, QLCs). Additionally, a refresh operation associated with garbage collection of valid data to a block 170 containing MLCs may be more efficient (e.g., it may clean up more data from the first block 170) than a refresh operation associated with garbage collection of valid data to another block 170 containing SLCs.

[0041] In an instance of system 100, host system 105 may receive indications of one or more parameters from memory system 110, and host system 105 may select a refresh operation (e.g., a relatively fast refresh operation, a relatively more efficient refresh operation) based on or in response to said one or more parameters. In some instances, said one or more parameters may be associated with the amount or allocation of data stored in block 170 of cache (e.g., indicating a higher or lower amount of data stored, indicating a higher concentration or a lower concentration of stored data allocation, indicating the concentration of valid data stored), or said one or more parameters may be associated with a time estimate (e.g., indicating the estimated time that it would take to release a given amount of buffer using different types of refresh operations). Additionally, host system 105 may utilize historical data, such as historical parameter information (e.g., and one or more techniques for analyzing information, such as machine learning), to select a refresh operation.

[0042] Once host system 105 selects a refresh operation to perform, it can instruct memory system 110 to perform the selected refresh operation. For example, host system controller 106 can write the indication of the selected refresh operation to register 125 (e.g., send a command to memory system 110 to write the indication to register 125). Memory system controller 115 can poll register 125 to identify the selected refresh operation and perform the refresh operation based on the indicated selected refresh operation. In another example, host system controller 106 can send a command to memory system controller 115 indicating the selected refresh operation, and memory system controller 115 can perform the refresh operation based on or in response to the command, where the command may indicate whether to perform a first refresh operation or a second refresh operation. Thus, memory system 110 can selectively perform one or more faster or more efficient refresh operations based on or in response to one or more parameters associated with the cache and memory system. In some cases, selectively performing faster or more efficient refresh operations can improve overall processing efficiency and, in some cases, improve the user experience.

[0043] System 100 may include any number of non-transitory computer-readable media that support configurable refresh operation speeds. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0044] Figure 2 An example of a system 200 supporting configurable refresh operation speed is shown, based on the examples disclosed herein. System 200 may be a reference. Figure 1 Examples of system 100 as described in the description of the present invention. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 upon request by host system 205 using access commands (e.g., read commands or write commands). System 200 may implement references. Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0045] In some instances, memory system 210 may include cache 230 that can be divided into multiple portions 240. For example, cache 230 may include portions 240-a, 240-b, 240-c, and 240-d. Portions 240 may be references. Figure 1 An instance of block 170 is described. In some instances, cache 230 may be an instance of a multi-level cache design. That is, cache 230 may contain portions 240 associated with different unit architectures. For example, in some instances, portions 240-a and 240-b may contain SLC, and portions 240-c and 240-d may contain MLC. Specifically, portion 240-c may contain TLC, and portion 240-d may contain QLC.

[0046] In some instances, memory system 210 may utilize one or more portions 240 of cache 230 as buffers (e.g., write booster buffers). For example, memory system 210 may utilize portion 240-a as a buffer. In some instances, memory system 210 may rely on buffers to improve the performance of memory system 210. For example, in response to a write command transmitted by host system 205 to memory system 210 containing a set of data to be stored at memory system 210, memory system 210 may write the set of data to a buffer (e.g., portion 240-a of cache 230). Then, if the used buffer space meets a threshold, such as becoming full or nearly full, memory system 210 may perform a flush operation on the buffer, writing the data stored in the buffer to another portion 240 of cache 230. Using the portion 240 of cache 230 containing SLC as a buffer can improve write performance compared to using, for example, the portion 240 of cache 230 containing MLC, because the programming time associated with MLC can be longer than the programming time associated with SLC. Furthermore, SLC is associated with higher reliability compared to MLC. More generally, using the portion 240 of cache 230 containing low-order units (e.g., SLC, double-level cell) as a buffer, rather than using the portion 240 of cache 230 containing higher-order units (e.g., TLC, QLC), can improve write performance because the programming time associated with higher-order units can be longer than that associated with lower-order units. Additionally, low-order units are associated with higher reliability compared to higher-order units.

[0047] Memory system 210 may perform maintenance operations on one or more portions 240 of cache 230. For example, memory system 210 may perform refresh operations or garbage collection operations. In response to memory system 201 performing a refresh operation on portion 240 of cache 230, memory system 210 may write a subset of data stored in portion 240 (e.g., valid data stored in portion 240) to another portion 240 of cache 230. For example, performing a refresh operation may include moving data from a first portion 240-a of cache 230 to another portion 240 of cache 230 (e.g., portion 240-b, portion 240-c, or portion 240-d). Similarly, performing a garbage collection operation may include moving valid data from the first portion 240-a of cache 230 to another portion 240 of cache 230 and erasing data stored in the first portion 240-a of cache 230.

[0048] The speed and efficiency of refresh and garbage collection operations performed on portions 240 (e.g., portion 240-a) of cache 230 can depend on the type of memory cells in portion 240 containing data written to cache 230 (e.g., stored in portion 240-a) and other aspects. For example, moving data from portion 240-a to portion 240-b containing SLC can be relatively fast compared to moving data from portion 240-a to portion 240-c containing TLC or portion 240-d containing QLC. That is, SLC programming can be faster than TLC or QLC programming, or more generally, programming lower-order cells can be faster than programming higher-order cells. Additionally, moving data from portion 240-a to portion 240-b containing SLC may be less efficient than moving data from portion 240-a to portion 240-c containing TLC or portion 240-d containing QLC. For example, the data storage capacity of portions 240-c and 240-d can be greater than that of portions 240-a and 240-c (e.g., because MLC stores more data bits than SLC). Therefore, a larger amount of data can be moved to portions 240-c and 240-d (which contain MLC) compared to portion 240-b (which contains SLC). Consequently, moving data to portion 240-c (e.g., containing SLC) corresponds to the fastest refresh operation, moving data to portion 240-d (e.g., containing QLC) corresponds to the slowest refresh operation, and moving data to portion 240-c (e.g., containing TLC) corresponds to an intermediate speed refresh operation.

[0049] Memory system 210 may be configured to select a refresh operation type (e.g., a relatively fast refresh operation, a relatively slow refresh operation) for execution at portion 240 (e.g., portion 240-a) of cache 230 based on or in response to one or more parameters associated with cache 230. Alternatively, host system 205 may be configured to indicate a recommended refresh operation type to memory system 210 in response to parameters associated with memory system 210 and cache 230. For example, host system 205 may receive an indication from memory system 210 of one or more parameters associated with portion 240-a. For example, memory system 210 may write the indication of the one or more parameters to register 225. Host system 205 may poll the register to receive the indication of the one or more parameters from memory system 210.

[0050] Host system 205 may determine a refresh operation (e.g., faster, intermediate, or slower) based on or in response to parameters. Host system 205 may then be configured to instruct (e.g., send) a recommended refresh operation type to memory system 210 in response to parameters associated with memory system 210 and cache 230. Memory system 210 may determine whether to perform the recommended refresh operation type indicated by host system 205 or whether to perform a refresh operation different from the recommended refresh operation type. For example, if memory system 210 determines that one or more parameters were incorrectly indicated to host system 205 or if the one or more parameters indicated to host system 205 are no longer valid, then memory system 210 may determine to perform a refresh operation different from the recommended refresh operation type. Parameters may include a logical saturation level, fragmentation level, or effective count allocation associated with portion 240-a. The logical saturation level may indicate the percentage of data stored in portion 240-a. If the logic saturation level is high (e.g., above a threshold), then host system 205 may choose a slower refresh operation (e.g., a more efficient refresh operation), allowing a relatively large amount of data to be moved from portion 240-a during the refresh operation. The fragmentation level indicates the sparsity of data storage within portion 240-a. If the fragmentation level is high (data is extremely sparse), then host system 205 may choose a faster refresh to enable faster programming of fragmented data, and therefore the amount of data to be moved from portion 240-a can be relatively small. Effective count allocation indicates the physical occupancy of the buffer. If effective count allocation is low and logic saturation is high, then host system 205 may choose a fast refresh.

[0051] The host system 205 may additionally select or determine a suggested refresh operation based on (e.g., in response to) one or more additional parameters (e.g., parameters other than those indicated by the memory system 210, previously determined by the host system 205, or from another source). For example, the host system 205 may assess the battery level of the memory system 210 and the location of the system 200. That is, the host system 205 may select a slower refresh operation (e.g., to conserve power) if the battery level of the memory system 210 is below a threshold or if the location of the system 200 is not associated with power (e.g., a remote or unknown location, rather than a home or known location). Additionally, the host system 205 may rely on historical data (e.g., incorporating heuristics of user usage) and utilize machine learning algorithms (e.g., artificial intelligence) and other techniques to predict the timing associated with the refresh operation (e.g., the active / idle time ratio). In some instances, the predicted timing may be based on or in response to one or more of battery levels, real-time location, etc.

[0052] Once host system 205 selects a refresh operation, it can instruct memory system 210 to perform the selected refresh operation. For example, host system 205 can instruct portion 240 of cache 230 to move data stored in portion 240-a. For example, if host system 205 selects a faster refresh operation, it can instruct memory system 210 to perform portion 240-b (e.g., containing SLC). Additionally, if host system 205 determines that an intermediate-speed refresh should be performed, it can instruct memory system 210 to perform portion 240-c (e.g., containing TLC). Furthermore, if host system 205 determines that a slower refresh should be performed, it can instruct memory system 210 to perform portion 240-d (e.g., containing QLC). In some instances, host system 205 can instruct portion 240 of cache 230 via command (e.g., by transmitting a refresh command to memory system 210). In another example, host system 205 may indicate portion 240 of cache 230 by writing an indication of selected portion 240 to register 225 coupled to memory system 210. In some cases, memory system controller 215 may poll register 225 to determine which portion 240 of cache 230 host system 205 indicates. In some cases, register 225 may be associated with a set of registers 225, wherein each register 225 is associated with one of the one or more additional portions of the cache. For example, a first register 225 may be associated with portion 240-b, a second register 225 may be associated with portion 240-c, and a third register 225 may be associated with portion 240-d. Here, host system 205 may indicate portion 240 of cache 230 by writing an indication to a register in the set of registers 225 associated with the indicated portion 240 of cache 230.

[0053] After receiving an instruction for a selected refresh operation from host system 205, memory system 210 may perform a refresh operation at portion 240-a. In some cases, memory system 210 may perform the refresh operation instructed by host system 205 (e.g., by writing data from portion 240-a to portion 240 of cache 230 instructed by host system 205). In other cases, memory system 210 may perform a refresh operation different from the refresh operation instructed by host system 205. For example, host system 205 may instruct a faster refresh operation (e.g., associated with portion 240-b), and memory system 210 may determine to perform an intermediate-speed refresh operation (e.g., associated with portion 240-c). For example, memory system may determine to perform an intermediate-speed refresh operation (e.g., instead of the instructed fast refresh operation) based on a high percentage of effective data (e.g., physical saturation) in portion 240-a and the determination that the efficiency of the faster refresh operation (e.g., the amount of effective data moved in portion 240-a during the faster refresh operation) is not high enough to refresh portion 240-a. Additionally, the memory system may determine to perform an intermediate speed operation (e.g., instead of the indicated fast refresh operation) based on the predicted power consumption, based on or in response to a high effective count allocation (e.g., 90%) in part 240-a, or some other parameter or factor.

[0054] Figure 3 An example of a process flow 300 supporting a configurable refresh operation speed is shown according to the examples disclosed herein. In some instances, process flow 300 may implement aspects of system 100 or system 200, or may be implemented by said aspects. For example, process flow 300 may include a host system 305 and a memory system 310, which may be examples of the host system and memory system described herein. Memory system 310 may include a cache with different portions (e.g., a first portion with SLC, and an additional portion with SLC or MLC). Process flow 300 may involve host system 305 selecting a refresh operation based on or in response to one or more parameters, and sending an indication of the selected refresh operation to memory system 310, wherein memory system 310 may or may not perform the refresh operation selected by host system 305. Alternative examples described below may be implemented, in which some steps are performed in a different order or not at all. In some cases, steps may include additional features not mentioned below, or other steps may be added.

[0055] Various aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to host system 305 or memory system 310). For example, in response to execution by a controller (e.g., host system controller), the instructions may cause the controller to perform at least some or all of the operations of process flow 300.

[0056] At 315, one or more parameters may be transmitted. For example, at 315, one or more parameters may be transmitted to host system 305 via memory system 310 (e.g., via registers). For example, memory system 310 may determine a fragmentation level or logical saturation (or both) associated with a first portion of the memory system's cache (e.g., the SLC portion of the cache contained in memory system 310). In some instances, memory system 310 may indicate a fragmentation level (e.g., via the bFragmentationLevel parameter) and logical saturation (e.g., via the bLogicSaturation parameter) to host system 305 by programming registers to store values ​​indicating said one or more parameters (e.g., manufacturer default values ​​(MDV)). For example, memory system 310 may indicate a low fragmentation level of the first portion of the cache (e.g., a buffer) by programming registers to store the '0h' value of the bFragmentationLevel parameter. Additionally, memory system 310 can indicate a higher fragmentation level of the first portion of the cache (e.g., a buffer), for example, compared to a threshold, by programming a register to store the 'FFH' value of the bFragmentationLevel parameter. In another example, memory system 310 can indicate a lower saturation level of the first portion of the cache (e.g., a buffer), for example, compared to a threshold, by programming a register to store the '0h' value of the bLogicSaturation parameter. Furthermore, memory system 310 can indicate 1%, 25%, 50%, 75%, and 100% logic saturation levels of the first portion of the cache by programming registers to store the '1h', '25h', '50h', '75h', and '100h' values ​​of the bLogicSaturation parameter, respectively.

[0057] At 320, one or more parameters can be identified. For example, at 320, the one or more parameters can be identified by host system 305. In some instances, host system 305 can identify the one or more parameters (e.g., fragmentation level, logic saturation, effective count allocation, etc.) received from memory system 310 by polling registers coupled to memory system 310. Alternatively, host system 305 can determine one or more additional parameters associated with memory system 310. For example, host system 305 can identify battery life associated with memory system 310, current location of memory system 310, data associated with one or more previous refresh operations at memory system 310, computing power of memory system 310, or any combination thereof.

[0058] At 325, a cache portion (e.g., for refresh operations) can be identified. For example, at 325, a cache portion (e.g., for refresh operations) can be identified by host system 305. That is, host system 305 can identify the cache portion to which memory system 310 writes data from the first portion of the cache (e.g., a buffer, a portion of the cache containing SLC) in response to performing a refresh operation on the first portion of the cache. In some cases, host system 305 can identify a cache portion containing SLC for fast refresh operations, a cache portion containing TLC for intermediate-speed refresh operations, and a cache portion containing QLC for slower refresh operations. In some instances, host system 305 can identify the cache portion for refresh operations based on or in response to one or more parameters determined at 320. For example, if host system 305 determines that the first portion of the cache has a high level of fragmentation, then host system 305 can identify a cache portion containing SLC for faster refresh operations. In another instance, if host system 305 determines that the battery level associated with memory system 310 is low, then host system 305 may identify a cache portion containing QLC for slower refresh operations (e.g., those that consume less power).

[0059] At 330, a cache portion indication can be received. For example, at 330, a cache portion indication can be received by memory system 310. That is, host system 305 can transmit an indication of a cache portion (e.g., identified by host system 305 for a refresh operation at 325) to memory system 310. In one example, host system 305 can indicate the cache portion by transmitting a command to perform a refresh operation at memory system, wherein the command includes an indication of the cache portion. In another example, host system 305 can indicate the cache portion by programming a register to store an indication of the cache portion for a refresh operation. Here, memory system 310 can read the register to receive an indication of the cache portion for a refresh operation from host system 305. In some cases, host system 305 can indicate the cache portion for a refresh operation by indicating the speed (e.g., via the bWBFlushSpeed ​​parameter) corresponding to the refresh operation destination (e.g., the cache portion). For example, the host system can set the bWBFlushSpeed ​​parameter to '0h' to indicate no refresh operation, to '1h' to indicate fast refresh operation (e.g., corresponding to garbage collection to other SLCs), to '2h' to indicate normal refresh operation (e.g., corresponding to garbage collection to TLCs), and to '3h' to indicate slow refresh operation (e.g., corresponding to garbage collection to QLCs).

[0060] At 335, a cache portion for a refresh operation can be selected (e.g., a cache portion from which valid data can be moved from a first portion of the cache). For example, at 335, memory system 310 can select a destination cache portion for a refresh operation, wherein memory system 310 moves valid data from a first portion of the cache (e.g., a buffer) to the selected cache portion. That is, memory system 310 can select a second portion of the cache from an additional portion of the cache (e.g., other than the first portion of the cache or a buffer) for performing the refresh operation. In some cases, the second portion of the cache may be the same as the cache portion indicated by host system 305 at 330. In other cases, the second portion of the cache may be different from the cache portion indicated by host system 305 at 330. For example, host system 305 may indicate a cache portion associated with a fast refresh operation, and memory system 310 may select a cache portion associated with a normal refresh operation.

[0061] At 340, a refresh operation can be performed. For example, at 340, a refresh operation can be performed via memory system 310. For example, based on or in response to an instruction received from host system 305 regarding a cache portion, the memory system writes a subset of the data (e.g., containing valid data) stored in a first portion of the cache to a second portion of the cache. In some cases, after writing the subset of data to the second portion of the cache, memory system 310 erases the data stored in the first portion of the cache.

[0062] Figure 4 A block diagram 400 illustrates a memory system 420 supporting configurable refresh operation speed according to an example disclosed herein. The memory system 420 may be a reference... Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing the various aspects of the configurable refresh operation speed described herein. For example, memory system 420 may include parameter manager 425, cache portion manager 430, refresh operation manager 435, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0063] Parameter manager 425 may be configured or otherwise supported to provide means for transmitting to the host system one or more parameters associated with data stored in a first portion of a cache in the memory system, the cache comprising a first portion having multiple SLCs and one or more additional portions having multiple SLCs or multiple MLCs. Cache portion manager 430 may be configured or otherwise supported to provide means for receiving, at least in part, an instruction from the host system for a cache portion of the one or more additional portions for a refresh operation based on the transmission of the one or more parameters. Refresh operation manager 435 may be configured or otherwise supported to provide means for writing a subset of data stored in the first portion of the cache to a second portion of the cache in the one or more additional portions of the cache, at least in part based on performing a refresh operation and at least in part based on receiving an instruction for a cache portion.

[0064] In some instances, to support writing a subset of data to a second part, the refresh operation manager 435 may be configured or otherwise support a component for writing a subset of data to the indicated part of the cache.

[0065] In some instances, the cache portion manager 430 may be configured or otherwise support components for selecting a second portion of the cache from the one or more additional portions of the cache, different from the indicated portion, based at least in part on a received instruction, wherein a subset of data is written to the second portion based at least in part on the selection.

[0066] In some instances, the selection of the second portion is based at least in part on a first speed of refresh operation associated with the second portion, a second speed of refresh operation associated with the indicated portion, a first amount of available space within the second portion, a second amount of available space within the indicated portion, or any combination thereof.

[0067] In some instances, the cache section's indication includes a value corresponding to one of a plurality of speeds for a refresh operation. In some instances, each of the one or more additional sections is associated with a corresponding speed among the plurality of speeds.

[0068] In some instances, a first additional portion of the one or more additional portions, having a cache of multiple SLCs, is associated with a first speed of refresh operations among the multiple speeds. In some instances, a second additional portion of the one or more additional portions, having a cache of multiple MLCs, is associated with a second speed of refresh operations among the multiple speeds, where the first speed is faster than the second speed.

[0069] In some instances, the one or more parameters include an indication of data fragmentation in a first portion of the cache, an indication of the percentage of valid data in the first portion of the cache, or both.

[0070] In some instances, to support receiving instructions, the cache portion manager 430 may be configured or otherwise support components for reading instructions stored in registers coupled to the memory system.

[0071] In some instances, to support receiving instructions, the cache portion manager 430 may be configured or otherwise support components for reading instructions stored in a set of registers coupled to the memory system, each of which is associated with one of the one or more additional portions of the cache.

[0072] In some instances, to support receiving instructions, the cache portion manager 430 may be configured or otherwise support components for receiving commands to perform refresh operations, wherein the commands contain instructions for the cache portion to be refreshed.

[0073] In some instances, to support the transmission of the one or more parameters, the parameter manager 425 may be configured or otherwise support components for writing indications of the one or more parameters into registers coupled to the memory system.

[0074] In some instances, to support refresh operations, the refresh operation manager 435 may be configured or otherwise supported to include means for identifying a subset of data stored in a first part of the cache based at least in part on the fact that a subset of the data contains valid data, wherein the subset of data written is based at least in part on said identification. In some instances, to support refresh operations, the refresh operation manager 435 may be configured or otherwise supported to erase data stored in the first part of the cache based at least in part on writing a subset of the data to a second part of the cache.

[0075] Figure 5 A block diagram 500 illustrates a host system 520 supporting configurable refresh operation speeds according to the examples disclosed herein. The host system 520 may be a reference... Figures 1 to 3 Examples of various aspects of the host system described herein. Host system 520 or its various components may be examples of constructs for performing the various aspects of the configurable refresh operation speed described herein. For example, host system 520 may include parameter receiver 525, cache portion identifier 530, cache portion indicator 535, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0076] Parameter receiver 525 may be configured or otherwise supported to include means for receiving from a memory system one or more parameters associated with data stored in a first portion of a cache in the memory system, the cache comprising a first portion having multiple SLCs and one or more additional portions having multiple SLCs or multiple MLCs. Cache portion identifier 530 may be configured or otherwise supported to include means for identifying, at least in part, cache portions of the one or more additional portions for refresh operations performed at the memory system based on the one or more parameters. Cache portion indicator 535 may be configured or otherwise supported to include means for indicating to the memory system the identified portion of the cache for a refresh operation.

[0077] In some instances, to support indication of the identified portion of the cache, the cache portion recognizer 530 may be configured or otherwise support means for writing values ​​to registers coupled to the memory system, wherein the values ​​indicate the identified portion of the cache.

[0078] In some instances, to support indicating the identified portion of the cache, the cache portion identifier 530 may be configured or otherwise support means for writing values ​​to a set of registers coupled to the memory system, wherein each register in the set of registers is associated with one of the one or more additional portions of the cache, and writing a value to one of the set of registers indicates the identified portion of the cache based on which portion of the one or more additional portions of the cache the one register is associated with.

[0079] In some instances, to support indication of the identified portion of the cache, the cache portion indicator 535 may be configured or otherwise support a component for transmitting commands to perform a refresh operation, wherein the commands indicate the identified portion of the cache for the refresh operation.

[0080] In some instances, to support the identification of cache portions used for refresh operations, the cache portion identifyer 530 may be configured or otherwise support the identification of cache portions based at least in part on the speed of refresh operations associated with the identified portion.

[0081] In some instances, to support receiving the one or more parameters, the parameter receiver 525 may be configured or otherwise supported as a component for polling registers at a memory system, wherein the registers store indications of the one or more parameters.

[0082] In some instances, the cache section's indication includes a value corresponding to one of a plurality of speeds for a refresh operation. In some instances, each of the one or more additional sections is associated with a corresponding speed among the plurality of speeds.

[0083] In some instances, a first additional portion of the one or more additional portions, having a cache of multiple SLCs, is associated with a first speed of refresh operations among the multiple speeds. In some instances, a second additional portion of the one or more additional portions, having a cache of multiple MLCs, is associated with a second speed of refresh operations among the multiple speeds, where the first speed is faster than the second speed.

[0084] In some instances, the one or more parameters include an indication of data fragmentation in a first portion of the cache, an indication of the percentage of valid data in the first portion of the cache, or both.

[0085] In some instances, the cache portion indicator 535 may be configured or otherwise support components for identifying cache portions for refresh operations based on or in response to one or more additional parameters, said one or more additional parameters including battery life associated with the memory system, the current location of the memory system, data associated with one or more previous refresh operations at the memory system, the computing power of the memory system, or any combination thereof.

[0086] Figure 6 A flowchart illustrating an example disclosed herein demonstrates a method 600 supporting configurable refresh operation speed. Operation of method 600 can be implemented by the memory system or its components described herein. For example, operation of method 600 can be provided by reference to... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system can use dedicated hardware to perform aspects of the function.

[0087] At 605, the method may include transmitting to the host system one or more parameters associated with data stored in a first portion of a cache in a memory system, the cache comprising a first portion having multiple SLCs and one or more additional portions having multiple SLCs or multiple MLCs. Operation 605 may be performed according to the examples disclosed herein. In some instances, aspects of operation 605 may be derived from references... Figure 4 The parameter manager 425 described is executed.

[0088] At 610, the method may include, at least in part, receiving an indication from the host system of a cache portion of the one or more additional portions used for a refresh operation, based on transmitting the one or more parameters. Operation 610 may be performed according to the examples disclosed herein. In some instances, aspects of operation 610 may be derived from references... Figure 4 The cache manager 430 described is executed.

[0089] At 615, the method may include writing a subset of data stored in a first portion of the cache to a second portion of the cache in one or more additional portions, based at least in part on performing a refresh operation and at least in part on receiving an instruction from a cache portion. Operation 615 may be performed according to the examples disclosed herein. In some instances, aspects of operation 615 may be derived from references... Figure 4 The refresh operation manager 435 is described as executing.

[0090] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting to a host system one or more parameters associated with data stored in a first portion of a cache in a memory system, the cache comprising a first portion having multiple SLCs and one or more additional portions having multiple SLCs or multiple MLCs; receiving from the host system, at least in part based on transmitting the one or more parameters, an instruction for a refresh operation in the cache portion of the one or more additional portions; and writing a subset of the data stored in the first portion of the cache into a second portion of the cache in the one or more additional portions, at least in part based on performing the refresh operation and at least in part based on receiving the instruction for the cache portion.

[0091] In some instances of the method 600 and device described herein, writing a subset of data to the second part may include operations, features, circuitry, logic, components, or instructions for writing a subset of data to the indicated part of the cache.

[0092] Some instances of the method 600 and device described herein may further include operations, features, circuitry, logic, components, or instructions for selecting, at least in part, a second portion of the cache from one or more additional portions that differs from the indicated portion, based at least in part on the received indication, wherein writing a subset of data to the second portion may be at least in part based on the selection.

[0093] Some examples of the method 600 and device described herein may further include operations, features, circuitry, logic, components, or instructions for selecting the second portion based at least in part on: a first speed of refresh operation associated with the second portion, a second speed of refresh operation associated with the indicated portion, a first amount of available space within the second portion, a second amount of available space within the indicated portion, or any combination thereof.

[0094] In some instances of the method 600 and device described herein, the indication of the cache portion includes a value corresponding to one of a plurality of speeds of a refresh operation, and each of the one or more additional portions is associated with a corresponding speed among the plurality of speeds.

[0095] In some instances of the method 600 and device described herein, a first additional portion of the one or more additional portions having a cache of multiple SLCs may be associated with a first speed of refresh operation among the multiple speeds, and a second additional portion of the one or more additional portions having a cache of multiple MLCs may be associated with a second speed of refresh operation among the multiple speeds, the first speed being faster than the second speed.

[0096] In some instances of the method 600 and device described herein, the one or more parameters include an indication of data fragmentation in a first portion of the cache, an indication of the percentage of valid data in the first portion of the cache, or both.

[0097] In some instances of the method 600 and device described herein, the receiving indication may include operations, features, circuitry, logic, components, or instructions for reading a cached portion of an indication stored in a register coupled to the memory system.

[0098] In some instances of the method 600 and device described herein, receiving an indication may include an operation, feature, circuitry, logic, component, or instruction for reading an indication stored in a cache portion coupled to a set of registers, wherein each of the set of registers is associated with one of the one or more additional portions of the cache.

[0099] In some instances of the method 600 and device described herein, the receiving indication may include an operation, feature, circuitry, logic, component, or instruction for receiving a command to perform a refresh operation, wherein the command includes an indication of a cached portion for the refresh operation.

[0100] In some instances of the method 600 and device described herein, transmitting the one or more parameters may include operations, features, circuitry, logic, components, or instructions for writing indications of the one or more parameters into registers coupled to a memory system.

[0101] In some instances of the method 600 and device described herein, performing a refresh operation may include operations, features, circuitry, logic, components, or instructions for: identifying a subset of data stored in a first portion of a cache based at least in part on the fact that a subset of data contains valid data, wherein writing the subset of data may be based at least in part on the identification; and erasing the data stored in the first portion of the cache based at least in part on writing the subset of data to a second portion of the cache.

[0102] Figure 7A flowchart illustrating an example disclosed herein demonstrates a method 700 supporting configurable refresh operation speed. The operation of method 700 can be implemented by the host system or its components described herein. For example, the operation of method 700 can be provided by a reference... Figures 1 to 3 The host system described in section 5 performs the functions described herein. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the functions described herein.

[0103] At 705, the method may include receiving from a memory system one or more parameters associated with data stored in a first portion of a cache of the memory system, said cache comprising a first portion having multiple SLCs and one or more additional portions having multiple SLCs or multiple MLCs. Operation 705 may be performed according to the examples disclosed herein. In some instances, aspects of operation 705 may be referenced from... Figure 5 The parameters described are executed by receiver 525.

[0104] At 710, the method may include identifying, at least in part, a cache portion of the one or more additional portions for a refresh operation performed at the memory system, based on the one or more parameters. Operation 710 may be performed according to the examples disclosed herein. In some instances, aspects of operation 710 may be derived from references... Figure 5 The cache segment recognizer 530 described is executed.

[0105] At 715, the method may include instructing the memory system of an identified portion of the cache for a refresh operation. Operation 715 may be performed according to the examples disclosed herein. In some instances, aspects of operation 715 may be derived from references... Figure 5 The described cache section indicator 535 is executed.

[0106] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving from a memory system one or more parameters associated with data stored in a first portion of a cache of the memory system, the cache comprising a first portion having multiple SLCs and one or more additional portions having multiple SLCs or multiple MLCs; identifying, at least in part, a cache portion of the one or more additional portions for a refresh operation performed at the memory system based on the one or more parameters; and indicating to the memory system the identified portion of the cache for the refresh operation.

[0107] In some instances of the method 700 and device described herein, the identified portion of the cache may include operations, features, circuitry, logic, components, or instructions for writing values ​​to registers coupled to a memory system, wherein the values ​​indicate the identified portion of the cache.

[0108] In some instances of the method 700 and device described herein, indicating an identified portion of a cache may include operations, features, circuitry, logic, components, or instructions for writing values ​​to a set of registers coupled to a memory system, wherein each register in the set of registers is associated with one of the one or more additional portions of the cache, and writing a value to one of the one of the set of registers indicates the identified portion of the cache based on which of the one registers is associated with the one or more additional portions of the cache.

[0109] In some instances of the method 700 and device described herein, the identified portion of the cache may include operations, features, circuitry, logic, components, or instructions for transmitting commands to perform a refresh operation, wherein the commands indicate the identified portion of the cache for the refresh operation.

[0110] In some instances of the method 700 and device described herein, identifying a cache portion for refresh operations may include operations, features, circuitry, logic, components, or instructions for identifying the cache portion based at least in part on the speed of the refresh operations associated with the identified portion.

[0111] In some instances of the method 700 and device described herein, receiving the one or more parameters may include operations, features, circuitry, logic, components, or instructions for polling registers at a memory system, wherein the registers store indications of the one or more parameters.

[0112] In some instances of the method 700 and device described herein, the indication of the cache portion includes a value corresponding to one of a plurality of speeds of a refresh operation, and each of the one or more additional portions is associated with a corresponding speed among the plurality of speeds.

[0113] In some instances of the method 700 and device described herein, a first additional portion of the one or more additional portions having a cache of multiple SLCs may be associated with a first speed of refresh operation among the multiple speeds, and a second additional portion of the one or more additional portions having a cache of multiple MLCs may be associated with a second speed of refresh operation among the multiple speeds, the first speed being faster than the second speed.

[0114] In some instances of the method 700 and device described herein, the one or more parameters include an indication of data fragmentation in a first portion of the cache, an indication of the percentage of valid data stored in the first portion of the cache, or both.

[0115] In some instances of the method 700 and device described herein, the device may include operations, features, circuitry, logic, components, or instructions for identifying cache portions for refresh operations based on or in response to one or more additional parameters, wherein the one or more additional parameters include battery life associated with the memory system, the current location of the memory system, data associated with one or more previous refresh operations at the memory system, the computing power of the memory system, or any combination thereof.

[0116] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0117] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0118] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, based on or in response to the operation of a device containing the connected components, the conductive path between electronically connected (or electrically contacting, connected, or coupled) components can be open or closed. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0119] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If, for example, one component of a controller couples other components together, then that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0120] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0121] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms are interchangeable if they are used to describe the connection between conditional actions, conditional processes, or parts of processes.

[0122] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0123] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other condition or action.

[0124] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0125] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0126] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0127] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0128] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0129] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0130] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0131] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0132] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: a cache comprising a first portion having a plurality of single-level units and one or more additional portions having a plurality of single-level units or a plurality of multi-level units; and a controller coupled with the cache and configured to cause the apparatus to: write data to the first portion of the cache based at least in part on receiving a command; transmit, to a host system, one or more parameters associated with the data stored in the first portion of the cache; receive, from the host system, an indication of a portion of the cache in the one or more additional portions for a refresh operation after writing the data to the first portion of the cache and based at least in part on transmitting the one or more parameters; and write, based at least in part on performing the refresh operation and based at least in part on receiving the indication of the portion of the cache, a subset of the data stored in the first portion of the cache to a second portion of the cache of the one or more additional portions.

2. The apparatus of claim 1, wherein writing the subset of the data to the second portion comprises: writing the subset of the data to the indicated portion of the cache for the refresh operation.

3. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: select, based at least in part on receiving the indication, a second portion of the one or more additional portions of the cache different from the indicated portion of the cache for the refresh operation, wherein writing the subset of the data to the second portion is based at least in part on the selection.

4. The apparatus of claim 3, wherein selecting the second portion is based at least in part on a first speed of the refresh operation associated with the second portion, a second speed of the refresh operation associated with the indicated portion, a first amount of available space within the second portion, a second amount of available space within the indicated portion, or any combination thereof.

5. The apparatus of claim 1, wherein: the indication of the portion of the cache comprises a value corresponding to one of a plurality of speeds for the refresh operation; and each of the one or more additional portions is associated with a respective speed of the plurality of speeds.

6. The apparatus of claim 5, wherein: a first additional portion of the one or more additional portions of the cache having a plurality of single-level units is associated with a first speed of the refresh operation of the plurality of speeds; and a second additional portion of the one or more additional portions of the cache having a plurality of multi-level units is associated with a second speed of the refresh operation of the plurality of speeds, the first speed being faster than the second speed.

7. The apparatus of claim 1, wherein the one or more parameters comprise an indication of fragmentation of the data stored in the first portion of the cache, an indication of a percentage of the first portion of the cache that stores valid data, or both.

8. The apparatus of claim 1, further comprising: a register coupled with the controller and configured to store the indication of the portion of the cache received from the host system, wherein the controller is further configured to cause the apparatus to read the indication of the portion of the cache stored at the register.

9. The apparatus of claim 1, further comprising: a set of registers coupled with the controller and configured to together store the indication of the portion of the cache received from the host system, wherein each register of the set of registers is associated with one of the one or more additional portions of the cache, and wherein the controller is further configured to cause the apparatus to read the indication of the portion of the cache stored at the set of registers.

10. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive a second command to perform the refresh operation, wherein the second command comprises the indication of the portion of the cache for the refresh operation.

11. The apparatus of claim 1, further comprising: a register coupled with the controller and configured to store an indication of the one or more parameters, wherein the controller is further configured to cause the apparatus to write the indication of the one or more parameters to the register.

12. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: identify the subset of the data stored in the first portion of the cache based at least in part on the subset of the data comprising valid data, wherein writing the subset of the data is based at least in part on the identification; and erasing the data stored in the first portion of the cache based at least in part on writing the subset of the data to the second portion of the cache.

13. An apparatus comprising: a controller configured to couple with a memory system, wherein the controller is configured to cause the apparatus to: transmit a command to the memory system to write data to a first portion of a cache of the memory system, the cache comprising the first portion having a plurality of single-level cells and one or more additional portions having a plurality of single-level cells or a plurality of multi-level cells; receive one or more parameters associated with the data stored in the first portion from the memory system; after transmitting the command to write the data to the first portion of the cache, identifying, based at least in part on the one or more parameters, a portion of the cache in the one or more additional portions for a refresh operation to be performed at the memory system, the refresh operation being associated with writing a subset of data stored in the first portion of the cache to a second portion of the cache of the one or more additional portions of the cache; and indicating the identified portion of the cache for the refresh operation to the memory system.

14. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: write an indication of the identified portion of the cache to a register at the memory system.

15. The apparatus of claim 13, wherein indicating the identified portion of the cache comprises: transmitting a second command to perform the refresh operation, wherein the second command indicates the identified portion of the cache for the refresh operation.

16. The apparatus of claim 13, wherein identifying the portion of the cache for the refresh operation comprises: identifying the portion of the cache based at least in part on a speed of the refresh operation associated with the identified portion.

17. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: poll a register at the memory system, wherein the register stores an indication of the one or more parameters.

18. The apparatus of claim 13, wherein: indicating the portion of the cache comprises indicating a value corresponding to one of a plurality of speeds for the refresh operation; and each of the one or more additional portions is associated with a respective speed of the plurality of speeds.

19. The apparatus of claim 18, wherein: a first additional portion of the one or more additional portions of the cache having a plurality of single-level cells is associated with a first speed of the plurality of speeds for the refresh operation; and a second additional portion of the one or more additional portions of the cache having a plurality of multi-level cells is associated with a second speed of the plurality of speeds for the refresh operation, the first speed being faster than the second speed.

20. The apparatus of claim 13, wherein: identifying the portion of the cache for the refresh operation is based at least in part on one or more additional parameters; and the one or more additional parameters comprise a battery life associated with the memory system, a current location of the memory system, data associated with one or more previous refresh operations at the memory system, a computational power of the memory system, or any combination thereof.

21. A non-transitory computer-readable medium storing code at a memory system, the code comprising instructions executable by a processor to: writing data to a first portion of a cache based at least in part on receiving a command, the cache including the first portion having a plurality of single-level cells and one or more additional portions having a plurality of single-level cells or a plurality of multi-level cells; transmitting, to a host system, one or more parameters associated with data stored in the first portion; receiving, from the host system, an indication of a portion of the cache from the one or more additional portions for a refresh operation after writing the data to the first portion of the cache and based at least in part on transmitting the one or more parameters; and writing a subset of the data stored in the first portion of the cache to a second portion of the cache of the one or more additional portions based at least in part on performing the refresh operation and based at least in part on receiving the indication of the portion of the cache.

22. The non-transitory computer-readable medium of claim 21, wherein the instructions to write the subset of the data to the second portion are executable by the processor to: write the subset of the data to the indicated portion of the cache for the refresh operation.

23. The non-transitory computer-readable medium of claim 21, wherein the instructions are further executable by the processor to: select, from the one or more additional portions of the cache, the second portion different from the indicated portion of the cache for the refresh operation based at least in part on receiving the indication, wherein writing the subset of the data to the second portion is based at least in part on the selection.

24. A non-transitory computer-readable medium storing code at a host system, the code comprising instructions executable by a processor to: transmit, to a memory system, a command to write data to a first portion of a cache of the memory system, the cache including the first portion having a plurality of single-level cells and one or more additional portions having a plurality of single-level cells or a plurality of multi-level cells; receive, from the memory system, one or more parameters associated with the data stored in the first portion; after transmitting the command to write the data to the first portion of the cache, identify, based at least in part on the one or more parameters, a portion of the cache from the one or more additional portions for a refresh operation to be performed at the memory system, the refresh operation associated with writing a subset of data stored in the first portion of the cache to a second portion of the cache of the one or more additional portions of the cache; and indicate, to the memory system, the identified portion of the cache for the refresh operation.

25. The non-transitory computer-readable medium of claim 24, wherein the instructions to indicate the identified portion of the cache are executable by the processor to: writing an indication of the identified portion of the cache to a register at the memory system.

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