Gate driving circuit and display panel

Abstract

The present invention discloses a gate driving circuit and a display panel. The gate driving circuit includes a first gate driving signal generating module for generating and outputting a first gate driving signal; a second gate driving signal generating module, the input end of the second gate driving signal generating module is connected to the output end of the first gate driving signal generating module; the second gate driving signal generating module is used to respond to a first control signal and a second control signal, modulate the first gate driving signal and output a second gate driving signal. In this embodiment, the second gate driving signal generating module can modulate the first gate driving signal to generate and output a second gate driving signal, thereby realizing the output of two sets of gate driving signals through the first gate driving circuit, simplifying the structure of the gate driving circuit, reducing the area of the gate driving circuit, and being beneficial to realizing the narrow border of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a display panel. Background Art

[0002] With the development of display technologies, the applications of display panels are becoming more and more extensive, and correspondingly, the requirements for display panels are also getting higher and higher.

[0003] Currently, display panels use an external compensation circuit to compensate for the influence caused by the change in the threshold voltage of driving transistors. However, different scanning signals in the external compensation circuit cannot be shared, and different gate driving circuits are required to generate different scanning signals, which further leads to an increase in the area of the gate driving circuit and an increase in the border of the display panel. Summary of the Invention

[0004] The present invention provides a gate driving circuit and a display panel to simplify the structure of the gate driving circuit, reduce the area of the gate driving circuit, and facilitate the realization of a narrow border.

[0005] According to one aspect of the present invention, a gate driving circuit is provided, including a first gate driving signal generation module for generating and outputting a first gate driving signal;

[0006] a second gate driving signal generation module, the input end of the second gate driving signal generation module being connected to the output end of the first gate driving signal generation module; the second gate driving signal generation module is configured to respond to a first control signal and a second control signal, and modulate the first gate driving signal and then output a second gate driving signal;

[0007] wherein, the first control signal and the second control signal are high and low level signals with respect to each other; the working process of the gate driving circuit includes a first stage and a second stage; in the first stage, the first gate driving signal and the second gate driving signal are the same;

[0008] In the second stage, the first gate driving signal and the second gate driving signal are different, and the second gate driving signal is a fixed level signal.

[0009] Optionally, the first gate driving signal generation module accesses a first clock signal and a second clock signal;

[0010] The second gate driving signal generating module includes an output unit and a control unit. The input end of the output unit is connected to the output end of the first gate driving signal generating module. The control unit is respectively connected to the input end and the control end of the output unit. The control unit is respectively connected to the first control signal, the second control signal and the first clock signal. The control unit is configured to control the output end of the output unit to output the second gate driving signal in response to the first control signal, the second control signal and the first clock signal.

[0011] Optionally, the control unit includes a storage unit, a first control unit and a second control unit. The first control unit is respectively connected to the first clock signal, the first control signal and a first level signal, and is configured to respond to the first clock signal and the first control signal in the first stage to control whether to transmit the first level signal to the control end of the output unit. The second control unit is connected to the second control signal and the first clock signal, and is configured to respond to the second control signal in the second stage to control the transmission of the first clock signal to the control end of the output unit.

[0012] The first end of the storage unit is connected to the input end of the output unit, and the second end of the storage unit is connected to the control end of the output unit.

[0013] Optionally, the first control unit includes:

[0014] A first transistor and a second transistor. The first pole of the first transistor is connected to the first level signal, the second pole of the first transistor is connected to the first pole of the second transistor, the gate of the first transistor is connected to the first control signal, the second pole of the second transistor is connected to the control end of the output unit, and the gate of the second transistor is connected to the first clock signal.

[0015] Alternatively, the first control unit includes: a first transistor, a second transistor and a third transistor. The first pole of the first transistor is connected to the first level signal, the second pole of the first transistor is connected to the first pole of the second transistor, the gate of the first transistor is connected to the first control signal, the second pole of the second transistor is connected to the first pole of the third transistor, the second pole of the second transistor is connected to the first clock signal, the second pole of the third transistor is connected to the control end of the output unit, and the gate of the third transistor is connected to the first level signal.

[0016] Optionally, the second control unit includes: a fourth transistor, a first pole of the fourth transistor is connected to the first clock signal, a second pole of the fourth transistor is connected to a second pole of the second transistor, and a gate of the fourth transistor is connected to the second control signal.

[0017] Optionally, the storage unit includes a storage capacitor, a first end of the storage capacitor is connected to an input end of the output unit, and a second end of the storage capacitor is connected to a control end of the output unit.

[0018] Optionally, the output unit includes: a fifth transistor, a first pole of the fifth transistor is connected to an output end of the first gate driving signal generation module, a second pole of the fifth transistor serves as an output end of the output unit, and a gate of the fifth transistor is connected to the control unit.

[0019] Optionally, the first gate driving signal generation module includes a shift register circuit, and the shift register circuit is connected to a first clock signal, a second clock signal, a first level signal, and a second level signal.

[0020] Optionally, the shift register circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, and a second capacitor;

[0021] The first pole of the sixth transistor is connected to an input signal, the second pole of the sixth transistor is connected to the first node, and the gate of the sixth transistor is connected to the first clock signal; the first pole of the seventh transistor is connected to the first node, the second pole of the seventh transistor is connected to the first pole of the eighth transistor, and the gate of the seventh transistor is connected to the second clock signal; the second pole of the eighth transistor is connected to the second level signal, and the gate of the eighth transistor is connected to the second node; the first pole of the ninth transistor is connected to the first clock signal, the second pole of the ninth transistor is connected to the second node, and the gate of the ninth transistor is connected to the first node; the first pole of the tenth transistor is connected to the first level signal, the second pole of the tenth transistor is connected to the second node, and the gate of the tenth transistor is connected to the first clock signal; the first pole of the eleventh transistor is connected to the first node, the second pole of the eleventh transistor is connected to the third node, and the gate of the eleventh transistor is connected to the first level signal; the first pole of the twelfth transistor is connected to the second clock signal, the second pole of the twelfth transistor is connected to the input end of the second gate driving signal generating module, and the gate of the twelfth transistor is connected to the third node; the first pole of the thirteenth transistor is connected to the second level signal, the second pole of the thirteenth transistor is connected to the second pole of the twelfth transistor, and the gate of the thirteenth transistor is connected to the second node; the first end of the first capacitor is connected to the gate of the twelfth transistor, the second end of the first capacitor is connected to the second pole of the twelfth transistor, the first end of the second capacitor is connected to the gate of the thirteenth transistor, and the second end of the second capacitor is connected to the first pole of the thirteenth transistor.

[0022] According to another aspect of the present invention, a display panel is provided, including the gate driving circuit described in any one of the above.

[0023] The gate driving circuit provided by the embodiment of the present invention includes: a first gate driving signal generating module, configured to generate and output a first gate driving signal; a second gate driving signal generating module, the input end of the second gate driving signal generating module is connected to the output end of the first gate driving signal generating module; the second gate driving signal generating module is configured to respond to a first control signal and a second control signal, modulate the first gate driving signal and output a second gate driving signal. In the first stage, the first gate driving signal and the second gate driving signal are the same; in the second stage, the first gate driving signal and the second gate driving signal are different, and the second gate driving signal is a fixed-level signal. In this embodiment, the second gate driving signal generating module can modulate the first gate driving signal to generate and output the second gate driving signal, thereby realizing the output of two groups of gate driving signals through the first gate driving circuit, simplifying the structure of the gate driving circuit, reducing the area of the gate driving circuit, and being beneficial to realizing the narrow border of the display panel.

[0024] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 is a schematic structural diagram of a pixel circuit applicable to external compensation in the related art;

[0027] Figure 2 is a driving timing diagram of the pixel circuit in the detection stage;

[0028] Figure 3 is a driving timing diagram of the pixel circuit in the display stage;

[0029] Figure 4 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0030] Figure 5 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0031] Figure 6 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0032] Figure 7It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0033] Figure 8 It is a driving timing diagram of a gate driving circuit provided by an embodiment of the present invention in the first stage;

[0034] Figure 9 It is a driving timing diagram of a gate driving circuit provided by an embodiment of the present invention in the first stage;

[0035] Figure 10 It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0036] Figure 11 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0037] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0039] Figure 1 It is a schematic structural diagram of a pixel circuit applicable to external compensation in the related art. Refer to Figure 1, the pixel circuit includes a driving transistor M0, a compensating transistor M1, a data writing transistor M2, and a light-emitting control transistor M3. The first pole of the driving transistor M0 is connected to the first power supply VDD, the second pole of the driving transistor M0 is connected to the first pole of the light-emitting control transistor M3, the second pole of the light-emitting control transistor M3 is connected to the first end of the light-emitting device LD, and the second end of the light-emitting device LD is connected to the second power supply VSS. The gate of the light-emitting control transistor M3 receives the light-emitting control signal EM. The first pole of the data writing transistor M2 is connected to the data line Vdata, the second pole of the data writing transistor M2 is connected to the gate of the driving transistor M0, and the gate of the data writing transistor M2 receives the first gate driving signal Sn. The first pole of the compensating transistor M1 is connected to the second pole of the driving transistor M0, the second pole of the compensating transistor M1 is connected to the gate of the driving transistor M0, and the gate of the compensating transistor M1 receives the second gate driving signal Sn_B. Exemplarily, Figure 1 the transistors are all P-type transistors. Figure 1 The working process of the pixel circuit shown includes a detection stage and a display stage. In the detection stage, the compensating transistor M1 and the data writing transistor M2 need to be turned on to write the threshold voltage information of the driving transistor M0 into the gate of the driving transistor M0, and the voltage of the gate of the driving transistor M0 is transmitted to the external chip through the data line Vdata. In the display stage, the compensating transistor M1 is turned off and the data writing transistor M2 is turned on, and the data line Vdata writes the compensated data voltage into the gate of the driving transistor M0. Among them, the compensated data voltage is determined according to the voltage of the gate of the driving transistor M0 detected in the detection stage and the voltage of the first power supply VDD. Specifically, the threshold voltage of the driving transistor M0 is equal to the difference between the voltage of the first power supply VDD and the voltage of the gate of the driving transistor M0, so the compensated data voltage is equal to the sum of the gray-scale voltage corresponding to the gray scale and the threshold voltage. Figure 2 is the driving timing diagram of the pixel circuit in the detection stage, Figure 3 is the driving timing diagram of the pixel circuit in the display stage. In the detection stage, the first gate driving signal Sn is the same as the second gate driving signal Sn_B to turn on both the compensating transistor M1 and the data writing transistor M2. In the display stage, the first gate driving signal Sn is always at a high level, and the second gate driving signal Sn_B has a pulse to turn off the compensating transistor M1 and turn on the data writing transistor M2. Therefore, the first gate driving signal Sn and the second gate driving signal Sn_B required for the external compensation pixel circuit are not completely the same during the entire working process of the external compensation pixel circuit. In the prior art, only one kind of gate driving signal can be generated. To generate the above different first gate driving signal Sn and second gate driving signal Sn_B, two sets of gate driving circuits are required, resulting in an increase in the area of the gate driving circuit, which is not conducive to the realization of a narrow border.

[0040] In view of the above technical problems, an embodiment of the present invention provides a gate driving circuit. Figure 4 FIG. Figure 4 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention. Refer to Figure 4 , the circuit includes a first gate driving signal generating module 10, configured to generate and output a first gate driving signal.

[0041] A second gate driving signal generating module 11, an input end of the second gate driving signal generating module 11 is connected to an output end OUT1 of the first gate driving signal generating module 10; the second gate driving signal generating module 11 is configured to respond to a first control signal K1 and a second control signal K2, and modulate the first gate driving signal and then output a second gate driving signal.

[0042] Wherein, the first control signal K1 and the second control signal K2 are complementary high and low level signals.

[0043] The working process of the gate driving circuit includes a first stage and a second stage. In the first stage, the first gate driving signal and the second gate driving signal are the same; in the second stage, the first gate driving signal and the second gate driving signal are different, and the second gate driving signal is a fixed level signal.

[0044] Exemplarily, the first gate driving signal generating module 10 may include any shift register circuit in the prior art for generating a scan signal, such as a 7T2C circuit, configured to output the first gate driving signal through its output end OUT1. An output end OUT2 of the second gate driving signal generating module 11 is configured to output a second gate driving signal. When the first control signal K1 is at a high level, the second control signal K2 is at a low level. When the first control signal K1 is at a low level, the second control signal K2 is at a high level.

[0045] Exemplarily, the working process of the gate driving circuit includes a first stage and a second stage. Among them, the first stage corresponds to the detection stage described above, and the second stage corresponds to the display stage described above. The first control signal K1 is at a low level in the first stage, and the second control signal K2 is at a high level in the first stage. The first control signal K1 is at a high level in the second stage, and the second control signal K2 is at a low level in the second stage. In the first stage, under the control of the first control signal K1 and the second control signal K2, the second gate driving signal output by the second gate driving signal generating module 11 is the same as the first gate driving signal. In the second stage, under the control of the first control signal K1 and the second control signal K2, the second gate driving signal output by the second gate driving signal generating module 11 is not exactly the same as the first gate driving signal, thereby meeting the requirements of the pixel circuit driven by the gate driving circuit for different gate driving signals in different stages.

[0046] In this embodiment, the second gate driving signal generation module can modulate the first gate driving signal to generate and output the second gate driving signal, thereby realizing the output of two groups of gate driving signals through a group of gate driving circuits, simplifying the structure of the gate driving circuit, reducing the area of the gate driving circuit, and facilitating the realization of a narrow border of the display panel.

[0047] Figure 5 FIG. is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. Refer to Figure 5 , optionally, the first gate driving signal generation module 10 accesses the first clock signal SCK1 and the second clock signal SCK2.

[0048] The second gate driving signal generation module 11 includes an output unit 111 and a control unit 112. The input end of the output unit 111 is connected to the output end OUT1 of the first gate driving signal generation module 10. The control unit 112 is respectively connected to the input end and the control end of the output unit 111. The control unit 112 accesses the first control signal K1, the second control signal K2, and the first clock signal SCK1. The control unit 112 is configured to control the output end of the output unit 111 to output the second gate driving signal in response to the first control signal K1, the second control signal K2, and the first clock signal SCK1.

[0049] The output end of the output unit 111 is the output end OUT2 of the second gate driving signal generation module 11 for outputting the second gate driving signal. The control unit 112 also accesses a first level signal, and the first level signal is a fixed level, which can be a high level or a low level. In the first stage, the control unit 112 responds to the first control signal K1, the second control signal K2, and the first clock signal SCK1 to control whether to transmit the first level signal to the control end of the output unit 111. In the second stage, the control unit 112 responds to the first control signal K1, the second control signal K2, and the first clock signal SCK1 to control the transmission of the first clock signal SCK1 to the control end of the output unit 111. In the first stage and the second stage, the output unit 111 is turned on or off in response to the signal at its control end. Wherein, the output unit 111 being turned on means that the input end and the output end of the output unit 111 are connected, and the output unit 111 being turned off means that the input end and the output end of the output unit 111 are not connected.

[0050] Figure 6 FIG. is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. Refer to Figure 6, Optionally, the control unit 112 includes a storage unit 1121, a first control unit 1122, and a second control unit 1123. The first control unit 1122 is respectively connected to a first clock signal SCK1, a first control signal K1, and a first level signal VGL, and is configured to respond to the first clock signal SCK1 and the first control signal K1 in a first stage to control whether to transmit the first level signal VGL to the control terminal of the output unit 111; the second control unit 1123 is connected to a second control signal K2 and the first clock signal SCK1, and is configured to respond to the second control signal K2 in a second stage to control the transmission of the first clock signal SCK1 to the control terminal of the output unit 111.

[0051] The first end of the storage unit 1121 is connected to the input terminal of the output unit 111, and the second end of the storage unit 1121 is connected to the control terminal of the output unit 111.

[0052] In the first stage, the first control unit 1122 controls whether to transmit the first level signal VGL to the control terminal of the output unit 111, where the first level signal VGL is a signal for controlling the conduction of the output unit 111. And in the first stage, the second control unit 1123 is turned off in response to the second control signal K2, so that the first clock signal SCK1 cannot be transmitted to the control terminal of the output unit 111. In the second stage, the first control unit 1122 is turned off, so that the first level signal VGL cannot be transmitted to the control terminal of the output unit 111, and the second control unit 1123 is turned on to enable the first clock signal SCK1 to be transmitted to the control terminal of the output unit 111. Herein, the conduction of the first control unit 1122 means that the first level signal VGL is connected to the control terminal of the output unit 111, and the turn-off of the first control unit 1122 means that the connection between the first level signal VGL and the control terminal of the output unit 111 is cut off. The conduction of the second control unit 1123 means that the first clock signal SCK1 is connected to the control terminal of the output unit 111, and the turn-off of the second control unit 1123 means that the connection between the first clock signal SCK1 and the control terminal of the output unit 111 is cut off.

[0053] Figure 7 The structure diagram of another gate driving circuit provided by the embodiment of the present invention is referred to Figure 7 , Optionally, the first control unit includes: a first transistor T1 and a second transistor T2. The first pole of the first transistor T1 is connected to the first level signal VGL, the second pole of the first transistor T1 is connected to the first pole of the second transistor T2, the gate of the first transistor T1 is connected to the first control signal K1, the second pole of the second transistor T2 is connected to the control terminal of the output unit 111, and the gate of the second transistor T2 is connected to the first clock signal SCK1.

[0054] The first transistor T1 is turned on or off in response to the first control signal K1 to control whether to transmit the first-level signal VGL to the first pole of the second transistor T2. The second transistor T2 is turned on or off in response to the first clock signal SCK1 to control whether to transmit the first-level signal VGL transmitted to the first pole of the second transistor T2 to the control end of the output unit 111.

[0055] Continue to refer to Figure 7 , optionally, the second control unit includes: a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the first clock signal SCK1, the second pole of the fourth transistor T4 is connected to the second pole of the second transistor T2, and the gate of the fourth transistor T4 is connected to the second control signal K2.

[0056] The fourth transistor T4 is turned on or off in response to the second control signal K2 to control whether to transmit the first clock signal SCK1 to the control end of the output unit 111. And in this embodiment, the second control unit only includes the fourth transistor T4, with a simple structure and easy to implement.

[0057] Continue to refer to Figure 7 , optionally, the storage unit includes a storage capacitor C0, the first end of the storage capacitor C0 is connected to the input end of the output unit 111, and the second end of the storage capacitor C0 is connected to the control end of the output unit 111.

[0058] The storage capacitor C0 is used to couple the voltage of its second end according to the voltage of its first end.

[0059] Continue to refer to Figure 7 , optionally, the output unit includes: a fifth transistor T5, the first pole of the fifth transistor T5 is connected to the output end OUT1 of the first gate driving signal generating module 10, the second pole of the fifth transistor T5 serves as the output end of the output unit 111, and the gate of the fifth transistor T5 is connected to the control unit 112.

[0060] The fifth transistor T5 is turned on or off in response to the signal of its gate. In this embodiment, the fifth transistor T5 is turned on or off in response to the first-level signal VGL or the first clock signal SCK1. After the fifth transistor T5 is turned on, the second gate driving signal Sn_B is the same as the first gate driving signal. After the fifth transistor T5 is turned off, the second gate driving signal Sn_B is different from the first gate driving signal.

[0061] Continue to refer to Figure 7 , optionally, the first gate driving signal generating module 10 includes a shift register circuit, and the shift register circuit is connected to the first clock signal SCK1, the second clock signal SCK2, the first-level signal VGL, and the second-level signal VGH.

[0062] Under the control of the first clock signal SCK1, the second clock signal SCK2, and the first level signal VGL, the shift register circuit alternately outputs the signal provided by the second level signal VGH and the second clock signal SCK2 at the output terminal OUT1 of the first gate driving signal generating module 10.

[0063] Continue to refer to Figure 7 , optionally, the shift register circuit includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2;

[0064] The first pole of the sixth transistor T6 is connected to the input signal SIN, the second pole of the sixth transistor T6 is connected to the first node N1, and the gate of the sixth transistor T6 is connected to the first clock signal SCK1; the first pole of the seventh transistor T7 is connected to the first node N1, the second pole of the seventh transistor T7 is connected to the first pole of the eighth transistor T8, and the gate of the seventh transistor T7 is connected to the second clock signal SCK2; the second pole of the eighth transistor T8 is connected to the second level signal VGH, and the gate of the eighth transistor T8 is connected to the second node N2; the first pole of the ninth transistor T9 is connected to the first clock signal SCK1, the second pole of the ninth transistor T9 is connected to the second node N2, and the gate of the ninth transistor T9 is connected to the first node N1; the first pole of the tenth transistor T10 is connected to the first level signal VGL, the second pole of the tenth transistor T10 is connected to the second node N2, and the gate of the tenth transistor T10 is connected to the first clock signal SCK1; the first pole of the eleventh transistor T11 is connected to the first node N1, the second pole of the eleventh transistor T11 is connected to the third node N3, and the gate of the eleventh transistor T11 is connected to the first level signal VGL; the first pole of the twelfth transistor T12 is connected to the second clock signal SCK2, the second pole of the twelfth transistor T12 is connected to the input terminal of the second gate driving signal generating module, and the gate of the twelfth transistor T12 is connected to the third node N3; the first pole of the thirteenth transistor T13 is connected to the second level signal VGH, the second pole of the thirteenth transistor T13 is connected to the second pole of the twelfth transistor T12, and the gate of the thirteenth transistor T13 is connected to the second node N2; the first end of the first capacitor C1 is connected to the gate of the twelfth transistor T12, the second end of the first capacitor C1 is connected to the second pole of the twelfth transistor T12, the first end of the second capacitor C2 is connected to the gate of the thirteenth transistor T13, and the second end of the second capacitor C2 is connected to the first pole of the thirteenth transistor T13.

[0065] The first capacitor C1 is used to maintain the potential of the gate of the twelfth transistor T12. At the same time, the twelfth transistor T12 and the first capacitor C1 form a bootstrap circuit, enabling the gate of the twelfth transistor T12 to reach an ultra-low potential, preventing the second clock signal SCK2 output from the output terminal OUT1 of the first gate driving signal generation module 10 from being unable to drop to the target value due to the influence of the threshold voltage of the twelfth transistor T12. The second capacitor C2 is used to store the potential of the gate of the thirteenth transistor T13. Arranging the eleventh transistor T11 between the first node N1 and the gate of the twelfth transistor T12 can inhibit the transmission of the ultra-low potential of the gate of the twelfth transistor T12 to the first node N1 due to the bootstrap effect of the first capacitor C1, reducing the probability of breakdown of the gate insulation layer of the sixth transistor T6 and improving the stability of the shift register circuit.

[0066] In this embodiment, on the basis of the above embodiments, it is exemplarily shown that the gate driving circuit includes a total of thirteen transistors, namely the first transistor T1 to the thirteenth transistor T13. Each transistor can be an N-type or a P-type.

[0067] Figure 8 It is a driving timing diagram of a gate driving circuit provided by an embodiment of the present invention in the first stage. Figure 9 It is a driving timing diagram of a gate driving circuit provided by an embodiment of the present invention in the first stage. Figure 8 and Figure 9 is applicable to Figure 7 the circuit structure shown, and Figure 7 the transistors in it are all P-type transistors. Referring to Figure 7 , Figure 8 and Figure 9 , the working process of the gate driving circuit includes a first stage and a second stage. In the first stage, the first control signal K1 is always at a low level and the second control signal K2 is always at a high level. In the second stage, the first control signal K1 is always at a high level and the second control signal K2 is always at a low level. The first stage includes a first sub-stage t01, a second sub-stage t02, and a third sub-stage t03. The second stage includes a fourth sub-stage t04, a fifth sub-stage t05, and a sixth sub-stage t06. Optionally, in the first stage, the first gate driving signal Sn and the second gate driving signal Sn_B are the same; in the second stage, the first gate driving signal Sn and the second gate driving signal Sn_B are different, and the second gate driving signal Sn_B is a fixed-level signal. Combining with the attached Figure 1It can be seen that in the first stage, the first gate driving signal Sn and the second gate driving signal Sn_B are the same, so that the compensation transistor M1 and the data writing transistor M2 are turned on simultaneously, so that the gate voltage of the driving transistor M0 is output to the external chip through the data line Vdata. In the second stage, the first gate driving signal Sn and the second gate driving signal Sn_B are different, and the second gate driving signal Sn_B is a fixed-level signal, so that the compensation transistor M1 is turned off and the data writing transistor M2 is turned on, and then the compensated data voltage is written into the gate of the driving transistor M0, realizing the external compensation of the pixel circuit. The specific working process of the gate driving circuit is as follows:

[0068] In the first sub-stage t01, the input signal SIN and the first clock signal SCK1 are both at low level, the second clock signal SCK2 is at high level, the first control signal K1 is at low level, and the second control signal K2 is at high level. The sixth transistor T6 and the tenth transistor T10 are turned on in response to the first clock signal SCK1. The input signal SIN is transmitted to the first node N1 through the turned-on sixth transistor T6, and the first node N1 becomes low level. The first level signal VGL is transmitted to the second node N2 through the turned-on tenth transistor T10, and the second node N2 is at low level. The ninth transistor T9 is turned on in response to the low level of the first node N1. The first clock signal SCK1 is transmitted to the second node N2 through the turned-on ninth transistor T9, and the second node N2 remains at low level. The eighth transistor T8 is turned on in response to the low level of the second node N2, and the seventh transistor T7 is turned off in response to the second clock signal SCK2. The first level signal VGH cannot be transmitted to the first node N1, avoiding the influence on the low level of the first node N1. The thirteenth transistor T13 is turned on in response to the low level of the second node N2. The second level signal VGH is transmitted to the output terminal OUT1 of the first gate driving signal generation module 10 through the turned-on thirteenth transistor T13. The twelfth transistor T12 is turned on in response to the low level of the third node N3. The second clock signal SCK2 is transmitted to the output terminal OUT1 of the first gate driving signal generation module 10 through the turned-on twelfth transistor T12. In the first sub-stage t01, the first gate driving signal Sn is at high level. The first transistor T1 is turned on in response to the first control signal K1, the second transistor T2 is turned on in response to the first clock signal SCK1, the fourth transistor T4 is turned off in response to the second control signal K2, and the first level signal VGL is transmitted to the gate of the fifth transistor T5 through the turned-on first transistor T1 and the second transistor T2. The fifth transistor T5 is turned on in response to the low level of its own gate, that is, the second gate driving signal Sn_B is the same as the first gate driving signal Sn, both are at high level.

[0069] In the second sub-stage t02, the input signal SIN and the first clock signal SCK1 are both at high level, the second clock signal SCK2 is at low level, the first control signal K1 is at low level, and the second control signal K2 is at high level. The sixth transistor T6 and the tenth transistor T10 are both turned off in response to the first clock signal SCK1, the first node N1 maintains the low level of the previous stage, and the ninth transistor T9 is controlled to conduct. The first clock signal SCK1 is transmitted to the second node N2 through the conducting ninth transistor T9, causing the potential of the second node N2 to become high level. The eighth transistor T8 and the thirteenth transistor T13 are both turned off in response to the high level of the second node N2, and the seventh transistor T7 is turned on in response to the second clock signal SCK2. The second level signal VGH cannot be transmitted to the first node N1 through the eighth transistor T8 and the seventh transistor T7, avoiding the influence on the low level of the first node N1. The twelfth transistor T12 is turned on in response to the low level of the third node N3, and the second clock signal SCK2 is transmitted to the output terminal OUT1 of the first gate drive signal generation module 10 through the conducting twelfth transistor T12. In the second sub-stage t01, the first gate drive signal Sn is at low level. The first transistor T1 is turned on in response to the first control signal K1, the second transistor T2 is turned off in response to the first clock signal SCK1, and the fourth transistor T4 is turned off in response to the second control signal K2. The potential of the output terminal OUT1 of the first gate drive signal generation module 10 changes from the high level in the first sub-stage t01 to the low level in the second sub-stage t02, causing the voltage at the first end of the storage capacitor C0 to decrease. Due to the coupling effect of the storage capacitor C0, the voltage at the second end of the storage capacitor C0 also decreases. Therefore, the gate of the fifth transistor T5 is at low level, controlling the fifth transistor T5 to continue to conduct. The second gate drive signal Sn_B is the same as the first gate drive signal Sn and is at low level.

[0070] In the third sub-phase t03, the input signal SIN and the second clock signal SCK2 are both at high level, the first clock signal SCK1 is at low level, the first control signal K1 is at low level, and the second control signal K2 is at high level. The sixth transistor T6 and the tenth transistor T10 are both turned on in response to the first clock signal SCK1. The input signal SIN is transmitted to the first node N1 through the turned-on sixth transistor T6, and the potential of the first node N1 becomes high level. The first level signal VGL is transmitted to the second node N2 through the turned-on tenth transistor T10, and the potential of the second node N2 becomes low level. The ninth transistor T9 is turned off in response to the high level of the first node N1. The eighth transistor T8 is turned on in response to the low level of the second node N2, and the seventh transistor T7 is turned off in response to the second clock signal SCK2. The twelfth transistor T12 is turned off in response to the high level of the third node N3, and the thirteenth transistor T13 is turned on in response to the low level of the second node N2. The second level signal VGH is transmitted to the output terminal OUT1 of the first gate drive signal generation module 10 through the turned-on thirteenth transistor T13. In the second sub-phase t01, the first gate drive signal Sn is at high level. The first transistor T1 is turned on in response to the first control signal K1, the second transistor T2 is turned on in response to the first clock signal SCK1, and the fourth transistor T4 is turned off in response to the second control signal K2. The first level signal VGL is transmitted to the gate of the fifth transistor T5 through the turned-on first transistor T1 and the second transistor T2, causing the fifth transistor T5 to be turned on. The second gate drive signal Sn_B is the same as the first gate drive signal Sn and is at high level.

[0071] In the fourth sub-phase t04, the input signal SIN and the first clock signal SCK1 are both at low level, the second clock signal SCK2 is at high level, the first control signal K1 is at high level, and the second control signal K2 is at low level. The operation process of the first gate drive signal generation module 10 is the same as that in the first sub-phase t01, and the first gate drive signal Sn is at high level. The first transistor T1 is turned off in response to the first control signal K1, the second transistor T2 is turned on in response to the first clock signal SCK1, the fourth transistor T4 is turned on in response to the second control signal K2, and the first clock signal SCK1 is transmitted to the gate of the fifth transistor T5 through the turned-on fourth transistor T4. The fifth transistor T5 is turned on in response to the low level of the gate. Therefore, the second gate drive signal Sn_B is the same as the first gate drive signal and is both at high level.

[0072] In the fifth sub-stage t05, the input signal SIN and the first clock signal SCK1 are both at a high level, and the second clock signal SCK2 is at a low level. The first control signal K1 is at a high level, and the second control signal K2 is at a low level. The working process of the first gate drive signal generation module 10 is the same as that in the second sub-stage t02, and the first gate drive signal Sn is at a low level. The first transistor T1 turns off in response to the first control signal K1, the second transistor T2 turns off in response to the first clock signal SCK1, the fourth transistor T4 turns on in response to the second control signal K2, and the fifth transistor T5 turns off in response to the high level of its own gate. When the fifth transistor T5 outputs the second gate drive signal, the second pole of the fifth transistor T5 is also connected to a capacitor, and the capacitor can maintain the potential of the second pole. During the off period of the fifth transistor T5, due to the storage effect of the capacitor, the second pole of the fifth transistor T5 still outputs the signal of the previous stage, i.e., the fourth sub-stage t04. Therefore, in the fifth sub-stage t05, the second gate drive signal Sn_B is at a high level.

[0073] In the sixth sub-stage t06, the input signal SIN and the second clock signal SCK2 are both at a high level, and the first clock signal SCK1 is at a low level. The first control signal K1 is at a high level, and the second control signal K2 is at a low level. The working process of the first gate drive signal generation module 10 is the same as that in the third sub-stage t03, and the first gate drive signal Sn is at a high level. The first transistor T1 turns off in response to the first control signal K1, the second transistor T2 turns on in response to the first clock signal SCK1, and the fourth transistor T4 turns on in response to the second control signal K2. The first clock signal SCK1 is transmitted to the gate of the fifth transistor T5 through the turned-on first transistor T1 and second transistor T2, causing the fifth transistor T5 to turn on. The second gate drive signal Sn_B is the same as the first gate drive signal Sn and is at a high level.

[0074] Figure 10 The structure diagram of another gate drive circuit provided by the embodiment of the present invention is shown in reference to Figure 10 , optionally, the first control unit includes: a first transistor T1, a second transistor T2, and a third transistor T3. The first pole of the first transistor T1 is connected to the first level signal VGL. The second pole of the first transistor T1 is connected to the first pole of the second transistor T2. The gate of the first transistor T1 is connected to the first control signal K1. The second pole of the second transistor T2 is connected to the first pole of the third transistor T3. The gate of the second transistor T2 is connected to the first clock signal SCK1. The second pole of the third transistor T3 is connected to the control end of the output unit 111. The gate of the third transistor T3 is connected to the first level signal VGL.

[0075] The structures of other units or modules of the gate drive circuit are the same as those in Figure 7 and will not be described in detail here. Figure 10The same as Figure 7 the working process of the circuit shown, Figure 10 The difference between it and Figure 7 is that a third transistor T3 is added between the gate of the fifth transistor T5 and the second pole of the second transistor T2. When the gate of the fifth transistor T5 is at a low level, for example, in the second sub-stage, if there is no third transistor T3, the gate of the fifth transistor T5 is directly connected to the second pole of the second transistor T2 and the second pole of the fourth transistor T4. The voltage of the second pole of the second transistor T2 is relatively low, while the gate voltage of the second transistor T2 is relatively high, so the gate-drain voltage difference of the second transistor T2 is relatively large, which is likely to cause damage to the second transistor T2. The same is true for the fifth transistor T5. After adding the third transistor T3, the gate of the fifth transistor T5 is isolated from the second transistor T2 and the fifth transistor T5, avoiding the influence of the low potential of the gate of the fifth transistor T5 on the second transistor T2 and the fifth transistor T5, which is beneficial to extending the service life of the second transistor T2 and the fifth transistor T5.

[0076] The embodiment of the present invention further provides a display panel, and the display panel includes the gate driving circuit in any one of the above embodiments. The beneficial effects of the display panel are the same as those of the gate driving circuit, and will not be elaborated herein.

[0077] Figure 11 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 7 and Figure 11, Optionally, the gate driving circuit includes a first clock signal terminal L1, a second clock signal terminal L2, an input signal terminal IN, a first potential signal terminal VL, a second potential signal terminal VH, a first control signal terminal M1, a second control signal terminal M2, a first output terminal 0U1, and a second output terminal OU2. The first clock signal terminal L1 is used to input a first clock signal SCK1, the second clock signal terminal L2 is used to input a second clock signal SCK2, the first control signal terminal M1 is used to input a first control signal K1, the second control signal terminal M2 is used to input a second control signal K2, the first potential signal terminal VL is used to input a first level signal VGL, and the second potential signal terminal VH is used to input a second level signal VGH. The first output terminal 0U1 is used to output a first gate driving signal, the second output terminal OU2 is used to output a second gate driving signal, and both the first output terminal 0U1 and the second output terminal OU2 are connected to the corresponding pixel circuit 02. The input signal terminal IN of the first-stage gate driving circuit 011 is connected to the input signal SIN, the input signal terminal IN of the second-stage gate driving circuit 012 is connected to the first output terminal OU1 of the first-stage gate driving circuit 011, the input signal terminal IN of the third-stage gate driving circuit 013 is connected to the first output terminal OU1 of the second-stage gate driving circuit 012, and so on. The display panel 01 realizes the progressive writing of two gate driving signals through the first gate driving signal and the second gate driving signal output by each stage of the gate driving circuit.

[0078] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A gate driving circuit, characterized in that, Comprising: A first gate driving signal generation module, configured to generate and output a first gate driving signal; A second gate driving signal generation module, an input end of the second gate driving signal generation module being connected to an output end of the first gate driving signal generation module; the second gate driving signal generation module being configured to respond to a first control signal and a second control signal, and modulate the first gate driving signal and then output a second gate driving signal; Wherein, the first control signal and the second control signal are complementary high and low level signals; the working process of the gate driving circuit includes a first stage and a second stage; In the first stage, the first gate driving signal and the second gate driving signal are the same; In the second stage, the first gate driving signal and the second gate driving signal are different, and the second gate driving signal is a fixed level signal; The first gate driving signal generation module is connected to a first clock signal and a second clock signal; The second gate driving signal generation module includes an output unit and a control unit, an input end of the output unit being connected to an output end of the first gate driving signal generation module, the control unit being respectively connected to an input end and a control end of the output unit, the control unit being respectively connected to the first control signal, the second control signal and the first clock signal, and the control unit being configured to control an output end of the output unit to output the second gate driving signal in response to the first control signal, the second control signal and the first clock signal.

2. The circuit according to claim 1, wherein The control unit includes a storage unit, a first control unit and a second control unit, the first control unit being respectively connected to the first clock signal, the first control signal and a first level signal, and being configured to control whether to transmit the first level signal to a control end of the output unit in response to the first clock signal and the first control signal in the first stage; The second control unit is connected to the second control signal and the first clock signal, and is configured to control to transmit the first clock signal to the control end of the output unit in response to the second control signal in the second stage; A first end of the storage unit is connected to an input end of the output unit, and a second end of the storage unit is connected to a control end of the output unit.

3. The circuit according to claim 2, characterized in that The first control unit includes: a first transistor and a second transistor, a first pole of the first transistor being connected to the first level signal, a second pole of the first transistor being connected to a first pole of the second transistor, a gate of the first transistor being connected to the first control signal, a second pole of the second transistor being connected to the control end of the output unit, and a gate of the second transistor being connected to the first clock signal; Alternatively, the first control unit includes: a first transistor, a second transistor, and a third transistor. A first pole of the first transistor is connected to a first-level signal, a second pole of the first transistor is connected to a first pole of the second transistor, a gate of the first transistor is connected to the first control signal, a second pole of the second transistor is connected to a first pole of the third transistor, a second pole of the second transistor is connected to the first clock signal, a second pole of the third transistor is connected to a control terminal of the output unit, and a gate of the third transistor is connected to the first-level signal.

4. The circuit according to claim 3, characterized in that, The second control unit includes: a fourth transistor. A first pole of the fourth transistor is connected to the first clock signal, a second pole of the fourth transistor is connected to a second pole of the second transistor, and a gate of the fourth transistor is connected to the second control signal.

5. The circuit according to claim 2, wherein The storage unit includes a storage capacitor. A first end of the storage capacitor is connected to an input terminal of the output unit, and a second end of the storage capacitor is connected to a control terminal of the output unit.

6. The circuit according to any one of claims 1-5, characterized in that The output unit includes: a fifth transistor. A first pole of the fifth transistor is connected to an output terminal of the first gate driving signal generation module, a second pole of the fifth transistor serves as an output terminal of the output unit, and a gate of the fifth transistor is connected to the control unit.

7. The circuit according to claim 1, wherein The first gate driving signal generation module includes a shift register circuit, and the shift register circuit is connected to a first clock signal, a second clock signal, a first-level signal, and a second-level signal.

8. The circuit according to claim 7, wherein The shift register circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first capacitor, and a second capacitor; The first pole of the sixth transistor is connected to an input signal, the second pole of the sixth transistor is connected to the first node, and the gate of the sixth transistor is connected to the first clock signal; the first pole of the seventh transistor is connected to the first node, the second pole of the seventh transistor is connected to the first pole of the eighth transistor, and the gate of the seventh transistor is connected to the second clock signal; the second pole of the eighth transistor is connected to the second level signal, and the gate of the eighth transistor is connected to the second node; the first pole of the ninth transistor is connected to the first clock signal, the second pole of the ninth transistor is connected to the second node, and the gate of the ninth transistor is connected to the first node; the first pole of the tenth transistor is connected to the first level signal, the second pole of the tenth transistor is connected to the second node, and the gate of the tenth transistor is connected to the first clock signal; the first pole of the eleventh transistor is connected to the first node, the second pole of the eleventh transistor is connected to the third node, and the gate of the eleventh transistor is connected to the first level signal; the first pole of the twelfth transistor is connected to the second clock signal, the second pole of the twelfth transistor is connected to the input end of the second gate driving signal generation module, and the gate of the twelfth transistor is connected to the third node; the first pole of the thirteenth transistor is connected to the second level signal, the second pole of the thirteenth transistor is connected to the second pole of the twelfth transistor, and the gate of the thirteenth transistor is connected to the second node; the first end of the first capacitor is connected to the gate of the twelfth transistor, the second end of the first capacitor is connected to the second pole of the twelfth transistor, the first end of the second capacitor is connected to the gate of the thirteenth transistor, and the second end of the second capacitor is connected to the first pole of the thirteenth transistor.

9. A display panel, characterized in that, Comprising: The gate driving circuit according to any one of claims 1-8.

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