Memory devices and methods supporting thin-film transistor stack-up selection

Abstract

This application relates to thin-film transistor stack selection in a memory device. The memory device may include memory arrays disposed in a stack of layers formed over a substrate, and stack selection components distributed between the layers to utilize a shared substrate-based circuitry. For example, each memory array in the stack may include a set of digital lines corresponding to the stack, and a stack selection circuitry operable to couple the set of digital lines to a column decoder shared across multiple stacks. To access a memory cell in a selected memory array on one stack, the stack selection circuitry corresponding to that memory array can be activated, while the stack selection circuitry corresponding to a non-selected memory array on another stack can be deactivated. The stack selection circuitry, such as transistors, may utilize thin-film fabrication techniques, such as various techniques for forming vertical transistors.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 327,042, filed May 21, 2021, entitled “Thin Film Transistor Deck Selection in Memory Device,” which is assigned to the assignee of this invention and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to the selection of thin-film transistor stacks in memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory (3DXpoint), NOR and NAND memory devices, and other devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power supply. Even without an external power supply, non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a sensing component operable for sensing memory cells of a memory die; and a column decoder of the memory die operable to be coupled to the sensing component. The device may further include a first memory array associated with a first layer on the substrate of the memory die, the first memory array including a first subgroup of the memory cells and a plurality of first digital lines, each first digital line operable to be coupled to the column decoder via a corresponding transistor of the first layer; a second memory array associated with the first layer, the second memory array including a second subgroup of the memory cells and a plurality of second digital lines, each second digital line operable to be coupled to the column decoder via a corresponding second transistor of the first layer; a third memory array associated with a second layer on the substrate of the memory die, the third memory array including a third subgroup of the memory cells and a plurality of third digital lines, each third digital line operable to be coupled to the column decoder via a corresponding third transistor of the first layer; and a fourth memory array associated with the second layer, the fourth memory array including a fourth subgroup of the memory cells and a plurality of fourth digital lines, each fourth digital line operable to be coupled to the column decoder via a corresponding fourth transistor of the first layer.

[0007] This invention describes a method. The method may include forming a sensing component operable for sensing memory cells of a memory die; and forming a column decoder of the memory die operable to be coupled to the sensing component. The method may further include forming a first memory array associated with a first layer on a substrate of the memory die, the first memory array including a first subgroup of memory cells and a plurality of first digital lines, each first digital line operable to be coupled to the column decoder via a corresponding first transistor of the first layer; forming a second memory array associated with the first layer, the second memory array including a second subgroup of memory cells and a plurality of second digital lines, each second digital line operable to be coupled to the column decoder via a corresponding second transistor of the first layer; forming a third memory array associated with a second layer on the substrate of the memory die, the third memory array including a third subgroup of memory cells and a plurality of third digital lines, each third digital line operable to be coupled to the column decoder via a corresponding third transistor of the first layer; and forming a fourth memory array associated with the second layer, the fourth memory array including a fourth subgroup of memory cells and a plurality of fourth digital lines, each fourth digital line operable to be coupled to the column decoder via a corresponding fourth transistor of the first layer.

[0008] This invention describes a method. The method may include identifying memory cell rows of a first memory array of a memory die for access operations, the memory die comprising: a first memory array in a first layer located on a substrate of the memory die, a second memory array of the memory die in the first layer, a third memory array of the memory die in a second layer located on the substrate, and a fourth memory array of the memory die in the second layer. The method may further include coupling the memory cell rows to a column decoder of the memory die based on the identification. Coupling the memory cell rows to the column decoder may include coupling the memory cell rows to a plurality of digital lines of the first memory array at least partially based on activating a plurality of first transistors in the first layer, and coupling the plurality of digital lines of the first memory array to the row decoder at least partially based on activating a plurality of second transistors in the second layer. Attached Figure Description

[0009] Figure 1 This describes an example of a memory device that supports thin-film transistor stack-up selection, based on examples disclosed herein.

[0010] Figure 2 This describes examples of transistor structures selected based on thin-film transistor stacks in supporting memory devices, as disclosed herein.

[0011] Figure 3 Examples of circuits supporting thin-film transistor stack-up selection in memory devices, as disclosed herein.

[0012] Figures 4 to 7 This describes an example layout of a memory die selected based on the thin-film transistor stack in a supporting memory device, as disclosed herein.

[0013] Figure 8 and 9 A flowchart illustrating a method for selecting a thin-film transistor stack in a supporting memory device, based on examples disclosed herein. Detailed Implementation

[0014] Memory devices may include various arrangements of memory arrays formed above a substrate, wherein memory cells of the memory array may be organized or addressed according to rows and columns. In some instances, circuitry supporting access to or operation of the memory array may be located below the memory array, which may refer to a location at least partially located between the memory array and the substrate. For example, among other types of decoding circuitry, row decoders or column decoders may be located below the memory array but above the substrate, and in some instances, may include transistors (e.g., substrate-based transistors, transistors having channels formed from doped crystalline silicon or other semiconductors) formed at least partially through a portion of the doped substrate. As memory devices scale with a larger number of layers or stacks above the substrate, the substrate area for such decoders or other supporting circuitry can increase, which can lead to various scaling limitations (e.g., a finite area of ​​the substrate to support an ever-increasing number of stacks, and consequently, an ever-increasing number and area of ​​such decoders or other supporting circuitry).

[0015] According to examples disclosed herein, a memory device may include memory arrays disposed in a stack of layers formed over a substrate, and stack selection components (e.g., stack selection transistors, stack decoders, or addressing circuitry) may be distributed between layers for utilizing a shared substrate-based circuitry. For example, each memory array in the stack may include a set of digital lines corresponding to the stack, and stack selection circuitry, such as stack selection transistors or other switching circuitry (e.g., corresponding to one stack, another stack), operable to couple a set of digital lines having a column decoder, which may be shared (e.g., coupled thereto) among multiple stacks. To access a memory cell of a selected memory array on one stack, the stack selection circuitry corresponding to the selected memory array may be activated (e.g., coupling the digital lines of the selected memory array to a shared column decoder), while the stack selection circuitry corresponding to an unselected memory array on another stack may be deactivated (e.g., isolating the digital lines of the unselected memory array from the shared column decoder). For example, a stacked selection circuit system for stacked selection transistors can utilize thin-film fabrication techniques, such as various techniques for forming vertical transistors (e.g., transistors with vertical channels, transistors with channels at least partially oriented along the thickness direction of the memory die, transistors with polysilicon channels) on a substrate. Implementing a stacked selection circuit system at various stacks of such memory dies can alleviate or mitigate the area utilization challenges of substrate layers, for example, by moving certain aspects of decoding or addressing to a stack or layer above the substrate, which can improve the scaling of the memory device by supporting a larger number of stacks for a given substrate-based circuitry region.

[0016] The features of this disclosure were originally described in reference to Figures 1 to 3The memory device and related circuitry are described in the context of the description. (See references.) Figures 4 to 7 The features of this disclosure are described in the context of memory die layout. References Figure 8 and 9 These and other features of this disclosure are further illustrated and described through flowcharts relating to the formation and operation of memory devices that support thin-film transistor stacking selection.

[0017] Figure 1 This describes an example of a memory device 100 that supports thin-film transistor stack-up selection, as disclosed herein. The memory device 100 may also be referred to as a memory die or electronic memory device. The memory device 100 may include memory cells 105 that are programmable to store different logic states. In some cases, memory cells 105 may be programmable to store two logic states, represented as logic 0 and logic 1. In some cases, memory cells 105 may be programmable to store more than two logic states (e.g., as a multi-level unit). The group of memory cells 105 may be part of a memory array 110 of the memory device 100, wherein, in some instances, the memory array 110 may refer to a contiguous block of data (e.g., a contiguous set of elements of a semiconductor chip) of memory cells 105.

[0018] In some instances, memory cell 105 may store charges representing programmable logic states (e.g., storing charges in a capacitor, a capacitive memory element, or a capacitive storage element). In one instance, charged and uncharged capacitors may each represent two logic states. In another instance, positively charged (e.g., first polarity, positive polarity) and negatively charged (e.g., second polarity, negative polarity) capacitors may each represent two logic states. DRAM or FeRAM architectures may use such designs, and the capacitors used may contain dielectric materials with linear or quasi-polarized properties as insulators. In some instances, different charge levels of the capacitors may represent different logic states, and in some instances, the logic states may support more than two logic states in a given memory cell 105. In some instances, such as FeRAM architectures, memory cell 105 may include ferroelectric capacitors having ferroelectric material as an insulating (e.g., non-conductive) layer between the terminals of the capacitor. Different polarization levels or polarities of the ferroelectric capacitors may represent different logic states (e.g., supporting two or more logic states in a given memory cell 105).

[0019] In some instances, memory cell 105 may include or otherwise be associated with a configurable material, which may be referred to as a material memory element, material storage element, material portion, or others. The configurable material may have one or more variable and configurable properties or characteristics (e.g., material states) that can represent different logical states. For example, the configurable material may take on different forms, different atomic configurations, different crystallinity, different atomic distributions, or otherwise maintain different properties that can be used to represent one logical state or another. In some instances, such properties may be associated with different resistances, different threshold characteristics, or other properties that are detectable or distinguishable during read operations to identify logical states written to or stored by the configurable material.

[0020] In some conditions, the configurable material of memory cell 105 can be associated with a threshold voltage. For example, when a voltage greater than the threshold voltage is applied across memory cell 105, current may flow through the configurable material, and when a voltage less than the threshold voltage is applied across memory cell 105, current may not flow through the configurable material, or may flow through the configurable material at a rate below a certain level (e.g., based on leakage rate). Therefore, the voltage applied to memory cell 105 can result in different current flows, or different sense resistances, or changes in resistance (e.g., threshold or switching events), depending on whether a portion of the configurable material of memory cell 105 is written to in one logic state or another. Therefore, the logic state written to or stored in memory cell 105 can be determined using the current magnitude or other characteristics (e.g., threshold behavior, resistance breakdown behavior, bounce behavior) associated with the current generated by applying a read voltage to memory cell 105.

[0021] In an example of memory device 100, each row of memory cells 105 may be connected to one or more word lines 120 (e.g., WL1 to WL). M The memory cells 105 are coupled to one or more digital lines 130 (e.g., DL1 to DL2). N Coupling. Each of the word line 120 and the digital line 130 may be an instance of an access line of the memory device 100. Generally, a memory cell 105 may be located at the intersection of the word line 120 and the digital line 130 (e.g., coupled thereto, coupled between thereto). This intersection may be referred to as the address of the memory cell 105. The target or selected memory cell 105 may be the memory cell 105 located at the intersection of the energized or otherwise selected word line 120 and the energized or otherwise selected digital line 130.

[0022] In some architectures, the memory components of memory cell 105 may be electrically isolated (e.g., selectively isolated) from digital lines 130 via a cell select component. In some instances, this may be referred to as a switching component or selector device of memory cell 105 or otherwise associated with the memory cell. Word line 120 may be coupled to the cell select component (e.g., via a control node or terminal of the cell select component) and may control the cell select component of memory cell 105. For example, the cell select component may be a transistor and word line 120 may be coupled to the gate of the transistor (e.g., where the gate node of the transistor may be the control node of the transistor). Activating word line 120 may result in an electrical connection or closure between the respective logic memory components of one or more memory cells 105 and one or more corresponding digital lines 130. This may be referred to as activating one or more memory cells 105 or coupling one or more memory cells 105 to the corresponding one or more digital lines 130. Digital lines 130 may then be accessed to read from or write to the respective memory cell 105.

[0023] In some instances, memory cell 105 may also be associated with one or more board lines 140 (e.g., PL1 to PL2). N Coupling. In some instances, each of the board lines 140 may be independently addressable (e.g., supporting individual selection or biasing). In some instances, the plurality of board lines 140 may represent a shared board or other shared node (e.g., a shared board node for each memory cell 105 in memory array 110), or otherwise be functionally equivalent to a shared board or other shared node. When memory cell 105 uses capacitors to store logic states, digital lines 130 provide access to a first terminal or first plate of the capacitor, and board lines 140 provide access to a second terminal or second plate of the capacitor. Although the plurality of board lines 140 of memory device 100 are shown as generally parallel to the plurality of digital lines 130, in other instances, the plurality of board lines 140 may be generally parallel to the plurality of word lines 120, or in any other configuration (e.g., shared planar conductors, shared board layers, shared board nodes).

[0024] Access operations such as read, write, rewrite, and refresh can be performed on memory cell 105 by activating or selecting word lines 120, digital lines 130, or board lines 140 coupled to memory cell 105. This may involve applying voltage, charge, or current to the respective access lines. When memory cell 105 is selected (e.g., in a read operation), the resulting signal can be used to determine the logic state stored by memory cell 105. For example, memory cell 105 with capacitive memory elements storing logic states can be selected, and the resulting charge flow or voltage across the access lines can be detected to determine the programmed logic state stored by memory cell 105.

[0025] Row component 125 (e.g., row decoder), column component 135 (e.g., column decoder), or board component 145 (e.g., board decoder), or combinations thereof, can be used to control access to memory cell 105. For example, row component 125 may receive a row address from memory controller 170 and activate the corresponding word line 120 based on the received row address. Similarly, column component 135 may receive a column address from memory controller 170 and activate the corresponding digital line 130. In some instances, such access operations may be accompanied by board component 145 biasing one or more of the board lines 140 (e.g., biasing one of the board lines 140, biasing some or all of the board lines 140, biasing a shared board).

[0026] In some instances, the memory controller 170 may use one or more components (e.g., row component 125, column component 135, board component 145, sensing component 150) to control the operation of the memory cell 105 (e.g., read operation, write operation, rewrite operation, refresh operation). In some cases, one or more of the row component 125, column component 135, board component 145, and sensing component 150 may be co-located with or otherwise included in the memory controller 170. The memory controller 170 may generate row and column address signals to activate the desired word line 120 and digital line 130. The memory controller 170 may also generate or control various voltages or currents used during the operation of the memory device 100.

[0027] When memory cell 105 is accessed (e.g., in cooperation with memory controller 170) to determine a logical state written to or stored in memory 105, memory cell 105 may be read (e.g., sensed) by sensing component 150. For example, sensing component 150 may be configured to evaluate current or charge transfer through or from memory cell 105 in response to a read operation, or to evaluate the voltage generated by coupling memory cell 105 to sensing component 150. Sensing component 150 may provide an output signal indicating the logical state read from memory cell 105 to one or more components (e.g., nematic decoder 135, input / output component 160, memory controller 170).

[0028] Sensing component 150 may include various switching components, selection components, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify differences in sensed signals (e.g., differences between read voltage and reference voltage, differences between read current and reference current, differences between read charge and reference charge), which in some instances may be referred to as latching. In some instances, sensing component 150 may include a set of repeating components (e.g., circuit elements) for each of a set or sub-set of digital lines 130 connected to sensing component 150. For example, sensing component 150 may include separate sensing circuitry (e.g., a single or duplicated sense amplifier, a single or duplicated signal generation component) for each of the set or sub-set of digital lines 130 coupled to sensing component 150, such as individually detecting the logic state of a corresponding memory cell 105 coupled to a corresponding one of the set of digital lines 130.

[0029] Memory cell 105 can be set or written by activating the associated word line 120, digital line 130, or board line 140 (e.g., via memory controller 170). In other words, logical state can be stored in memory cell 105. Row component 125, column component 135, or board component 145 can, for example, accept data to be written to memory cell 105 via input / output component 160. In some instances, the write operation can be performed at least partially by sensing component 150, or the write operation can be configured to bypass sensing component 150.

[0030] In the case of capacitive memory elements, memory cell 105 can be written by applying a voltage to or across a capacitor, and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write to memory cell 105, a floating capacitor) to store the charge associated with the desired logic state in the capacitor. In the case of ferroelectric memory, the ferroelectric memory elements (e.g., ferroelectric capacitors) of memory cell 105 can be written by applying a voltage of magnitude sufficient to polarize the ferroelectric memory elements with the polarization associated with the desired logic state (e.g., applying a saturation voltage), and the ferroelectric memory elements can be isolated (e.g., floating), or a zero net voltage or bias can be applied across the ferroelectric memory elements (e.g., grounding, virtual grounding, or voltage equalization across the ferroelectric memory elements). In the case of a material memory architecture, memory cell 105 can be written by applying current, voltage, or other heating or bias to the material memory elements to configure the material according to the corresponding logic state.

[0031] In some instances, memory device 100 may include a plurality of memory arrays 110 arranged in a stacked or layered manner relative to a substrate of memory device 100 (e.g., a semiconductor substrate, a crystalline silicon substrate, a crystalline semiconductor substrate, or a portion of a semiconductor wafer). Circuitry supporting access to or operation of the memory arrays 110 may be located below the memory arrays 110, referring to a location at least partially between the memory arrays 110 and the substrate. For example, one or more row components 125, one or more column components 135, one or more board components 145, one or more sensing components 150, or one or more input / output components 160, or any combination thereof, may be located below the memory arrays 110 but above the substrate, and in some instances, may include transistors (e.g., substrate-based transistors, transistors having channels formed by doped crystalline silicon or other semiconductors) formed at least partially through a portion of the doped substrate. When the memory device 100 is scaled with a larger number of memory arrays 110 stacks or layers, the substrate area used to support the circuitry can increase, which can lead to scaling limitations (e.g., the limited area of ​​the substrate to support the circuitry for accessing an ever-growing number of memory arrays 110 stacks or layers, and consequently, the ever-growing number and area of ​​such decoders or other supporting circuitry), and other challenges.

[0032] According to examples disclosed herein, memory device 100 may include memory arrays 110 disposed in a stack of layers formed above a substrate, and stack selection components (e.g., stack selection transistors, stack decoding, or addressing circuitry) distributed between the stacks to utilize a shared substrate-based circuitry. For example, each memory array 110 in the stack may include a set of digital lines 130 corresponding to the stack, and stack selection circuitry, such as transistors (e.g., corresponding to another stack), operable to couple a set of digital lines 130 having a column decoder that may be shared (e.g., coupled thereto, for access or multiplexing) among multiple stacks. To access a memory cell 105 of a selected memory array 110 on one stack, the stacked selection circuitry corresponding to the selected memory array 110 (e.g., transistors or other switching components) can be activated (e.g., coupling the digital line 130 of the selected memory array to a common column decoder), and the stacked selection circuitry corresponding to an unselected memory array 110 on another stack can be deactivated (e.g., isolating the digital line 130 of the unselected memory array from the common column decoder). In some instances, the stacked selection transistor may comprise a thin-film transistor utilizing thin-film fabrication techniques, such as various techniques for forming vertical transistors (e.g., transistors with vertical channels, transistors with channels at least partially oriented along the thickness direction relative to the substrate, transistors with channel portions at least partially formed of polysilicon). Implementing stack-up selection circuitry at various stacks of such memory device 100 can mitigate or reduce the area utilization challenges of substrate layers, such as moving certain aspects of decoding or addressing to stacks or layers above the substrate. This can improve the scaling of the memory device by supporting a larger number of stacks for a given substrate-based circuitry region.

[0033] Figure 2 This document describes an example of a transistor structure 200 selected to support a thin-film transistor stack in a memory device, based on examples disclosed herein. The transistor structure 200 illustrates an example of a transistor formed at least partially from a portion of a substrate 220 (e.g., a doped portion 240 of the substrate 220), and may illustrate an arrangement of features of transistors configured as a planar transistor arrangement. The substrate 220 may be part of a semiconductor chip, such as a silicon chip of a memory die (e.g., crystalline silicon, monocrystalline silicon). For illustrative purposes, aspects of the transistor structure 200 may be described with reference to the x, y, and z directions (e.g., the height direction) of coordinate system 210. In some examples, the z direction may describe a direction perpendicular to a surface of the substrate 220 (e.g., a surface in the xy plane, on which other materials may be deposited), and each of the structures, as illustrated by its corresponding cross-section in the xz plane, may extend a distance (e.g., a length) along the y direction.

[0034] Transistor structure 200 illustrates an example of a transistor channel electrically coupled between terminals 270-a-1 and 270-a-2, which may include one or more doped portions 240 of substrate 220. In various examples, one of terminals 270-a-1 or 270-a-2 may be referred to as the source terminal, and the other of terminals 270-a-1 or 270-a-2 may be referred to as the drain terminal, wherein such designation or nomenclature may be based on the configuration of the circuit including transistor structure 200 or relative bias. The channel or channel portion of the transistor may include or refer to one or more portions of the transistor structure operable to turn on or off the conductive path between the source and drain (e.g., between terminals 270-a-1 and 270-a-2) at least partially based on a voltage of the gate (e.g., gate terminal, gate portion 250) (e.g., modulating conductivity, forming a channel, turning on the channel, turning off the channel). In other words, the channel portion of the transistor structure can be configured to be activated, deactivated, conductive, or non-conductive at least in part based on the voltage of, for example, the gate portion of the gate portion 250. In some instances of the transistor structure 200 (e.g., a planar transistor arrangement), the channel portion formed by one or more doped portions 240 of the substrate 220 can support conductive paths in a generally horizontal or in-plane direction (e.g., along the x-direction, in the xy plane, within the surface of the substrate 220, or parallel to the surface of the substrate).

[0035] In some instances, the gate portion 250 may be physically separated from the channel portion (e.g., separated from the substrate 220, and separated from one or more of the doped portions 240) via a gate insulating portion 260 (e.g., a gate dielectric). Each of the terminals 270 may be contacted with or otherwise coupled to a corresponding doped portion 240-a (e.g., electrical coupling, physical coupling), and each of the terminals 270 and the gate portion 250 may be formed of a conductive material, such as a metal or metal alloy, or a polycrystalline semiconductor (e.g., polycrystalline silicon).

[0036] In some instances, transistor structure 200 may operate as an n-type or n-channel transistor, wherein applying a relatively positive voltage exceeding a threshold voltage (e.g., an applied voltage having a positive order of magnitude greater than the threshold voltage relative to the source terminals) to gate portion 250 activates the channel portion or otherwise enables a conductive path between terminals 270-a-1 and 270-a-2 (e.g., along a direction generally aligned with the x-direction within substrate 220). In such instances, doped portion 240-a may refer to a portion having n-type doping or an n-type semiconductor, and doped portion 240-b may refer to a portion having p-type doping or a p-type semiconductor (e.g., a channel portion having an NPN configuration along the x-direction or channel direction).

[0037] In some instances, transistor structure 200 may operate as a p-type or p-channel transistor, wherein applying a relatively negative voltage above a threshold voltage (e.g., an applied voltage having a negative order of magnitude greater than the threshold voltage relative to the source terminals) to gate portion 250 activates the channel portion or otherwise enables the conductive path between terminals 270-a-1 and 270-a-2. In such instances, doped portion 240-a may refer to a portion having p-type doping or p-type semiconductor, and doped portion 240-b may refer to a portion having n-type doping or n-type semiconductor (e.g., a channel portion having a PNP configuration along the x-direction or channel direction).

[0038] In some instances, circuitry operable to support access operations to memory cells 105 (e.g., row assembly 125, column assembly 135, board assembly 145, sensing assembly 150, memory controller 170, or various combinations thereof) may be formed from respective groups of transistors, each having a transistor structure 200, wherein each of the transistors may have a channel portion formed by a corresponding doped portion 240 of the substrate 220. In some instances, such transistors may utilize a crystalline semiconductor material of the substrate 220 to achieve various performance or fabrication characteristics of such materials or arrangements. Some instances of such arrangements may be implemented in complementary metal-oxide-semiconductor (CMOS) configurations, which may refer to various instances of complementary and symmetrical pairs of p-type and n-type transistors (e.g., for logic functions). However, such structures or arrangements of substrate-based transistors may be limited by the available area of ​​the substrate 220 (e.g., below the memory array 110 or a stack of layers or stacks of the memory array 110).

[0039] According to the examples disclosed herein, various aspects of column assembly 135 may alternatively be positioned away from substrate 220 (e.g., on it), comprising layers or stacks that distribute various components or circuit systems to the memory array 110. For example, certain circuit systems (e.g., transistors) supporting decoding or addressing aspects associated with column assembly 135 may be formed in one or more layers or stacks on substrate 220, wherein such transistors may be included or referred to as thin-film transistors or vertical transistors, and other configurations or terms.

[0040] Figure 3This section describes an example of circuitry 300 supporting thin-film transistor stack selection in a memory device, based on examples disclosed herein. Circuitry 300 may include a plurality of memory arrays 110-a (e.g., memory arrays 110-a-1 to 110-aj), each memory array being associated with a stack (e.g., level, vertical position, height) on a substrate (e.g., substrate 220) of a memory die. For clarity, the components of memory array 110-a are described with reference to the first memory array 110-a-1, but each of the memory arrays 110-a-1 to 110-aj of circuitry 300 may be associated with a corresponding component or functionality, i.e., similar, different, or a combination thereof.

[0041] The first memory array 110-a-1 may include a set of memory cells 105-a arranged in m columns and n rows (e.g., memory cells 105-a-11 to 105-a-mn, a set of memory cells 105 associated with the first memory array 110-a-1). In an example of circuit 300, each of the memory cells 105-a includes a corresponding capacitor 320-a and a corresponding cell selection component 330-a (e.g., a cell selection transistor). In some instances, one or more of the capacitors 320-a may be ferroelectric capacitors operable to store charge or polarization corresponding to a logic state (e.g., for ferroelectric memory cells 105-a according to a ferroelectric memory architecture). The ferroelectric material used in the ferroelectric capacitor 320 can be characterized by polarization, wherein the material maintains a non-zero charge in the absence of an electric field. The polarization within the ferroelectric capacitor 320 generates a net charge at the surface of the ferroelectric material and attracts opposite charges through the terminals of the ferroelectric capacitor 320. Therefore, charge can be stored at the interface between the ferroelectric material and the capacitor terminals. In some instances, memory cell 105-a may contain memory elements of different memory architectures, such as linear capacitors (e.g., in DRAM applications), transistors (e.g., in NAND applications, in SRAM applications), or material memory elements (e.g., chalcogenide memory elements, resistive memory elements, threshold memory elements), as well as other types of memory elements.

[0042] Each of the memory cells 105-a may be coupled to a word line 120 (e.g., one of word lines 120-a-1 to 120-an), a digital line 130 (e.g., one of digital lines 130-a-1 to 130-am), and a board line 140-a. In some illustrative examples, memory cells 105-a-11 to 105-a-1n may represent a group or a row of memory cells 105 coupled to or coupled between the digital line 130 (e.g., digital line 130-a-1) and the board line 140-a. In some illustrative examples, memory cells 105-a-11 to 105-a-m1 may represent a group or a row of memory cells 105 coupled to a word line 120 (e.g., word line 120-a-1). Although memory array 110-a-1 is described as including a common board line 140-a for all memory cells 105-a, some instances of circuit 300 may include a separate board line 140 for each row of memory cells 105-a (e.g., an independently accessible board line 140 associated with each of the word lines 120-a) or a separate board line 140 for each column of memory cells 105-a (e.g., an independently accessible board line 140 associated with each of the digital lines 130-a), and other configurations.

[0043] As explained, each of word lines 120-a (e.g., word lines WL1 to WL) n Each of these can be associated with the corresponding word line voltage V. WL Associated with and coupled to line component 125-a (e.g., line decoder). Line component 125-a may couple one or more of the word lines 120-a to various voltage sources (not shown). In some illustrative examples, line component 125-a may selectively couple one or more of the word lines 120-a to a voltage source having a relatively high voltage (e.g., a selection voltage, which may be a voltage greater than 0 V) ​​or a voltage source having a relatively low voltage (e.g., a deselect voltage, which may be a 0 V ground voltage, or a negative voltage). As illustrated, each of the digital lines 130-a (e.g., digital lines DL1 to DL...) m Each of them can be associated with the corresponding digital line voltage V. DL Associatedly, memory cell 105-a or capacitor 320-a or other memory element may be coupled to digital line 130-a at least in part based on the activation or activation voltage of associated word line 120-a.

[0044] In some instances, row component 125-a may be shared (e.g., coupled, for decoding, addressing, or access) among memory arrays 110-a-1 to 110-aj, and the activation of word line 120-a in memory array 110-a-1 may be accompanied by the corresponding activation of one or more word lines 120 in other memory arrays 110-a (e.g., activating a row in each of memory arrays 110-a-1 to 110-aj, or activating a row in a subgroup of memory arrays 110-a-1 to 110-aj). For example, each output terminal or node of row component 125-a may be coupled to a corresponding word line 120 or a subgroup thereof of each of memory arrays 110-a-1 to 110-aaj, which may include interconnects (e.g., vias, sockets, through silicon vias) of word lines 120 of different stacks or levels interconnecting (e.g., different memory arrays in memory array 110-a) through the stacks or levels of memory device 100 or memory die containing circuitry 300.

[0045] As explained, board line 140-a (e.g., board line PL) can be connected to board line voltage V. PL It is associated with and can be coupled to board assembly 145-a (e.g., board decoder). Board assembly 145-a can couple board line 140-a to various voltage sources (not shown). In one example, board assembly 145-a can selectively couple board line 140-a to a voltage source having a relatively high voltage (e.g., board high voltage, which may be a voltage greater than 0 V) ​​or a voltage source having a relatively low voltage (e.g., board low voltage, which may be a 0 V ground voltage, or a negative voltage).

[0046] In some instances, board assembly 145-a may be shared (e.g., coupled, for decoding, addressing, or access) among memory arrays 110-a-1 to 110-aj, and activation of word line 140-a in memory array 110-a-1 may be accompanied by corresponding activation of one or more board lines 140 in other memory arrays 110-a (e.g., activation of a common board in each of memory arrays 110-a-1 to 110-aj, activation of a common board in a subgroup of memory arrays 110-a-1 to 110-aj). For example, each output terminal or node of board assembly 145-a may be coupled to a corresponding board line 140 or a subgroup thereof in each of memory arrays 110-a-1 to 110-aj, and may include interconnects (e.g., vias, sockets, TSVs) through stacks or layers of memory device 100 or memory die including circuitry 300 to interconnect board lines 140 of different stacks or layers. In some instances, one or more board lines 140 of each of the memory arrays 110-a may be independently addressable, or may be otherwise independently biased to each other via board assembly 145-a.

[0047] Sensing component 150-a may include various components for accessing (e.g., reading, writing) memory cells 105 of memory arrays 110-a-1 to 110-a-j. For example, sensing component 150-a may include a set of i sensing amplifiers 340-a (e.g., sensing amplifiers 340-a-1 to 340-a-1), each sensing amplifier being coupled between a corresponding signal line 345-a and a reference line 355. Each sensing amplifier 340-a may include various transistors or amplifiers to detect, convert, or amplify differences in signals, which may be referred to as latching. For example, sensing amplifier 340-a may include circuit elements that receive a sensed signal voltage (e.g., V) from the corresponding signal line 345-a. sig ) and compare it with the reference signal voltage (e.g., V) of the reference line 355 that can be provided by the reference component 350. ref The comparison is performed at sense amplifier 390. Based on the comparison at sense amplifier 390, the output of sense amplifier 340 can be driven to a higher (e.g., positive) or lower (e.g., negative, ground) voltage.

[0048] In some instances, the electrical signals associated with such latching can be transmitted between sensing component 150-a (e.g., sensing amplifier 340-a) and input / output component 160, for example, via I / O line 195 (not shown). In some instances, sensing component 150-a can communicate electronically with a memory controller (not shown), for example, by referring to... Figure 1 The described memory controller 170 controls various operations of the sensing component 150-a. In some instances, the activation logic signal SE may be referred to as "enabling" or "activating" the sensing component 150-a or its sensing amplifier 340-a. In some instances, the activation logic signal SE may be referred to as, or referred to as, as part of the operation of "latching" the result of accessing the memory cell 105.

[0049] Circuit 300 may implement various techniques for multiplexing digital lines 130 with sense amplifiers 340-a to support access to memory cells 105-a. For example, the number of sense amplifiers 340-a in the sensing assembly 150-a may be less than the number of digital lines 130 in the memory arrays 110-a-1 to 110-aj, and some digital lines 130 in the memory arrays 110-a-1 to 110-aj may be coupled to some sense amplifiers in the sense amplifiers 340-a for a given duration during an access operation. According to examples disclosed herein, circuit 300 may use a combination of column decoder 360 and cascade decoder 370 to support such multiplexing, as referred to herein. Figure 1 The described column component 135 is a component or functional distribution or separation.

[0050] The column decoder 360 can be configured to support i sense amplifiers 340-a or i signal lines 345-a (e.g., signal lines 345-a-1 to 345-ai, SL1 to SL). i ) and m intermediate lines 365 (e.g., intermediate lines 365-a-1 to 365-am, IL1 to IL) m Multiplexing or coupling between (i, i, i). In some instances, m may be greater than i, for example, m is an integer multiple of i. In some instances, m may be equal to the number of digital lines 130 or columns in each of the memory arrays 110-a-1 to 110-aj.

[0051] The cascaded decoder 370 is operable to select from memory arrays 110-a, and may include selective coupling or isolation of corresponding transistors 380-a (e.g., cascaded selection transistors) between one or more intermediate lines 365-a of the selected memory arrays 110-a and digital lines 130-a. In an example of circuit 300, each memory array 110-a may be associated with a corresponding row of transistors 380-a, which can be activated using a corresponding cascaded selection line 375. For example, memory array 110-a-1 may be associated with transistors 380-a-11 to 380-a-1m and cascaded selection line 375-a-1, memory array 110-a-j may be associated with transistors 380-a-j1 to 380-a-jm and cascaded selection line 375-a-j, and so on. In some instances, the number of memory arrays 110-a and stack-up select lines 375-a (e.g., number j) may be equal to the number of stacks or layers of circuitry 300 (e.g., the number of memory devices 100 or memory dies containing circuitry 300). In some instances (e.g., when multiple memory arrays 110-a are located on the same stack or layer), the number of memory arrays 110-a and stack-up select lines 375-a may be greater than the number of stacks or layers (e.g., an integer multiple of the number of stacks or layers).

[0052] In some instances, when an access operation is to be performed on memory cell 105-a of memory array 110-a-1, the stack-up decoder 370 may activate stack-up select line 375-a-1. Activating stack-up select line 375-a-1 activates each of transistors 380-a-11 to 380-a-1m, thereby coupling digital lines 130-a-1 to 130-am to column decoder 360 (e.g., via intermediate lines 365-a-1 to 365-am). Column decoder 360 is thus operable to couple one or more of the selected digital lines 130-a-1 to 130-am of memory array 110-a-1 to sense amplifiers 340-a-1 to 340-ai to support various access operations (e.g., read operations, write operations).

[0053] In some instances, when an access operation is to be performed on memory cell 105-a of memory array 110-a-1, the cascade decoder 370 may deactivate other cascade select lines 375 (e.g., cascade select line 375-aj and other cascade select lines), which may deactivate each of other transistors 380 (e.g., transistors 380-a-j1 to 380-a-jm and other transistors), thereby decoupling the digital lines 130 of other memory array 110-a from the column decoder 360 (e.g., with intermediate lines 365-a-1 to 365-am). In some instances, such isolation may improve the read tolerance, power consumption, or other operation of circuit 300 due to reduced inherent capacitance from the perspective of sense amplifier 340-a, or reduced charge leakage or dissipation (e.g., via unselected memory array 110-a) and other phenomena. Furthermore, such isolation can support simplified row decoding (e.g., when word lines 120 of different memory arrays 110-a are coupled to the same or shared outputs of row components 125-a), because multiple rows of memory arrays 110-a can be activated only when the digital lines 130 of some selected memory arrays 110-a are coupled to a circuitry that supports a given access operation.

[0054] The configuration of components in circuit 300 can also support improved flexibility in the layout or formation of the memory device 100 or memory die containing circuit 300. For example, row assembly 125-a, board assembly 145-a, sensing assembly 150-a, reference assembly 350, or column decoder 360, or various combinations thereof, can be formed at least partially by a circuit system located below or at least outside the memory array 110-a on another stack or level. In some instances, such circuit systems can be formed at least partially on a substrate (e.g., substrate 220, a crystalline semiconductor portion) and can include various configurations of substrate-based transistors (e.g., one or more sets of transistors included in a CMOS configuration according to transistor structure 200). However, in some instances, the area of ​​such circuit systems can be larger than the area of ​​each in the memory array 110-a, which can limit the scaling of circuit 300 on the memory die or result in relatively inefficient substrate utilization.

[0055] According to examples disclosed herein, transistor 380 may be located on the substrate at various locations including between stacks or layers of the memory array 110-a (e.g., between one or more stacks or layers distributed on the substrate). For example, transistor 380 may be formed using thin-film fabrication techniques, such as including a corresponding channel portion formed of a polycrystalline semiconductor material (e.g., deposited over substrate 220). In some instances, transistor 380 may be formed as a vertical transistor (e.g., a transistor having a channel portion aligned in a height direction relative to substrate 220), including various configurations utilizing one or more conductive channel material pillars that can be modulated based on the voltage of the corresponding gate portion. By moving transistor 380 on the substrate, circuitry 300 can support improved flexibility for distributing decoding circuitry systems throughout the memory die, which can improve area utilization or semiconductor material utilization, among other benefits.

[0056] Figure 4 This document describes an example of a memory structure 400 that supports the selection of a thin-film transistor stack in a memory device, as illustrated in the examples disclosed herein. The memory structure 400 may illustrate a portion of a memory device 100 or memory die that may be formed together with or on a substrate 220-a, which may be a reference substrate. Figure 2 An example of substrate 220 is described. Memory structure 400 can be illustrated for implementation of the reference. Figure 3Examples of aspects of the described circuit 300. For illustrative purposes, aspects of the memory structure 400 may be described with reference to the x, y, and z directions of coordinate system 401. The z direction may describe the direction perpendicular to the surface of substrate 220-a (e.g., a surface in the xy plane, on which other materials may be deposited or on top of it), and each of the related structures illustrated by its corresponding cross-section in the xz plane may extend a certain distance along the y direction, or repeat a certain number (e.g., according to the pitch dimension), or both. In some instances, for illustrative purposes, the x direction may be aligned with or referred to as the column direction (e.g., along a column of memory cells), and the y direction may be aligned with or referred to as the row direction (e.g., along a row of memory cells 105).

[0057] Memory structure 400 illustrates an example of a memory array 110 associated with different layers 420 (e.g., different stacks, stacked layers, hierarchical stacks). For example, memory array 110-b-1 may be associated with layer 420-a-1 at a first height or location relative to substrate 220-a, and memory array 110-b-2 may be associated with layer 420-a-2 at a second (e.g., different) height or location relative to substrate 220-a (e.g., above layer 420-a-1 relative to substrate 220-a). Although memory structure 400 illustrates an example with two layers 420-a, the described techniques are applicable to any number of memory structures with two or more layers 420.

[0058] At least some (if not every) of the memory arrays 110-b may contain a corresponding set of memory cells 105-b arranged or addressed according to rows (e.g., aligned along the y-direction, addressed according to position along the x-direction) or columns (e.g., aligned along the x-direction, addressed according to position along the y-direction). For example, a column of memory array 110-b-1 may contain n memory cells 105-b-11 to 105-b-1n and may be associated with (e.g., formed on, contacted with, or coupled to) a digital line conductor 410-a-11 (e.g., an instance of digital line 130). In some instances, a column of memory array 110-b-2 may contain the same number of memory cells 105-b, which may be physically aligned or misaligned (e.g., along the z-direction) or overlapped (e.g., when viewed in the xy-plane) with the memory cells 105-b of memory array 110-b-1. A certain number of columns, m, can be formed by repeating the described memory cell 105 and digital line conductor 410-a along the y-direction, as well as other features.

[0059] At least some (if not every one) of the memory cells 105-b in memory structure 400 may include a corresponding capacitor 320-b and a corresponding cell selection component 330-b (e.g., a transistor). In an example of memory structure 400, each of the cell selection components 330-b may be formed as a vertical transistor, which may include at least a portion of a channel (e.g., a vertical channel) or a portion thereof (e.g., along the z-direction) formed by a corresponding pillar 430-a, and a gate portion formed at least partially by a corresponding word line conductor 440-a (e.g., an example of word line 120). In some examples, the gate portion of the cell selection component 330-b may be a portion or region of word line 120 or word line conductor 440-a, operable to activate the channel portion of the cell selection component 330-b (e.g., modulating the conductivity of the channel portion). Word line conductor 440-a may extend from one memory cell 105-b along a direction such as the y-direction (e.g., the row direction, along the row of memory cell 105-b) to another memory cell 105-b, and may be coupled to row assembly 125 (not shown) for selecting or activating the row of memory cell 105-b (e.g., by applying a bias voltage to word line conductor 440-a).

[0060] In some instances, word line conductors 440-a of one memory array 110-b (e.g., memory array 110-b-1) may be coupled or connected to word line conductors 440-a of another memory array 110-b (e.g., memory array 110-b-2), such that rows of memory cells 105-b may be activated across multiple memory arrays 110-b or multiple levels 420-a (e.g., via shared nodes or outputs of shared row components 125, not shown). In some instances, interconnections between word line conductors 440-a of different levels 420-a may be formed at least partially along the z-direction by one or more vias, sockets, or TSVs, which may be located at or near the boundaries of memory array 110-b (e.g., along the y-direction), and other locations relative to memory array 110-b.

[0061] Each capacitor 320-b for memory cell 105-b may include a corresponding dielectric portion 450-a formed between a post 430-a associated with memory cell 105-b and a board conductor 460-a (e.g., an example of board line 140, board node, or a shared board). In some instances, a portion of the post 430-a of capacitor 320-b may be the same material or combination of materials (e.g., a doped semiconductor material, a polycrystalline semiconductor) as a portion of the post 430-a of the corresponding cell selection component 330-b. In some instances, a portion of the post 430-a of capacitor 320-b may be or include a different material or combination of materials (e.g., a metal or conductor portion, a metal layer deposited over the surface of the post 430-a) than a portion of the post 430-a of the corresponding cell selection component 330-b. In some instances, the dielectric portion 450-a may be formed of a ferroelectric material that is operable to maintain a non-zero charge in the absence of an electric field (e.g., corresponding to a stored logic state).

[0062] In an example of memory structure 400, memory array 110-b-1 may be associated with (e.g., coupled to, contained in, or used for access) plate conductor 460-a-1, and memory array 110-b-2 may be associated with (e.g., coupled to, contained in, or used for access) plate conductor 460-a-2. Each of the plate conductors 460-a may be coupled to a board assembly 145 (not shown) for biasing the plate conductor 460-a. In an example of memory structure 400, each plate conductor 460-a may be associated with at least one row of memory cells 105-b. In some examples, each of the plate conductors 460-a may also extend along a row of memory cells 105-b in the y-direction, in which case each of the plate conductors 460-a may be associated with all the memory cells 105-b of the corresponding memory array 110-b. In some instances, the plate conductor 460-a may be a metal or other conductor formed above or between the dielectric portions 450-a of the memory cells 105-b of the respective memory array 110-b.

[0063] In an example of memory structure 400, each column of memory cells 105-b in each memory array 110-b may be associated with a corresponding transistor 380-b, which may also be formed as a vertical transistor. Each transistor 380-b is operable to couple a corresponding digital line conductor 410-a to a middle line conductor 465-a (e.g., an example of middle line 365). In an example of memory structure 400, each middle line conductor 465-a may be a combination of a horizontal metal layer formed in contact with a post 470-a (e.g., on top of, opposite to, the digital line conductor 410-a) and a vertical portion coupled to a column decoder 360-a formed by one or more vias, sockets, or TSVs. In an example of memory structure 400, in order to support m columns of each memory array 110-b, m intermediate line conductors 465-a can be formed along the y direction, and each intermediate line conductor 465-a can be coupled or connected to transistors 380-b of each memory array 110-b or each level 420-a (for example, intermediate line conductor 465-a-1 is coupled to transistors 380-b-11 and 380-b-21).

[0064] At least some (if not every) of the stacked select transistors 380-a may include a channel portion (e.g., a vertical channel) formed at least partially by one or more corresponding pillars 470-a and a gate portion formed at least partially by one or more corresponding stacked select conductors 480-a (e.g., instances of stacked select lines 375). In some instances, the gate portion of transistor 380-b may be a portion or region of the stacked select line 375, operable to activate the channel portion of transistor 380-b (e.g., modulate the conductivity of the channel portion). The stacked select conductors 480-a may extend from one column of memory cells 105-b to another column, or from one transistor 380-b to another, along a direction such as the y-direction (e.g., along the row direction, along rows of memory cells 105), and may be coupled to a stacked decoder 370 (not shown) for selecting or activating the memory array 110-b (e.g., by applying a bias voltage to the stacked select conductors 480-a, by activating rows of transistors 380-b).

[0065] The set of m intermediate line conductors 465-a can be coupled to the column decoder 360-a, which in turn can be coupled to the sensing component 150-b (e.g., via multiple signal lines 345). Therefore, the combination of the stacked decoder 370 (not shown) and the column decoder 360-a can be used for multiplexing, addressing, or otherwise selectively coupling the digital line conductors 410-a and 110-b-2 of the memory arrays 110-ba and 110-b-2 to the sensing component 150-b or its sensing amplifier 340 to support various access operations. In some instances, the circuitry of the stacked decoder 370, the column decoder 360-a, or the sensing component 150-b can be substrate-based, for example, comprising transistors formed at least partially from doped portions of the substrate 220-a (e.g., transistors configured in a CMOS arrangement according to transistor structure 200). By including transistors 380-b at a location on substrate 220-a, memory structure 400 supports improved flexibility for distributing decoding circuitry throughout the memory die, which can improve area utilization or semiconductor material utilization, among other benefits.

[0066] In various instances, each of posts 430 and 470 is operable to support at least a portion of the channel of the corresponding transistor (e.g., a channel aligned along the z-direction or an operable conductive path that supports electrical coupling or conductive path between the source and drain terminals based at least in part on the voltage of the corresponding gate portion, gate terminal, or gate conductor), and may include one or more doped semiconductor portions. For example, to support an n-type transistor, post 430 or post 470 may include at least a p-type semiconductor portion, or may include a stack of n-type semiconductors (e.g., in the z-direction), p-type and n-type semiconductors (e.g., arranged in an NPN configuration along the z-direction), and other constituent materials or arrangements. To support a p-type transistor, post 430 or post 470 may include at least one n-type semiconductor portion, or may include a stack of p-type semiconductors (e.g., in the z-direction), n-type and p-type semiconductors (e.g., arranged in a PNP configuration along the z-direction), and other constituent materials or arrangements. In some instances, a post as described herein (e.g., post 430, post 470) may include one or more electrodes or electrode portions, such as electrodes at one or both ends of the post (e.g., top end, bottom end, or both).

[0067] Each of pillars 430 and 470 may be associated with a height or height dimension relative to the substrate (e.g., a lower extent in the z-direction, an upper extent in the z-direction, a span in the z-direction), which may be defined as part of various performance criteria for balancing the memory array 110. In some instances, the height dimension or extent in the z-direction of pillar 430 of the memory array 110 may be the same as or at least partially overlap with the height dimension or extent in the z-direction of pillar 470 of the memory array 110. For example, each of pillars 430 and 470 may have a common height dimension relative to the substrate (e.g., a common upper extent, a common lower extent, or both). In some instances, pillar 430 may have a different height or height dimension than pillar 470, for example, pillar 430 may have an extended height along the z-direction to support one or more features of capacitor 320. Columns 430 and 470 may be formed to have various cross-sectional shapes (e.g., in the xy plane), such as square, rectangle, circle, ellipse or polygon and other shapes, wherein columns 430 and 470 may have common or different shapes, or common or different dimensions.

[0068] Posts 430 and 470 can be formed according to various techniques. In some instances, one or more layers or stacks of doped semiconductor material can be deposited on or above a substrate (e.g., on or in contact with the digital line conductor 410 or its corresponding metal layer), and portions of the deposited layer between the respective posts 430 and 470 (e.g., along the x-direction, along the y-direction) can be etched away or slotted to form the respective posts. In some instances, posts 430 and 470 can be formed of the same material or a combination of materials (e.g., of the same layers or stacks). In some instances, such layers can include one or more electrode layers, such as electrode layers above the stack of doped semiconductor material layers, electrode layers below the stack of doped semiconductor material layers, or both, and such electrode layers may or may not be etched or slotted during the post formation process. Alternatively or concurrently, in some instances, holes or trenches may be etched through the material (e.g., through the dielectric material and the gate dielectric material in the z-direction) and the material for posts 430 and 470 (e.g., one or more doped semiconductor materials, one or more electrode materials) may be deposited in the etched holes or trenches. In instances where post material is deposited into holes, trenches, or other recesses, posts 430 and 470 may be formed of or may not be formed of the same material or a combination of materials.

[0069] In various instances, the number or configuration of posts 430 and 470 for a given transistor can be defined or selected for specific characteristics, such as associated drive strength (e.g., drive current), impedance, activation threshold, or leakage characteristics of a particular transistor or transistor group. In some instances, multiple posts 430 or multiple posts 470 may be described or configured as a parallel physical structure (e.g., parallel channel) of a shared transistor or transistor assembly. For example, as illustrated, each of transistors 380-b may include or otherwise form two posts 470-a. However, in other instances, transistors 380 or cell selection assembly 330 may each include or otherwise form any number of one or more posts 470 or 430. Similarly, in various instances, capacitor 320 may be formed with any number of one or more posts 430. In some instances, each pillar 430 or 470 in a group of parallel configurations (e.g., co-activated) can be described or configured as a component of a single transistor, such that the corresponding cell selection or stack selection can be described or configured as having multiple transistors arranged in parallel.

[0070] In some instances, the word line conductors 440 and the stacked select conductors 480 of a given memory array 110 may be formed using one or more common operations, one or more common materials, or otherwise share various aspects of their formation or configuration. For example, the word line conductors 440 and the stacked select conductors 480 may be formed using one or more common conductor formation processes (e.g., common masking processes, common etching processes, common deposition processes, or various combinations thereof). In some instances, the word line conductors 440 and the stacked select conductors 480 may be formed to have a height dimension within or overlapping with at least the doped semiconductor portions of the pillars 430 and 470 (e.g., supporting the function of modulating conductivity through the channel portions of the cell select component 330 and the transistor 380, respectively).

[0071] In various examples, the word line conductor 440 and the stacked select conductor 480 may be formed of metal or metal alloy (e.g., copper, tungsten, gold, silver, tin, aluminum, or alloys thereof). Such conductors may be separated from posts 430 or 470 (along the x-direction, along the y-direction, along both the x-direction and y-direction, or in the radial direction) by a gate dielectric that partially contacts the conductors and the respective posts. In some examples, the gate conductors may be located adjacent to the respective posts (e.g., as a lateral gate, as a through gate, as a pair of gate conductors on either side of the post), comprising conductors extending between the posts along the y-direction and separated from the posts along the x-direction by a gate dielectric. In some examples, the gate conductors may comprise (e.g., partially, completely) at least a portion surrounding the respective post (e.g., as a wraparound gate, as a circumferential gate, as an omnidirectional gate), wherein at least the respective post may be wound (e.g., partially wound, completely wound) with a circumferential gate dielectric that contacts the post and the conductors. In various instances, the digital line conductor 410 or intermediate line conductor 465, as well as other components such as conductors, may be formed of metal or metal alloy, which may be the same material or a different material as the conductors used to support the transistor gate portion (e.g., word line conductor 440, stack-up select conductor 480).

[0072] In some instances, the circuitry of the stacked decoder 370 (not shown), the column decoder 360-a, or the sensing component 150-b, or any combination thereof, may be substrate-based, for example, comprising transistors (e.g., transistors configured in a CMOS arrangement according to transistor structure 200) formed at least partially from doped portions of substrate 220-b. By including transistor 380-b at a location on substrate 220-a, memory structure 400 can support improved flexibility in distributing the decoding circuitry across the entire memory die, which can improve area utilization or semiconductor substrate material utilization, among other benefits.

[0073] Figure 5 This describes an example layout of a memory structure 500 that supports the stacking of thin-film transistors in a memory device, as illustrated in the examples disclosed herein. The memory structure 500 may illustrate a portion of a memory device 100 or memory die that may be formed together with or on a substrate 220-b, which may be a reference substrate. Figure 2 An example of substrate 220 is described. Memory structure 500 illustrates its use for implementation reference. Figure 3Examples of aspects of the described circuit 300. For illustrative purposes, aspects of the memory structure 500 may be described with reference to the x, y, and z directions of coordinate system 501. The z direction may describe a direction perpendicular to the surface of substrate 220-b (e.g., a surface in the xy plane, on which other materials may be deposited), and each of the related structures illustrated by its corresponding cross-section in the xz plane may extend a certain distance along the y direction, or repeat a certain number (e.g., according to the pitch dimension), or both. In some instances, for illustrative purposes, the x direction may be aligned with or referred to as the column direction (e.g., along a column of memory cells), and the y direction may be aligned with or referred to as the row direction (e.g., along row 105 of memory cells). In some instances, the memory structure 500 may include alternative arrangements of components similar to those described in the reference memory structure 400, including components with similar reference numerals, and the description of such components or their formation in the reference memory structure 400 may be applied to the components of the memory structure 500.

[0074] Memory structure 500 illustrates an example of a memory array 110 associated with different layers 420. For example, memory arrays 110-c-1 and 110-c-3 may be associated with layer 420-b-1 at a first height or location relative to substrate 220-b, and memory arrays 110-c-2 and 110-c-4 may be associated with layer 420-b-2 at a second (e.g., different) height or location relative to substrate 220-b (e.g., above layer 420-b-1 relative to substrate 220-b). Although memory structure 500 illustrates an example with two layers 420-b, the described techniques can be applied to any number of memory structures with two or more layers 420.

[0075] Memory structure 500 also illustrates examples of memory arrays 110 associated with different groups 510 memory arrays 110 (e.g., different subgroups of memory arrays 110, which may be located differently above substrate 220 along the x-direction, along the y-direction, or both). For example, memory arrays 110-c-1 and 110-c-2 may be associated with a group 510-a-1, and memory arrays 110-c-3 and 110-c-4 may be associated with a group 510-a-2. In some instances, the memory arrays 110 of group 510 may be coupled to or otherwise shared with corresponding column decoders 360. For example, group 510-a-1 may be associated with (e.g., coupled to, configured for accessing or addressing using) column decoder 360-b-1, and group 510-a-2 may be associated with column decoder 360-b-2. In an example of memory structure 500, groups 510-a-1 and 510-a-2 may be coupled to or otherwise shared with sensing components 150-c (e.g., sensing components 150 are shared or shared by each of the memory arrays 110-c of group 510-a), which are accessible via a corresponding column decoder 360-b corresponding to group 510-a. Although memory structure 500 illustrates an example with two groups 510-a, the described techniques can be applied to any number of memory structures having two or more groups 510 (e.g., and associated column decoders 360 operable to be coupled to or otherwise shared with the shared sensing components 150-c).

[0076] At least some (if not every) of the memory arrays 110-c may contain a corresponding set of memory cells 105-c arranged or addressed according to rows (e.g., aligned along the y-direction, addressed according to position along the x-direction) or columns (e.g., aligned along the x-direction, addressed according to position along the y-direction). For example, each column of the memory arrays 110-c may contain n memory cells, and each memory cell may be associated with (e.g., formed on, contacted with, or coupled to) a digital line conductor 410-b (e.g., an instance of digital line 130). A number of columns, m in number, may be formed by repeating the illustrated memory cells 105-c and digital line conductor 410-b, along with other features, along the y-direction.

[0077] At least some (if not every one) of the memory cells 105-c in memory structure 500 may include a corresponding capacitor 320-c and a corresponding cell selection component 330-c (e.g., a transistor). In an example of memory structure 500, each of the cell selection components 330-c may be formed as a vertical transistor, which may include at least a channel portion (e.g., a vertical channel) or a portion thereof (e.g., along the z-direction) formed by a corresponding pillar 430-b, and a gate portion formed at least partially by a corresponding word line conductor 440-b (e.g., an example of word line 120). In some examples, the gate portion of the cell selection component 330-c may be a portion or region of word line 120 or word line conductor 440-b, operable to activate the channel portion of the cell selection component 330-c (e.g., modulating the conductivity of the channel portion). Word line conductor 440-b may extend from one memory cell 105-c along, for example, the y-direction (e.g., the row direction, along the row of memory cell 105-c) to another memory cell 105-c, and may be coupled to row assembly 125 (not shown) for selecting or activating a row of memory cell 105-c (e.g., by applying a bias voltage to word line conductor 440-b).

[0078] In some instances, word line conductors 440-b of one memory array 110-c may be coupled or connected to word line conductors 440-b of another memory array 110-c, such that rows of memory cells 105-c can be co-activated across multiple memory arrays 110-c, including memory arrays 110-c spanning multiple levels 420-b, or memory arrays 110-c spanning multiple groups 510-a, or both (e.g., via shared nodes or outputs of shared row components 125, not shown). In instances where shared, shared, or otherwise concurrent activation across memory arrays 110-c across multiple levels 420-b is supported, word line conductors 440-b-1n and 440-b-2n may be coupled to each other or to shared or common outputs of row components 125, or word line conductors 440-b-3n and 440-b-4n may be coupled to each other or to shared or common outputs of row components 125, and so on. In instances where multiple groups 510-a span memory array 110-c supporting shared, shared, or otherwise concurrent activation, word line conductors 440-b-1n and 440-b-3n may be coupled to each other or to a shared or common output of row component 125, or word line conductors 440-b-2n and 440-b-4n may be coupled to each other or to a shared or common output of row component 125, and so on. In instances where multiple levels 420-b and groups 510-a span memory array 110-c supporting shared, shared, or otherwise concurrent activation, word line conductors 440-b-1n, 440-b-2n, 440-b-3n, and 440-b-4n may be coupled to each other or to a shared or common output of row component 125, and so on.

[0079] In some instances, the interconnects between word line conductors 440-b of different levels 420-b may be formed at least partially along, for example, the z-direction by one or more vias, sockets, or TSVs, which may be located at or near the boundary of memory array 110-c (e.g., along the y-direction), and other locations relative to memory array 110-c. In some instances, the interconnects between word line conductors 440-b of different groups 510-a may be formed at least partially along the x-direction by one or more wiring levels or layers, which may be located along the z-direction at locations different from memory array 110-c, such as above, below, or between memory array 110-c, and other locations.

[0080] Each capacitor 320-c for memory cell 105-c may include a corresponding dielectric portion 450-b formed between a post 430-b associated with memory cell 105-c and a board conductor 460-b (e.g., an example of board line 140, board node, or a shared board). In some instances, a portion of the post 430-b of capacitor 320-b may be the same material or combination of materials (e.g., a doped semiconductor material, a polycrystalline semiconductor) as a portion of the post 430-b of the corresponding cell selection component 330-c. In some instances, a portion of the post 430-b of capacitor 320-c may be or include a different material or combination of materials (e.g., a metal or conductor portion, a metal layer deposited over the surface of the post 430-b) than a portion of the post 430-b of the corresponding cell selection component 330-c. In some instances, the dielectric portion 450-b may be formed of a ferroelectric material that is operable to maintain a non-zero charge in the absence of an electric field (e.g., corresponding to a stored logic state).

[0081] In an example of memory structure 500, each of the memory arrays 110-c may be associated with (e.g., coupled to, contained in, or used for access) a corresponding plate conductor 460-b. Each of the plate conductors 460-b may be coupled to a plate assembly 145 (not shown) for biasing the plate conductor 460-b, respectively. In an example of memory structure 500, each plate conductor 460-b may be associated with at least one row of memory cells 105-c. In some examples, each of the plate conductors 460-b may also extend along a row of memory cells 105-c in the y-direction, in which case each of the plate conductors 460-b may be associated with all the memory cells 105-c of the corresponding memory array 110-c.

[0082] In an example of memory structure 500, at least some (if not every) of at least some (if not every column) memory cells 105-c of memory array 110-c may be associated with corresponding transistors 380-c, which may also be configured as vertical transistors. At least some (if not every) of transistors 380-c are operable to couple corresponding digital line conductors 410-b to intermediate line conductors 465-b (e.g., an example of intermediate line 365). In an example of memory structure 500, in order to support each memory array 110-cm column, m intermediate line conductors 465-b can be formed along the y direction for each group 510-a, and each intermediate line conductor 465-b can be coupled or connected to the transistor 380-c of each memory array 110-c of each level 420-b of a group 510-a (for example, intermediate line conductor 465-b-11 is coupled to transistors 380-c-11 and 380-c-21, and intermediate line conductor 465-b-21 is coupled to transistors 380-c-31 and 380-c-41).

[0083] At least some (if not every) of the stacked select transistors 380-c may include a channel portion (e.g., a vertical channel) formed at least partially by one or more corresponding pillars 470-b and a gate portion formed at least partially by one or more corresponding stacked select conductors 480-b (e.g., instances of stacked select lines 375). In some instances, the gate portion of the transistor 380-c may be a portion or region of the stacked select line 375, operable to activate the channel portion of the transistor 380-c (e.g., modulate the conductivity of the channel portion). The stacked select conductors 480-b may extend from one column of memory cells 105-c to another column, or from one transistor 380-c to another, along a direction such as the y-direction (e.g., along the row direction, along rows of memory cells 105), and may be coupled to a stacked decoder 370 (not shown) for selecting or activating the memory array 110-c (e.g., by applying a bias voltage to the stacked select conductors 480-b, by activating rows of transistors 380-c).

[0084] Each group of m intermediate conductors 465-b of 510-a can be coupled to a corresponding column decoder 360-b, which can in turn be coupled to or otherwise coupled to a sensing component 150-c (e.g., a sensing component 150 shared by each or all memory arrays 110-c in the column decoders 360-b, operable to access the memory cells 105-c of all or any memory arrays 110-c). In some instances, the memory structure 500 may include a switching component 515 for coupling or isolating the corresponding column decoders 360-b and sensing components 150-c (e.g., activating switching component 515-a-1 according to logic signal SW1 and activating switching component 515-a-2 according to logic signal SW2). Although a single switching component 515-a is shown for each of the column decoders 360-b, in some instances, the memory structure 500 may include multiple switching components 515 (e.g., multiple switching components 515 per group 510-a), such as switching components 515 for each of the multiple signal lines 345 (not shown) between the respective column decoder 360-b and the sensing component 150-c. In other instances, such functionality may be contained in the column decoder 360-b, or contained in the sensing component 150-c, or distributed between the column decoder 360-b and the sensing component 150-c, or any combination thereof, such that the column decoder 360-b can be additionally operated to couple with the sensing component 150-c. Therefore, the combination of the stacked decoder 370 (not shown), the column decoder 360-b, and one or more switching components 515 (if applicable) can be used to multiplex, address, or otherwise selectively couple the digital line conductors 410-b of the memory arrays 110-c-1 to 110-c-4 with the sensing component 150-c or its sensing amplifier 340 to support various access operations.

[0085] Although memory structure 500 illustrates an instance where intermediate line conductor 465-b and column decoder 360-b are positioned along the x-direction toward an outer extent, and sensing component 150-c is centered along the x-direction (e.g., between column decoders 360-b), the components of memory structure 500 can be arranged alternately. For example, each of the yz plane display groups 510-a and their corresponding circuitry can be centered along the x-direction such that intermediate line conductor 465-b and column decoder 360-b are centered along the x-direction (e.g., between memory arrays 110-c, relatively closer to the middle dimension along the x-direction than the extension of memory arrays 110-c), and the digital line conductor 410-b and memory array 110-c of each group 510-a can extend along the x-direction toward an outer extent. In some instances, sensing component 150-c can still be centered, for example, centered between column decoders 360-b-1 and 360-b-2. In some instances, the sensing component 150-c may be located in different positions, such as different positions on the substrate 220-b along the y-direction, different positions along the x-direction (e.g., on the same side as both column decoders 360-b-1 and 360-b-2 along the x-direction), or different positions in the z-direction (e.g., above or below column decoder 360-b), and other positions.

[0086] In some instances, the circuitry of the stacked decoder 370 (not shown), column decoder 360-b, switching component 515 (where applicable), or sensing component 150-c, or any combination thereof, may be substrate-based, for example, comprising transistors (e.g., transistors configured in a CMOS arrangement according to transistor structure 200) formed at least partially from doped portions of substrate 220-b. By including transistor 380-c in a location on substrate 220-b, memory structure 500 can support improved flexibility for distributing the decoding circuitry across the entire memory die, which can improve area utilization or semiconductor substrate material utilization, among other benefits. Furthermore, by including sensing component 150-c accessible by different column decoders 360-b (e.g., sensing component 150 shared or common to column decoders 360-b), memory structure 500 can support improved flexibility for decoding, addressing, or other operations. For example, the first column decoder 360-b may be coupled to the sensing component 150-c, while the second column decoder 360-b is isolated from the sensing component 150-c. This allows certain operations to be performed using the sensing component 150-c via the first column decoder 360-b (e.g., sensing the logic state stored by a memory cell 105 in one of the memory arrays 110-c) and other operations to be performed without using the sensing component 150-c (e.g., row selection or biasing, column selection or biasing, stack-up selection, signal development, which may be isolated from the sensing component 150-c via the second column decoder 360-b or an associated switching component 515). In some instances, such techniques may support a degree of parallel operation between the memory arrays 110-c.

[0087] Figure 6 This describes an example layout of a memory structure 600 that supports thin-film transistor stacking selection in a memory device, as disclosed herein. The memory structure 600 may illustrate a portion of a memory device 100 or memory die that may be formed together with or on a substrate 220-c, which may be a reference substrate. Figure 2 An example of substrate 220 is described. Memory structure 600 can be illustrated for implementation reference. Figure 3Examples of aspects of the described circuit 300. For illustrative purposes, aspects of the memory structure 600 may be described with reference to the x, y, and z directions of coordinate system 601. The z direction may describe a direction perpendicular to the surface of substrate 220-c (e.g., a surface in the xy plane, on which other materials may be deposited or on top of it), and each of the related structures illustrated by its corresponding cross-section in the xz plane may extend a certain distance along the y direction, or repeat a certain number (e.g., according to the pitch dimension), or both. In some instances, for illustrative purposes, the x direction may be aligned with or referred to as the column direction (e.g., along a column of memory cells), and the y direction may be aligned with or referred to as the row direction (e.g., along row 105 of memory cells). In some instances, the memory structure 600 may include alternative arrangements of components similar to those described in the reference memory structure 400, including components with similar reference numerals, and the description of such components or their formation in the reference memory structure 400 may be applied to the components of the memory structure 600.

[0088] Memory structure 600 illustrates an example of a memory array 110 associated with different layers 420. For example, memory arrays 110-d-1 and 110-d-3 may be associated with layer 420-c-1 at a first height or position relative to substrate 220-c, and memory arrays 110-d-2 and 110-d-4 may be associated with layer 420-c-2 at a second (e.g., different) height or position relative to substrate 220-c (e.g., above layer 420-c-1 relative to substrate 220-c). Although memory structure 600 illustrates an example with two layers 420-c, the described techniques are applicable to any number of memory structures having two or more layers 420.

[0089] The memory structure 600 also illustrates examples of memory arrays 110 associated with different groups 610 of the memory array 110 (e.g., different subgroups of memory array 110 that may have different locations above the substrate 220 along the x-direction, along the y-direction, or both). For example, memory arrays 110-d-1 and 110-d-2 may be associated with group 610-a-1, and memory arrays 110-d-3 and 110-d-4 may be associated with group 610-a-2. In some instances, the memory arrays 110 of group 610 may be coupled to or otherwise shared with the same column decoder 360, but different groups 610 may be located on different sides or locations relative to a shared intermediate conductor 465 or other circuitry. For example, group 610-a-1 may be located on a first side (e.g., the left side) of intermediate conductor 465-c, and group 610-a-2 may be located on a second side (e.g., the right side) of intermediate conductor 465-c.

[0090] At least some (if not every) of the memory arrays 110-d may contain a corresponding set of memory cells 105-d arranged or addressed according to rows (e.g., aligned along the y-direction, addressed according to position along the x-direction) or columns (e.g., aligned along the x-direction, addressed according to position along the y-direction). For example, each column of the memory arrays 110-d may contain n memory cells, and each memory cell may be associated with (e.g., formed on, contacted with, or coupled to) a digital line conductor 410-c (e.g., an instance of digital line 130). A number of columns, m, may be formed by repeating the illustrated memory cells 105-d and digital line conductor 410-c along the y-direction, along with other features.

[0091] At least some (if not every one) of the memory cells 105-d in the memory structure 600 may include a corresponding capacitor 320-d and a corresponding cell selection component 330-d (e.g., a transistor). In an example of the memory structure 600, each of the cell selection components 330-d may be formed as a vertical transistor, which may include at least a channel portion (e.g., a vertical channel) or a portion thereof (e.g., along the z-direction) formed by a corresponding post 430-c, and a gate portion formed at least partially by a corresponding word line conductor 440-c (e.g., an example of word line 120). In some examples, the gate portion of the cell selection component 330-d may be a portion or region of word line 120 or word line conductor 440-c, operable to activate the channel portion of the cell selection component 330-d (e.g., modulating the conductivity of the channel portion). The word line conductor 440-c can extend from one memory cell 105-d along, for example, the y-direction (e.g., the row direction, along the row of memory cell 105-d) to another memory cell 105-d, and can be coupled to the row assembly 125 (not shown) for selecting or activating the row of memory cell 105-d (e.g., by applying a bias voltage to the word line conductor 440-c).

[0092] In some instances, word line conductors 440-c of one memory array 110-d may be coupled or connected to word line conductors 440-c of another memory array 110-d, such that rows of memory cells 105-d can be co-activated across multiple memory arrays 110-d, including memory arrays 110-d spanning multiple levels 420-c, or memory arrays 110-d spanning multiple groups 610-a, or both (e.g., via shared nodes or outputs of shared row components 125, not shown). In instances where shared, shared, or otherwise concurrent activation across memory arrays 110-d across multiple levels 420-c is supported, word line conductors 440-c-11 and 440-c-21 may be coupled to each other or to shared or common outputs of row components 125, or word line conductors 440-c-31 and 440-c-41 may be coupled to each other or to shared or common outputs of row components 125, and so on. In instances where multiple groups 610-a span memory arrays 110-d supporting shared, shared, or otherwise concurrent activation, word line conductors 440-c-11 and 440-c-31 may be coupled to each other or to a shared or common output of row component 125, or word line conductors 440-c-21 and 440-c-41 may be coupled to each other or to a shared or common output of row component 125, and so on. In instances where multiple levels 420-c and groups 610-a span memory arrays 110-d supporting shared, shared, or otherwise concurrent activation, word line conductors 440-c-11, 440-c-21, 440-c-31, and 440-c-41 may be coupled to each other or to a shared or common output of row component 125, and so on.

[0093] In some instances, the interconnections between word line conductors 440-c of different levels 420-c may be formed at least partially along, for example, the z-direction by one or more vias, sockets, or TSVs, which may be located at or near the boundary of memory array 110-d (e.g., along the y-direction), and other locations relative to memory array 110-d. In some instances, the interconnections between word line conductors 440-c of different groups 610-a may be formed at least partially along the x-direction by one or more wiring levels or layers, which may be located along the z-direction at locations different from memory array 110-d, such as above, below, or between memory array 110-d, and other locations.

[0094] At least some (if not every) of the capacitors 320-d for the memory cell 105-d may include a corresponding dielectric portion 450-c formed between a post 430-c associated with the memory cell 105-d and a board conductor 460-c (e.g., an example of a board line 140, a board node, or a shared board). In some instances, a portion of the post 430-c of the capacitor 320-d may be the same material or combination of materials (e.g., a doped semiconductor material, a polycrystalline semiconductor) as a portion of the post 430-c of the corresponding cell selection component 330-d. In some instances, a portion of the post 430-c of the capacitor 320-d may be or include a different material or combination of materials (e.g., a metal or conductor portion, a metal layer deposited over the surface of the post 430-c) than a portion of the post 430-c of the corresponding cell selection component 330-d. In some instances, the dielectric portion 450-c may be formed of a ferroelectric material that is operable to maintain a non-zero charge in the absence of an electric field (e.g., corresponding to a stored logic state).

[0095] In an example of memory structure 600, at least some (if not every) of the memory arrays 110-d may be associated with (e.g., coupled to, contained in, or used for access) a corresponding plate conductor 460-c. At least some (if not every) of the plate conductors 460-c may be coupled to a plate assembly 145 (not shown) for biasing the plate conductors 460-c respectively. In an example of memory structure 600, each plate conductor 460-c may be associated with at least one row of memory cells 105-d. In some examples, each of the plate conductors 460-c may also extend along a row of memory cells 105-d in the y-direction, in which case each of the plate conductors 460-c may be associated with all the memory cells 105-d of the corresponding memory array 110-d.

[0096] In an example of memory structure 600, at least some (if not every) of at least some (if not every column) memory cells 105-d of memory array 110-d may be associated with corresponding transistors 380-d, which may also be configured as vertical transistors. At least some (if not every) of transistors 380-d are operable to couple corresponding digital line conductors 410-c to intermediate line conductors 465-c (e.g., an example of intermediate line 365). In an example of memory structure 600, to support m columns of each memory array 110-d, m intermediate line conductors 465-c can be formed along the y-direction, and each intermediate line conductor 465-c can be coupled or connected to transistors 380-d of each memory array 110-d in each of the layers 420-c and each of the groups 610-a (e.g., intermediate line conductor 465-c-1 is coupled to transistors 380-d-11, 380-d-21, 380-d-31, and 380-d-41). The groups of m intermediate line conductors 465-c can be coupled to column decoders 360-c, which in turn can be coupled to or otherwise operably coupled to sensing components 150-d.

[0097] At least some (if not every) of the stacked select transistors 380-d may include a channel portion (e.g., a vertical channel) formed at least partially by one or more corresponding pillars 470-c and a gate portion formed at least partially by one or more corresponding stacked select conductors 480-c (e.g., instances of stacked select lines 375). In some instances, the gate portion of transistor 380-d may be a portion or region of the stacked select line 375, operable to activate the channel portion of transistor 380-d (e.g., modulate the conductivity of the channel portion). The stacked select conductors 480-c may extend from one column of memory cells 105-d to another column, or from one transistor 380-d to another, along a direction such as the y-direction (e.g., along the row direction, along rows of memory cells 105), and may be coupled to a stacked decoder 370 (not shown) for selecting or activating the memory array 110-d (e.g., by applying a bias voltage to the stacked select conductors 480-c, by activating rows of transistors 380-d).

[0098] In some instances, the circuitry of the stacked decoder 370 (not shown), column decoder 360-c, or sensing component 150-d, or any combination thereof, may be substrate-based, for example, comprising transistors (e.g., transistors configured in a CMOS arrangement according to transistor structure 200) formed at least partially from doped portions of substrate 220-c. By including transistor 380-d in a location above substrate 220-c, memory structure 600 can support improved flexibility for distributing the decoding circuitry across the entire memory die, which can improve area utilization or semiconductor substrate material utilization, among other benefits. Furthermore, by implementing a shared intermediate conductor 465-c and a shared column decoder 360-c for different layers 420-a and different groups 610-a, memory structure 600 can further utilize distributed stacking selection by individually addressing multiple memory arrays 110-d of the same layer 420-c. Such techniques can further improve area utilization or semiconductor substrate material utilization, and can also be implemented for selecting subgroups of memory cells 105-d associated with relatively short digital line conductors 410-c, or for isolating a larger number of memory cells 105-d that are not targeted for access operations (e.g., by deactivating transistors 380-d to effectively isolate unselected memory arrays 110-d). In some instances, such techniques can reduce the inherent capacitance of the conductor between the target memory cell 105-d and the sensing component 150-d, or can reduce charge leakage during access operations (e.g., via unselected memory arrays 110-d), which can improve read tolerance, improve write tolerance, or reduce power consumption, among other benefits.

[0099] Figure 7 This document describes an example layout of a memory structure 700 that supports the selection of a thin-film transistor stack in a memory device, based on examples disclosed herein. The memory structure 700 may illustrate a portion of a memory device 100 or memory die that may be formed together with or on a substrate 220-d, which may be a reference substrate. Figure 2 An example of substrate 220 is described. Memory structure 700 illustrates its use for implementation reference. Figure 3Examples of aspects of the described circuit 300. For illustrative purposes, aspects of the memory structure 700 may be described with reference to the x, y, and z directions of coordinate system 701. The z direction may describe the direction perpendicular to the surface of substrate 220-d (e.g., a surface in the xy plane, on which other materials may be deposited), and each of the related structures illustrated by its corresponding cross-section in the xz plane may extend a certain distance along the y direction, or repeat a certain number (e.g., according to the pitch dimension), or both. In some instances, for illustrative purposes, the x direction may be aligned with or referred to as the column direction (e.g., along a column of memory cells), and the y direction may be aligned with or referred to as the row direction (e.g., along row 105 of memory cells). In some instances, the memory structure 700 may include alternative arrangements of components similar to those described in the reference memory structure 400, including components with similar reference numerals, and the description of such components or their formation in the reference memory structure 400 may be applied to the components of the memory structure 700.

[0100] Memory structure 700 illustrates an example of a memory array 110 associated with different layers 420. For example, memory arrays 110-e-1 and 110-e-3 may be associated with layer 420-d-1 at a first height or position relative to substrate 220-d, and memory arrays 110-e-2 and 110-e-4 may be associated with layer 420-d-2 at a second (e.g., different) height or position relative to substrate 220-d (e.g., above layer 420-d-1 relative to substrate 220-d). Although memory structure 700 illustrates an example with two layers 420-d, the described techniques can be applied to any number of memory structures with two or more layers 420.

[0101] The memory structure 700 also illustrates examples of memory arrays 110 associated with different groups 710 (e.g., different subgroups of memory arrays 110, which may be located differently above substrate 220 along the x-direction, along the y-direction, or both). For example, memory arrays 110-e-1 and 110-e-2 may be associated with group 710-a-1, and memory arrays 110-e-3 and 110-e-4 may be associated with group 710-a-2. In some instances, the memory arrays 110 of group 710 may be coupled to or otherwise shared with the same column decoder 360, but different groups 710 may be located on different sides or positions relative to a shared intermediate conductor 465 or other circuitry. For example, group 710-a-1 may be located on a first side (e.g., the left side) of intermediate conductor 465-d, and group 710-a-2 may be located on a second side (e.g., the right side) of intermediate conductor 465-d.

[0102] At least some (if not every) of the memory arrays 110-e may contain a corresponding set of memory cells 105-e arranged or addressed according to rows (e.g., aligned along the y-direction, addressed according to position along the x-direction) or columns (e.g., aligned along the x-direction, addressed according to position along the y-direction). For example, each column of the memory arrays 110-e may contain n memory cells, and each memory cell may be associated with (e.g., formed on, contacted with, or coupled to) a digital line conductor 410-d (e.g., an instance of digital line 130). A number of columns, m in total, may be formed by repeating the illustrated memory cells 105-e and digital line conductor 410-d along the y-direction, along with other features.

[0103] At least some (if not every one) of the memory cells 105-e in the memory structure 700 may include a corresponding capacitor 320-e and a corresponding cell selection component 330-e (e.g., a transistor). In an example of the memory structure 700, each of the cell selection components 330-e may be formed as a vertical transistor, which may include at least a channel portion (e.g., a vertical channel) or a portion thereof (e.g., along the z-direction) formed by a corresponding pillar 430-d, and a gate portion (e.g., an example of word line 120) formed by a corresponding word line conductor 440-d. In some examples, the gate portion of the cell selection component 330-e may be a portion or region of word line 120 or word line conductor 440-d, operable to activate the channel portion of the cell selection component 330-e (e.g., modulate the conductivity of the channel portion). Word line conductor 440-d can extend from one memory cell 105-e along a direction such as the y-direction (e.g., the row direction, along the row of memory cell 105-e) to another memory cell 105-e, and can be coupled to row assembly 125 (not shown) for selecting or activating the row of memory cell 105-e (e.g., by applying a bias voltage to word line conductor 440-d).

[0104] In some instances, word line conductors 440-d of one memory array 110-e may be coupled or connected to word line conductors 440-d of another memory array 110-e, such that rows of memory cells 105-e can be co-activated across multiple memory arrays 110-e, including memory arrays 110-e spanning multiple levels 420-d, or memory arrays 110-e spanning multiple groups 710-a, or both (e.g., via shared nodes or outputs of shared row components 125, not shown). In instances where co-, shared, or otherwise concurrent activation across memory arrays 110-e across multiple levels 420-d is supported, word line conductors 440-d-11 and 440-d-21 may be coupled to each other or to shared or common outputs of row components 125, or word line conductors 440-d-31 and 440-d-41 may be coupled to each other or to shared or common outputs of row components 125, and so on. In instances where multiple groups 710-a span memory arrays 110-e and support shared, shared, or otherwise concurrent activation, word line conductors 440-d-11 and 440-d-31 may be coupled to each other or to a shared or common output of row component 125, or word line conductors 440-d-21 and 440-d-41 may be coupled to each other or to a shared or common output of row component 125, and so on. In instances where multiple levels 420-d and groups 710-a span memory arrays 110-e and support shared, shared, or otherwise concurrent activation, word line conductors 440-d-11, 440-d-21, 440-d-31, and 440-d-41 may be coupled to each other or to a shared or common output of row component 125, and so on.

[0105] In some instances, the interconnections between word line conductors 440-d of different levels 420-d may be formed at least partially along, for example, the z-direction by one or more vias, sockets, or TSVs, which may be located at or near the boundary of memory array 110-e (e.g., along the y-direction), and other locations relative to memory array 110-e. In some instances, the interconnections between word line conductors 440-d of different groups 710-a may be formed at least partially along the x-direction by one or more wiring levels or layers, which may be located along the z-direction at locations different from memory array 110-e, such as above, below, or between memory array 110-e, and other locations.

[0106] Each capacitor 320-e for memory cell 105-e may include a corresponding dielectric portion 450-d formed between a post 430-d associated with memory cell 105-e and a board conductor 460-d (e.g., an example of board line 140, board node, or a shared board). In some instances, a portion of the post 430-d of capacitor 320-e may be the same material or combination of materials (e.g., a doped semiconductor material, a polycrystalline semiconductor) as a portion of the post 430-c of the corresponding cell selection component 330-e. In some instances, a portion of the post 430-d of capacitor 320-e may be or include a different material or combination of materials (e.g., a metal or conductor portion, a metal layer deposited over the surface of the post 430-d) than a portion of the post 430-d of the corresponding cell selection component 330-e. In some instances, the dielectric portion 450-d may be formed of a ferroelectric material that is operable to maintain a non-zero charge in the absence of an electric field (e.g., corresponding to a stored logic state).

[0107] In an example of memory structure 700, each of the memory arrays 110-e may be associated with (e.g., coupled to, contained in, or used for access) a corresponding plate conductor 460-d. Each of the plate conductors 460-d may be coupled to a plate assembly 145 (not shown) for biasing the plate conductor 460-d, respectively. In an example of memory structure 700, each plate conductor 460-d may be associated with at least one row of memory cells 105-e. In some examples, each of the plate conductors 460-d may also extend along the y-direction along a row of memory cells 105-e, in which case each of the plate conductors 460-d may be associated with all the memory cells 105-e of the corresponding memory array 110-e.

[0108] In an example of memory structure 700, at least some (if not every) of the memory cells 105-e of memory array 110-e may be associated with corresponding transistors 380-e, which may also be configured as vertical transistors. At least some (if not every) of the transistors 380-e are operable to couple corresponding digital line conductors 410-d to intermediate line conductors 465-d (e.g., an example of intermediate line 365). In an example of memory structure 700, to support m columns of each memory array 110-e, m intermediate line conductors 465-d can be formed along the y-direction, and each intermediate line conductor 465-d can be coupled or connected to a transistor 380-e associated with each of each of the layers 420-d and each of each of the groups 710-a for each memory array 110-e (e.g., intermediate line conductor 465-d-1 is coupled to transistors 380-e-11, 380-e-21, 380-e-31, and 380-e-41). The groups of m intermediate line conductors 465-d can be coupled to column decoders 360-d, which can in turn be coupled to or otherwise operable to be coupled to sensing components 150-e.

[0109] At least some (if not every) of the stacked select transistors 380-e may include a channel portion (e.g., a vertical channel) formed at least partially by one or more corresponding pillars 470-d and a gate portion formed at least partially by one or more corresponding stacked select conductors 480-d (e.g., instances of stacked select lines 375). In some instances, the gate portion of transistor 380-e may be a portion or region of the stacked select line 375, operable to activate the channel portion of transistor 380-e (e.g., modulate the conductivity of the channel portion). The stacked select conductors 480-d may extend from one column of memory cells 105-e to another column, or from one transistor 380-e to another, along a direction such as the y-direction (e.g., along the row direction, along rows of memory cells 105), and may be coupled to a stacked decoder 370 (not shown) for selecting or activating the memory array 110-e (e.g., by applying a bias voltage to the stacked select conductors 480-d, by activating rows of transistors 380-e).

[0110] An example of memory structure 700 illustrates the configuration in which each of the transistors 380 can be located on the same level 420. For example, each of transistors 380-e-11, 380-e-21, 380-e-31, and 380-e-41, and their corresponding repetitions along the y-direction for a certain number of columns, can be associated with level 420-d or otherwise. In some instances, such a configuration can support pillars 470-d and stacked select conductors 480-d for all transistors 380-e in memory structure 700, the transistors being formed using common processes or otherwise concurrently.

[0111] In some instances, the configuration of memory structure 700 may be supported by corresponding conductors 740 operable to couple between intermediate line conductor 465-d and digital line conductor 410-d of level 420-d-1. For example, conductor 740-a-11 may be operable to couple between intermediate line conductor 465-d-1 (e.g., via transistor 380-e-11) and digital line conductor 410-d-11 (e.g., via transistor 720-a-11 or other circuitry), conductor 740-a-31 may be operable to couple between intermediate line conductor 465-d-1 (e.g., via transistor 380-e-31) and digital line conductor 410-d-31 (e.g., via transistor 720-a-31 or other circuitry), and so on.

[0112] In some instances, conductor 740 may be formed as part of a metallization process, which may include various deposition or etching operations or both. In some instances, such a process may also include forming conductor portions 750 that are coupled to or otherwise associated with each of the digital line conductors 410-d in the second level 420-d-2. Each of the conductor portions 750 may be coupled to the corresponding digital line conductor 410-d (e.g., along the z-direction) via a corresponding conductor portion 755 (e.g., a vertical conductor), which may include one or more vias, sockets, or TSVs between the digital line conductor 410-d and the corresponding conductor portion 750. In some instances, to mitigate dimensional tolerance or accuracy requirements of the connections between layers 420-d (e.g., “pitch” tolerances, such as column pitch, associated with the spacing or repetition of digital line conductors 410-d or memory cells 105-e along the y-direction), conductor portions 755 can be implemented in varying ways, such as an interleaving method, wherein conductor portions 755 of columns adjacent to each other along the y-direction may be located in different positions along the x-direction according to various interleaving techniques or repetitions. Among other benefits, the interleaving method can also improve interconnect accuracy or interconnect tolerance between layers 420-d, or support a relatively large cross-sectional area (e.g., in the xy-plane) at the top of conductor portions 755 (e.g., the end relatively far from the substrate 220-d) compared to the bottom of conductor portions 755. This can be associated with an etching process for etching holes for depositing conductive material for conductor portions 755 (e.g., where this etching process can extend the upper cross-section in the xy-plane as etching proceeds downward along the z-direction).

[0113] At least some (if not every) of the transistors 720-a may include a channel portion (e.g., a vertical channel) formed at least partially by one or more corresponding pillars 730 and a gate portion formed at least partially by one or more corresponding stacked select conductors 725. In some instances, the gate portion of the transistor 720-a may be a portion or region of the conductor 725 operable to activate the channel portion of the transistor 720-a (e.g., modulate the conductivity of the channel portion). The conductor 725 may extend from one column of memory cells 105-e to another column, or from one transistor 720-a to another, along a direction such as the y-direction (e.g., along the row direction, along a row of memory cells 105).

[0114] In some instances, post 730 may be formed using the same process or material as post 470-d, in which case transistor 720-a may be formed as a transistor of the same type as transistor 380-e (e.g., an n-type or p-type transistor). In some instances, post 730 and post 470-d may be formed using different processes or materials, in which case transistor 720-a may be formed as a transistor of a different type than transistor 380-e. Although the examples of memory structure 700 illustrate an example with transistor 380-e coupled to (e.g., formed thereon) the intermediate line conductor 465-d and transistor 720-a coupled to (e.g., formed thereon) the digital line conductor 410-d, in some instances, the relative positions may be interchanged, such that transistor 380-e may be coupled to (e.g., formed thereon) the digital line conductor 410-d and transistor 720-a may be coupled to (e.g., formed thereon) the intermediate line conductor 465-d.

[0115] In some instances, transistor 720-a may be activated according to various techniques to support the operation of memory structure 700. In some instances, the transistor may be configured to be "always on," wherein conductor 725 may be activated whenever power or voltage is applied to or supplied to memory structure 700 or whenever memory structure 700 is operable to support access operations (e.g., operation in active mode). In some instances, transistor 720-a may be configured to be activated during access to a first memory array, a second memory array, a third memory array, or a fourth memory array, or any combination thereof. In some instances, transistor 720-a may be activated when a corresponding memory array 110-e is selected for access operations, in which case both corresponding transistors 380-e and 720 may be activated (e.g., activating transistors 380-e-11 and 720-a-11, and the corresponding repeating transistor along the y-direction during access to memory array 110-e-1). In some instances, a stacked decoder 370 and other circuitry can be used to perform such combined or concurrent activation. Although instances of memory structure 700 include transistor 720-a, in some instances, transistor 720-a may be replaced by a metal conductor (e.g., a via, socket, TSV) that electrically connects digital line conductor 410-d to the corresponding conductor 740-a.

[0116] In some instances, the circuitry of the stacked decoder 370 (not shown), the column decoder 360-c, or the sensing component 150-d, or any combination thereof, may be substrate-based, for example, comprising transistors (e.g., transistors configured for a CMOS arrangement according to transistor structure 200) formed at least partially by doped portions of substrate 220-c. By including transistor 380-d in a location above substrate 220-c, memory structure 600 can support improved flexibility in distributing the decoding circuitry throughout the memory die, which can improve area utilization or semiconductor substrate material utilization, among other benefits. Furthermore, in some instances, such a configuration can support an auxiliary circuitry region 760 (e.g., within or otherwise associated with layer 420-d-2) to be allocated to other circuitry supporting the operation of memory structure 700. For example, auxiliary circuitry region 760 can provide areas for forming power or voltage supply circuitry, such as capacitors supporting power or voltage regulation or other signal conditioning for the operation of memory structure 700.

[0117] Examples of memory structures 400, 500, 600, and 700 illustrate various techniques for implementing stack-up selection according to the examples disclosed herein, including the techniques schematically illustrated in circuit 300. In some examples, memory device 100 or associated memory dies may implement multiple instances of one of memory structures 400, 500, 600, or 700. For example, any of memory structures 400, 500, 600, or 700 may be associated with a cross-sectional area (e.g., span or range along the x and y directions, span or range in the xy plane) or a pitch (e.g., repeating distance along the x direction, repeating distance along the y direction), and one or more aspects of the respective memory structure may be repeated or extended along the x or y direction or both to expand the storage capacity of memory device 100 or associated memory dies. In some examples, each such repeat may be independently operable or addressable, which may support various aspects of parallel or otherwise concurrent access operations between repeats of the respective memory structures. In some instances, memory device 100 or associated memory die may implement two or more instances of memory structures 400, 500, 600 or 700, or both, or may combine two or more aspects of the respective memory structures.

[0118] Figure 8The flowchart illustrates a method 800 for selecting a thin-film transistor stack in a supporting memory device according to examples disclosed herein. Operation of method 800 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control functional elements of the manufacturing system to perform the described functions. Alternatively, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0119] At point 805, the method may include forming a sensing component (e.g., sensing component 150) operable for sensing memory cells of a memory die. Operation at point 805 may be performed according to the examples and techniques disclosed herein, including references to... Figures 1 to 3 and one or more aspects described in 7.

[0120] At 810, the method may include a column decoder (e.g., column decoder 360) forming a memory die, the column decoder being operable to couple with a sensing component. Operation of 810 may be performed according to examples and techniques disclosed herein, including references to... Figures 1 to 3 and one or more aspects described in 7.

[0121] At 815, the method may include forming a first memory array associated with a first level on a substrate of a memory die, the first memory array including a first subgroup of memory cells and a plurality of first digital lines, each first digital line operable to be coupled to a column decoder via a corresponding first transistor (e.g., transistor 380) of the first level. Operation of 815 may be performed according to the examples and techniques disclosed herein, including references to... Figures 1 to 3 and one or more aspects described in 7.

[0122] At 820, the method may include forming a second memory array associated with the first level, the second memory array comprising a second subgroup of memory cells and a plurality of second digital lines, each second digital line operable to be coupled to a column decoder via a corresponding second transistor (e.g., transistor 380) of the first level. Operation of 820 may be performed according to the examples and techniques disclosed herein, including references to... Figures 1 to 3 and one or more aspects described in 7.

[0123] At 825, the method may include forming a third memory array associated with a second level on a substrate of a memory die, the third memory array comprising a third subgroup of memory cells and a plurality of third digital lines, each third digital line operable to be coupled to a column decoder via a corresponding third transistor (e.g., transistor 380) of the first level. Operation of 825 may be performed according to the examples and techniques disclosed herein, including references to... Figures 1 to 3and one or more aspects described in 7.

[0124] At 830, the method may include forming a fourth memory array associated with the second level, the fourth memory array comprising a fourth subgroup of memory cells and a plurality of fourth digital lines, each fourth digital line operable to be coupled to a column decoder via a corresponding fourth transistor (e.g., transistor 380) of the first level. Operation of 830 may be performed according to the examples and techniques disclosed herein, including references to... Figures 1 to 3 and one or more aspects described in 7.

[0125] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., instructions executable by a processor for non-transitory computer-readable media storage) for performing the following operations: forming a sensing component operable for sensing memory cells of a memory die; forming a column decoder of the memory die operable to couple with the sensing component; forming a first memory array associated with a first level on a substrate of the memory die, the first memory array including a first subgroup of the memory cells and a plurality of first digital lines, each first digital line operable to couple with the column decoder via a corresponding first transistor of the first level; forming a second memory array associated with the first level, the second memory array... The column includes a second subgroup of the memory cells and a plurality of second digital lines, each second digital line operable to be coupled to the column decoder via a corresponding second transistor of the first level; forming a third memory array associated with a second level on the substrate of the memory die, the third memory array including a third subgroup of the memory cells and a plurality of third digital lines, each third digital line operable to be coupled to the column decoder via a corresponding third transistor of the first level; and forming a fourth memory array associated with the second level, the fourth memory array including a fourth subgroup of the memory cells and a plurality of fourth digital lines, each fourth digital line operable to be coupled to the column decoder via a corresponding fourth transistor of the first level.

[0126] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: forming a plurality of conductors (e.g., associated with intermediate line 365) of a first level, each conductor being coupled to one of a first transistor, one of a second transistor, one of a third transistor, one of a fourth transistor, and a column decoder.

[0127] In some examples of the method 800 and apparatus described herein, a channel portion of one of the first transistors is at least partially based on a corresponding set of one or more first semiconductor pillars (e.g., pillar 470) forming contacts with conductors among the plurality of conductors; a channel portion of one of the second transistors is at least partially based on a corresponding set of one or more second semiconductor pillars (e.g., pillar 470) forming contacts with conductors among the plurality of conductors; a channel portion of one of the third transistors is at least partially based on a corresponding set of one or more third semiconductor pillars (e.g., pillar 470) forming contacts with conductors among the plurality of conductors; and a channel portion of one of the fourth transistors is at least partially based on a corresponding set of one or more fourth semiconductor pillars (e.g., pillar 470) forming contacts with conductors among the plurality of conductors.

[0128] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for: forming one or more first gate conductors (e.g., one or more stacked select conductors 480) of a first layer, each first gate conductor operable to modulate the conductivity of a channel portion of each of the first transistors; forming one or more second gate conductors (e.g., one or more stacked select conductors 480) of a first layer, each second gate conductor operable to modulate the conductivity of a channel portion of each of the second transistors; forming one or more third gate conductors (e.g., one or more stacked select conductors 480) of a first layer, each third gate conductor operable to modulate the conductivity of a channel portion of each of the third transistors; and forming one or more fourth gate conductors (e.g., one or more stacked select conductors 480) of a first layer, each fourth gate conductor operable to modulate the conductivity of a channel portion of each of the fourth transistors.

[0129] Figure 9 The flowchart illustrates a method 900 for selecting a thin-film transistor stack in a memory device according to an example disclosed herein. Operation of method 900 can be implemented by memory device 100 or its components as described herein. For example, operation of method 900 can be performed by a stack decoder 370, a column decoder 360, or a row component 125, or various combinations thereof, as referenced herein. Figures 1 to 3 As described in section 7. In some instances, memory device 100 may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, memory device 100 may use dedicated hardware to perform aspects of the described functions.

[0130] At 905, the method may include identifying memory cell rows of a first memory array of a memory die for access operations, the memory die comprising: a first memory array in a first layer above a substrate of the memory die, a second memory array of the memory die in the first layer, a third memory array of the memory die in a second layer above the substrate, and a fourth memory array of the memory die in the second layer. The operation of 905 may be performed according to the examples and techniques disclosed herein, including references... Figures 1 to 3 And one or more aspects described in 7. In some instances, the operation of 905 may be performed by memory controller 170 or row component 125 or a combination thereof.

[0131] At 910, the method may include coupling the memory cell row to a column decoder of the memory die, at least in part based on the identification. In some instances, coupling the memory cell row to the column decoder may include coupling the memory cell row to a plurality of digital lines of the first memory array, at least in part based on activating a plurality of first transistors (e.g., cell selection component 330) of the first level, and coupling the plurality of digital lines of the first memory array to the row decoder, at least in part based on activating a plurality of second transistors (e.g., transistor 380) of the second level. The operation of 910 may be performed according to the examples and techniques disclosed herein, including references to Figures 1 to 3 And one or more aspects described in 7. In some instances, an access operation may be performed after the operation in 910, which may include performing a read operation on one or more memory cells of the identified row, or performing a write operation on one or more memory cells of the identified row, or another access operation or a combination of access operations.

[0132] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: identifying memory cell rows of a first memory array of a memory die for access operations, the memory die comprising: a first memory array in a first layer above a substrate of the memory die, a second memory array of the memory die in the first layer, a third memory array of the memory die in a second layer above the substrate, and a fourth memory array of the memory die in the second layer; and coupling the memory cell rows to a column decoder of the memory die at least partially based on identification, wherein coupling the memory cell rows to the column decoder comprises coupling the memory cell rows to a plurality of digital lines of the first memory array at least partially based on activating a plurality of first transistors in the first layer, and coupling the plurality of digital lines of the first memory array to the column decoder at least partially based on activating a plurality of second transistors in the second layer.

[0133] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: isolating a second memory cell row of a second memory array from a column decoder, at least in part based on the identification, wherein isolating the second memory cell row from the column decoder may include coupling the second memory cell row to a plurality of digital lines of the second memory array, at least in part based on activating a plurality of third transistors (e.g., cell selection component 330) of a first level, and isolating a plurality of digital lines of the second memory array from the column decoder, at least in part based on deactivating a plurality of fourth transistors (e.g., transistor 380) of a second level.

[0134] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: isolating a third memory cell row of a third memory array from a column decoder, at least in part based on the identification, wherein isolating the third memory cell row from the column decoder may include coupling the third memory cell row to a plurality of digital lines of the third memory array, at least in part based on activating a plurality of fifth transistors of the second level (e.g., cell selection component 330), and isolating a plurality of digital lines of the third memory array from the column decoder, at least in part based on deactivating a plurality of sixth transistors of the second level (e.g., transistor 380).

[0135] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing operations at least in part based on activating a plurality of seventh transistors (e.g., transistor 720) of a second level, and at least in part based on enabling access to the memory die, coupling a plurality of digital lines of a third memory array to a plurality of sixth transistors.

[0136] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0137] Describe an apparatus. The apparatus may include: a sensing component (e.g., sensing component 150) operable for sensing memory cells of a memory die; a column decoder for the memory die (e.g., column decoder 360) operable to couple with the sensing component; a first memory array associated with a first level on a substrate of the memory die, the first memory array including a first subgroup of the memory cells and a plurality of first digital lines, each first digital line operable to couple with the column decoder via a corresponding first transistor (e.g., transistor 380) of the first level; and a second memory array associated with the first level, the second memory array including a second subgroup of the memory cells and a plurality of second digital lines, each second digital line operable to couple with the column decoder via a corresponding first transistor (e.g., transistor 380) of the first level; and a second memory array associated with the first level, the second memory array including a second subgroup of the memory cells and a plurality of second digital lines, each second digital line operable to couple with the column decoder via a corresponding first transistor (e.g., transistor 380) of the first level. A line operable to be coupled to the column decoder via a corresponding second transistor (e.g., transistor 380) of the first layer; a third memory array associated with the second layer on the substrate of the memory die, the third memory array comprising a third subgroup of the memory cells and a plurality of third digital lines, each third digital line operable to be coupled to the column decoder via a corresponding third transistor (e.g., transistor 380) of the first layer; and a fourth memory array associated with the second layer, the fourth memory array comprising a fourth subgroup of the memory cells and a plurality of fourth digital lines, each fourth digital line operable to be coupled to the column decoder via a corresponding fourth transistor (e.g., transistor 380) of the first layer.

[0138] In some instances, the device may include multiple conductors (e.g., multiple intermediate lines 365) at a first level, each conductor being coupled to one of a first transistor, one of a second transistor, one of a third transistor, one of a fourth transistor, and a column decoder.

[0139] In some instances of the device, for each of the plurality of conductors, a channel portion of one of the first transistors includes a corresponding set of one or more first semiconductor pillars (e.g., pillar 470) in contact with the conductors of the plurality of conductors; a channel portion of one of the second transistors includes a corresponding set of one or more second semiconductor pillars (e.g., pillar 470) in contact with the conductors of the plurality of conductors; a channel portion of one of the third transistors includes a corresponding set of one or more third semiconductor pillars (e.g., pillar 470) in contact with the conductors of the plurality of conductors; and a channel portion of one of the fourth transistors includes a corresponding set of one or more fourth semiconductor pillars (e.g., pillar 470) in contact with the conductors of the plurality of conductors.

[0140] In some instances, the device may include: one or more first gate conductors (e.g., one or more stacked select conductors 480) of a first level, each first gate conductor operable to modulate the conductivity of a channel portion of each of the first transistors; one or more second gate conductors (e.g., one or more stacked select conductors 480) of a first level, each second gate conductor operable to modulate the conductivity of a channel portion of each of the second transistors; one or more third gate conductors (e.g., one or more stacked select conductors 480) of a first level, each third gate conductor operable to modulate the conductivity of a channel portion of each of the third transistors; and one or more fourth gate conductors (e.g., one or more stacked select conductors 480) of a first level, each fourth gate conductor operable to modulate the conductivity of a channel portion of each of the fourth transistors.

[0141] In some instances of the device, each memory cell in a first subgroup of memory cells may be associated with a corresponding fifth transistor (e.g., cell select component 330), operable to couple the memory cell to a digital line among a plurality of first digital lines. Each of the fifth transistors includes a corresponding channel portion comprising a corresponding set of one or more fifth semiconductor pillars (e.g., pillar 430). Each memory cell in a second subgroup of memory cells may be associated with a corresponding sixth transistor (e.g., cell select component 330), operable to couple the memory cell to a digital line among a plurality of second digital lines. Each of the sixth transistors includes a corresponding channel portion comprising a corresponding set of one or more sixth semiconductor pillars (e.g., pillar 430). 30) Each memory cell of the third subgroup of memory cells may be associated with a corresponding seventh transistor (e.g., cell select component 330), the seventh transistor being operable to couple the memory cell to a digital line among a plurality of third digital lines, each of the seventh transistors including a corresponding channel portion including a corresponding set of one or more seventh semiconductor pillars (e.g., pillar 430), and each memory cell of the fourth subgroup of memory cells may be associated with a corresponding eighth transistor (e.g., cell select component 330), the eighth transistor being operable to couple the memory cell to a digital line among a plurality of fourth digital lines, each of the eighth transistors including a corresponding channel portion including a corresponding set of one or more eighth semiconductor pillars (e.g., pillar 430).

[0142] In some instances of the device, one or more first semiconductor pillars, one or more second semiconductor pillars, one or more third semiconductor pillars, one or more fourth semiconductor pillars, one or more fifth semiconductor pillars, and one or more sixth semiconductor pillars may overlap relative to the substrate and one or more seventh semiconductor pillars along the height dimension (e.g., along the z-direction), and one or more eighth semiconductor pillars may overlap relative to the substrate along the height dimension.

[0143] In some instances, the device may include a plurality of ninth transistors (e.g., transistor 720), each operable to couple one of a plurality of conductors to a corresponding one of a plurality of first digital lines, and a plurality of tenth transistors (e.g., transistor 720), each operable to couple one of a plurality of conductors to a corresponding one of a plurality of second digital lines.

[0144] In some instances of the device, each of the plurality of ninth transistors and each of the plurality of tenth transistors may be configured to be activated during access to a first memory array, a second memory array, a third memory array, or a fourth memory array, or any combination thereof.

[0145] In some instances, the device may include a plurality of fifth transistors (e.g., cell selection component 330) at a first level, each fifth transistor operable to couple a corresponding memory cell of a first subgroup of memory cells to a digital line of a plurality of first digital lines; a plurality of sixth transistors (e.g., cell selection component 330) at a first level, each sixth transistor operable to couple a corresponding memory cell of a second subgroup of memory cells to a digital line of a plurality of second digital lines; a plurality of seventh transistors (e.g., cell selection component 330) at a second level, each seventh transistor operable to couple a corresponding memory cell of a third subgroup of memory cells to a digital line of a plurality of third digital lines; and a plurality of eighth transistors (e.g., cell selection component 330) at a second level, each eighth transistor operable to couple a corresponding memory cell of a fourth subgroup of memory cells to a digital line of a plurality of fourth digital lines.

[0146] In some instances, the device may include a plurality of word line conductors (e.g., word line conductor 440), each word line conductor operable to activate a corresponding row of a plurality of fifth transistors, a corresponding row of a plurality of sixth transistors, a corresponding row of a plurality of seventh transistors, and a corresponding row of a plurality of eighth transistors.

[0147] In some instances of the device, the column decoder and sensing components each contain transistors formed at least partially by doped portions of the substrate.

[0148] In some instances, the device may include multiple voltage-controlled capacitors, each of which is at least partially located in a second layer between the third and fourth memory arrays.

[0149] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0150] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support signal flow between them. Components are considered to be in electronic communication (or electrically connected, connected, or coupled to each other) if there is any conductive path between them that can readily support signal flow. At any given time, the conductive path between components that are in electronic communication (or electrically connected, connected, or coupled to each other) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path or an indirect conductive path, which may include intermediate components such as switches, transistors, or other components. In some instances, for example, by using one or more intermediate components such as switches or transistors, the signal flow between connected components can be interrupted for a period of time.

[0151] The term "coupling" refers to a shift from an open-circuit relationship between components (where signals cannot currently communicate between components via conductive paths) to a closed-circuit relationship between components (where signals can communicate between components via conductive paths). When a component (e.g., a controller) couples other components together, that component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0152] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, when a switch is open, two components separated by the switch located between them are isolated from each other. When a controller isolates two components from each other, the controller influences a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0153] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sub-levels.

[0154] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0155] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0156] The descriptions set forth herein, in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0157] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by following the reference numeral with a dash and a second numeral to differentiate between similar components. If only the first reference numeral is used in the specification, then the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0158] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0159] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using any of the following devices designed to perform the functions described herein: a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0160] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be considered a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be considered in the same manner as the phrase "at least partially based on".

[0161] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art without departing from its scope, and the general principles defined herein may be applied to other variations. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A sensing component operable for sensing memory cells of a memory die; The column decoder of the memory die is operable to be coupled to the sensing component; A first memory array, associated with a first level on the substrate of the memory die, the first memory array including a first subgroup of the memory cells and a plurality of first digital lines, each first digital line operable to couple to the column decoder via a corresponding first transistor of the first level; A second memory array, associated with the first level, includes a second subgroup of the memory cells and a plurality of second digital lines, each second digital line operable to couple to the column decoder via a corresponding second transistor of the first level; A third memory array, associated with a second level above the substrate of the memory die, the third memory array including a third subgroup of the memory cells and a plurality of third digital lines, each third digital line operable to couple to the column decoder via a corresponding third transistor of the first level; and A fourth memory array, associated with the second level, includes a fourth subgroup of the memory cells and a plurality of fourth digital lines, each of which is operable to couple to the column decoder via a corresponding fourth transistor of the first level.

2. The device according to claim 1, further comprising: The first layer has multiple conductors, each conductor being coupled to one of the first transistors, one of the second transistors, one of the third transistors, one of the fourth transistors, and the column decoder.

3. The device according to claim 2, wherein for each of the plurality of conductors: The channel portion of one of the first transistors includes a corresponding set of one or more first semiconductor pillars in contact with the conductor of the plurality of conductors; The channel portion of one of the second transistors includes a corresponding set of one or more second semiconductor pillars in contact with one of the plurality of conductors; The channel portion of one of the third transistors includes a corresponding set of one or more third semiconductor pillars in contact with the conductor of the plurality of conductors; and The channel portion of one of the fourth transistors includes a corresponding set of one or more fourth semiconductor pillars in contact with the conductors of the plurality of conductors.

4. The device according to claim 3, further comprising: The first level has one or more first gate conductors, each of which is operable to modulate the conductivity of the channel portion of each of the first transistors; The first level has one or more second gate conductors, each second gate conductor being operable to modulate the conductivity of the channel portion of each of the second transistors; One or more third gate conductors of the first level, each third gate conductor operable to modulate the conductivity of the channel portion of each of the third transistors; and The first layer has one or more fourth gate conductors, each fourth gate conductor being operable to modulate the conductivity of the channel portion of each of the fourth transistors.

5. The device according to claim 3, wherein: Each memory cell of the first subgroup of the memory cells is associated with a corresponding fifth transistor, the fifth transistor being operable to couple the memory cell to a digital line among the plurality of first digital lines, each of the fifth transistors including a corresponding channel portion including a corresponding set of one or more fifth semiconductor pillars; Each memory cell of the second subgroup of the memory cells is associated with a corresponding sixth transistor, the sixth transistor being operable to couple the memory cell to a digital line among the plurality of second digital lines, each of the sixth transistors including a corresponding channel portion including a corresponding set of one or more sixth semiconductor pillars; Each memory cell in the third subgroup of the memory cells is associated with a corresponding seventh transistor, the seventh transistor being operable to couple the memory cell to a digital line among the plurality of third digital lines, each of the seventh transistors including a corresponding channel portion including a corresponding set of one or more seventh semiconductor pillars; and Each memory cell in the fourth subgroup of the memory cells is associated with a corresponding eighth transistor, the eighth transistor being operable to couple the memory cell to a digital line in one of the plurality of fourth digital lines, each of the eighth transistors including a corresponding channel portion including a corresponding set of one or more eighth semiconductor pillars.

6. The device according to claim 5, wherein: The one or more first semiconductor pillars, the one or more second semiconductor pillars, the one or more third semiconductor pillars, the one or more fourth semiconductor pillars, the one or more fifth semiconductor pillars, and the one or more sixth semiconductor pillars overlap along the height dimension relative to the substrate, and The one or more seventh semiconductor pillars overlap with the one or more eighth semiconductor pillars along the height dimension relative to the substrate.

7. The device according to claim 3, further comprising: A plurality of ninth transistors, each ninth transistor being operable to couple one of the plurality of conductors to a corresponding one of the plurality of first digital lines; and A plurality of tenth transistors, each tenth transistor being operable to couple one of the plurality of conductors to a corresponding one of the plurality of second digital lines.

8. The device of claim 7, wherein each of the plurality of ninth transistors and each of the plurality of tenth transistors is configured to be activated during access to the first memory array, the second memory array, the third memory array, or the fourth memory array, or any combination thereof.

9. The device according to claim 1, further comprising: The first level has a plurality of fifth transistors, each fifth transistor being operable to couple a corresponding memory cell of the first subgroup of the memory cells to a digital line among the plurality of first digital lines; The first level has a plurality of sixth transistors, each sixth transistor being operable to couple a corresponding memory cell of the second subgroup of the memory cells to a digital line among the plurality of second digital lines; The second level has a plurality of seventh transistors, each of which is operable to couple a corresponding memory cell of the third subgroup of the memory cells to a digital line among the plurality of third digital lines; and The second level has a plurality of eighth transistors, each of which is operable to couple a corresponding memory cell of the fourth subgroup of the memory cells to a digital line among the plurality of fourth digital lines.

10. The device according to claim 9, further comprising: Multiple word line conductors, each word line conductor operable to activate a corresponding row of the multiple fifth transistors, a corresponding row of the multiple sixth transistors, a corresponding row of the multiple seventh transistors, and a corresponding row of the multiple eighth transistors.

11. The device of claim 1, wherein the column decoder and the sensing component each comprise a transistor formed at least partially by a doped portion of the substrate.

12. The device according to claim 1, further comprising: Multiple voltage-controlled capacitors, each voltage-controlled capacitor being at least partially located in the second level between the third memory array and the fourth memory array.

13. A method comprising: A sensing component is formed, which is operable for sensing memory cells of a memory die; A column decoder is formed to form the memory die, the column decoder being operable to couple with the sensing component; A first memory array is formed, which is associated with a first level on the substrate of the memory die. The first memory array includes a first subgroup of the memory cells and a plurality of first digital lines, each of which is operable to be coupled to the column decoder via a corresponding first transistor of the first level. A second memory array is formed, which is associated with the first level. The second memory array includes a second subgroup of the memory cells and a plurality of second digital lines, each of which is operable to be coupled to the column decoder via a corresponding second transistor of the first level. A third memory array is formed, which is associated with a second level on the substrate of the memory die. The third memory array includes a third subgroup of the memory cells and a plurality of third digital lines, each of which is operable to couple to the column decoder via a corresponding third transistor of the first level. and A fourth memory array is formed, which is associated with the second level. The fourth memory array includes a fourth subgroup of the memory cells and a plurality of fourth digital lines, each of which is operable to couple to the column decoder via a corresponding fourth transistor of the first level.

14. The method of claim 13, further comprising: A plurality of conductors are formed in the first layer, each conductor being coupled to one of the first transistors, one of the second transistors, one of the third transistors, one of the fourth transistors, and the column decoder.

15. The method of claim 14, further comprising forming on each of the plurality of conductors: The channel portion of one of the first transistors is at least partially based on a corresponding set of one or more first semiconductor pillars forming contact with the conductors of the plurality of conductors; The channel portion of one of the second transistors is at least partially based on a corresponding set of one or more second semiconductor pillars forming contact with the conductors of the plurality of conductors; The channel portion of one of the third transistors is at least partially based on a corresponding set of one or more third semiconductor pillars forming contact with the conductors of the plurality of conductors; and The channel portion of one of the fourth transistors is at least partially based on a corresponding set of one or more fourth semiconductor pillars forming contact with the conductors of the plurality of conductors.

16. The method of claim 15, further comprising: One or more first gate conductors are formed in the first layer, each first gate conductor being operable to modulate the conductivity of the channel portion of each of the first transistors; One or more second gate conductors are formed in the first layer, each second gate conductor being operable to modulate the conductivity of the channel portion of each of the second transistors; One or more third gate conductors are formed in the first layer, each third gate conductor being operable to modulate the conductivity of the channel portion of each of the third transistors; and One or more fourth gate conductors are formed in the first layer, each fourth gate conductor being operable to modulate the conductivity of the channel portion of each of the fourth transistors.

17. A method comprising: Identifying memory cell rows of a first memory array for access operations on a memory die, the memory die comprising: a first memory array in a first layer above a substrate of the memory die; a second memory array of the memory die in the first layer; a third memory array of the memory die in a second layer above the substrate; and a fourth memory array of the memory die in the second layer; and The memory cell row is coupled to a column decoder of the memory die at least in part based on the identification, wherein coupling the memory cell row to the column decoder includes: The memory cell rows are coupled to a plurality of digital lines of the first memory array, at least in part, based on activating a plurality of first transistors of the first level; and The plurality of digital lines of the first memory array are coupled to the column decoder, at least in part, based on activating a plurality of second transistors of the second level.

18. The method of claim 17, further comprising: The second memory cell row of the second memory array is isolated from the column decoder at least in part based on the identification, wherein the isolation of the second memory cell row from the column decoder includes: The second memory cell row is coupled to a plurality of digital lines of the second memory array, at least in part, based on activating a plurality of third transistors of the first level; and The plurality of digital lines of the second memory array are isolated from the column decoder, at least in part, by deactivating the plurality of fourth transistors of the second level.

19. The method of claim 17, further comprising: Isolating the third memory cell row of the third memory array from the column decoder, at least in part based on the identification, wherein isolating the third memory cell row from the column decoder includes: The third memory cell row is coupled to a plurality of digital lines of the third memory array, at least in part, based on activating a plurality of fifth transistors of the second level; and The plurality of digital lines of the third memory array are isolated from the column decoder, at least in part, based on deactivating the plurality of sixth transistors of the second level.

20. The method of claim 19, further comprising: The plurality of digital lines of the third memory array are coupled to the plurality of sixth transistors at least in part based on activating the plurality of seventh transistors of the second level and at least in part based on enabling access to the memory die.

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