Data transfer circuitry and memory

Abstract

The embodiment of the present application relates to a kind of data transmission circuit and memory, the data transmission circuit, comprising data write module, the data write module includes: logic operation unit, for obtaining the data signal to be written from data bus via data write node, and in response to the write enable signal of external input, according to the data signal to be written respectively output pull-up enable signal and pull-down enable signal, the pull-up enable signal and the pull-down enable signal time enable effective;Pull-up unit is connected with the logic operation unit, for outputting global data signal according to the pull-up enable signal of enable effective;Pull-down unit is connected with the logic operation unit, for outputting global data signal according to the pull-down enable signal of enable effective;Wherein, the level state of the global data signal is identical with the level state of the data signal to be written, and the global data signal is used to write storage unit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of memory, and in particular, to a data transmission circuit and a memory. BACKGROUND

[0002] Semiconductor memory is a kind of memory using semiconductor circuit for access, among which, dynamic random access memory (DRAM) is widely used in various fields due to its fast storage speed and high integration. In some miniaturized electronic devices, small size and high integration semiconductor memory needs to be correspondingly arranged. However, there are too many wirings in the data transmission circuit used for supporting data read / write process, and the area of the data transmission circuit is large, which greatly affects the application prospect of semiconductor memory in miniaturized electronic devices. SUMMARY

[0003] Embodiments of the present application provide a data transmission circuit and a memory, which can optimize the number of wirings in the data transmission circuit, thereby reducing the overall area of the data transmission circuit.

[0004] A data transmission circuit, comprising a data write-in module, the data write-in module comprising:

[0005] a logic operation unit, configured to acquire a to-be-written data signal from a data bus via a data write-in node, and in response to an externally input write enable signal, output an up enable signal and a down enable signal respectively according to the to-be-written data signal, the up enable signal and the down enable signal being enabled in time sequence;

[0006] an up unit, connected with the logic operation unit, configured to output a global data signal according to the up enable signal which is enabled;

[0007] a down unit, connected with the logic operation unit, configured to output a global data signal according to the down enable signal which is enabled;

[0008] wherein, the level state of the global data signal is the same as that of the to-be-written data signal, and the global data signal is used for writing into a storage unit.

[0009] In one of the embodiments, the logic operation unit is configured to generate the up enable signal and the down enable signal in response to the write enable signal and a pre-charge enable signal, and the logic operation unit comprises:

[0010] a first NOT gate, an input end of the first NOT gate being configured to receive the pre-charge enable signal;

[0011] an AND gate, one input end of the AND gate being used for receiving the write enable signal, another input end of the AND gate being used for receiving the data signal to be written;

[0012] a first NOR gate, a first input end of the first NOR gate being connected with an output end of the AND gate, a second input end of the first NOR gate being connected with an output end of the first NAND gate, and an output end of the first NOR gate being connected with the pull-up unit.

[0013] In one of the embodiments, the logic operation unit further comprises:

[0014] a first NAND gate, a first input end of the first NAND gate being used for receiving a pre-charge enable signal, and a second input end of the first NAND gate being used for receiving the write enable signal;

[0015] a second NOR gate, a first input end of the second NOR gate being used for receiving the data signal to be written, a second input end of the second NOR gate being connected with an output end of the first NAND gate, and an output end of the second NOR gate being connected with the pull-down unit.

[0016] In one of the embodiments, the output end of the first NOR gate is further connected with the pull-down unit.

[0017] In one of the embodiments, the data reading module further comprises:

[0018] an input unit, used for receiving a global data signal in response to an externally input read enable signal;

[0019] a reference unit, used for receiving a reference data signal in response to the read enable signal;

[0020] a pre-charge unit, connected with the input unit at a first node and connected with the reference unit at a second node, and used for pre-charging the first node and the second node to a preset level respectively in response to a pre-charge enable signal;

[0021] an output unit, connected with the input unit and the reference unit respectively, used for generating a read data signal according to the global data signal and the reference data signal, and transmitting the read data signal to the data bus through a data reading node.

[0022] In one of the embodiments, the data reading module further comprises:

[0023] a pulse width adjusting unit, connected with the input unit and the reference unit respectively, used for adjusting the read enable signal according to a pre-charge enable signal to generate an enable adjusting signal;

[0024] The pulse width of the enable adjustment signal is less than the pulse width of the read enable signal and less than the width of the pre-charge enable signal.

[0025] In one embodiment, the input unit comprises:

[0026] A first read transistor, a control terminal of the first read transistor is configured to receive the global data signal, a first terminal of the first read transistor is connected with the pulse width adjustment unit, and a second terminal of the first read transistor is connected with the first node.

[0027] In one embodiment, the input unit further comprises:

[0028] A second read transistor, a control terminal of the second read transistor is configured to receive the global data signal, a first terminal of the second read transistor is connected with the first terminal of the first read transistor, and a second terminal of the second read transistor is connected with the second terminal of the first read transistor.

[0029] In one embodiment, the input unit further comprises:

[0030] A first switch, the first switch comprises two first terminals and one second terminal, one first terminal of the first switch is configured to receive the global data signal, the other first terminal of the first switch is grounded, and the second terminal of the first switch is connected with the control terminal of the second read transistor, the first switch is configured to select transmission of the global data signal or a ground signal to the control terminal of the second read transistor.

[0031] In one embodiment, the input unit further comprises:

[0032] A first control circuit, configured to generate an adjustment control signal according to the global data signal and a first control signal.

[0033] A third read transistor, a control terminal of the third read transistor is connected with the first control circuit and configured to receive the adjustment control signal, a first terminal of the third read transistor is connected with the first terminal of the first read transistor, and a second terminal of the third read transistor is connected with the second terminal of the first read transistor.

[0034] In one embodiment, the reference unit comprises:

[0035] A fourth read transistor, a control terminal of the fourth read transistor is configured to receive the reference data signal, a first terminal of the fourth read transistor is configured to receive the enable adjustment signal, and a second terminal of the fourth read transistor is connected with the second node.

[0036] In one of the embodiments, the reference unit further comprises:

[0037] A second control circuit configured to generate a reference control signal according to a second control signal.

[0038] A fifth read transistor, a control terminal of the fifth read transistor is connected with the second control circuit, a first terminal of the fifth read transistor is connected with the first terminal of the fourth read transistor, and a second terminal of the fifth read transistor is connected with the second terminal of the fourth read transistor.

[0039] In one of the embodiments, the number of read transistors connected with the first node is the same as the number of read transistors connected with the second node.

[0040] In one of the embodiments, the reference unit comprises:

[0041] A sixth read transistor, a control terminal of the sixth read transistor is configured to receive the reference data signal, a first terminal of the sixth read transistor is configured to receive the enable adjustment signal, and a second terminal of the sixth read transistor is connected with the first terminal of the fourth read transistor, and the fourth read transistor receives the enable adjustment signal through the sixth read transistor.

[0042] A second switch, two terminals of the second switch are connected with the first terminal of the sixth read transistor and the second terminal of the sixth read transistor respectively.

[0043] In one of the embodiments, the reference unit further comprises:

[0044] A second control circuit configured to generate a reference control signal according to a second control signal.

[0045] A seventh read transistor, a control terminal of the seventh read transistor is connected with the second control circuit, a first terminal of the seventh read transistor is connected with the first terminal of the sixth read transistor, and a second terminal of the seventh read transistor is connected with the second terminal of the sixth read transistor.

[0046] In one of the embodiments, the reference unit further comprises:

[0047] At least one matching component connected in parallel, each of the matching components being connected to the second node respectively, the matching component being used for matching the second coupling capacitance at the second node with the first coupling capacitance at the first node.

[0048] In one of the embodiments, the matching component comprises:

[0049] A matching transistor, a control end of the matching transistor being connected to the second node, a first end and a second end of the matching transistor being connected to ground respectively.

[0050] In one of the embodiments, the matching component comprises:

[0051] A matching capacitor, one end of the matching capacitor being connected to the second node, the other end of the matching capacitor being connected to ground.

[0052] In one of the embodiments, the matching component further comprises:

[0053] A third switch, one end of the third switch being connected to the second node, the other end of the third switch being connected to the matching capacitor.

[0054] In one of the embodiments, the output unit comprises two signal output circuits, the two signal output circuits being a first output circuit and a second output circuit respectively, each of the signal output circuits comprising a first input end, a second input end and an output end;

[0055] The first input end of the first output circuit is connected to the first node, the first input end of the second output circuit is connected to the second node, the output end of the first output circuit is connected to the second input end of the second output circuit, the second input end of the first output circuit is connected to the output end of the second output circuit; wherein,

[0056] The node at which the output end of the first output circuit is connected to the second input end of the second output circuit is used for outputting the readout data signal, the node at which the second input end of the first output circuit is connected to the output end of the second output circuit is used for outputting the inverted signal of the readout data signal.

[0057] In one of the embodiments, the signal output circuit comprises:

[0058] An eighth read transistor, a control end of the eighth read transistor being used as the first input end of the signal output circuit, a first end of the eighth read transistor being connected to high level, a second end of the eighth read transistor being used as the output end of the signal output circuit;

[0059] a ninth read transistor, a control terminal of the ninth read transistor being connected with a control terminal of the eighth read transistor, a first terminal of the ninth read transistor being connected with a second terminal of the eighth read transistor;

[0060] a tenth read transistor, a control terminal of the tenth read transistor being a second input terminal of the signal output circuit, a first terminal of the tenth read transistor being connected with a second terminal of the eighth read transistor, a second terminal of the tenth read transistor being grounded;

[0061] an eleventh read transistor, a control terminal of the eleventh read transistor being connected with a control terminal of the tenth read transistor, a first terminal of the eleventh read transistor being connected with a high level, a second terminal of the eleventh read transistor being connected with a second terminal of the eighth read transistor.

[0062] In one of the embodiments, the output unit further comprises:

[0063] a first reset transistor, a control terminal of the first reset transistor being used for receiving an externally input reset signal, a first terminal of the first reset transistor being connected with a high level, a second terminal of the first reset transistor being connected with a second terminal of the eighth read transistor;

[0064] a second reset transistor, a control terminal of the second reset transistor being used for receiving the reset signal, a first terminal of the second reset transistor being connected with a second terminal of the tenth read transistor, a second terminal of the second reset transistor being grounded.

[0065] A memory comprises:

[0066] a data bus, provided with a data write node;

[0067] a plurality of storage units;

[0068] a plurality of data transmission circuits as described above, connected with the data write node and the storage units respectively, the data transmission circuit being used for acquiring a to-be-written data signal from the data bus through the data write node, generating a global data signal according to the to-be-written data, the level state of the global data signal being the same as that of the to-be-written data signal, and writing the global data signal into the corresponding storage unit.

[0069] The aforementioned data transmission circuit and memory, wherein the data transmission circuit includes a data writing module, the data writing module comprising: a logic operation unit, configured to acquire a data signal to be written from a data bus via a data writing node, and in response to an externally input write enable signal, output a pull-up enable signal and a pull-down enable signal respectively according to the data signal to be written, wherein the pull-up enable signal and the pull-down enable signal are enabled in a time-division multiplexing manner; a pull-up unit, connected to the logic operation unit, configured to output a global data signal according to the enabled pull-up enable signal; and a pull-down unit, connected to the logic operation unit, configured to output a global data signal according to the enabled pull-down enable signal; wherein the level state of the global data signal is the same as the level state of the data signal to be written, and the global data signal is used to write to the memory unit. The data transmission circuit of this embodiment processes the data signal to be written through the logic operation unit and generates a global data signal through the pull-up unit and the pull-down unit, requiring only one signal trace to transmit the global data signal, thereby greatly reducing the number of traces in the data transmission circuit, i.e., providing a data transmission circuit with a smaller area. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0071] Figure 1 This is a structural block diagram of a data writing module according to one embodiment;

[0072] Figure 2 This is one of the structural schematic diagrams of a data writing module according to an embodiment;

[0073] Figure 3 This is a second schematic diagram of the structure of a data writing module according to one embodiment;

[0074] Figure 4 This is a structural block diagram of a data reading module according to one embodiment;

[0075] Figure 5 This is one of the partial structural diagrams of a data reading module according to an embodiment;

[0076] Figure 6 for Figure 5 Signal timing diagram of the pulse width modulation unit in the embodiment;

[0077] Figure 7 This is a schematic diagram of the structure of a first control circuit according to an embodiment;

[0078] Figure 8 Structure diagram of a second control circuit of an embodiment;

[0079] Figure 9 Structure diagram of an output unit of an embodiment;

[0080] Figure 10 Structure diagram of an output unit of an embodiment;

[0081] Figure 11 Partial structure diagram of a data reading module of an embodiment;

[0082] Figure 12 Partial structure diagram of a data reading module of an embodiment;

[0083] Figure 13 Partial structure diagram of a data reading module of an embodiment.

[0084] Element number explanation:

[0085] Logic operation unit: 100; first NOT gate: 110; AND gate: 120; first OR NOT gate: 130; first NAND gate: 140; second OR NOT gate: 150; pull-up unit: 200; pull-down unit: 300; input unit: 400; first switch: 410; first control circuit: 420; reference unit: 500; second control circuit: 510; second switch: 520; matching component: 530; third switch: 531; pre-charge unit: 600; output unit: 700; first output circuit: 710; second output circuit: 720; pulse width adjustment unit: 800. DETAILED DESCRIPTION

[0086] In order to facilitate the understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are given in the accompanying drawings of the present application. However, the embodiments of the present application can be realized in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0087] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present application belong. The terminology used in the description of the embodiments of the present application herein is only for the purpose of describing the specific embodiments of the present application and is not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0088] It can be appreciated that the terms "first", "second", and the like as used herein can be used to describe various elements, but the elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first node YIONloc can be referred to as a second node YIOloc, and similarly, a second node YIOloc can be referred to as a first node YIONloc without departing from the scope of the present application. Both the first node YIONloc and the second node YIOloc are nodes, but they are not the same node.

[0089] In addition, the terms "first", "second", and the like are used only to describe the purpose and should not be construed as indicating or implying relative importance or implying the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise explicitly and specifically limited.

[0090] Embodiments of the present application provide a data transmission circuit, applied to a semiconductor memory, the semiconductor memory comprising a plurality of memory cells, after the data to be stored is input from an interface, it is transmitted to the memory cells for storage in turn through a data bus, a global data line, a local data line and a bit line. Similarly, after the data to be read is read from the memory cell, it is transmitted to the interface for output in turn through the bit line, the local data line, the global data line and the data bus. The data transmission circuit of the embodiments of the present application is connected with the data bus and the global data line respectively, and is used for transmitting data signals between the data bus and the global data line. The data transmission circuit of the embodiments of the present application comprises a data write module, and the data write module is used for transmitting data on the data bus to the global data line. Specifically, Figure 1 is a structural block diagram of the data write module of an embodiment, with reference to Figure 1 In the present embodiment, the data write module is included, and the data write module comprises a logic operation unit 100, a pull-up unit 200 and a pull-down unit 300.

[0091] The logic operation unit 100 is configured to obtain the data signal Data to be written from the data bus via the data writing node, and output a pull-up enable signal and a pull-down enable signal according to the data signal Data to be written in response to an externally input write enable signal WrEn. Specifically, when the write enable signal WrEn is disabled, the logic operation unit 100 outputs the pull-up enable signal and the pull-down enable signal in a preset level state, i.e., the signal output by the logic operation unit 100 is irrelevant to the signal on the data bus. When the write enable signal WrEn is enabled, the logic operation unit 100 generates the pull-up enable signal and the pull-down enable signal according to the level state of the data signal Data to be written. The logic operation unit 100 can include a plurality of logic gates, but the number and type of the logic gates are not specifically limited in the embodiment.

[0092] The pull-up unit 200 is connected to the logic operation unit 100, and is configured to output a global data signal YIO according to the pull-up enable signal that is enabled. The pull-down unit 300 is connected to the logic operation unit 100, and is configured to output the global data signal YIO according to the pull-down enable signal that is enabled, the global data signal YIO being used for writing the storage unit. The pull-up unit 200 can be understood as a circuit structure capable of pulling up the level state of the global data signal YIO to a high level, and the pull-down unit 300 can be understood as a circuit structure capable of pulling down the level state of the global data signal YIO to a low level. In the embodiment, the pull-up enable signal and the pull-down enable signal are enabled at different times, so that the global data signal YIO has a determined level state. The determined level state specifically refers to the same level state as the data signal Data to be written.

[0093] The enable mode includes high-level enable and low-level enable. For example, the pull-up unit 200 and the pull-down unit 300 can have the same enable mode, and the level states of the pull-up enable signal and the pull-down enable signal are always opposite, so that the pull-up enable signal and the pull-down enable signal are enabled at different times. For another example, the pull-up unit 200 and the pull-down unit 300 can also have opposite enable modes, and the level states of the pull-up enable signal and the pull-down enable signal are always the same, so that the pull-up enable signal and the pull-down enable signal are enabled at different times. It can be understood that the structure of the pull-up unit 200 and the pull-down unit 300 is not specifically limited in the embodiment, and the pull-up unit 200 and the pull-down unit 300 can each include a separate element or a plurality of connected elements. It should be noted that, for the sake of simplicity, in each embodiment of the present application, one of the pull-up unit 200 and the pull-down unit 300 is enabled in a high level, and the other is enabled in a low level.

[0094] In the embodiment, the logic operation unit 100 processes the data signal Data to be written, and generates a global data signal YIO through the pull-up unit 200 and the pull-down unit 300. Therefore, only one signal line is needed to transmit the global data signal YIO, so that the number of lines in the data transmission circuit is greatly reduced. That is, a data transmission circuit with smaller area is provided.

[0095] Figure 2 FIG. 1 shows a structure diagram of a data write module according to an embodiment of the present application; Figure 2 The logic operation unit 100 of the embodiment is used to generate the pull-up enable signal and the pull-down enable signal in response to the write enable signal WrEn and the pre-charge enable signal EQ. For the sake of simplicity, the pull-up unit 200 includes a low-level enabled PMOS tube, and the pull-down unit 300 includes a high-level enabled NMOS tube in the embodiments of the present application. In the embodiment, the logic operation unit 100 includes a first NOT gate 110, an AND gate 120 and a first NOR gate 130.

[0096] The input end of the first NOT gate 110 is used to receive the pre-charge enable signal EQ. One input end of the AND gate 120 is used to receive the write enable signal WrEn, and the other input end of the AND gate 120 is used to receive the data signal Data to be written. The first input end of the first NOR gate 130 is connected with the output end of the AND gate 120, the second input end of the first NOR gate 130 is connected with the output end of the first NOT gate 110, and the output end of the first NOR gate 130 is connected with the control end of the pull-up unit 200.

[0097] In the data writing stage, the write enable signal WrEn is high, thus the signal outputted by the AND gate 120 follows the data signal Data inputted at the input end. One input end of the first NOR gate 130 is connected with the output end of the AND gate 120, and the other input end of the first NOR gate 130 is used to receive the inverse pre-charge enable signal EQN, which is used to switch the data writing module to the pre-charge stage or the data writing stage. Further, the output end of the first NOR gate 130 can also be connected with the control end of the pull-down unit 300, so as to control the pull-up unit 200 and the pull-down unit 300 based on one signal, thus saving the number of signal lines. In the pre-charge stage, the pre-charge enable signal EQ is low, thus the signal outputted by the first NOR gate 110 is high, and if one input end of the first NOR gate 130 is high, the outputted signal must be low, thus keeping the first write signal received by the control end of the pull-up unit 200 and the pull-down unit 300 unchanged. In the data writing stage, the pre-charge enable signal EQ and the write enable signal WrEn are both high, thus the global data signal YIO corresponds to the data signal Data to be written.

[0098] Figure 3 FIG. 2 is a structural schematic diagram of a data writing module according to an embodiment; Figure 3 In this embodiment, the logic operation unit 100 further comprises a first NAND gate 140 and a second NOR gate 150.

[0099] The first input end of the first NAND gate 140 is used to receive the pre-charge enable signal EQ, and the second input end of the first NAND gate 140 is used to receive the write enable signal WrEn. The first input end of the second NOR gate 150 is used to receive the data signal Data to be written, the second input end of the second NOR gate 150 is connected with the output end of the first NAND gate 140, and the output end of the second NOR gate 150 is connected with the control end of the pull-down unit 300.

[0100] The pull-up unit 200 is controlled by the first NOR gate 130. The control method is the same as the previous embodiment, which will not be repeated here. In the pre-charge phase, the pre-charge enable signal EQ is low, and the signal output by the first NAND gate 140 is high. If one input of the second NOR gate 150 is high, the output of the second NOR gate 150 must be low, thereby keeping the first write signal received by the control terminals of the pull-up unit 200 and the pull-down unit 300 unchanged. In the data write phase, the pre-charge enable signal EQ and the write enable signal WrEn are both high, thereby making the global data signal YIO correspond to the data signal Data to be written. In this embodiment, the pull-up unit 200 and the pull-down unit 300 are controlled by two logic gates respectively and one-to-one, which can effectively improve the control reliability of the pull-up unit 200 and the pull-down unit 300.

[0101] In one embodiment, the data transmission circuit includes a data reading module for transmitting data on the global data line to the data bus. Specifically, Figure 4 The structure block diagram of the data reading module of one embodiment is shown in Figure 4 In this embodiment, the data reading module includes an input unit 400, a reference unit 500, a pre-charge unit 600, and an output unit 700.

[0102] The input unit 400 is configured to receive the global data signal YIO in response to an externally input read enable signal RdEn. The reference unit 500 is configured to receive a reference data signal Ref in response to the read enable signal RdEn. The pre-charge unit 600 is connected to a first node YIONloc with the input unit 400 and connected to a second node YIOloc with the reference unit 500. The pre-charge unit 600 is configured to pre-charge the first node YIONloc and the second node YIOloc to a preset level in response to a pre-charge enable signal EQ before data reading. The output unit 700 is connected to the input unit 400 and the reference unit 500, respectively, and is configured to generate a read data signal Data according to the global data signal YIO and the reference data signal Ref, and transmit the read data signal Data to the data bus through a data reading node. In this embodiment, first, in the pre-charge phase, the first node YIONloc and the second node YIOloc are pre-charged to enable accurate and fast reading of the read data. Then, in the data reading phase, the reference data signal Ref received by the reference unit 500 can adjust the process and result of the read data, thereby improving the accuracy of data reading. According to the performance test results of the semiconductor memory before leaving the factory, the specific reference data signal Ref can be pre-set and stored in the semiconductor memory.

[0103] Figure 5Fig. 1 is a schematic diagram of a partial structure of a data reading module according to an embodiment of the present application; Figure 5 In the embodiment, the pre-charge unit 600 includes transistors T14-T22. Specifically, the transistors T14-T16 constitute a pre-charge circuit, the first terminal of the transistor T14 is connected to a power supply terminal, the first terminal of the transistor T15 is connected to the power supply terminal, the first terminal of the transistor T16 is connected to the second terminal of the transistor T14, and the second terminal of the transistor T16 is connected to the second terminal of the transistor T15. The control terminals of the above three transistors simultaneously receive a pre-charge enable signal EQ, thereby realizing fast pre-charge. The transistors T17-T20 collectively constitute a positive feedback circuit, i.e., the transistors T17-T20 constitute an amplification circuit. In the data reading stage, the signals of the first node YIONloc and the second node YIOloc are amplified, so that the signal of the global data line YIO is transmitted to the subsequent output unit. Specifically, the control terminals of the transistors T17 and T19 are respectively connected to the second terminal of the transistor T16, the control terminals of the transistors T18 and T20 are respectively connected to the first terminal of the transistor T16, the first terminals of the transistors T17 and T18 are respectively connected to the power supply terminal, the second terminal of the transistor T17 is connected to the first terminal of the transistor T19, the second terminal of the transistor T18 is connected to the first terminal of the transistor T20, and the second terminals of the transistors T19 and T20 are respectively connected to the first terminal of the transistor T11. In some embodiments, the pre-charge circuit further includes the transistors T21 and T22, the control terminals of which respectively receive the pre-charge enable signal EQ, the first terminals of the transistors T21 and T22 are respectively connected to the power supply terminal, the second terminal of the transistor T21 is connected to the first node YIONloc, and the second terminal of the transistor T22 is connected to the second node YIOloc. It should be noted that, Figure 5 The positive feedback circuit (amplification circuit) in the embodiment is only used for illustrative purposes, and does not limit the protection scope of the present application. Other positive feedback circuits having the same function also belong to the protection scope of the present application. It should be noted that the embodiment Figure 5 The amplification circuit is attributed to the pre-charge unit, which is only for the convenience of description and does not limit the protection scope of the present application. Those skilled in the art should understand that the pre-charge circuit and the amplification circuit realize different functions. In the pre-charge stage, the pre-charge circuit works and the amplification circuit does not work. In the data reading stage, the pre-charge circuit does not work and the amplification circuit works to amplify the global data signal.

[0104] Continuing to refer to Figure 5In some embodiments, the data reading module further includes a pulse width adjustment unit 800. The pulse width adjustment unit 800 is connected to the input unit 400 and the reference unit 500, respectively, and is used to adjust the read enable signal RdEn according to the precharge enable signal EQ to generate an enable adjustment signal. The input unit 400 and the reference unit 500 are respectively used to generate corresponding data signals in response to the enable adjustment signal. That is, the input unit 400 controls the data signal of the first node YIONloc in response to the enable adjustment signal, and the reference unit 500 controls the data signal of the second node YIOloc in response to the enable adjustment signal. Figure 6 for Figure 5 The signal timing diagram in the pulse width adjustment unit 800 of the embodiment is shown in the reference diagram. Figure 6 The pulse width of the enable adjustment signal is smaller than the pulse width of the read enable signal RdEn, and smaller than the width of the precharge enable signal EQ when it is disabled. In this embodiment, based on the wider read enable signal RdEn and the inverted precharge enable signal EQN, a signal with a pulse width of less than 500ps can be generated, thereby achieving a more accurate signal generation function.

[0105] Continue to refer to Figure 5 In one embodiment, the input unit 400 includes a first read transistor T1. The control terminal of the first read transistor T1 is used to receive the global data signal YIO. A first terminal of the first read transistor T1 is connected to the pulse width adjustment unit 800, and a second terminal of the first read transistor T1 is connected to the first node YIONloc. When the global data signal YIO is high, the first read transistor T1 is turned on, transmitting an enable adjustment signal to the first node YIONloc. The level of the enable adjustment signal can be adjusted by a switching structure in the pulse width adjustment unit 800, thereby controlling the signal transmitted to the first node YIONloc. When the global data signal YIO is low, the first read transistor T1 is turned off, and the level of the first node YIONloc remains unchanged. Based on the above structure, the input unit 400 can transmit the data information carried by the global data signal YIO to the first node YIONloc.

[0106] Further, the input unit 400 further comprises a second read transistor T2. A control terminal of the second read transistor T2 is configured to receive the global data signal YIO, a first terminal of the second read transistor T2 is connected with the first terminal of the first read transistor T1, and a second terminal of the second read transistor T2 is connected with the second terminal of the first read transistor T1. Further, the input unit 400 further comprises a first switch 410. The first switch 410 comprises two first terminals and one second terminal. One first terminal of the first switch 410 is configured to receive the global data signal YIO, the other first terminal of the first switch 410 is grounded, and the second terminal of the first switch 410 is connected with the control terminal of the second read transistor T2. The first switch 410 is configured to select the global data signal YIO or the ground signal to be transmitted to the control terminal of the second read transistor T2. When the first switch 410 selects the ground path, the second read transistor T2 is always off. When the first switch 410 selects the global data signal YIO, the second read transistor T2 is turned on or off according to the level state of the global data signal YIO, i.e., the second read transistor T2 is synchronized with the first read transistor T1 and transmits the same enable adjustment signal, so that the response speed of the global data signal YIO can be effectively improved. It can be understood that the semiconductor memory comprises a plurality of data reading modules, and due to the difference in process, the signal transmission speeds of different data reading modules are not completely the same. Therefore, by setting the first switch 410, the response speed of the reading module can be more flexibly adjusted, and the reading performance of the semiconductor memory can be improved.

[0107] In one embodiment, the input unit 400 further comprises a first control circuit 420 and a third read transistor T3. The first control circuit 420 is configured to generate an adjustment control signal according to the global data signal YIO and a first control signal. In some examples, the first control signal can be a signal generated according to the fuse state. In other examples, the first control signal can also be a signal input from outside the memory. A control terminal of the third read transistor T3 is connected with the first control circuit 420 and configured to receive the adjustment control signal. A first terminal of the third read transistor T3 is connected with the first terminal of the first read transistor T1, and a second terminal of the third read transistor T3 is connected with the second terminal of the first read transistor T1. Specifically, Figure 7 A structure diagram of the first control circuit 420 of one embodiment is shown in FIG. 4B. As shown in FIG. 4B, the first control circuit 420 comprises a first input terminal 421, a second input terminal 422, a first output terminal 423, and a second output terminal 424. The first input terminal 421 is configured to receive the global data signal YIO, and the second input terminal 422 is configured to receive the first control signal. The first output terminal 423 is connected with the control terminal of the third read transistor T3, and the second output terminal 424 is connected with the control terminal of the second read transistor T2. Figure 7The first control circuit 420 includes a pull-up transistor and a pull-down transistor. The first terminal of the pull-up transistor is connected to the power supply terminal, and the second terminal of the pull-up transistor is connected to the first terminal of the pull-down transistor. The second terminal of the pull-down transistor is grounded. The two transistors have different enabling methods. Each transistor receives the same first control signal and, under the control of the first control signal, outputs a corresponding adjustment control signal. For example... Figure 7 As shown, if the first control signal is a time-division multiplexing signal, the first control circuit 420 will also output different adjustment control signals YIO_opt1 and YIO_opt through one output terminal in a time-division multiplexing manner. It can be understood that the number of first control signals corresponds to the number of third read transistors T3 in the input unit 400, and the level of the first control signal can also be set according to sensitivity requirements. In this embodiment, using multiple first control signals allows for more flexible control of the sensitivity characteristics of the input unit 400, while also controlling manufacturing defects, thereby improving the reliability of the semiconductor memory.

[0108] Continue to refer to the diagram Figure 5 In one embodiment, the reference unit 500 includes a fourth readout transistor T4. The control terminal of the fourth readout transistor T4 is used to receive the reference data signal Ref, the first terminal of the fourth readout transistor T4 is used to receive the enable adjustment signal, and the second terminal of the fourth readout transistor T4 is connected to the second node YIOloc, thereby adjusting the voltage of the second node YIOloc according to the reference data signal Ref.

[0109] Furthermore, the reference unit 500 also includes a second control circuit 510 and a fifth readout transistor T5. The second control circuit 510 is used to generate a reference control signal based on the second control signal. The control terminal of the fifth readout transistor T5 is connected to the second control circuit 510 and is used to receive the reference control signal. The first terminal of the fifth readout transistor T5 is connected to the first terminal of the fourth readout transistor T4, and the second terminal of the fifth readout transistor T5 is connected to the second terminal of the fourth readout transistor T4. Specifically, Figure 8 This is a schematic diagram of the structure of the second control circuit 510 according to one embodiment, with reference to... Figure 8 The second control circuit 510 includes a pull-up transistor and a pull-down transistor. The first terminal of the pull-up transistor is connected to the power supply terminal, and the second terminal of the pull-up transistor is connected to the first terminal of the pull-down transistor. The second terminal of the pull-down transistor is grounded. The two transistors have different enabling methods. Each transistor receives the same second control signal and, under the control of the second control signal, outputs a corresponding adjustment control signal. For example... Figure 8As shown, if the second control signal is a time-division multiplexing signal, the second control circuit 510 will also output different adjustment control signals Ref_opt2, Ref_opt1, and Ref_opt through one output terminal in a time-division multiplexing manner. It can be understood that the number of second control signals corresponds to the number of fourth read transistors T4 in the input unit 400, and the level of the second control signals can also be set according to sensitivity requirements. In this embodiment, using multiple second control signals allows for more flexible control of the sensitivity characteristics of the reference unit 500, while also controlling manufacturing defects, thereby improving the reliability of the semiconductor memory.

[0110] Figure 9 This is one of the structural schematic diagrams of the output unit 700 in one embodiment, with reference to... Figure 9 In this embodiment, the output unit 700 includes two signal output circuits 710. The two signal output circuits 710 are a first output circuit 710 and a second output circuit 720, each including a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first output circuit 710 is connected to the first node YIONloc, the first input terminal of the second output circuit 720 is connected to the second node YIOloc, the output terminal of the first output circuit 710 is connected to the second input terminal of the second output circuit 720, and the second input terminal of the first output circuit 710 is connected to the output terminal of the second output circuit 720. The node connecting the output terminal of the first output circuit 710 to the second input terminal of the second output circuit 720 is used to output the read data signal Data, and the node connecting the second input terminal of the first output circuit 710 to the output terminal of the second output circuit 720 is used to output the inverted signal of the read data signal Data.

[0111] Specifically, the signal output circuit 710 comprises an eighth read transistor, a ninth read transistor, a tenth read transistor and an eleventh read transistor. The control terminal of the eighth read transistor is the first input terminal of the signal output circuit 710, the first terminal of the eighth read transistor is connected to a high level, and the second terminal of the eighth read transistor is the output terminal of the signal output circuit 710. The control terminal of the ninth read transistor is connected to the control terminal of the eighth read transistor, and the first terminal of the ninth read transistor is connected to the second terminal of the eighth read transistor. The control terminal of the tenth read transistor is the second input terminal of the signal output circuit 710, the first terminal of the tenth read transistor is connected to the second terminal of the eighth read transistor, and the second terminal of the tenth read transistor is grounded. The control terminal of the eleventh read transistor is connected to the control terminal of the tenth read transistor, the first terminal of the eleventh read transistor is connected to a high level, and the second terminal of the eleventh read transistor is connected to the second terminal of the eighth read transistor.

[0112] Based on Figure 9 In an embodiment, the working principle of the output unit 700 is described. If the level state of the first node YIONloc is a high level, the level state of the corresponding second node YIOloc is opposite, i.e., the level state of the second node YIOloc is a low level. The low level of the second node YIOloc turns on the eighth transistor in the second output circuit 720, thereby pulling the inverted signal of the read data signal Data to a low level, and correspondingly, the read data signal Data is a high level. If the level state of the first node YIONloc is a low level, the level state of the corresponding second node YIOloc is opposite, i.e., the level state of the second node YIOloc is a high level. The low level of the first node YIONloc turns on the eighth transistor in the first output circuit 710, thereby pulling the read data signal Data to a high level, and correspondingly, the inverted signal of the read data signal Data is a low level.

[0113] Figure 10 For the second structural schematic diagram of the output unit 700 of an embodiment, reference is made to FIG. 7B. Figure 10In the embodiment, the output unit 700 further comprises a first reset transistor T12 and a second reset transistor T13. The control terminal of the first reset transistor T12 is configured to receive an externally input reset signal, the first end of the first reset transistor T12 is connected to a high level, and the second end of the first reset transistor T12 is connected to the second end of the eighth read transistor. The control terminal of the second reset transistor T13 is configured to receive the reset signal, the first end of the second reset transistor T13 is connected to the second end of the tenth read transistor, and the second end of the second reset transistor T13 is grounded. By arranging the reset transistors, the read data signal Data line can be reset before data reading, thereby improving the reliability of data reading. Specifically, when the reset signal is at a low level, the first reset transistor T12 is turned on, thereby pulling the voltage on the read data signal Data line to a high level.

[0114] In one embodiment, the number of read transistors connected to the first node YIONloc is the same as the number of read transistors connected to the second node YIOloc. For example, the number of read transistors connected to the first node YIONloc and the number of read transistors connected to the second node YIOloc can be determined based on the load capacitance of the first node YIONloc and the load capacitance of the second node YIOloc. Figure 5 The data reading module of the embodiment further comprises a third read transistor T3 in the input unit 400, so that the first node YIONloc is connected to four read transistors, and the second node YIOloc is also connected to four read transistors. By the above arrangement, the load capacitances of the first node YIONloc and the second node YIOloc can be equal, so that the charge conditions of the two nodes in the initial state are the same, thereby improving the balance between the input unit 400 and the reference unit 500, and achieving more accurate reading of the global data signal YIO.

[0115] Figure 11 FIG. 2 is a partial structure diagram of a data reading module according to an embodiment of the present application. As shown in FIG. 2, the data reading module comprises an input unit 400, a reference unit 500, a first control circuit 420, an output unit 700, and a second control circuit 710. Figure 11 In the embodiment, the input unit 400, the pre-charge unit 600, and the pulse width adjustment unit 800 are the same as those of the embodiment, and the first control circuit 420 and the output unit 700 of the embodiment can also correspond to the first control circuit 420 and the output unit 700 of the embodiment. Figure 5 In the embodiment, the input unit 400, the pre-charge unit 600, and the pulse width adjustment unit 800 are the same as those of the embodiment, and the first control circuit 420 and the output unit 700 of the embodiment can also correspond to the first control circuit 420 and the output unit 700 of the embodiment. Figure 7 to Figure 10The reference unit 500 of the embodiment further comprises a sixth read transistor T6 and a second switch 520. The control terminal of the sixth read transistor T6 is configured to receive the reference data signal Ref, the first terminal of the sixth read transistor T6 is configured to receive the enable adjustment signal, and the second terminal of the sixth read transistor T6 is connected to the first terminal of the fourth read transistor T4. The second terminal of the fourth read transistor T4 receives the enable adjustment signal through the sixth read transistor T6. The two terminals of the second switch 520 are connected to the first terminal of the sixth read transistor T6 and the second terminal of the sixth read transistor T6, respectively.

[0116] Specifically, when the second switch 520 is closed, the sixth read transistor T6 is short-circuited, and the second terminal of the fourth read transistor T4 is directly connected to the pulse width adjustment unit 800, so that the enable adjustment signal output by the pulse width adjustment unit 800 can be quickly transmitted to the fourth read transistor T4. When the second switch 520 is turned on, the sixth read transistor T6 needs to be turned on or turned off in response to the reference data signal Ref. If the reference data signal Ref controls the fourth read transistor T4 and the sixth read transistor T6 to be turned on, the enable adjustment signal needs to pass through the sixth read transistor T6 before being transmitted to the fourth read transistor T4, thereby changing the transmission speed of the enable adjustment signal. It can be understood that the semiconductor memory includes a plurality of data reading modules, and due to the difference in process, the signal transmission speed of different data reading modules is not completely the same. Therefore, by setting the second switch 520, the response speed of the reading module can be more flexibly adjusted, thereby improving the reading performance of the semiconductor memory.

[0117] Continuing to refer to Figure 11 In one embodiment, the reference unit 500 further comprises a second control circuit 510 and a seventh read transistor T7. The second control circuit 510 is configured to generate a reference control signal according to a second control signal. It can be understood that the second control circuit 510 of the embodiment can refer to the second control circuit 510 of the embodiment of the pulse width adjustment unit 800, which will not be described here. Figure 8 In the embodiment, the second control signal can be used to more flexibly control the sensitivity characteristics of the reference unit 500, and at the same time, the process manufacturing defects can be controlled, thereby improving the reliability of the semiconductor memory.

[0118] Figure 12 For a partial structure diagram of the data reading module of one embodiment, refer to Figure 12In the embodiment, the reference unit 500 further comprises at least one matching component 530 connected in parallel. Each of the matching components 530 is connected to the second node YIOloc, and the matching component 530 is configured to match the second coupling capacitance at the second node YIOloc with the first coupling capacitance at the first node YIONloc. In the embodiment, by arranging the matching component 530, the load on the second node YIOloc can be increased, so that the load capacitances on the first node YIONloc and the second node YIOloc are equal, i.e., the charge conditions of the two nodes in the initial state are the same, and thus the balance between the input unit 400 and the reference unit 500 is improved, so as to achieve more accurate reading of the global data signal YIO. Further, referring to Figure 12 In the embodiment, the matching component 530 comprises a matching transistor. The control terminal of the matching transistor is connected to the second node YIOloc, and the first terminal and the second terminal of the matching transistor are grounded.

[0119] Figure 13 FIG. 4 is a partial structural schematic diagram of a data reading module according to an embodiment, referring to Figure 13 In the embodiment, the matching component 530 comprises a matching capacitor. One terminal of the matching capacitor is connected to the second node YIOloc, and the other terminal of the matching capacitor is grounded. Further, referring to Figure 13 In the embodiment, the matching component 530 further comprises a third switch 531. One terminal of the third switch 531 is connected to the second node YIOloc, and the other terminal of the third switch 531 is connected to the matching capacitor. In the embodiment, by arranging the matching capacitor, the capacitance on the second node YIOloc can be increased, so that the charge conditions of the two nodes in the initial state are the same, and thus the balance between the input unit 400 and the reference unit 500 is improved, so as to achieve more accurate reading of the global data signal YIO.

[0120] The embodiment of the present application further provides a memory, comprising a data bus, a plurality of storage units and a plurality of data transmission circuits as described above. The data bus is provided with a data write node, the data transmission circuits are connected with the data write node and the storage units respectively, the data write module in the data transmission circuit is used for obtaining a to-be-written data signal Data from the data bus through the data write node, generating a global data signal YIO according to the to-be-written data, the level state of the global data signal YIO being the same as that of the to-be-written data signal Data, and writing the global data signal YIO into the corresponding storage unit. Based on the data transmission circuit in the foregoing embodiment, the present application provides a memory with less wiring quantity and smaller size. Further, the data bus is further provided with a data read node, and the data read module in the data transmission circuit is used for transmitting the global data signal YIO to the data bus through the data read node.

[0121] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0122] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A data transmission circuit, characterized by The data write module comprises: a logic operation unit configured to obtain a to-be-written data signal from a data bus via a data write node, and output an up pull enable signal and a down pull enable signal respectively according to the to-be-written data signal in response to an externally input write enable signal, the up pull enable signal and the down pull enable signal being enabled at different times; an up pull unit connected with the logic operation unit, configured to output a global data signal according to the up pull enable signal enabled; a down pull unit connected with the logic operation unit, configured to output a global data signal according to the down pull enable signal enabled; wherein a level state of the global data signal is the same as that of the to-be-written data signal, and the global data signal is used for writing a storage unit; the logic operation unit is configured to generate the up pull enable signal and the down pull enable signal in response to the write enable signal and a pre-charge enable signal, and the logic operation unit comprises: a first NOT gate, an input end of the first NOT gate being configured to receive the pre-charge enable signal; an AND gate, one input end of the AND gate being configured to receive the write enable signal, and the other input end of the AND gate being configured to receive the to-be-written data signal; a first NOR gate, a first input end of the first NOR gate being connected with an output end of the AND gate, a second input end of the first NOR gate being connected with an output end of the first NOT gate, and an output end of the first NOR gate being connected with the up pull unit.

2. The data transmission circuit of claim 1, wherein, The logic operation unit further comprises: a first NAND gate, a first input end of the first NAND gate being configured to receive the pre-charge enable signal, and a second input end of the first NAND gate being configured to receive the write enable signal; a second NOR gate, a first input end of the second NOR gate being configured to receive the to-be-written data signal, a second input end of the second NOR gate being connected with an output end of the first NAND gate, and an output end of the second NOR gate being connected with the down pull unit.

3. The data transmission circuit of claim 1, wherein, The output end of the first NOR gate is further connected with the down pull unit.

4. The data transmission circuit of claim 1, wherein, The data read module comprises: an input unit configured to receive a global data signal in response to an externally input read enable signal; a reference unit configured to receive a reference data signal in response to the read enable signal; a pre-charge unit connected with the input unit at a first node and connected with the reference unit at a second node, the pre-charge unit being configured to pre-charge the first node and the second node to a preset level respectively in response to a pre-charge enable signal; an output unit connected with the input unit and the reference unit respectively, configured to generate a read data signal according to the global data signal and the reference data signal, and transmit the read data signal to a data bus via a data read node.

5. The data transmission circuit of claim 4, wherein, The data read module further comprises: a pulse width adjustment unit connected with the input unit and the reference unit respectively, configured to adjust the read enable signal to generate an enable adjustment signal according to a pre-charge enable signal; The pulse width of the enable adjustment signal is less than the pulse width of the read enable signal and less than the width of the pre-charge enable signal disablement. The input unit and the reference unit are configured to generate corresponding data signals in response to the enable adjustment signal.

6. The data transmission circuit of claim 5, wherein, The input unit comprises: A first read transistor, a control terminal of the first read transistor is configured to receive the global data signal, a first terminal of the first read transistor is connected with the pulse width adjustment unit, and a second terminal of the first read transistor is connected with the first node.

7. The data transmission circuit of claim 6, wherein, The input unit further comprises: A second read transistor, a control terminal of the second read transistor is configured to receive the global data signal, a first terminal of the second read transistor is connected with the first terminal of the first read transistor, and a second terminal of the second read transistor is connected with the second terminal of the first read transistor.

8. The data transmission circuit of claim 7, wherein, The input unit further comprises: A first switch, the first switch comprises two first terminals and one second terminal, one first terminal of the first switch is configured to receive the global data signal, the other first terminal of the first switch is grounded, and the second terminal of the first switch is connected with the control terminal of the second read transistor, the first switch is configured to select transmission of the global data signal or a ground signal to the control terminal of the second read transistor.

9. The data transmission circuit of claim 6, wherein, The input unit further comprises: A first control circuit, configured to generate an adjustment control signal according to a first control signal; A third read transistor, a control terminal of the third read transistor is connected with the first control circuit, configured to receive the adjustment control signal, a first terminal of the third read transistor is connected with the first terminal of the first read transistor, and a second terminal of the third read transistor is connected with the second terminal of the first read transistor.

10. The data transmission circuit of claim 5, wherein, The reference unit comprises: A fourth read transistor, a control terminal of the fourth read transistor is configured to receive the reference data signal, a first terminal of the fourth read transistor is configured to receive the enable adjustment signal, and a second terminal of the fourth read transistor is connected with the second node.

11. The data transmission circuit of claim 10, wherein, The reference unit further comprises: A second control circuit, configured to generate a reference control signal according to a second control signal; A fifth read transistor, a control terminal of the fifth read transistor is connected with the second control circuit, configured to receive the reference control signal, a first terminal of the fifth read transistor is connected with the first terminal of the fourth read transistor, and a second terminal of the fifth read transistor is connected with the second terminal of the fourth read transistor.

12. The data transmission circuit of claim 11, wherein, The number of read transistors connected with the first node is the same as the number of read transistors connected with the second node.

13. The data transmission circuit of claim 10, wherein, The reference unit comprises: A sixth read transistor, a control terminal of the sixth read transistor is configured to receive the reference data signal, a first terminal of the sixth read transistor is configured to receive the enable adjustment signal, and a second terminal of the sixth read transistor is connected with the first terminal of the fourth read transistor, the fourth read transistor receives the enable adjustment signal through the sixth read transistor; A second switch, two ends of the second switch are connected with the first end of the sixth reading transistor and the second end of the sixth reading transistor respectively.

14. The data transmission circuit of claim 13, wherein, The reference unit further comprises: A second control circuit, configured to generate a reference control signal according to a second control signal; A seventh reading transistor, a control end of the seventh reading transistor is connected with the second control circuit, a first end of the seventh reading transistor is connected with the first end of the sixth reading transistor, and a second end of the seventh reading transistor is connected with the second end of the sixth reading transistor.

15. The data transmission circuit of claim 14, wherein, The reference unit further comprises: At least one matching component connected in parallel, each matching component is connected with the second node, and the matching component is configured to match the second coupling capacitance at the second node with the first coupling capacitance at the first node.

16. The data transmission circuit of claim 15, wherein, The matching component comprises: A matching transistor, a control end of the matching transistor is connected with the second node, and a first end and a second end of the matching transistor are grounded.

17. The data transmission circuit of claim 15, wherein, The matching component comprises: A matching capacitor, one end of the matching capacitor is connected with the second node, and the other end of the matching capacitor is grounded.

18. The data transmission circuit of claim 17, wherein, The matching component further comprises: A third switch, one end of the third switch is connected with the second node, and the other end of the third switch is connected with the matching capacitor.

19. The data transmission circuit of claim 4, wherein, The output unit comprises two signal output circuits, the two signal output circuits are a first output circuit and a second output circuit respectively, and each signal output circuit comprises a first input end, a second input end and an output end; The first input end of the first output circuit is connected with the first node, the first input end of the second output circuit is connected with the second node, the output end of the first output circuit is connected with the second input end of the second output circuit, and the second input end of the first output circuit is connected with the output end of the second output circuit; wherein The node, at which the output end of the first output circuit is connected with the second input end of the second output circuit, is configured to output the readout data signal, and the node, at which the second input end of the first output circuit is connected with the output end of the second output circuit, is configured to output an inverted signal of the readout data signal.

20. The data transmission circuit of claim 19, wherein, The signal output circuit comprises: An eighth reading transistor, a control end of the eighth reading transistor serves as a first input end of the signal output circuit, a first end of the eighth reading transistor is connected with a high level, and a second end of the eighth reading transistor serves as an output end of the signal output circuit; A ninth reading transistor, a control end of the ninth reading transistor is connected with the control end of the eighth reading transistor, and a first end of the ninth reading transistor is connected with the second end of the eighth reading transistor; A tenth reading transistor, a control end of the tenth reading transistor serves as a second input end of the signal output circuit, a first end of the tenth reading transistor is connected with the second end of the eighth reading transistor, and a second end of the tenth reading transistor is grounded; and An eleventh reading transistor, a control end of the eleventh reading transistor is connected with the control end of the tenth reading transistor, and a first end of the eleventh reading transistor is connected with the second end of the tenth reading transistor. An eleventh reading transistor, a control terminal of the eleventh reading transistor is connected with the control terminal of the tenth reading transistor, a first terminal of the eleventh reading transistor is connected with a high level, and a second terminal of the eleventh reading transistor is connected with the second terminal of the eighth reading transistor.

21. The data transmission circuit of claim 20, wherein, The output unit further comprises: A first reset transistor, a control terminal of the first reset transistor is used for receiving a reset signal, a first terminal of the first reset transistor is connected with a high level, and a second terminal of the first reset transistor is connected with the second terminal of the eighth reading transistor; A second reset transistor, a control terminal of the second reset transistor is used for receiving the reset signal, a first terminal of the second reset transistor is connected with the second terminal of the tenth reading transistor, and a second terminal of the second reset transistor is grounded.

22. A memory, comprising: Comprise: A data bus, provided with a data write node; A plurality of storage units; A plurality of data transmission circuits according to any one of claims 1 to 21, connected with the data write node and the storage units respectively, the data transmission circuit is used for acquiring a to-be-written data signal from the data bus through the data write node, generating a global data signal according to the to-be-written data, the level state of the global data signal is the same as that of the to-be-written data signal, and writing the global data signal into the corresponding storage unit.

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